SYS8256RKXLI-12_技术文档

256K x 8 SRAM MODULE

SYS8256RKX - 55/70/85/10/12

11403 West Bernado Court, Suite 100, San Diego, CA 92127.

Tel No: (619) 674 2233, Fax No: (619) 674 2230

Issue 2.0 : February 1999

Features

• Access Times of 55/70/85/100/120 ns.

Description

The SYS8256RKX is a plastic 2M Static RAM Module

housed in a standard 32 pin Single In-Line package • 32 Pin Single-In-Line package.

organised as 256K x 8. This offers a very high PCB

packing density, with the possibility of placing the

modules on a 5mm pitch.

• 5 Volt Supply ± 10%.

• Low Power Dissipation:

Average (min cycle) 566 mW (max).

Fast access times of 55 to 85 ns are available as well

Standby (CMOS)

61 mW (max).

as standard times of 100 to 120 ns, with the faster • Completely Static Operation.

modules operating at a slightly higher power

consumption.

• Low Voltage V_CCData Retention.

• Directly TTL Compatible.

The SYS8256RKX is offered as standard and low

power versions, with the -L module having a low

voltage data retention mode.

• On-board Supply Decoupling Capacitors.

Block Diagram

Pin Definition

A0 - A16

D0 - D17

WE

1

2

3

4

5

6

7

8

Vcc

A0

A1

A2

A3

D0

D1

A4

A5

OE

128K X 8

SRAM

128K X 8

SRAM

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

A6

A7

A8

A13

D2

CS

A15

A16

A17

A9

GND

OE

A14

D3

CS

A17

DECODER

Pin Functions

D4

D5

Address Inputs

A0 ~ A17

D0 ~ D7

CS

Data Input/Output

Chip Select Input

Read/Write Input

Output Enable Input

Power (+5V)

WE

A10

A11

A12

D6

WE

OE

D7

GND

V_CC

Ground

GND

ISSUE 2.0 February 1999

SYS8256RKX - 55/70/85/10/12

DC OPERATING CONDITIONS

Absolute Maximum Ratings ⁽¹⁾

Parameter

Symbol

V_T

min typ max

unit

V

Voltage on any pin relative to GND

Power Dissipation

-0.5V

-

1.0

-

+7.0

-

P_T

W

^oC

Storage Temperature

T_STG

-55

+150

Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at those or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

(2) V_Tcan be -3.5V pulse of less than 20ns.

Recommended Operating Conditions

Parameter

Symbol

V_CC

V_IH

min typ max

4.5 5.0 5.5

Unit

V

Supply Voltage

Input High Voltage

Input Low Voltage

Operating Temperature

2.2

-0.3

0

-

6.0

0.8

70

V

V_IL

V

T_A

⁰C

T_AI

-40

85

DC Electrical Characteristics (V_CC=5V±10%)

TA 0 to 70^OC

Parameter

Symbol Test Condition

min typ max Unit

I/P Leakage Current

O/P Leakage Current

I_LI1

I_Lo

0V - V_IN- V_CC

CS = V_IH, V_I/O= GND to Vcc

-

±4

µA

D0~D7

-

Average Supply Current 55/70/85

I_CC1t_CYC= 55ns, CS = V_IL,

V_IN= V_IL/V_CC-2.1V

55

103 mA

Average Supply Current 10/12/15

I_CC2t_CYC= 100ns, CS= V_IL,

V_IN=V_IL/V_CC-2.1V

-

45

7

70

11

mA

Standby Supply Current TTL levels I_SB

CS = V_CC-2.1V, V_IL> V_IN> V_CC-2.1V

-

mA

CMOS levels

I_SB1CS = V_CC-0.2V, 0.2 > V_IN> V_CC-0.2V

I_SB2As above

-

0.05 5

-L part, CMOS levels

-

10

-

300 µA

Output Low Voltage

V_OLI_OL= 2.1mA

-

0.4

-

V

Output High Voltage

V_OHI_OH= -1.0mA

2.4

-

Typical values are at V_CC=5.0V,T_A=25^°C and specified loading.

2

SYS8256RKX - 55/70/85/10/12

ISSUE 2.0 February 1999

Capacitance (V_CC=5V±10%,T_A=25^°C)

Parameter

Symbol Test Condition

max

8

Unit

pF

Input Capacitance (CS, A17)

Input Capacitance (other)

I/O Capacitance

C_IN1

C_IN2

C_I/O

V_IN= 0V

V_I/O= 0V

12

16

pF

Data Retention Characteristics - L Version Only

Parameter

Symbol

V_DR

Test Condition

CS > V_CC-0.2V

min typ⁽¹⁾max

Unit

V

V_CCfor Data Retention

Data Retention Current

2.0

-

V_CC= 3.0V, CS > V_CC-0.2V

T_OP= 0°C to 40°C

T_OP= T_A

(2)

I_CCDR1

-

5

-

100

150(3)

TBA

-

µA

ns

I_CCDR2

I_CCDR3

t_CDR

-

T_OP= T_AI

-

Chip Deselect to

See Retention Waveform

0

-

Data Retention Time

Operation Recovery Time

t_R

See Retention Waveform

5

-

ms

Notes

(1) Typical figures are measured at 25°C.

(2) This parameter is guaranteed not tested.

(3) Maximum figure at 70^OC

AC Test Conditions

Output Load

I/O Pin

645Ω

* Input pulse levels: 0V to 3.0V

* Input rise and fall times: 5ns

* Input and Output timing reference levels: 1.5V

* Output load: see diagram

1.76V

100pF

* V_CC=5V±10%

3

ISSUE 2.0 February 1999

SYS8256RKX - 55/70/85/10/12

AC OPERATING CONDITIONS

Read Cycle

-55

-70

-85

Parameter

Symbol min max min max min max Unit

Read Cycle Time

t_RC

55

-

70

-

85

-

ns

Address Access Time

t_AA

55

30

-

70

35

-

85

55

-

Chip Select Access Time

t_ACS

t_OE

-

Output Enable to Output Valid

Output Hold from Address Change

Chip Selection to Output in Low Z ⁽²⁾

Output Enable to Output in Low Z ⁽²⁾

Chip Deselection to O/P in High Z ⁽²⁾

Output Disable to Output in High Z ⁽²⁾

-

t_OH

5

0

10

5

10

5

t_CLZ

t_OLZ

t_CHZ

t_OHZ

-

20

0

25

0

30

0

Read Cycle

-10

-12

Parameter

Symbol min max min max Unit

Read Cycle Time

t_RC

100

-

100

60

-

120

-

ns

Address Access Time

t_AA

120 ns

Chip Select Access Time

t_ACS

t_OE

-

Output Enable to Output Valid

Output Hold from Address Change

Chip Selection to Output in Low Z ⁽²⁾

Output Enable to Output in Low Z ⁽²⁾

Chip Deselection to O/P in High Z ⁽²⁾

Output Disable to Output in High Z ⁽²⁾

-

70

-

ns

t_OH

10

5

10

5

t_CLZ

t_OLZ

t_CHZ

t_OHZ

-

0

35

0

45

0

4

SYS8256RKX - 55/70/85/10/12

ISSUE 2.0 February 1999

Write Cycle

-55

-70

-85

Parameter

Symbol min max min max min max Unit

Write Cycle Time

t_WC

t_CW

t_AW

t_AS

55

50

0

-

0

-

70

60

0

-

85

80

0

-

ns

Chip Selection to End of Write

Address Valid to End of Write

Address Setup Time

-

Write Pulse Width

t_WP

t_WR

t_WHZ

t_DW

t_DH

40

0

50

0

-

65

5

-

Write Recovery Time

-

Write to Output in High Z ⁽¹¹⁾

Data to Write Time Overlap

Data Hold from Write Time

Output active from end of write ⁽¹⁰⁾

02

30

0

25

-

0

30

-

35

0

35

0

-

t_OW

5

-

5

-

Write Cycle

-10

-12

Parameter

Symbol min max min max Unit

Write Cycle Time

t_WC

t_CW

t_AW

t_AS

100

90

0

-

120

100

0

-

ns

Chip Selection to End of Write

Address Valid to End of Write

Address Setup Time

-

Write Pulse Width

t_WP

t_WR

t_WHZ

t_DW

t_DH

75

5

-

85

10

0

-

Write Recovery Time

-

Write to Output in High Z ⁽¹¹⁾

Data to Write Time Overlap

Data Hold from Write Time

Output active from end of write ⁽¹⁰⁾

0

35

-

40

-

40

0

45

0

-

t_OW

5

-

5

-

5

ISSUE 2.0 February 1999

SYS8256RKX - 55/70/85/10/12

Read Cycle Timing Waveform

t _RC

Address

OE

t_AA

t_OE

t_OLZ

t_OH

CS

Don't

care.

t_ACS

t_CLZ

t_OHZ

Dout

Data Valid

t_CHZ

Notes (1) WE is High for Read Cycle.

(2) t_HZand t_OHZare defined as the time at which the outputs achieve open circuit conditions and are not

referenced to output voltage levels.These parameters are sampled and not 100% tested.

Write Cycle No.1 Timing Waveform

t_WC

Address

t_WR(4)

t_AS(3)

OE

t_AW

t _CW(2)

(6)

CS

Don't

Care

WE

t_OHZ(5)

t_WP(1)

t_OW

High-Z

Dout

Din

t_DH

t_DW

High-Z

6

SYS8256RKX - 55/70/85/10/12

ISSUE 2.0 February 1999

Write Cycle No.2 Timing Waveform

t_{W C}

Address

t _{A S (3)}

t _{C W}

(2)

t_{W R (4)}

C S

t_{A W}

t_{W P (1)}

W E

D out

D in

t_{O H}

D on't

C are

(8)

t _{W H Z (5)}

t _{O W}

(7)

H igh-Z

t_{D H}

t_{D W}

H igh-Z

(9)

AC Characteristics Notes

(1) A write occurs during the overlap (t_WP) of a low CS and a low WE.

(2) t_CWis measured from the earlier of CS or WE going high to the end of write cycle.

(3) t_ASis measured from the address valid to the beginning of write.

(4) t_WRis measured from the earliest of CS or WE going high to the end of write.

(5) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.

(6) If CS goes low simultaneously with WE going low or after WE going low , outputs remain in a high

impedance state.

(7) D_OUTis in the same phase as written data of this write cycle.

(8) D_OUTis the read data of next address.

(9) If CS is low during this period, I/O pins are in the output state, and inputs out of phase must not be

applied to I/O pins.

(10) This parameter is sampled and not 100% tested.

(11) t_WHZisdefinedasthetimeatwhichtheoutputsachieveopencircuitconditionsandisnotreferencedtooutput

voltage levels. This parameter is sampled and not 100% tested.

Data Retention Waveform

DATA RETENTION MODE

Vcc

4.5V

2.2V

t_CDR

t_R

2.2V

V_DR

CS > Vcc -0.2V

CS

0V

7

ISSUE 2.0 February 1999

SYS8256RKX - 55/70/85/10/12

Package Information

32 Pin SIP

5.50 MAX

82.63 MAX

U1

M1

C1

M2

C2

3.50 +/- 0.50

2.54 TYP.

0.50 TYP.

Dimensions in mm

Ordering Information

SYS8256RKXLI - 10

Speed

55 = 55 ns (Commercial only)

70 = 70 ns

85 = 85 ns

10 = 100 ns

12 = 120 ns

Temperature Range

Power Consumption

Blank = Commercial Temperature

I = Industrial Temperature

Blank = Standard Part

L = Low Power Part

Package

RKX = Plastic 32 pin SIL

8256 = 256K x 8

Organization

Memory Type

SYS = Static RAM

I-55 parts are not available at present

Note :

Although this data is believed to be accurate, the information contained herein is not intended to and does not create

any warranty of merchantibility or fitness for a particular purpose.

Our products are subject to a constant process of development. Data may be changed at an time without notice.

Products are not authorised for use as critical components in life support devices without the express written approval of

a company director.

8


型号：	SYS8256RKXLI-12
厂家：	MOSAIC
描述：	SRAM Module, 256KX8, 120ns, CMOS, PLASTIC, SIP-32 静态存储器内存集成电路
文件：	总8页 (文件大小：93K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SYS8256RKXLI-12 [MOSAIC]

相关型号：

SYS8256RKXLI-70

SYS8256RKXLI-85

SYS84000RKX-10

SYS84000RKX-12

SYS84000RKX-70

SYS84000RKX-85

SYS84000RKXI-10

SYS84000RKXI-12

SYS84000RKXI-70

SYS84000RKXI-85

SYS84000RKXL-10

SYS84000RKXL-12