MSU2031C25 [MOSEL]
low working voltage 16 MHz ROM less MCU; 低工作电压为16 MHz ROM MCU少
| 型号： | MSU2031C25 |
| 厂家： | 
MOSEL VITELIC, CORP |
| 描述： | low working voltage 16 MHz ROM less MCU |
| 文件： | 总21页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MO SEL VITELIC
MSU2051/U2031
Product List
MSU2031L16, low working voltage 16 MHz ROM less MCU
MSU2031S16, small sink current 16 MHz ROM less MCU
MSU2031C16, 16 MHz ROM less MCU
MSU2031C25, 25 MHz ROM less MCU
MSU2031C40, 40 MHz ROM less MCU
MSU2051L16, low working voltage 16 MHz 4 KB internal ROM MCU
MSU2051S16, small sink current 16 MHz 4 KB internal ROM MCU
MSU2051C16, 16 MHz 4 KB internal ROM MCU
MSU2051C25, 25 MHz 4 KB internal ROM MCU
MSU2051C40, 40 MHz 4 KB internal ROM MCU
Description
Features
Working voltage : L series at 2.7V through 4.5V
while S & C series at 4.5 V through 5.5 V
General 80C51 family compatible
64 K byte External Memory Space
4 K byte ROM
128 byte data RAM
Two 16 bit Timers/Counters
Four 8-bit I/O ports
The MVI MSU2051 series product is an 8 - bit
single chip microcontroller. It provides hardware
features and a powerful instruction set,
necessary to make it a versatile and cost
effective controller for those applications
demand up to 32 I/O pins or need up to 64 K
byte external memory either for program or for
data or mixed.
A serial input / output port is provided for I/O
expansion, Inter - processor communications,
and full duplex UART.
Full duplex serial channel
Bit operation instructions
Page free jumps
Ordering Information
8 - bit Unsigned Division
8 - bit Unsigned Multiply
BCD arithmatic
MSU2031ihhk
MSU2051ihh - yyyk
i: process identifier {S, L, C}.
Direct Addressing
hh: working clock in MHz {16, 25, 40}.
yyy: production code {001, ..., 999}
k: package type postfix {as below table}.
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A serial I/O port
Power save modes:
Idle mode and Power down mode
Working at 16/25/40 MHz Clock
Pin/Pad
Configuration
Logo Size at
Top Marking
Cross Reference
Postfix
Package
Dimension
blank
dice
page 18
page 2
page 18
page 14
page 15
page 16
page 17
-
M.V.I.
W.B.
MSU2051
W78C51
80C51
MSU2031
W78C31
80C31
P
J
40L PDIP
44L PLCC
44L PQFP
44L LQFP
5.0 x 4.2 mm
4.5 x 3.8 mm
2.8 x 2.4 mm
2.8 x 2.4 mm
page 2
page 2
Philips
L.G.
Q
U
GMS80C501
80C51
GMS80C301
80C31
page 2
Intel
CCL. itri
Atmel
CIC80510
AT80C51
- - - - -
AT80C31
Specifications subject to change without notice, contact your sales representatives for the most recent information.
Rev. 1.0 February 1998
1
MO SEL VITELIC
MSU2051/U2031
Pin Configurations
44 43 42 41 40 41 40 39 38 37 34
6
5
4
3
2
1
44 43 42 41 40
39
33
32
AD4/P 0.4
7
8
1
P 1.5
P 1.6
P 1.5
AD4/P 0.4
AD5/P 0.5
AD6/P 0.6
38
37
2
3
P 1.6
P 1.7
AD5/P 0.5
AD6/P 0.6
31
9
P 1.7
30
29
MSU2031ihhQ,
MSU2051ihh-
yyyQ
AD7/P 0.7
MSU2031ihhJ,
MSU2051ihh-
yyyJ
10
36
4
RES
RES
AD7/P 0.7
#E A
NC
11
35
34
RXD/P 3.0
5
6
RXD/P 3.0
NC
#EA
NC
28
12
13
NC
27
26
ALE
33
7
TXD/P 3.1
TXD/P 3.1
ALE
44L PLCC
44L PQFP
#P SEN
14
32
31
#INT0/P 3.2
8
9
#INT0/P 3.2
#INT1/P 3.3
#PSE N
25
24
23
A15/P 2.7
15
16
#INT1/P 3.3
A15/P 2.7
A14/P 2.6
A13/P 2.5
30
10
11
T0/P 3.4
T1/P 3.5
T0/P 3.4
T1/P 3.5
A14/P 2.6
A13/P 2.5
(Top View)
(Top View)
17
29
18 19 20 21 22 23 24 25 26 27 28
XT L1
12 13 14 15 16 17 18 19 20 21 22
P 1.0
40
39
1
2
VDD
AD0/P0.0
P 1.1
P 1.2
44 43 42 41 40 41 40 39 38 37 34
38
37
3
4
AD1/P0.1
AD2/P0.2
AD4/P 0.4
AD5/P 0.5
P 1.5
33
1
2
P 1.3
P 1.6
P 1.7
32
31
P 1.4
P 1.5
36
35
5
6
AD3/P0.3
AD4/P0.4
AD6/P 0.6
AD7/P 0.7
3
4
RES
30
P 1.6
34
7
AD5/P0.5
#E A
RXD/P 3.0
NC
29
28
5
MSU2031ihhU,
MSU2051ihh-
yyyU
P 1.7
RES
33
32
8
9
AD6/P0.6
AD7/P0.7
NC
6
7
ALE
TXD/P 3.1
27
RXD/P 3.0
31
10
#EA
#P SEN
#INT0/P 3.2
#INT1/P 3.3
26
25
8
TXD/P 3.1
30
29
11
12
ALE
A15/P 2.7
A14/P 2.6
9
44L LQFP
#INT0/P 3.2
#PSEN
T0/P 3.4
T1/P 3.5
24
23
10
#INT1/P 3.3
T0/P 3.4
28
13
A15/P2.7
A13/P 2.5
11
27
26
12 13 14 15 16 17 18 19 20 21 22
14
15
A14/P2.6
A13/P2.5
T1/P 3.5
#WR/P 3.6
25
24
16
17
A12/P2.4
A11/P2.3
#RD/P 3.7
XTAL2
XTAL1
23
22
18
19
A10/P2.2
A9/P2.1
VSS
21
20
A8/P2.0
Rev. 1.0 February 1998
2
MO SEL VITELIC
MSU2051/U2031
Block Diagram
Decoder &
Register
128 bytes
RAM
4K bytes
ROM
Stack
Timer 1
Timer 0
Pointer
Register
Buffer
to pertinent blocks
to whole chip
RES
Reset
Circuit
Acc
Vdd
Vss
Power
Circuit
DPTR
Buffer2
Buffer1
to pertinent blocks
Interrupt
Circuit
PC
Increamenter
ALU
XTAL2
XTAL1
#EA
Timming
PSW
Program
Counter
to whole system
Generator
#PSEN
ALE
Instruction
Register
Port 3
Latch
Port 1
Latch
Port 2
Latch
Port 0
Latch
Port 3
Driver
Port 1
Driver
Port 2
Driver
Port 0
Driver
8
8
8
8
Rev. 1.0 February 1998
3
MO SEL VITELIC
MSU2051/U2031
Pin Descriptions
40 PDIP Dice 44 LQFP 44 PQFP 44 PLCC Symbol
Active I/O
Names
Pin# Pad#
Pin#
40
41
42
43
44
1
Pin#
40
41
42
43
44
1
Pin#
2
1
1
2
P1.0
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i
bit 0 of Port 1
2
3
P1.1
bit 1 of Port 1
3
3
4
P1.2
bit 2 of Port 1
4
4
5
P1.3
bit 3 of Port 1
5
5
6
P1.4
bit 4 of Port 1
6
6
7
P1.5
bit 5 of Port 1
7
7
2
2
8
P1.6
bit 6 of Port 1
8
8
3
3
9
P1.7
bit 7 of Port 1
9
9
4
4
10
11
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
RES
Reset
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
10
11
12
13
14
15
16
17
18
19
20-22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42,43
5
5
RXD/P3.0
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
#WR/P3.6
#RD/P3.7
XTAL2
i/o
i/o
bit 0 of Port 3 & Receive data
bit 1 of Port 3 & Transmit data
7
7
L/-
L/-
8
8
i/o
i/o
i/o
i/o
i/o
i/o
o
bit 2 of Port 3 & low true Interrupt 0
bit 3 of Port 3 & low true Interrupt 1
bit 4 of Port 3 & Timer 0
9
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
bit 5 of Port 3 & Timer 1
L/-
L/-
bit 6 of Port 3 & Write (low enable)
bit 7 of Port 3 & Read (low enable)
Crystal out
XTAL1
i
Crystal in
VSS
Sink Voltage, Ground
A8/P2.0
A9/P2.1
A10/P2.2
A11/P2.3
A12/P2.4
A13/P2.5
A14/P2.6
A15/P2.7
#PSEN
ALE
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
bit 0 of Port 2 & Address 8
bit 1 of Port 2 & Address 9
bit 2 of Port 2 & Address 10
bit 3 of Port 2 & Address 11
bit 4 of Port 2 & Address 12
bit 5 of Port 2 & Address 13
bit 6 of Port 2 & Address 14
bit 7 of Port 2 & Address 15
Program store enable (low enable)
Address latch enable
L
H
L
o
#EA
i
External access first 4K memory
bit 7 of Port 0 & Address or Data 7
bit 6 of Port 0 & Address or Data 6
bit 5 of Port 0 & Address or Data 5
bit 4 of Port 0 & Address or Data 4
bit 3 of Port 0 & Address or Data 3
bit 2 of Port 0 & Address or Data 2
bit 1 of Port 0 & Address or Data 1
bit 0 of Port 0 & Address or Data 0
Drive Voltage, +3 Vcc (or +5 Vcc)
AD7/P0.7
AD6/P0.6
AD5/P0.5
AD4/P0.4
AD3/P0.3
AD2/P0.2
AD1/P0.1
AD0/P0.0
VDD
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
Rev. 1.0 February 1998
4
MO SEL VITELIC
MSU2051/U2031
#EA
Pin Descriptions
Vss
When held at a TTL high level, the MSU2051 executes
instructions from the internal ROM when the PC is less
than 4096. When held at a TTL low level, the
MSU2051 fetches all instuctions from external Program
Memory.
Circuit ground potential.
VDD
+3V (or +5 V) power supply during operation.
XTAL 1
PORT 0
Input to the oscillator's high gain amplifier. A crystal or
external source can be used.
Port 0 is an 8-bit open drain bidirectional I/O port.
It is also the multiplexed low-order address and data
bus when using external memory.
XTAL 2
Output from the oscillator's amplifier. Required when a
crystal is used.
PORT 1
Port 1 is an 8-bit quasi-bidirectional I/O port with
internal pull-up resistance.
Terms
PORT 2
Idle Mode
Port 2 is an 8-bit quasi-bidirectional I/O port with
internal pull-up resistance. It also emit the high-order
address byte when accessing external memory.
During idle mode, the CPU is stopped but below blocks
are kept functioning: clock generator, RAM, timer/
counters, serial port and interrupt block. To save power
consumption, user's software program can invoke this
mode. The on-chip data RAM retains the values during
this mode, but the processor stops executing
instructions. In Idle mode (IDL=1), the oscillator
continues to run and the interrput, and timer blocks
continue to be clocked but the clock signal is gated off
to the CPU. The activities of the CPU no longer exist
unless waiting for an interrupt request.
-An instruction that sets flag (PCON.0) causes that to be
the last instruction executed before going into the Idle
Mode.
-In the Idle Mode, the internal clock signal is gated off to
the CPU, but not to the interrupt, Timer function.
-The CPU status is entirely preserved in its:
the Stack Pointer, Program Counter, Program Status
Word, Accumulator, and all other registers maintain
their data during Idle mode.
PORT 3
Port 3 is an 8-bit quasi-bidirectinal I/O port with internal
pull-up resistance. It also contains the interrupt, timer,
serial port and #RD as well as #WR pins that are used
by various options. The output latch corresponding to a
secondary function must be programmed to one (1) for
that function to operate. The secondary functions are
assigned to the pins of port 3, as follows:
- RXD/data (P3.0). Serial port's transmitter data output
(asynchronous) or data input/output (asynchronous).
- TXD/clock (P3.1). Serial port's transmitter data
output (asynchronous) or data output (asynchronous).
- #INT0 (P3.2). Interrupt 0 input or gate control input
for counter 0.
- #INT1 (P3.3). Interrupt 1 input or gate control input
for counter 1.
- T0 (P3.4). Input to counter 0.
- T1 (P3.4). Input to counter 1.
-There are three ways to terminate the Idle Mode.
1) By interrupt
Activation of any enabled interrupt will cause flag
(PCON.0) to be cleared by hardware, termination the
Idle Mode. After the program wakes up, the PC value
will point as interrupt vector (if enable IE register) and
execute interrupt service routine then return to PC+1
address after the program wakes up.
- #WR (P3.6). The write control signal latches the data
byte from Port 0 into the External Data Memory.
- #RD (P3.7). The read control signal enables External
Data Memory to Port 0.
RES
2) By hardware reset
Since the clock oscillator is still running, the hardware
reset needs to be held active for only two machine
cycles (24 oscillator periods) to complete the reset. All
SFR and PC value will be cleared to reset value.
3) By one of CLK, DATA, PORT 2.0-2.7 transition to
low (falling edge trigger)
After the program wakes up, the PC value will be
0023h (if enable IE register) and execute interrupt
service routine and then returns to PC+1 address after
the program wakes up.
A high on this pin for two machine cycles (24 clocks)
while the oscillator is running, resets the device. The
data in RAM is preserved when reset signals - reset
does not clear the data in RAM.
ALE
Provides Address Latch Enable output used for latching
the address into external memory during normal opera-
tion.
#PSEN
The Program Store Enable output is a control signal that
enables the external Program Memory to the bus during
normal fetch operations.
Rev. 1.0 February 1998
5
MO SEL VITELIC
MSU2051/U2031
Power Down Mode
General of above
It saves the RAM content, stops the clock generator
and disables every other blocks' function until the
coming hardware reset. To save even more power
consumption, user's software program can invoke this
mode. The SFRs and the on-chip data RAM retain
their values during this mode, but the porcessor stops
executing instructions. In Power-Down mode (PD=1)
the oscillator is frozen.
-An instruction that sets flag (PCON.1) causes that to
be the last instruction executed before going into the
Power Down Mode.
-In the Power Down Mode, the on-chip oscillator is
stopped.
User should fix the attention on using wake up from
port 2:
-The user should write the power down or idle mode
flag value to one RAM address before write PCON to
distinguish waking up from power down mode or idle
mode.
-After idle mode or power down mode wakes up, the
interrupt service routine will be executed first and then
executes PC+1 address if the IE register is enabled
before entering power down mode or idle mode. The
interrupt service routine will not be executed but CPU
executes PC+1 address program if disable IE register.
-After wake up power down or idle mode the IDF flag
will be set by hardware. The IDF flag be cleared at
the ISR execution time. If IE register is disable, the
IDF flag will not be cleared when power down or idle
mode wakes up.
With the clock frozen, all functions are stopped, but
the on-chip RAM and Special Function Registers are
held.
-Reset redefines all the SFRs, but does not change the
on-chip RAM.
-There are two ways to terminate the Power Down
Mode.
1) By hardware reset
All SFR and PC value will be cleared to reset value.
2) One of CLK, DATA, PORT 2.0-2.7 transition to low
(falling edge trigger)
After the program wakes up, the PC value will be
0023h (if enable IE register) and execute interrupt
service routine and then returns to PC+1 address after
the program wakes up.
-Care must be taken, however, to ensure that VCC is
not reduced before the Power Down Mode is invoked,
and that VCC is restored to its normal operating level
before the Power Down Mode is terminated.
-The hardware reset must be held active long enough
to allow the oscillator to restart and stabilize.
The state of pins during Idle and Power-Down Mode
Mode
Program
memory
ALE
#PSEN
Port 0
Port 1
Port 2
Port 3
Idle
Idle
Internal
External
Internal
External
1
1
0
0
1
1
0
0
Data
Float
Data
Float
Data
Data
Data
Data
Data
Data
Data
Data
Data
Address
Data
Power Down
Power Down
Data
Absolute Maximal Rating
* Note:
Symbol
Name
Rating
Unit
V
Remark
Operation beyond Absolute Maximal Rating
can adversely affect device reliability.
Vdd - Vss
DC supply Voltage
-0.5 ~ +5.0
-0.5 ~ +7.0
U20x1L
U20x1S,U20x1C
V
VIN
Input voltage
output voltage
Vss-0.3 ~ Vdd+0.3
Vss ~ Vdd
V
VOUT
T (Operating) Operating Temperature
T (Storage) Storage Temperature
0 ~ +70
°C
°C
-55 ~ +125
Rev. 1.0 February 1998
6
MO SEL VITELIC
MSU2051/U2031
Operating Conditions
Symbol
Description
Min.
0
Typ.
25
Max.
70
Unit
°C
Remarks
t
A
Ambient temperature under bias
Supply voltage
V CC3
V CC5
f osc 16
f osc 25
f osc 40
2.7
4.5
3.0
16
3.0
5.0
16
4.5
5.5
16
V
U20x1L
V
U20x1S, U20x1C
U20x1i16
Oscillator Frequency
MHz
MHz
MHz
25
25
U20x1i25
25
40
40
U20x1i40
AC Characteristics
(16/25/40 MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=150pF; CL for all OtherOutputs=80pF)
f osc 16
Valid
Cycle
RD/WRT
RD/WRT
RD/WRT
RD
Variable f osc
Parameter
Min. Typ. Max
Min.
Typ.
Max.
Unit Remarks
Symbol
T LHLL
T AVLL
T LLAX
T LLIV
ALE pulse width
115
43
nS
nS
nS
2xT - 10
T - 20
Address Valid to ALE low
Address Hold after ALE low
ALE low to Valid Instruction In
ALE low to #PSEN low
#PSEN pulse width
53
T - 10
240
4xT - 10 nS
RD
53
nS
T LLPL
T PLPH
T PLIV
T - 10
RD
173
177
0
nS
3xT - 10 nS
nS
3xT - 15
#PSEN low to Valid Instruction In
Instruction Hold after #PSEN
Instruction Float after #PSEN
Address to Valid Instruction In
#PSEN low to Address Float
#RD pulse width
RD
T PXIX
RD
0
RD
87
T + 25 nS
5xT - 20 nS
10 nS
nS
T PXIZ
RD
292
10
T AVIV
T PLAZ
T RLRH
T WLWH
T RLDV
T RHDX
T RHDZ
T LLDV
T AVDV
T LLYL
T AVYL
T QVWH
T QVWX
T WHQX
T RLAZ
T YHLH
T CHCL
T CLCX
T CLCH
T CHCX
T, T CLCL
RD
RD
365
365
302
0
6xT - 10
6xT - 10
#WR pulse width
WRT
RD
nS
#RD low to Valid Data in
Data Hold after #RD
5xT - 10 nS
nS
RD
0
Data Float after #RD
RD
145
490
542
2xT + 20 nS
8xT - 10 nS
9xT - 20 nS
3xT + 10 nS
nS
ALE low to Valid Data In
Address to Valid Data In
ALE low to #WR or #RD low
RD
RD
RD/WRT
178
230
403
38
197
3xT - 10
4xT - 20
7xT - 35
T - 25
Address Valid to #WR or #RD low RD/WRT
Data Valid to #WR High
Data Valid to #WR transition
Data hold after #WR
#RD low to Address Float
#WR or #RD high to ALE high
Clock fall time
WRT
WRT
WRT
RD
nS
nS
73
nS
T + 10
5
nS
RD/WRT
53
72
T + 10 nS
T - 10
nS
nS
nS
nS
nS
Clock low time
Clock rise time
Clock high time
Clock period
63
1/ fosc
Rev. 1.0 February 1998
7
MO SEL VITELIC
MSU2051/U2031
DC Characteristics
(16/25/40 MHz, typical operating conditons, valid for U20x1C series)
Parameter
Valid
Min.
Typ.
Max
Unit Test Conditions
Symbol
V ILX
Input Low Voltage
XTAL1
#EA
V
V
-0.5
0
20%Vcc-0.1
20%Vcc-0.3
20%Vcc-0.1
Vcc+0.5
Vcc+0.5
Vcc+0.5
450
V ILE
"
"
RES
V
V ILR
-0.5
Input High Voltage
XTAL1
#EA
V
V IHX
V IHE
V IHR
V OLA
V OL0
V OL1
V OHA
70%Vcc
20%Vcc+0.9
70%Vcc
"
V
"
RES
V
Output Low Voltage
ALE, #PSEN
ports 0,3
ports 1,2
ALE, #PSEN
mV
mV
mV
V
I OL = 3.2 mA
I OL = 3.2 mA
I OL = 1.6 mA
I OH = -60 uA
I OH = -10 uA
I OH = -800 uA
I OH = -80 uA
I OH = -60 uA
I OH = -10 uA
I OH = -60 uA
I OH = -10 uA
V OL = 0.45V, note 1
V in = 0.45 V
V in = 5.0 V
"
450
"
450
Output High Voltage
2.4
90%Vcc
2.4
"
V
V OH0
V OH1
V OH2
"
port 0
V
"
V
90%Vcc
2.4
"
ports 1,3
port 2
V
"
90%Vcc
2.4
V
"
V
"
V
90%Vcc
Output Low Current
Logical 0 Input Current
Logical 1 Input Current
ports 0,3
ports 1,2,3
port 0
mA
uA
uA
I OL0
I IL
18
-50
1.5
I IH
I TL
Logic Transition Current
Input Leakage Current
Reset Pulldown Resistance
ports 1,2,3
port 0
-650
10
uA
uA
V in = 2.0 V
0.45V < Vin < Vcc
I LI
RES
Kohm
R RES
R X
50
90
150
Crystal feedback Resistance XTAL1,2
Pin Capacitance
330 Kohm
C IO
I CC
10
8
pF
mA
mA
uA
Freq=1MHz, Ta=25 ¢J
Active mode, 16 MHz
Idle mode, 16MHz
Power Supply Current
Vdd
Vdd
Vdd
5
3
5
10
45
Power down mode
note 1 : no more than 80 mA I OLs for all 16-bit ports 0 & 3 output pins.
DC Characteristics
(16 MHz, typical operating conditons, valid for U20x1S series)
Symbol
I OL0
Parameter
Valid
Min.
Typ.
Max.
Unit
Test conditions
Output Low Current
ports 0 & 3
3
mA
V OL = 0.45V
others
identical to U20x1C series'
Rev. 1.0 February 1998
8
MO SEL VITELIC
MSU2051/U2031
DC Characteristics
(16 MHz, typical operating conditons, valid for U20x1L series)
Parameter
Valid
XTAL1
#EA
Min.
Typ.
Max
Unit
mV
mV
mV
V
Test Conditions
Symbol
V ILX
Input Low Voltage
V ILE
"
"
RES
V ILR
Input High Voltage
XTAL1
#EA
Vcc+0.3
Vcc+0.3
Vcc+0.3
V IHX
V IHE
V IHR
V OLA
V OL0
V OL1
V OHA
"
V
"
RES
V
Output Low Voltage
ALE, #PSEN
ports 0,3
ports 1,2
ALE, #PSEN
mV
mV
mV
V
I OL = 3.2 mA
I OL = 3.2 mA
I OL = 1.6 mA
I OH = -60 uA
I OH = -10 uA
I OH = -800 uA
I OH = -80 uA
I OH = -60 uA
I OH = -10 uA
I OH = -60 uA
I OH = -10 uA
400
400
400
"
"
Output High Voltage
1.8
"
"
"
"
"
"
"
2.4
2.2
2.4
1.8
2.4
1.8
2.4
V
port 0
V
V OH0
V OH1
V OH2
V
ports 1,3
port 2
V
V
V
V
Logical 0 Input Current
Logical 1 Input Current
ports 1,2,3
port 0
uA
uA
V in = 0.45 V
V in = 3.0 V
I IL
45
1
I IH
Logic Transition Current
Input Leakage Current
Reset Pulldown Resistance
ports 1,2,3
port 0
uA
uA
V in = 1.4 V
I TL
250
8
0.45V < Vin < Vcc
I LI
R RES
R X
RES
50
90
150 Kohm
330 Kohm
Crystal feedback Resistance XTAL1,2
Pin Capacitance
pF
mA
mA
uA
Freq=1MHz, Ta=25 ¢J
Active mode, 16 MHz
Idle mode, 16MHz
C IO
I CC
10
7
Power Supply Current
Vdd
Vdd
Vdd
2
1
4.5
45
Power down mode
10
Rev. 1.0 February 1998
9
MO SEL VITELIC
MSU2051/U2031
Data Memory Read Cycle Timing
T12
T1
T2
T3
T4
T5
T6
T7
T8 T9
T10 T11 T12 T1
T2
T3
OSC
1
2
ALE
#PSEN
#RD
5
7
3
ADDRESS A - A
15
PORT2
PORT0
8
3
4
6
8
INST in Float
A
-A
Float
DATA in
Float
ADDRESS
or Flloat
7
0
Program Memory Read Cycle Timing
T12 T1
T2
T3
T4
T5
T6
T7
T8 T9
T10 T11 T12 T1
T2
OSC
1
2
ALE
5
7
#PSEN
#RD, #WR
PORT2
PORT0
3
ADDRESS A - A
15
ADDRESS A -A
15
8
8
3
4
6
8
Float
A
-A
Float
INST in
Float
A
-A
Float
INST in
Float
7
0
7
0
Rev. 1.0 February 1998
10
MO SEL VITELIC
MSU2051/U2031
Data Memory Write Cycle Timing
T12
T1
T2
T3
T4
T5
T6
T7
T8 T9
T10 T11 T12 T1
T2
T3
OSC
1
ALE
#PSEN
#WR
5
6
2
2
ADDRESS A - A
15
PORT2
PORT0
8
3
4
INST
Float
A
-A
DATA OUT
7
0
ADDRESS
or Floa
I/O Ports Timing
T6
T7
T8
T9
T10 T11 T12
T1
T2
T3
T4
T5
T6
T7
T8
X1
sampled
inputs P0, P1
sampled
inputs P2, P3
Output by
MOV Px,Src
current data
next data
RxD at Serial Port
Shift Clock
sampled
(Mode 0)
Rev. 1.0 February 1998
11
MO SEL VITELIC
MSU2051/U2031
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
T CLCL
Vdd-0.5V
70%Vdd
0.45V
20%Vdd-0.1V
T CHCX
T CLCX
T CHCL
T CLCH
Tm.I External Program Memory Read Cycle
T PLPH
#PSEN
ALE
T LHLL
T AVLL
T LLPL
T LLIV
T PLAZ
T PXIZ
T PXIX
T LLAX
T PLIV
PORT 0
PORT 2
A0 - A7
Instruction. IN
A0 - A7
T AVIV
A8 - A15
A8 - A15
Tm.II External Data Memory Read Cycle
#PSEN
T YHLH
ALE
T LLDV
T LLYL
T RLRH
#RD
T AVLL
T LLAX
T RHDZ
T RHDX
DATA IN
T RLDV
T RLAZ
A0-A7
from Ri or
A0-A7
From
INSTR.
IN
PORT 0
PORT 2
T AVYL
T AVDV
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Rev. 1.0 February 1998
12
MO SEL VITELIC
MSU2051/U2031
Tm.III External Data Memory Write Cycle
#PSEN
T YHLH
ALE
T LHLL
T LLYL
T WLWH
#WR
PORT 0
PORT 2
T QVWX
T AVLL
T WHQX
T LLAX
T QVWH
A0-A7
From
PCL
A0-A7
from Ri or
DPL
INSTR.
IN
DATA OUT
T AVYL
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Application Reference
Valid for U2051L16/ U2031L16/
U2051S16/ U2031S16
X'tal
C1
C2
R
3 MHz
15 pF
15 pF
open
6 MHz 12 MHz 16 MHz
X1
15 pF
15 pF
open
30 pF
30 pF
open
30 pF
30 pF
open
MSU2051/U2031
X'tal
R
Valid for U2051C16/ U2031C16/
U2051C25/ U2031C25/
U2051C40/ U2031C40
X2
X'tal
C1
C2
R
12 MHz 16 MHz 25 MHz
40 MHz
5 pF
C1
C2
30 pF
30 pF
open
30 pF
30 pF
15 pF
15 pF
5 pF
open 62 Kohm 4.7 Kohm
Rev. 1.0 February 1998
13
MO SEL VITELIC
MSU2051/U2031
40L 600mil PDIP Information
E
D
S
E1
C
A1
A2
A
L
e1
eA
B1
B
£\
Note:
Dimension inInch
minimal/maximal
- / 0.210
Dimension in mm
minimal/maximal
- / 5.33
1.Dimension D Max & S include mold flash or tie bar
Symbol
A
burrs.
2.Dimension E1 does not include interlead flash.
3.Dimenseion D & E1 include mold mismatch and are
determined at the mold parting line.
4.Dimension B1 does not include dambar protrusion/
infrusion.
A1
A2
B
0.010 / -
0.25 / -
3.81 / 4.06
0.41 / 0.56
1.22 / 1.37
0.20 / 0.36
- / 52.58
0.150 / 0.160
0.016 / 0.022
0.048 / 0.054
0.008 / 0.014
- / 2.070
B1
C
D
5.Controlling dimension is inch.
6.General appearance spec. should base on final
visualinspection spec.
E
14.99 / 15.49
13.72 / 14.02
2.29 / 2.79
3.05 / 3.56
0° / 15°
0.590 / 0.610
0.540 / 0.552
0.090 / 0.110
0.120 / 0.140
0° / 15°
E1
e1
L
£\
eA
S
0.630 / 0.670
/ 0.090
16.00 / 17.02
- / 2.29
Rev. 1.0 February 1998
14
MO SEL VITELIC
MSU2051/U2031
44L Plastic Leaded Chip Carrier (PLCC)
L
6
7
E
HE
GE
y
A2
A
D
A1
HD
C
b1
b
Dimension in Inch
minimal/maximal
- / 0.185
Dimension in mm
minimal/maximal
- / 4.70
e
Symbol
A
0
GD
A1
A2
b1
b
0.020 / -
0.51 / -
0.145 / 0.155
0.026 / 0.032
0.016 / 0.022
0.008 / 0.014
0.648 / 0.658
0.648 / 0.658
0.050 BSC
0.590 / 0.630
0.590 / 0.630
0.680 / 0.700
0.680 / 0.700
0.090 / 0.110
- / 0.004
3.68 / 3.94
0.66 / 0.81
0.41 / 0.56
0.20 / 0.36
16.46 / 16.71
16.46 / 16.71
1.27BSC
Note:
C
1.Dimension D & E does not include interlead flash.
2.Dimension b1 does not include dambar protrusion/
intrusion.
D
E
e
GD
GE
HD
HE
L
3.Controlling dimension:Inch
14.99 / 16.00
14.99 / 16.00
17.27 / 17.78
17.27 / 17.78
2.29 / 2.79
- / 0.10
4.General appreance spec. should base on final visual
inspection spec.
y
θ
/
/
Rev. 1.0 February 1998
15
MO SEL VITELIC
MSU2051/U2031
44L Plastic Quad Flat Package
C
L
L1
S
θ2
e
R1
D2 D1 D
Gage Plane
0.25 mm
b
A2
θ3
R2
A1
E2
E1
A
E
01
seating plane
C
θ
Dimension in Inch
minimal/maximal
- / 0.100
Dimension in mm
minimal/maximal
- / 2.55
Note:
Symbol
A
1.
2.
Dimension D1 and E1 do not include mold
protrustion. Allowance protrusion is 0.25mm per side.
Dimensions D1 and E1 do include mold mismatch
and are determined at datum plane.
Dimension b does not include dambar protrusion.
Allowance dambar protrusion shall be 0.08 mm total
in excess of the b dimension at maximum material
condition. Dambar cannot be located on the lower
radius or the lead foot.
0.006 / 0.014
0.071 / 0.087
0.012 / 0.018
0.004 / 0.009
0.520 BSC
0.394 BSC
0.315
A1
A2
b
0.15 / 0.35
1.80 / 2.20
0.30 / 0.45
0.09 / 0.20
13.20 BSC
10.00 BSC
8.00
c
D
D1
D2
E
0.520 BSC
0.394 BSC
0.315
13.20 BSC
10.00 BSC
8.00
E1
E2
e
0.031 BSC
0.029 / 0.041
0.063
0.80 BSC
0.73 / 1.03
1.60
L
L1
R1
R2
S
0.005 / -
0.13 / -
0.005 / 0.012
0.008 / -
0.13 / 0.30
0.20 / -
θ
0° / 7°
as left
θ1
θ2
θ3
C
0° / -
as left
10° REF
as left
7° REF
as left
0.004
0.10
Rev. 1.0 February 1998
16
MO SEL VITELIC
MSU2051/U2031
44L Low profile Quad Flat Package
C
L
L1
S
θ2
e
R1
D2 D1 D
Gage Plane
0.25 mm
b
A2
θ3
R2
A1
E2
E1
E
A
01
seating plane
C
θ
Dimension in Inch
minimal/maximal
Dimension in mm
minimal/maximal
- / 1.60
Note:
Symbol
A
1.
Dimension D1 and E1 do not include mold
protrustion. Allowance protrusion is 0.25mm per side.
D1 and E1 are maximal plastic body size dimensions
including mold mismatch.
- / 0.063
A1
A2
b
0.05 / 0.15
1.35 / 1.45
0.30 / 0.45
0.09 / 0.20
12.00 BSC
10.00 BSC
8.00
0.002 / 0.006
0.053 / 0.057
0.012 / 0.018
0.004 / 0.008
0.472 BSC
2. Dimension b does not include dambar protrusion.
Allowance dambar protrusion shall not cause the
lead width to exceed the maximal b dimension by
more than 0.08 mm.
c
D
D1
D2
E
0.393 BSC
0.315
0.472 BSC
0.393 BSC
0.315
12.00 BSC
10.00 BSC
8.00
3.
Dambar can not be located on the lower radius or the
foot. Minimal space between protrusion and an
adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm
pitch packages.
E1
E2
e
0.031 BSC
0.018 / 0.030
0.039 REF
0.003 / -
0.80 BSC
0.45 / 0.75
1.00 REF
0.08 / -
L
L1
R1
R2
S
0.003 / 0.008
0.08 / 0.20
0.20 / -
0.008 / -
0° / 7°
0° / -
θ
as left
θ1
θ2
θ3
C
as left
as left
11°/13°
/13°
11°
0.004
as left
0.10
Rev. 1.0 February 1998
17
MO SEL VITELIC
MSU2051/U2031
Bonding Information
PAD-NAME
Y-COORD
X-COORD
Y-COORD
ORDER
1
X-COORD
ORDER
23
24
PAD-NAME
1964
1964
1964
1964
1964
1721
1558
1399
1236
1077
914
1463
1623
1786
1945
2108
2281
2281
2281
2281
2281
2281
2281
2281
2281
2281
2038
1876
1716
1554
1393
1241
186
186
1080
921
758
599
436
186
186
186
186
186
186
186
186
186
186
255
418
577
839
1000
1151
1302
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
#PSEN
ALE
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
RES
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7
XTAL2
XTAL1
GND
GND
GND
2
3
4
5
25
26
27
186
186
186
270
432
6
7
28
29
8
9
30
31
32
592
754
10
11
12
13
14
15
16
17
18
19
20
21
22
914
33
34
1077
1236
1399
1558
1721
1964
1964
1964
1964
1964
1964
1964
#EA
754
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
VDD
VDD
35
36
37
592
432
270
38
39
186
186
40
41
42
186
186
186
43
186
Logo
27
37 36 35 34 33 32 31 30 29 28
38
26
25
24
23
22
21
20
19
18
17
16
39
40
41
MSU2051/U2031
42
2570 x 2250 (µm)
43
PAD SIZE : 96 x 96 (µm)
substrate should be bonded to Vss
(Gnd)
1
2
3
4
pid 251* 11/95
pid 251** 01/96
pid 251*** 03/96
pid 251**** 08/96
pid 251***** 10/96
pid 251A 11/96
pid 263* 11/97
pid 251B 01/98
5
6
7
8
9
10 11 12 13 14 15
Rev. 1.0 February 1998
18
MO SEL VITELIC
MSU2051/U2031
To: Mosel Vitelic Inc.
886-3-578-4732 (fax #)
Attn: Sales & Marketing Department
Product Request Form
We hereby request MVI to start producing MSU2051 which is specified below.
Please send us the product code and a hardcopy of data code as well as data code file duplicated on floppy
diskette. No further confirmation is necessary.
Production will start automatically once you receive our data code and verify that the checksum is match.
Mass Production of the captioned device shall be done in accordance with the purchase order(s) issued by
us or a company specified by us. All terms and conditions are based on the development agreement and/or
contract signed between MVI and us.
Data Code Descriptions
Code Length
IC descriptions
U2051S16, 16 MHz small current
Dice form
P type = 40L-PDIP
J type = 44L-PLCC
Q type = 44L-PQFP
L type = 44L-LQFP
U2051L16, 16 MHz low working voltage
U2051C16, 16 MHz
File Length
U2051C25, 25 MHz
File Name
Checksum
U2051C40, 40 MHz
h
Top Marking (fill only for packaged)
00h filled
Unused
Data Byte
Use MVI logo, date code and part number
Use my specifications as described below
FFh filled
HEX format
Format
Media
Specify below fields only for customer top marking
Binary code format
EPROM
Date code location descriptions
Use regular date code as MVI's
Leave it as blank
8751 chip
use right side five letters
File on Floppy
E-mail file
Logo Specifications
Leave it blank
Use my specifications as attachment
Part number specified, less than 15 digits
Phone # :
Fax # :
Company Name :
Signature :
Name (Typed) :
Position Title :
Department, Section :
Signature Date :
Rev. 1.0 February 1998
19
MO SEL VITELIC
MSU2051/U2031
To: Mosel Vitelic Inc.
886-3-578-4732 (fax#)
Attn: Sales & Marketing Department
Logo Top Marking Request & spec.
We hereby request MVI to have our logo printed on top of the device package. Below is the
specification of our logo in 20:1 scale base. This logo diagram is clear enough and is able to be
shrunk directly to fit into available top marking area described on page.
Phone # :
Company Name :
Signature :
Fax # :
Name (Typed) :
Position Title :
Department, Section :
Signature Date :
Rev. 1.0 February 1998
20
MO SEL VITELIC WORLDWIDE OFFICES
MSU2051/U2031
U.S.A.
TAIWAN
JAPAN
GERMANY
(CONTINENTAL
EUROPE & ISRAEL )
71083 HERRENBERG
BENZSTR. 32
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
7F, NO. 102
WBG MARINE WEST 25F
6, NAKASE 2-CHOME
MIHAMA-KU, CHIBA-SHI
CHIBA 261-71
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
PHONE: 81-43-299-6000
FAX: 81-43-299-6555
HONG KONG
19 DAI FU STREET
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 852-2665-4883
FAX: 852-2664-7535
1 CREATION ROAD I
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-578-3344
FAX: 886-3-579-2838
IRELAND & UK
BLOCK A UNIT 2
BROOMFIELD BUSINESS PARK
MALAHIDE
CO. DUBLIN, IRELAND
PHONE: +353 1 8038020
FAX: +353 1 8038049
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
SOUTHWESTERN
SUITE 200
5150 E. PACIFIC COAST HWY.
LONG BEACH, CA 90804
PHONE: 562-498-3314
FAX: 562-597-2174
CENTRAL & SOUTHEASTERN
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 972-690-1402
FAX: 972-690-0341
NORTHEASTERN
SUITE 436
20 TRAFALGAR SQUARE
NASHUA, NH 03063
PHONE: 603-889-4393
FAX: 603-889-9347
1/98
Printed in U.S.A.
© Copyright 1998, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MO SEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明