DSP56309UM [MOTOROLA]
24-Bit Digital Signal Processor; 24位数字信号处理器
| 型号： | DSP56309UM |
| 厂家： | 
MOTOROLA |
| 描述： | 24-Bit Digital Signal Processor |
| 文件： | 总424页 (文件大小：4157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
DSP56309 OVERVIEW
SIGNAL/CONNECTION DESCRIPTIONS
MEMORY CONFIGURATION
CORE CONFIGURATION
1
2
3
4
GENERAL PURPOSE I/O
HOST INTERFACE (HI08)
ENHANCED SYNCHRONOUS SERIAL INTERFACE
SERIAL COMMUNICATION INTERFACE (SCI)
TIMER MODULE
5
6
7
8
9
ON-CHIP EMULATION MODULE
JTAG PORT
10
11
A
B
C
D
I
BOOTSTRAP PROGRAM
EQUATES
BSDL LISTING
PROGRAMMING REFERENCE
INDEX
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1
2
DSP56309 OVERVIEW
SIGNAL/CONNECTION DESCRIPTIONS
MEMORY CONFIGURATION
CORE CONFIGURATION
GENERAL PURPOSE I/O
HOST INTERFACE (HI08)
ENHANCED SYNCHRONOUS SERIAL INTERFACE
SERIAL COMMUNICATION INTERFACE (SCI)
TIMER MODULE
3
4
5
6
7
8
9
10
11
A
B
C
D
I
ON-CHIP EMULATION MODULE
JTAG PORT
BOOTSTRAP PROGRAM
EQUATES
BSDL LISTING
PROGRAMMING REFERENCE
INDEX
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Rev. 0
DSP56309
24-Bit Digital Signal Processor
UserÕs Manual
Motorola, Incorporated
Semiconductor Products Sector
DSP Division
6501 William Cannon Drive West
Austin, TX 78735-8598
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This document (and other documents) can be viewed on the World Wide
Web at http://www.mot.com/SPS/DSP/documentation/
This manual is one of a set of three documents. You need the following
manuals to have complete product information: Family Manual, UserÕs
Manual, and Technical Data.
ä
OnCE is a trademark of Motorola, Inc.
Ò
Intel is a registered trademark of the Intel Corporation.
All other trademarks are those of their respective owners.
ã MOTOROLA INC., 1998
ÒReg. U.S. Pat. & Tm. Off.
Order this document by DSP56309UM/D
Motorola reserves the right to make changes without further notice to any products
herein to improve reliability, function, or design. Motorola does not assume any
liability arising out of the application or use of any product or circuit described
herein; neither does it convey any license under its patent rights nor the rights of
others. Motorola products are not authorized for use as components in life support
devices or systems intended for surgical implant into the body or intended to
support or sustain life. Buyer agrees to notify Motorola of any such intended end use
whereupon Motorola shall determine availability and suitability of its product or
products for the use intended. Motorola and
are registered trademarks of
Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity /Affirmative
Action Employer.
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TABLE OF CONTENTS
SECTION 1
DSP56309 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
1.2
1.3
1.4
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
MANUAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
MANUAL CONVENTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
DSP56309 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
DSP56309 CORE DESCRIPTION. . . . . . . . . . . . . . . . . . . . . 1-7
General Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Hardware Debugging Support . . . . . . . . . . . . . . . . . . . . . . 1-7
Reduced Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . 1-7
DSP56300 CORE FUNCTIONAL BLOCKS. . . . . . . . . . . . . . 1-8
Data ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Data ALU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Multiplier-Accumulator (MAC) . . . . . . . . . . . . . . . . . . . . 1-9
Address Generation Unit (AGU) . . . . . . . . . . . . . . . . . . . . 1-9
Program Control Unit (PCU) . . . . . . . . . . . . . . . . . . . . . . 1-10
PLL and Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
JTAG TAP and OnCE Module. . . . . . . . . . . . . . . . . . . . . 1-11
On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Off-Chip Memory Expansion . . . . . . . . . . . . . . . . . . . . . . 1-12
INTERNAL BUSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
DSP56309 BLOCK DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . 1-14
DIRECT MEMORY ACCESS (DMA) . . . . . . . . . . . . . . . . . . 1-15
DSP56309 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . 1-15
GPIO Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Host Interface (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Enhanced Synchronous Serial Interface (ESSI) . . . . . . . 1-16
Serial Communications Interface (SCI) . . . . . . . . . . . . . . 1-16
Timer Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.5
1.5.1
1.5.2
1.5.3
1.6
1.6.1
1.6.1.1
1.6.1.2
1.6.2
1.6.3
1.6.4
1.6.5
1.6.6
1.6.7
1.7
1.8
1.9
1.10
1.10.1
1.10.2
1.10.3
1.10.4
1.10.5
SECTION 2
SIGNAL/CONNECTION DESCRIPTIONS. . . . . . . . 2-1
2.1
SIGNAL GROUPINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2
POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
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2.3
2.4
2.5
2.6
2.6.1
2.6.2
2.6.3
2.7
GROUND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
PHASE-LOCKED LOOP (PLL) . . . . . . . . . . . . . . . . . . . . . . . 2-8
EXTERNAL MEMORY EXPANSION PORT (PORT A). . . . . 2-9
External Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
External Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
External Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
INTERRUPT AND MODE CONTROL . . . . . . . . . . . . . . . . . 2-14
HOST INTERFACE (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Host Port Usage Considerations. . . . . . . . . . . . . . . . . . . 2-16
Host Port Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
ENHANCED SYNCHRONOUS SERIAL INTERFACE . . . . 2-24
ESSI0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
ESSI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
SERIAL COMMUNICATION INTERFACE (SCI). . . . . . . . . 2-32
TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
ONCE/JTAG INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2.8
2.8.1
2.8.2
2.9
2.9.1
2.9.2
2.10
2.11
2.12
SECTION 3
MEMORY CONFIGURATION . . . . . . . . . . . . . . . . . 3-1
3.1
MEMORY SPACES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Program Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Data Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
X Data Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Y Data Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Memory Space Configuration . . . . . . . . . . . . . . . . . . . . . . 3-5
RAM CONFIGURATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
On-Chip Program Memory (Program RAM) . . . . . . . . . . . 3-6
On-Chip X Data Memory (X Data RAM) . . . . . . . . . . . . . . 3-6
On-Chip Y Data Memory (Y Data RAM) . . . . . . . . . . . . . . 3-7
Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
MEMORY CONFIGURATIONS. . . . . . . . . . . . . . . . . . . . . . . 3-7
Memory Space Configurations . . . . . . . . . . . . . . . . . . . . . 3-7
RAM Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
MEMORY MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
INTERNAL I/O MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . 3-18
3.1.1
3.1.2
3.1.2.1
3.1.2.2
3.1.3
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.3
3.3.1
3.3.2
3.4
3.5
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SECTION 4
CORE CONFIGURATION . . . . . . . . . . . . . . . . . . . . 4-1
4.1
4.2
4.3
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
BOOTSTRAP PROGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Mode 0: Expanded Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Modes 1 to 7: Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Mode 8: Expanded Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Mode 9: Boot from Byte-Wide External Memory . . . . . . . . 4-7
Mode A: Boot from SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Mode B: Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Modes C, D, E, F: Boot from HI08. . . . . . . . . . . . . . . . . . . 4-8
Mode C: In ISA/DSP5630X Mode (8-Bit Bus) . . . . . . . 4-8
Mode D: In HC11 Non-multiplexed Mode . . . . . . . . . . 4-8
Mode E: In 8051 Multiplexed Bus Mode . . . . . . . . . . . 4-9
Mode F: In 68302/68360 Bus Mode . . . . . . . . . . . . . . . 4-9
INTERRUPT SOURCES AND PRIORITIES . . . . . . . . . . . . . 4-9
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Interrupt Priority Levels . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Interrupt Source Priorities Within an IPL . . . . . . . . . . . . . 4-14
DMA REQUEST SOURCES . . . . . . . . . . . . . . . . . . . . . . . . 4-16
OPERATING MODE REGISTER (OMR) . . . . . . . . . . . . . . . 4-17
PLL CONTROL REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . 4-18
PCTL PLL Multiplication Factor Bits 0Ð11 . . . . . . . . . . . . 4-18
PCTL XTAL Disable Bit (XTLD) Bit 16. . . . . . . . . . . . . . . 4-18
PCTL Predivider Factor Bits (PD0ÐPD3) Bits 20Ð23. . . . 4-18
DEVICE IDENTIFICATION REGISTER (IDR) . . . . . . . . . . . 4-18
AA CONTROL REGISTERS (AAR0ÐAAR3) . . . . . . . . . . . . 4-19
JTAG BOUNDARY SCAN REGISTER (BSR) . . . . . . . . . . . 4-20
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.7.1
4.3.7.2
4.3.7.3
4.3.7.4
4.4
4.4.1
4.4.2
4.4.3
4.5
4.6
4.7
4.7.1
4.7.2
4.7.3
4.8
4.9
4.10
SECTION 5
GENERAL-PURPOSE I/O . . . . . . . . . . . . . . . . . . . . 5-1
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Port B Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-3
Port C Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-3
Port D Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-4
Port E Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-4
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5.2.5
Triple Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
SECTION 6
HOST INTERFACE (HI08) . . . . . . . . . . . . . . . . . . . 6-1
6.1
6.2
6.2.1
6.2.2
6.3
6.4
6.5
6.5.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
HI08 FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Host to DSP Core Interface. . . . . . . . . . . . . . . . . . . . . . . . 6-3
HI08-to-Host Processor Interface . . . . . . . . . . . . . . . . . . . 6-4
HI08 HOST PORT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . 6-6
HI08 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
HI08 DSP SIDE PROGRAMMERÕS MODEL. . . . . . . . . . . . . 6-8
Host Receive Data Register (HRX). . . . . . . . . . . . . . . . . . 6-8
Host Transmit Data Register (HTX) . . . . . . . . . . . . . . . . . 6-9
Host Control Register (HCR). . . . . . . . . . . . . . . . . . . . . . . 6-9
HCR Host Receive Interrupt Enable (HRIE) Bit 0 . . . 6-10
HCR Host Transmit Interrupt Enable (HTIE) Bit 1 . . . 6-10
HCR Host Command Interrupt Enable (HCIE) Bit 2. . 6-10
HCR Host Flags 2,3 (HF[3:2]) Bits 3, 4 . . . . . . . . . . . 6-10
HCR Reserved Bits 5-15 . . . . . . . . . . . . . . . . . . . . . . 6-10
Host Status Register (HSR) . . . . . . . . . . . . . . . . . . . . . . 6-11
HSR Host Receive Data Full (HRDF) Bit 0 . . . . . . . . 6-11
HSR Host Transmit Data Empty (HTDE) Bit 1 . . . . . . 6-11
HSR Host Command Pending (HCP) Bit 2 . . . . . . . . 6-11
HSR Host Flags 0, 1 (HF[1:0]) Bits 3, 4 . . . . . . . . . . . 6-11
HSR Reserved Bits 5-15 . . . . . . . . . . . . . . . . . . . . . . 6-11
Host Base Address Register (HBAR) . . . . . . . . . . . . . . . 6-12
HBAR Base Address (BA[10:3]) Bits 0-7 . . . . . . . . . . 6-12
HBAR Reserved Bits 8-15 . . . . . . . . . . . . . . . . . . . . . 6-12
Host Port Control Register (HPCR). . . . . . . . . . . . . . . . . 6-12
HPCR Host GPIO Port Enable (HGEN) Bit 0. . . . . . . 6-13
HPCR Host Address Line 8 Enable (HA8EN) Bit 1 . . 6-13
HPCR Host Address Line 9 Enable (HA9EN) Bit 2 . . 6-13
HPCR Host Chip Select Enable (HCSEN) Bit 3. . . . . 6-13
HPCR Host Request Enable (HREN) Bit 4 . . . . . . . . 6-14
HPCR Host Acknowledge Enable (HAEN) Bit 5. . . . . 6-14
HPCR Host Enable (HEN) Bit 6 . . . . . . . . . . . . . . . . . 6-14
HPCR Reserved Bit 7. . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.5.2
6.5.3
6.5.3.1
6.5.3.2
6.5.3.3
6.5.3.4
6.5.3.5
6.5.4
6.5.4.1
6.5.4.2
6.5.4.3
6.5.4.4
6.5.4.5
6.5.5
6.5.5.1
6.5.5.2
6.5.6
6.5.6.1
6.5.6.2
6.5.6.3
6.5.6.4
6.5.6.5
6.5.6.6
6.5.6.7
6.5.6.8
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6.5.6.9
6.5.6.10
6.5.6.11
6.5.6.12
6.5.6.13
6.5.6.14
6.5.6.15
6.5.6.16
6.5.7
6.5.8
6.5.9
6.5.10
6.6
6.6.1
6.6.1.1
6.6.1.2
6.6.1.3
6.6.1.4
6.6.1.5
6.6.1.6
6.6.1.7
6.6.1.8
6.6.2
HPCR Host Request Open Drain (HROD) Bit 8 . . . . . 6-14
HPCR Host Data Strobe Polarity (HDSP) Bit 9. . . . . . 6-14
HPCR Host Address Strobe Polarity (HASP) Bit 10 . . 6-15
HPCR Host Multiplexed Bus (HMUX) Bit 11. . . . . . . . 6-15
HPCR Host Dual Data Strobe (HDDS) Bit 12 . . . . . . . 6-15
HPCR Host Chip Select Polarity (HCSP) Bit 13 . . . . . 6-16
HPCR Host Request Polarity (HRP) Bit 14. . . . . . . . . 6-16
HPCR Host Acknowledge Polarity (HAP) Bit 15 . . . . . 6-16
Host Data Direction Register (HDDR) . . . . . . . . . . . . . . . 6-17
Host Data Register (HDR) . . . . . . . . . . . . . . . . . . . . . . . . 6-17
DSP Side Registers After Reset . . . . . . . . . . . . . . . . . . . 6-18
Host Interface DSP Core Interrupts. . . . . . . . . . . . . . . . . 6-19
HI08-EXTERNAL HOST PROGRAMMERÕS MODEL . . . . . 6-20
Interface Control Register (ICR) . . . . . . . . . . . . . . . . . . . 6-22
ICR Receive Request Enable (RREQ) Bit 0 . . . . . . . . 6-23
ICR Transmit Request Enable (TREQ) Bit 1. . . . . . . . 6-23
ICR Double Host Request (HDRQ) Bit 2. . . . . . . . . . . 6-23
ICR Host Flag 0 (HF0) Bit 3 . . . . . . . . . . . . . . . . . . . . 6-24
ICR Host Flag 1 (HF1) Bit 4 . . . . . . . . . . . . . . . . . . . . 6-24
ICR Host Little Endian (HLEND) Bit 5. . . . . . . . . . . . . 6-24
ICR Reserved Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
ICR Initialize Bit (INIT) Bit 7 . . . . . . . . . . . . . . . . . . . . 6-24
Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . 6-25
CVR Host Vector (HV[6:0]) Bits 0Ð6 . . . . . . . . . . . . . . 6-25
CVR Host Command Bit (HC) Bit 7. . . . . . . . . . . . . . . 6-26
Interface Status Register (ISR) . . . . . . . . . . . . . . . . . . . . 6-26
ISR Receive Data Register Full (RXDF) Bit 0. . . . . . . 6-26
ISR Transmit Data Register Empty (TXDE) Bit 1 . . . . 6-27
ISR Transmitter Ready (TRDY) Bit 2 . . . . . . . . . . . . . 6-27
ISR Host Flag 2 (HF2) Bit 3 . . . . . . . . . . . . . . . . . . . . 6-27
ISR Host Flag 3 (HF3) Bit 4 . . . . . . . . . . . . . . . . . . . . 6-27
ISR Reserved Bits 5, 6 . . . . . . . . . . . . . . . . . . . . . . . . 6-27
ISR Host Request (HREQ) Bit 7 . . . . . . . . . . . . . . . . . 6-27
Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . . . . 6-28
Receive Byte Registers (RXH: RXM: RXL) . . . . . . . . . . . 6-28
Transmit Byte Registers (TXH:TXM:TXL) . . . . . . . . . . . . 6-29
6.6.2.1
6.6.2.2
6.6.3
6.6.3.1
6.6.3.2
6.6.3.3
6.6.3.4
6.6.3.5
6.6.3.6
6.6.3.7
6.6.4
6.6.5
6.6.6
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6.6.7
6.6.8
6.7
6.7.1
6.7.2
6.7.3
6.8
Host Side Registers After Reset . . . . . . . . . . . . . . . . . . . 6-30
General-Purpose I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
SERVICING THE HOST INTERFACE . . . . . . . . . . . . . . . . 6-31
HI08 Host Processor Data Transfer . . . . . . . . . . . . . . . . 6-31
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
Servicing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
HI08 PROGRAMMING MODEL QUICK REFERENCE. . . . 6-34
SECTION 7
ENHANCEDSYNCHRONOUSSERIALINTERFACE(ESSI)
7-1
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
ENHANCEMENTS TO THE ESSI . . . . . . . . . . . . . . . . . . . . . 7-3
ESSI DATA AND CONTROL SIGNALS . . . . . . . . . . . . . . . . 7-4
Serial Transmit Data (STD) Signal . . . . . . . . . . . . . . . . . . 7-4
Serial Receive Data Signal (SRD) . . . . . . . . . . . . . . . . . . 7-4
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Serial Control Signal (SC0). . . . . . . . . . . . . . . . . . . . . . . . 7-6
Serial Control Signal (SC1). . . . . . . . . . . . . . . . . . . . . . . . 7-7
Serial Control Signal (SC2). . . . . . . . . . . . . . . . . . . . . . . . 7-8
ESSI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . 7-8
ESSI Control Register A (CRA). . . . . . . . . . . . . . . . . . . . 7-11
CRA Prescale Modulus Select PM[7:0] Bits 7Ð0 . . . . 7-11
CRA Reserved Bits 8Ð10 . . . . . . . . . . . . . . . . . . . . . . 7-11
CRA Prescaler Range (PSR) Bit 11. . . . . . . . . . . . . . 7-11
CRA Frame Rate Divider Control DC[4:0] Bits 16Ð12 7-12
CRA Reserved Bit 17 . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
CRA Alignment Control (ALC) Bit 18 . . . . . . . . . . . . . 7-13
CRA Word-length Control (WL[2:0]) Bits 21Ð19. . . . . 7-14
CRA Select SC1 (SSC1) Bit 22 . . . . . . . . . . . . . . . . . 7-14
CRA Reserved Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
ESSI Control Register B (CRB). . . . . . . . . . . . . . . . . . . . 7-15
CRB Serial Output Flags (OF0, OF1) Bits 0, 1. . . . . . 7-15
CRB Serial Output Flag 0 (OF0) Bit 0 . . . . . . . . . . 7-15
CRB Serial Output Flag 1 (OF1) Bit 1 . . . . . . . . . . 7-16
CRB Serial Control Direction 0 (SCD0) Bit 2 . . . . . . . 7-16
CRB Serial Control Direction 1 (SCD1) Bit 3 . . . . . . . 7-16
7.3.6
7.4
7.4.1
7.4.1.1
7.4.1.2
7.4.1.3
7.4.1.4
7.4.1.5
7.4.1.6
7.4.1.7
7.4.1.8
7.4.1.9
7.4.2
7.4.2.1
7.4.2.1.1
7.4.2.1.2
7.4.2.2
7.4.2.3
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7.4.2.4
7.4.2.5
7.4.2.6
7.4.2.7
7.4.2.8
7.4.2.9
7.4.2.10
7.4.2.11
7.4.2.12
7.4.2.13
7.4.2.14
7.4.2.15
7.4.2.16
7.4.2.17
7.4.2.18
7.4.2.19
7.4.2.20
7.4.2.21
7.4.2.22
7.4.2.23
7.4.3
7.4.3.1
7.4.3.2
7.4.3.3
7.4.3.4
7.4.3.5
7.4.3.6
7.4.3.7
7.4.3.8
7.4.4
CRB Serial Control Direction 2 (SCD2) Bit 4 . . . . . . . 7-16
CRB Clock Source Direction (SCKD) Bit 5 . . . . . . . . . 7-16
CRB Shift Direction (SHFD) Bit 6 . . . . . . . . . . . . . . . . 7-17
CRB Frame Sync Length FSL[1:0] Bits 7 and 8 . . . . . 7-17
CRB Frame Sync Relative Timing (FSR) Bit 9 . . . . . . 7-17
CRB Frame Sync Polarity (FSP) Bit 10. . . . . . . . . . . . 7-17
CRB Clock Polarity (CKP) Bit 11. . . . . . . . . . . . . . . . . 7-18
CRB Synchronous /Asynchronous (SYN) Bit 12. . . . . 7-18
CRB ESSI Mode Select (MOD) Bit 13 . . . . . . . . . . . . 7-20
Enabling, Disabling ESSI Data Transmission . . . . . . . 7-22
CRB ESSI Transmit 2 Enable (TE2) Bit 14. . . . . . . . . 7-22
CRB ESSI Transmit 1 Enable (TE1) Bit 15. . . . . . . . . 7-23
CRB ESSI Transmit 0 Enable (TE0) Bit 16. . . . . . . . . 7-24
CRB ESSI Receive Enable (RE) Bit 17. . . . . . . . . . . . 7-26
CRB ESSI Transmit Interrupt Enable (TIE) Bit 18. . . . 7-26
CRB ESSI Receive Interrupt Enable (RIE) Bit 19 . . . . 7-26
Transmit Last Slot Interrupt Enable (TLIE) Bit 20 . . . . 7-26
Receive Last Slot Interrupt Enable (RLIE) Bit 21 . . . . 7-27
Transmit Exception Interrupt Enable (TEIE) Bit 22 . . . 7-27
Receive Exception Interrupt Enable (REIE) Bit 23 . . . 7-27
ESSI Status Register (SSISR). . . . . . . . . . . . . . . . . . . . . 7-27
SSISR Serial Input Flag 0 (IF0) Bit 0 . . . . . . . . . . . . . 7-28
SSISR Serial Input Flag 1 (IF1) Bit 1 . . . . . . . . . . . . . 7-28
SSISR Transmit Frame Sync Flag (TFS) Bit 2 . . . . . . 7-28
SSISR Receive Frame Sync Flag (RFS) Bit 3 . . . . . . 7-28
SSISR Transmitter Underrun Error Flag (TUE) Bit 4 . 7-29
SSISR Receiver Overrun Error Flag (ROE) Bit 5 . . . . 7-29
ESSI Transmit Data Register Empty (TDE) Bit 6 . . . . 7-29
ESSI Receive Data Register Full (RDF) Bit 7 . . . . . . . 7-30
ESSI Receive Shift Register . . . . . . . . . . . . . . . . . . . . . . 7-33
ESSI Receive Data Register (RX) . . . . . . . . . . . . . . . . . . 7-33
ESSI Transmit Shift Registers . . . . . . . . . . . . . . . . . . . . . 7-33
ESSI Transmit Data Registers (TX0-2) . . . . . . . . . . . . . . 7-34
ESSI Time Slot Register (TSR) . . . . . . . . . . . . . . . . . . . . 7-34
Transmit Slot Mask Registers (TSMA, TSMB) . . . . . . . . 7-34
Receive Slot Mask Registers (RSMA, RSMB). . . . . . . . . 7-35
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
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7.5
7.5.1
7.5.2
7.5.3
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
ESSI After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
ESSI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
ESSI Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
Operating Modes: Normal, Network, and On-Demand . . 7-40
Normal/Network/On-Demand Mode Selection . . . . . . 7-40
Synchronous/Asynchronous Operating Modes . . . . . 7-40
Frame Sync Selection . . . . . . . . . . . . . . . . . . . . . . . . 7-41
Frame Sync Signal Format . . . . . . . . . . . . . . . . . . 7-41
Frame Sync Length for Multiple Devices. . . . . . . . 7-41
Word-Length Frame Sync and Data-Word Timing 7-41
Frame Sync Polarity . . . . . . . . . . . . . . . . . . . . . . . 7-42
Byte Format (LSB/MSB) for the Transmitter . . . . . . . 7-42
Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42
GPIO SIGNALS AND REGISTERS. . . . . . . . . . . . . . . . . . . 7-43
Port Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . 7-43
Port Direction Register (PRR). . . . . . . . . . . . . . . . . . . . . 7-44
Port Data Register (PDR) . . . . . . . . . . . . . . . . . . . . . . . . 7-45
7.5.4
7.5.4.1
7.5.4.2
7.5.4.3
7.5.4.3.1
7.5.4.3.2
7.5.4.3.3
7.5.4.3.4
7.5.4.4
7.5.5
7.6
7.6.1
7.6.2
7.6.3
SECTION 8
SERIAL COMMUNICATION INTERFACE (SCI) . . 8-1
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.1.1
8.3.1.2
8.3.1.3
8.3.1.4
8.3.1.5
8.3.1.6
8.3.1.7
8.3.1.8
8.3.1.9
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
SCI I/O SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Receive Data (RXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Transmit Data (TXD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
SCI Serial Clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
SCI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . 8-4
SCI Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . 8-8
SCR Word Select (WDS[0:2]) Bits 0Ð2 . . . . . . . . . . . . 8-8
SCR SCI Shift Direction (SSFTD) Bit 3 . . . . . . . . . . . . 8-9
SCR Send Break (SBK) Bit 4 . . . . . . . . . . . . . . . . . . . . 8-9
SCR Wakeup Mode Select (WAKE) Bit 5 . . . . . . . . . . 8-9
SCR Receiver Wakeup Enable (RWU) Bit 6 . . . . . . . . 8-9
SCR Wired-OR Mode Select (WOMS) Bit 7. . . . . . . . 8-10
SCR Receiver Enable (RE) Bit 8 . . . . . . . . . . . . . . . . 8-10
SCR Transmitter Enable (TE) Bit 9 . . . . . . . . . . . . . . 8-10
SCR Idle Line Interrupt Enable (ILIE) Bit 10. . . . . . . . 8-11
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8.3.1.10
8.3.1.11
8.3.1.12
8.3.1.13
8.3.1.14
8.3.1.15
8.3.2
8.3.2.1
8.3.2.2
8.3.2.3
8.3.2.4
8.3.2.5
8.3.2.6
8.3.2.7
8.3.2.8
8.3.3
8.3.3.1
8.3.3.2
8.3.3.3
8.3.3.4
8.3.3.5
8.3.4
8.3.4.1
8.3.4.2
8.4
SCR SCI Receive Interrupt Enable (RIE) Bit 11 . . . . . 8-11
SCR SCI Transmit Interrupt Enable (TIE) Bit 12. . . . . 8-12
SCR Timer Interrupt Enable (TMIE) Bit 13 . . . . . . . . . 8-12
SCR Timer Interrupt Rate (STIR) Bit 14 . . . . . . . . . . . 8-12
SCR SCI Clock Polarity (SCKP) Bit 15 . . . . . . . . . . . . 8-12
Receive with Exception Interrupt Enable (REIE) Bit 168-13
SCI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . 8-13
SSR Transmitter Empty (TRNE) Bit 0. . . . . . . . . . . . . 8-13
SSR Transmit Data Register Empty (TDRE) Bit 1 . . . 8-13
SSR Receive Data Register Full (RDRF) Bit 2 . . . . . . 8-14
SSR Idle Line Flag (IDLE) Bit 3. . . . . . . . . . . . . . . . . . 8-14
SSR Overrun Error Flag (OR) Bit 4. . . . . . . . . . . . . . . 8-14
SSR Parity Error (PE) Bit 5 . . . . . . . . . . . . . . . . . . . . . 8-14
SSR Framing Error Flag (FE) Bit 6 . . . . . . . . . . . . . . . 8-15
SSR Received Bit 8 (R8) Address Bit 7 . . . . . . . . . . . 8-15
SCI Clock Control Register (SCCR) . . . . . . . . . . . . . . . . 8-15
SCCR Clock Divider (CD[11:0]) Bits 11Ð0 . . . . . . . . . 8-16
SCCR Clock Out Divider (COD) Bit 12 . . . . . . . . . . . . 8-16
SCCR SCI Clock Prescaler (SCP) Bit 13 . . . . . . . . . . 8-17
SCCR Receive Clock Mode Source (RCM) Bit 14 . . . 8-17
SCCR Transmit Clock Source Bit (TCM) Bit 15 . . . . . 8-18
SCI Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
SCI Receive Registers (SRX) . . . . . . . . . . . . . . . . . . . 8-19
SCI Transmit Registers. . . . . . . . . . . . . . . . . . . . . . . . 8-20
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
SCI After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
SCI Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
SCI Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . 8-25
Preamble, Break, and Data Transmission Priority. . . . . . 8-26
SCI Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
GPIO SIGNALS AND REGISTERS . . . . . . . . . . . . . . . . . . . 8-27
Port E Control Register (PCRE) . . . . . . . . . . . . . . . . . . . 8-27
Port E Direction Register (PRRE) . . . . . . . . . . . . . . . . . . 8-27
Port E Data Register (PDRE) . . . . . . . . . . . . . . . . . . . . . 8-28
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.5
8.5.1
8.5.2
8.5.3
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SECTION 9
TRIPLE TIMER MODULE . . . . . . . . . . . . . . . . . . . . 9-1
9.1
9.2
9.2.1
9.2.2
9.3
9.3.1
9.3.2
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
TRIPLE TIMER MODULE ARCHITECTURE . . . . . . . . . . . . 9-3
Triple Timer Module Block Diagram . . . . . . . . . . . . . . . . . 9-3
Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
TRIPLE TIMER MODULE PROGRAMMING MODEL. . . . . . 9-5
Prescaler Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Timer Prescaler Load Register (TPLR). . . . . . . . . . . . . . . 9-7
TPLR Prescaler Preload Value (PL[20:0]) Bits 20-0 . . 9-7
TPLR Prescaler Source (PS[1:0]) Bits 22-21 . . . . . . . . 9-7
TPLR Reserved Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
Timer Prescaler Count Register (TPCR). . . . . . . . . . . . . . 9-8
TPCR Prescaler Counter Value (PC[20:0]) Bits 20-0. . 9-9
TPCR Reserved Bits 23-21 . . . . . . . . . . . . . . . . . . . . . 9-9
Timer Control/Status Register (TCSR) . . . . . . . . . . . . . . . 9-9
Timer Enable (TE) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . 9-9
Timer Overflow Interrupt Enable (TOIE) Bit 1 . . . . . . . 9-9
Timer Compare Interrupt Enable (TCIE) Bit 2 . . . . . . 9-10
Timer Control (TC[3:0]) Bits 4-7 . . . . . . . . . . . . . . . . . 9-10
Inverter (INV) Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
Timer Reload Mode (TRM) Bit 9 . . . . . . . . . . . . . . . . 9-13
Direction (DIR) Bit 11 . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Data Input (DI) Bit 12 . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Data Output (DO) Bit 13. . . . . . . . . . . . . . . . . . . . . . . 9-14
Prescaler Clock Enable (PCE) Bit 15. . . . . . . . . . . . . 9-14
Timer Overflow Flag (TOF) Bit 20 . . . . . . . . . . . . . . . 9-14
Timer Compare Flag (TCF) Bit 21 . . . . . . . . . . . . . . . 9-15
TCSR Reserved Bits 3, 10, 14, 16-19, 22, 23 . . . . . . 9-15
Timer Load Register (TLR) . . . . . . . . . . . . . . . . . . . . . . . 9-15
Timer Compare Register (TCPR) . . . . . . . . . . . . . . . . . . 9-16
Timer Count Register (TCR) . . . . . . . . . . . . . . . . . . . . . . 9-16
TIMER OPERATIONAL MODES. . . . . . . . . . . . . . . . . . . . . 9-16
Timing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
Timer GPIO (Mode 0). . . . . . . . . . . . . . . . . . . . . . . . . 9-17
Timer Pulse (Mode 1). . . . . . . . . . . . . . . . . . . . . . . . . 9-18
Timer Toggle (Mode 2). . . . . . . . . . . . . . . . . . . . . . . . 9-19
9.3.2.1
9.3.2.2
9.3.2.3
9.3.3
9.3.3.1
9.3.3.2
9.3.4
9.3.4.1
9.3.4.2
9.3.4.3
9.3.4.4
9.3.4.5
9.3.4.6
9.3.4.7
9.3.4.8
9.3.4.9
9.3.4.10
9.3.4.11
9.3.4.12
9.3.4.13
9.3.5
9.3.6
9.3.7
9.4
9.4.1
9.4.1.1
9.4.1.2
9.4.1.3
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9.4.1.4
9.4.2
Timer Event Counter (Mode 3) . . . . . . . . . . . . . . . . . . 9-20
Signal Measurement Modes . . . . . . . . . . . . . . . . . . . . . . 9-20
Measurement Accuracy . . . . . . . . . . . . . . . . . . . . . . . 9-21
Measurement Input Width (Mode 4) . . . . . . . . . . . . . . 9-21
Measurement Input Period (Mode 5) . . . . . . . . . . . . . 9-22
Measurement Capture (Mode 6). . . . . . . . . . . . . . . . . 9-23
Pulse Width Modulation (PWM, Mode 7). . . . . . . . . . . . . 9-24
Watchdog Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
Watchdog Pulse (Mode 9). . . . . . . . . . . . . . . . . . . . . . 9-25
Watchdog Toggle (Mode 10). . . . . . . . . . . . . . . . . . . . 9-26
Reserved Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
Timer Behavior during Wait. . . . . . . . . . . . . . . . . . . . . 9-27
Timer Behavior during Stop . . . . . . . . . . . . . . . . . . . . 9-27
DMA Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
9.4.2.1
9.4.2.2
9.4.2.3
9.4.2.4
9.4.3
9.4.4
9.4.4.1
9.4.4.2
9.4.5
9.4.6
9.4.6.1
9.4.6.2
9.4.7
SECTION 10 ON-CHIP EMULATION MODULE . . . . . . . . . . . . . 10-1
10.1
10.2
10.3
10.4
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
ONCE MODULE SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
DEBUG EVENT (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
ONCE CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
OnCE Command Register (OCR) . . . . . . . . . . . . . . . . . . 10-5
Register Select (RS4ÐRS0) Bits 0Ð4 . . . . . . . . . . . . . 10-5
Exit Command (EX) Bit 5 . . . . . . . . . . . . . . . . . . . . . . 10-5
GO Command (GO) Bit 6 . . . . . . . . . . . . . . . . . . . . . . 10-6
Read/Write Command (R/W) Bit 7 . . . . . . . . . . . . . . . 10-6
OnCE Decoder (ODEC). . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
OnCE Status and Control Register (OSCR) . . . . . . . . . . 10-8
Trace Mode Enable (TME) Bit 0 . . . . . . . . . . . . . . . . . 10-8
Interrupt Mode Enable (IME) Bit 1. . . . . . . . . . . . . . . . 10-8
Software Debug Occurrence (SWO) Bit 2. . . . . . . . . . 10-8
Memory Breakpoint Occurrence (MBO) Bit 3 . . . . . . . 10-8
Trace Occurrence (TO) Bit 4. . . . . . . . . . . . . . . . . . . . 10-9
Reserved OCSR Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Core Status (OS0, OS1) Bits 6-7 . . . . . . . . . . . . . . . . 10-9
Reserved Bits 8-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.1
10.4.1.1
10.4.1.2
10.4.1.3
10.4.1.4
10.4.2
10.4.3
10.4.3.1
10.4.3.2
10.4.3.3
10.4.3.4
10.4.3.5
10.4.3.6
10.4.3.7
10.4.3.8
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10.5
ONCE MEMORY BREAKPOINT LOGIC. . . . . . . . . . . . . . . 10-9
OnCE Memory Address Latch (OMAL). . . . . . . . . . . . . 10-11
OnCE Memory Limit Register 0 (OMLR0). . . . . . . . . . . 10-11
OnCE Memory Address Comparator 0 (OMAC0). . . . . 10-11
OnCE Memory Limit Register 1 (OMLR1). . . . . . . . . . . 10-11
OnCE Memory Address Comparator 1 (OMAC1). . . . . 10-11
OnCE Breakpoint Control Register (OBCR) . . . . . . . . . 10-12
Memory Breakpoint Select (MBS0ÐMBS1) . . . . . . . 10-12
Breakpoint 0 Read/Write Select (RW00ÐRW01) . . . 10-12
Breakpoint 0 Condition Code Select (CC00ÐCC01). 10-13
Breakpoint 1 Read/Write Select (RW10ÐRW11) . . . 10-13
Breakpoint 1 Condition Code Select (CC10ÐCC11). 10-14
Breakpoint 0 and 1 Event Select (BT0ÐBT1) . . . . . . 10-14
OnCE Memory Breakpoint Counter (OMBC) . . . . . . 10-14
Reserved Bits 12-15. . . . . . . . . . . . . . . . . . . . . . . . . 10-15
ONCE TRACE LOGIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
METHODS OF ENTERING DEBUG MODE . . . . . . . . . . . 10-16
External Debug Request During RESET Assertion . . . 10-16
External Debug Request During Normal Activity . . . . . 10-16
Executing the JTAG DEBUG_REQUEST Instruction . . 10-17
External Debug Request During Stop. . . . . . . . . . . . . . 10-17
External Debug Request During Wait . . . . . . . . . . . . . . 10-17
Software Request During Normal Activity. . . . . . . . . . . 10-18
Enabling Trace Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
Enabling Memory Breakpoints . . . . . . . . . . . . . . . . . . . 10-18
PIPELINE INFORMATION AND OGDB REGISTER. . . . . 10-18
OnCE PDB Register (OPDBR) . . . . . . . . . . . . . . . . . . . 10-19
OnCE PIL Register (OPILR) . . . . . . . . . . . . . . . . . . . . . 10-19
OnCE GDB Register (OGDBR). . . . . . . . . . . . . . . . . . . 10-20
DEBUGGING RESOURCES. . . . . . . . . . . . . . . . . . . . . . . 10-20
OnCE PAB Register for Fetch (OPABFR) . . . . . . . . . . 10-20
PAB Register for Decode (OPABDR) . . . . . . . . . . . . . . 10-20
OnCE PAB Register for Execute (OPABEX) . . . . . . . . 10-20
Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21
10.5.1
10.5.2
10.5.3
10.5.4
10.5.5
10.5.6
10.5.6.1
10.5.6.2
10.5.6.3
10.5.6.4
10.5.6.5
10.5.6.6
10.5.6.7
10.5.6.8
10.6
10.7
10.7.1
10.7.2
10.7.3
10.7.4
10.7.5
10.7.6
10.7.7
10.7.8
10.8
10.8.1
10.8.2
10.8.3
10.9
10.9.1
10.9.2
10.9.3
10.9.4
10.10 SERIAL PROTOCOL DESCRIPTION . . . . . . . . . . . . . . . . 10-22
10.11 TARGET SITE DEBUG SYSTEM REQUIREMENTS . . . . 10-23
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10.12 ONCE MODULE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . 10-23
10.12.1
10.12.2
10.12.3
10.12.4
10.12.5
10.12.6
10.12.7
10.12.8
Checking Whether the Chip Has Entered Debug Mode 10-24
Polling the JTAG Instruction Shift Register . . . . . . . . . . 10-24
Saving Pipeline Information. . . . . . . . . . . . . . . . . . . . . . 10-25
Reading the Trace Buffer. . . . . . . . . . . . . . . . . . . . . . . . 10-25
Displaying a Specified Register. . . . . . . . . . . . . . . . . . . 10-26
Displaying X Memory Area Starting at Address $xxxx . 10-26
Returning from Debug to Normal Mode (Same Program)10-28
Returning from Debug to Normal Mode (New Program)10-28
10.13 JTAG PORT/ONCE MODULE INTERACTION . . . . . . . . . 10-29
SECTION 11 JTAG PORT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1
11.2
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
JTAG SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Test Data Input (TDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Test Data Output (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
TAP CONTROLLER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Boundary Scan Register (BSR). . . . . . . . . . . . . . . . . . . . 11-7
Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
EXTEST (B[3:0] = 0000) . . . . . . . . . . . . . . . . . . . . . . . 11-8
SAMPLE/PRELOAD (B[3:0] = 0001). . . . . . . . . . . . . . 11-9
IDCODE (B[3:0] = 0010) . . . . . . . . . . . . . . . . . . . . . . . 11-9
CLAMP (B[3:0] = 0011). . . . . . . . . . . . . . . . . . . . . . . 11-10
HI-Z (B[3:0] = 0100) . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
ENABLE_ONCE(B[3:0] = 0110) . . . . . . . . . . . . . . . . 11-11
DEBUG_REQUEST(B[3:0] = 0111) . . . . . . . . . . . . . 11-11
BYPASS (B[3:0] = 1111) . . . . . . . . . . . . . . . . . . . . . 11-11
DSP56300 RESTRICTIONS . . . . . . . . . . . . . . . . . . . . . . . 11-12
DSP56309 BOUNDARY SCAN REGISTER . . . . . . . . . . . 11-13
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.3
11.3.1
11.3.2
11.3.2.1
11.3.2.2
11.3.2.3
11.3.2.4
11.3.2.5
11.3.2.6
11.3.2.7
11.3.2.8
11.4
11.5
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APPENDIX A BOOTSTRAP PROGRAMS . . . . . . . . . . . . . . . . . . A-1
APPENDIX B EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1
B.2
B.3
B.4
B.5
B.6
B.7
B.8
B.9
B.10
I/O EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
HOST INTERFACE (HI08) EQUATES . . . . . . . . . . . . . . . . . B-3
SCI EQUATES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
ESSI EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
EXCEPTION PROCESSING EQUATES . . . . . . . . . . . . . . . B-7
TIMER MODULE EQUATES . . . . . . . . . . . . . . . . . . . . . . . . B-9
DIRECT MEMORY ACCESS (DMA) EQUATES . . . . . . . . B-10
PHASE-LOCKED LOOP (PLL) EQUATES . . . . . . . . . . . . . B-12
BUS INTERFACE UNIT (BIU) EQUATES . . . . . . . . . . . . . B-13
INTERRUPT EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15
APPENDIX C DSP56309 BSDL LISTING . . . . . . . . . . . . . . . . . . . C-1
APPENDIX D PROGRAMMING REFERENCE . . . . . . . . . . . . . . . D-1
D.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3
Peripheral Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3
Interrupt Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3
Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3
Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3
INTERNAL I/O MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . D-4
INTERRUPT ADDRESSES AND SOURCES . . . . . . . . . . . D-11
INTERRUPT PRIORITIES. . . . . . . . . . . . . . . . . . . . . . . . . . D-13
D.1.1
D.1.2
D.1.3
D.1.4
D.2
D.3
D.4
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LIST OF FIGURES
Figure 1-1
Figure 2-1
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 6-1
Figure 6-2
Figure 6-3
DSP56309 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Signals Identified by Functional Group . . . . . . . . . . . . . . . . . . . . 2-4
Default Settings (0, 0, 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Instruction Cache Enabled (0, 0, 1). . . . . . . . . . . . . . . . . . . . . . 3-11
Switched Program RAM (0, 1, 0). . . . . . . . . . . . . . . . . . . . . . . . 3-12
Switched Program RAM and Instruction Cache Enabled (0, 1, 1)3-13
16-bit Space with Default RAM (1, 0, 0) . . . . . . . . . . . . . . . . . . 3-14
16-bit Space with Instruction Cache Enabled (1, 0, 1) . . . . . . . 3-15
16-bit Space with Switched Program RAM (1, 1, 0) . . . . . . . . . 3-16
16-bit Space, Switched Program RAM, Instruction Cache . . . . 3-17
Interrupt Priority Register C (IPR-C) (X:$FFFFFF) . . . . . . . . . . 4-13
Interrupt Priority Register P (IPR-P) (X:$FFFFFE) . . . . . . . . . . 4-13
DSP56309 Operating Mode Register (OMR) . . . . . . . . . . . . . . 4-17
PLL Control (PCTL) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Identification Register Configuration (Revision 0) . . . . . . . . . . . 4-19
Address Attribute Registers (AAR0ÐAAR3). . . . . . . . . . . . . . . . 4-20
HI08 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Host Control Register (HCR) (X:$FFFFC2). . . . . . . . . . . . . . . . . 6-9
Host Status Register (HSR) (X:$FFFFC3) . . . . . . . . . . . . . . . . 6-11
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Figure 6-4
Figure 6-5
Figure 6-6
Figure 6-7
Figure 6-8
Figure 6-9
Figure 6-10
Figure 6-11
Figure 6-12
Figure 6-13
Figure 6-14
Figure 6-15
Figure 6-16
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Host Base Address Register (HBAR) (X:$FFFFC5). . . . . . . . . . 6-12
Self Chip Select Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Host Port Control Register (HPCR) (X:$FFFFC4) . . . . . . . . . . . 6-13
Single Strobe Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Dual Strobe Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Host Data Direction Register (HDDR) (X:$FFFFC8) . . . . . . . . . 6-17
Host Data Register (HDR) (X:$FFFFC9) . . . . . . . . . . . . . . . . . . 6-17
HSR-HCR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
Interface Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . . . . . . 6-25
Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
Interrupt Vector Register (IVR). . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
HI08 Host Request Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
ESSI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
ESSI Control Register A (CRA) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
ESSI Control Register B (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
ESSI Status Register (SSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
ESSI Transmit Slot Mask Register A (TSMA) . . . . . . . . . . . . . . 7-10
ESSI Transmit Slot Mask Register B (TSMB) . . . . . . . . . . . . . . 7-10
ESSI Receive Slot Mask Register A (RSMA). . . . . . . . . . . . . . . 7-10
ESSI Receive Slot Mask Register B (RSMB). . . . . . . . . . . . . . . 7-10
ESSI Clock Generator Functional Block Diagram . . . . . . . . . . . 7-12
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Figure 7-10
Figure 7-11
Figure 7-12
Figure 7-13
Figure 7-14
Figure 7-15
Figure 7-16
Figure 7-17
Figure 7-18
Figure 7-19
Figure 7-20
Figure 8-1
Figure 8-2
Figure 8-3
Figure 8-4
Figure 8-5
Figure 8-6
Figure 8-7
Figure 8-8
Figure 8-9
Figure 8-10
Figure 9-1
ESSI Frame Sync Generator Functional Block Diagram. . . . . . 7-13
CRB FSL0 and FSL1 Bit Operation (FSR = 0) . . . . . . . . . . . . . 7-19
CRB SYN Bit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
CRB MOD Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame) . 7-22
Network Mode, External Frame Sync (8 Bit, 2 Words in Frame) 7-23
ESSI Data Path Programming Model (SHFD = 0). . . . . . . . . . . 7-31
ESSI Data Path Programming Model (SHFD = 1). . . . . . . . . . . 7-32
Port Control Register (PCR) (PCRC X:$FFFFBF). . . . . . . . . . . 7-44
Port Direction Register (PRR)(PRRC X:$FFFFBE). . . . . . . . . . 7-44
Port Data Register (PDR) (PDRC X:$FFFFBD) . . . . . . . . . . . . 7-45
SCI Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
SCI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
SCI Clock Control Register (SCCR) . . . . . . . . . . . . . . . . . . . . . . 8-5
SCI Data Word Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
16 x Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
SCI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
SCI Programming Model Data Registers . . . . . . . . . . . . . . . . . 8-19
Port E Control Register (PCRE) . . . . . . . . . . . . . . . . . . . . . . . . 8-27
Port E Direction Register (PRRE) . . . . . . . . . . . . . . . . . . . . . . . 8-28
Port E Data Register (PDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
Triple Timer Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . 9-4
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Figure 9-2
Figure 9-3
Figure 9-4
Figure 9-5
Figure 9-6
Figure 10-1
Figure 10-2
Figure 10-3
Figure 10-4
Figure 10-5
Figure 10-6
Figure 10-7
Figure 10-8
Figure 10-9
Figure 10-10
Figure 11-1
Figure 11-2
Figure 11-3
Figure 11-4
Figure 11-5
Figure D-1
Figure D-2
Timer Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Timer Module ProgrammerÕs Model. . . . . . . . . . . . . . . . . . . . . . . 9-6
Timer Prescaler Load Register (TPLR) . . . . . . . . . . . . . . . . . . . . 9-7
Timer Prescaler Count Register (TPCR) . . . . . . . . . . . . . . . . . . . 9-8
Timer Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
OnCE Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
OnCE Module Multiprocessor Configuration . . . . . . . . . . . . . . . 10-4
OnCE Controller Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 10-5
OnCE Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
OnCE Status and Control Register (OSCR). . . . . . . . . . . . . . . . 10-8
OnCE Memory Breakpoint Logic 0. . . . . . . . . . . . . . . . . . . . . . 10-10
OnCE Breakpoint Control Register (OBCR). . . . . . . . . . . . . . . 10-12
OnCE Trace Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . 10-15
OnCE Pipeline Information and GDB Registers . . . . . . . . . . . 10-19
OnCE Trace Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
TAP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-15
Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . .D-16
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Figure D-3
Figure D-4
Figure D-5
Figure D-6
Figure D-7
Figure D-8
Figure D-9
Figure D-10
Figure D-11
Figure D-12
Figure D-13
Figure D-14
Figure D-15
Figure D-16
Figure D-17
Figure D-18
Figure D-19
Figure D-20
Figure D-21
Figure D-22
Figure D-23
Figure D-24
Interrupt Priority RegisterÐCore (IPRÐC). . . . . . . . . . . . . . . . . . D-17
Interrupt Priority Register Ð Peripherals (IPRÐP). . . . . . . . . . . . D-18
Phase-Locked Loop Control Register (PCTL). . . . . . . . . . . . . . D-19
Host Receive and Host Transmit Data Registers . . . . . . . . . . . D-20
Host Control and Host Status Registers . . . . . . . . . . . . . . . . . . D-21
Host Base Address and Host Port Control Registers . . . . . . . . D-22
Interrupt Control and Interrupt Status Registers . . . . . . . . . . . . D-23
Interrupt Vector and Command Vector Registers . . . . . . . . . . . D-24
Host Receive and Host Transmit Data Registers . . . . . . . . . . . D-25
ESSI Control Register A (CRA). . . . . . . . . . . . . . . . . . . . . . . . . D-26
ESSI Control Register B (CRB). . . . . . . . . . . . . . . . . . . . . . . . . D-27
ESSI Status Register (SSISR). . . . . . . . . . . . . . . . . . . . . . . . . . D-28
ESSR Transmit and Receive Slot Mask Registers (TSM, RSM)D-29
SCI Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . D-30
SCI Status and Clock Control Registers (SSR, SCCR). . . . . . . D-31
SCI Receive and Transmit Data Registers (SRX, TRX) . . . . . . D-32
Timer Prescaler Load/Count Register (TPLR, TPCR). . . . . . . . D-33
Timer Control/Status Register (TCSR) . . . . . . . . . . . . . . . . . . . D-34
Timer Load, Compare, Count Registers (TLR, TCPR, TCR) . . D-35
Host Data Direction and Host Data Registers (HDDR, HDR) . . D-36
Port C Registers (PCRC, PRRC, PDRC) . . . . . . . . . . . . . . . . . D-37
Port D Registers (PCRD, PRRD, PDRD) . . . . . . . . . . . . . . . . . D-38
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Figure D-25
Port E Registers (PCRE, PRRE, PDRE) . . . . . . . . . . . . . . . . .D-39
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LIST OF TABLES
Table 1-1
Table 1-2
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 2-9
Table 2-10
Table 2-11
Table 2-12
Table 2-13
Table 2-14
Table 2-15
Table 2-16
Table 3-1
High True/Low True Signal Conventions . . . . . . . . . . . . . . . . . . 1-5
On Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
DSP56309 Functional Signal Groupings . . . . . . . . . . . . . . . . . . 2-3
Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Phase-Locked Loop Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
External Address Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
External Data Bus Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
External Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Host Port Usage Considerations . . . . . . . . . . . . . . . . . . . . . . . 2-17
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Enhanced Synchronous Serial Interface 0 (ESSI0) . . . . . . . . . 2-24
Enhanced Synchronous Serial Interface 1 (ESSI1) . . . . . . . . . 2-28
Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . 2-32
Triple Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
OnCE/JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
Memory Space Configuration Bit Settings for the DSP56309 . . . 3-5
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Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 4-1
Table 4-2
Table 4-3
Table 4-4
Table 4-5
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Table 6-5
Table 6-6
Table 6-7
Table 6-8
Table 6-9
Table 6-10
Table 6-11
Table 6-12
RAM Configuration Bit Settings for the DSP56309 . . . . . . . . . . . 3-5
Memory Space Configurations for the DSP56309 . . . . . . . . . . . . 3-7
RAM Configurations for the DSP56309 . . . . . . . . . . . . . . . . . . . . 3-8
Memory Locations for Program RAM and Instruction Cache. . . . 3-8
Memory Locations for Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
DSP56309 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Interrupt Priority Level Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Interrupt Source Priorities within an IPL . . . . . . . . . . . . . . . . . . 4-14
DMA Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
HI08 Signal Definitions for Various Operational Modes . . . . . . . . 6-6
HI08 Data Strobe Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
HI08 Host Request Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Host Command Interrupt Priority List . . . . . . . . . . . . . . . . . . . . . 6-10
HDR and HDDR Functionality . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
DSP Side Registers after Reset. . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Host Side Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
TREQ and RREQ modes (HDRQ = 0). . . . . . . . . . . . . . . . . . . . 6-23
TREQ and RREQ modes (HDRQ = 1). . . . . . . . . . . . . . . . . . . . 6-23
INIT Command Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
HREQ and HDRQ Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
Host Side Registers After Reset. . . . . . . . . . . . . . . . . . . . . . . . . 6-30
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Table 6-13
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
Table 8-1
Table 8-2
Table 8-3
Table 8-4
Table 9-1
Table 9-2
Table 9-3
Table 10-1
Table 10-2
Table 10-3
Table 10-4
Table 10-5
Table 10-6
Table 10-7
Table 10-8
Table 10-9
HI08 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
ESSI Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
ESSI Word Length Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
FSL1 and FSL0 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
Mode and Signal Definition Table . . . . . . . . . . . . . . . . . . . . . . 7-24
Port Control Register and Port Direction Register Bits . . . . . . . 7-45
Word Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
TCM and RCM Bit Configuration . . . . . . . . . . . . . . . . . . . . . . . 8-17
SCI Registers after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
Port Control Register and Port Direction Register Bits . . . . . . . 8-28
Prescaler Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
Timer Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Inverter (INV) Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
EX Bit Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
GO Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
R/W Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
OnCE Register Select Encoding . . . . . . . . . . . . . . . . . . . . . . . 10-6
Core Status Bits Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Memory Breakpoint 0 and 1 Select Table . . . . . . . . . . . . . . . . 10-12
Breakpoint 0 Read/Write Select Table . . . . . . . . . . . . . . . . . . 10-13
Breakpoint 0 Condition Select Table . . . . . . . . . . . . . . . . . . . 10-13
Breakpoint 1 Read/Write Select Table . . . . . . . . . . . . . . . . . . 10-13
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Table 10-10
Table 10-11
Table 10-12
Table 10-13
Table 10-14
Table 11-1
Table 11-2
Table D-1
Breakpoint 1 Condition Select Table. . . . . . . . . . . . . . . . . . . . 10-14
Breakpoint 0 and 1 Event Select Table . . . . . . . . . . . . . . . . . . 10-14
TMS Sequencing for DEBUG_REQUEST . . . . . . . . . . . . . . . 10-29
TMS Sequencing for ENABLE_ONCE . . . . . . . . . . . . . . . . . . 10-30
TMS Sequencing for Reading Pipeline Registers . . . . . . . . . 10-31
JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
DSP56309 BSR Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . 11-13
Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-4
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-11
Interrupt Source Priorities within an IPL . . . . . . . . . . . . . . . . . .D-13
Table D-2
Table D-3
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SECTION 1
DSP56309 OVERVIEW
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DSP56309 Overview
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
MANUAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
MANUAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
DSP56309 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
DSP56309 CORE DESCRIPTION . . . . . . . . . . . . . . . . . . . . 1-7
DSP56300 CORE FUNCTIONAL BLOCKS . . . . . . . . . . . . . 1-8
INTERNAL BUSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
DSP56309 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . 1-14
DIRECT MEMORY ACCESS (DMA). . . . . . . . . . . . . . . . . . 1-15
DSP56309 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . 1-15
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DSP56309 Overview
Introduction
1.1
INTRODUCTION
This manual describes the DSP56309 24-bit digital signal processor (DSP), its memory,
operating modes, and peripheral modules. The DSP56309 is an implementation of the
DSP56300 core with a unique configuration of on-chip memory, cache, and peripherals.
This manual is intended to be used with the DSP56300 Family Manual (DSP56300FM/AD),
which describes the central processing unit (CPU), core programming models, and
instruction set details. DSP56309 Technical Data (DSP56309/D) provides electrical
specifications, timing, pinout, and packaging descriptions of the DSP56309.
You can obtain these documents, as well as MotorolaÕs DSP development tools, through
a local Motorola Semiconductor Sales Office or authorized distributor.
To receive the latest information about this DSP, access the Motorola DSP home page at
the address on the back cover of this document.
1.2
MANUAL ORGANIZATION
This manual contains the following sections and appendices:
Section 1ÑDSP56309 Overview
Ð Features list and block diagram
Ð Related documentation needed to use this chip
Ð The organization of this manual
Section 2ÑSignal/Connection Descriptions
Ð Signals on the DSP56309 pins and their functional groupings
Section 3ÑMemory Configuration
Ð DSP56309 memory spaces, RAM configuration, memory configuration bit
settings, memory configurations, and memory maps
Section 4ÑCore Configuration
Ð Registers for configuring the DSP56300 core to program the DSP56309, in
particular the interrupt vector locations and the operation of the interrupt
priority registers
Ð Operating modes and how they affect the processorÕs program and data
memories
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DSP56309 Overview
Manual Organization
Section 5ÑGeneral-Purpose I/O
Ð DSP56309 general-purpose input/output (GPIO) capability and the
programming model for the GPIO signals (operation, registers, and control)
Section 6ÑHost Interface (HI08)
Ð 8-bit host interface (HI08), including a quick reference to the HI08
programming model
Section 7ÑEnhanced Synchronous Serial Interface (ESSI)
Ð 24-bit ESSI, which provides two identical full duplex UART-style serial ports
for communications with devices such as codecs, DSPs, microprocessors, and
peripherals implementing the Motorola serial peripheral interface (SPI)
Section 8ÑSerial Communication Interface (SCI)
Ð 24-bit SCI, a full duplex serial port for serial communication to DSPs,
microcontrollers, or other peripherals (such as modems or other RS-232
devices)
Section 9ÑTriple Timer Module
Ð The three identical internal timers/event counter devices
Section 10ÑOn-Chip Emulation Module
Ð The On-Chip Emulation (OnCEª) module, which is accessed through the
JTAG port
Section 11ÑJTAG Port
Ð Specifics of the Joint Test Action Group (JTAG) port on the DSP56309
Appendix AÑBootstrap Programs
Ð Bootstrap code used for the DSP56309
Appendix BÑEquates
Ð Equates (I/O, HI08, SCI, ESSI, exception processing, timer, DMA, PLL, BIU,
and interrupts) for the DSP56309
Appendix CÑDSP56309 BSDL Listing
Ð BSDL listing for the DSP56309
Appendix DÑProgramming Reference
Ð Peripheral addresses, interrupt addresses, and interrupt priorities for the
DSP56309
Ð Programming sheets listing the contents of the major DSP56309 registers for
programmerÕs reference
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DSP56309 Overview
Manual Conventions
1.3
MANUAL CONVENTIONS
This manual uses the following conventions:
¥ Bits within registers are always listed from most significant bit (MSB) to least
significant bit (LSB).
¥ Bits within a register are indicated AA[n:m], n>m, when more than one bit is
involved in a description. For purposes of description, the bits are presented as if
they are contiguous within a register. However, this is not always the case. Refer
to the programming model diagrams or to the programmerÕs sheets to see the
exact location of bits within a register.
¥ When a bit is described as Òset,Ó its value is 1. When a bit is described as
Òcleared,Ó its value is 0.
¥ The word ÒassertÓ means that a high true (active high) signal is pulled high to
V
or that a low true (active low) signal is pulled low to ground. The word
CC
ÒdeassertÓ means that a high true signal is pulled low to ground or that a low true
signal is pulled high to V . See Table 1-1.
CC
Table 1-1 High True/Low True Signal Conventions
Signal/Symbol
Logic State
True
Signal State
Asserted
Voltage
1
2
PIN
Ground
3
PIN
False
Deasserted
V
CC
PIN
PIN
True
False
Asserted
V
CC
Deasserted
Ground
1. PIN is a generic term for any pin on the chip.
2. Ground is an acceptable low voltage level. See the
appropriate data sheet for the range of acceptable low
voltage levels (typically a TTL logic low).
3.
V
is an acceptable high voltage level. See the
CC
appropriate data sheet for the range of acceptable high
voltage levels (typically a TTL logic high).
¥ Pins or signals that are asserted low (made active when pulled to ground)
Ð In text, have an overbar. For example, RESET is asserted low.
Ð In code examples, have a tilde in front of their names. In Example 1-1, line 3
refers to the SS0 signal (shown as ~SS0).
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DSP56309 Overview
DSP56309 Features
¥ Sets of signals are indicated by the first and last signals in the set, for instance
HA1ÐHA8.
¥ Code examples are displayed in a monospaced font, as shown in Example 1-1.
Example 1-1 Sample Code Listing
BFSET
#$0007,X:PCC; Configure:
MISO0, MOSI0, SCK0 for SPI master
; ~SS0 as PC3 for GPIO
line 1
line 2
line 3
;
¥ Hex values are indicated with a dollar sign ($) preceding the hex value. For
example, $FFFFFF is the X memory address for the core interrupt priority register
(IPR-C).
¥ The word ÔresetÕ is used in four different contexts in this manual:
Ð the reset signal, written as RESET;
Ð the reset instruction, written as RESET;
Ð the reset operating state, written as Reset; and
Ð the reset function, written as reset.
1.4
DSP56309 FEATURES
The DSP56309 is a member of the DSP56300 family of programmable CMOS DSPs. The
DSP56309 uses the DSP56300 core, a high-performance engine with a single clock cycle
per instruction. The DSP56300 core provides up to twice the performance of Motorola's
popular DSP56000 core family, while retaining code compatibility.
The DSP56300 core family offers a new level of performance in speed and power
provided by its rich instruction set and low-power dissipation, enabling a new
generation of wireless, telecommunications, and multimedia products. The DSP56300
core is composed of the data arithmetic logic unit (Data ALU), address generation unit
(AGU), program controller (PC), instruction cache controller, bus interface unit, direct
memory access (DMA) controller, On-Chip Emulation (OnCE) module, and a PLL-based
clock oscillator. Significant architectural enhancements to the DSP56300 core family
include a barrel shifter, 24-bit addressing, an instruction cache, and DMA.
The DSP56300 core family members contain the DSP56300 core and additional modules.
The modules are chosen from a library of standard pre-designed elements, such as
memories and peripherals. New modules can be added to the library to meet customer
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DSP56309 Overview
DSP56309 Core Description
specifications. A standard interface between the DSP56300 core and the on-chip memory
and peripherals supports a wide variety of memory and peripheral configurations.
The DSP56309 targets telecommunications applications, such as multi-line
voice/data/fax processing, video conferencing, audio applications, control, and general
digital signal processing.
1.5
DSP56309 CORE DESCRIPTION
The DSP56300 Family Manual fully describes core features; this manual describes
pinout, memory, and peripheral features.
1.5.1
General Features
¥ 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0 -
3.6 V
¥ Object-code compatible with the DSP56000 core
¥ Highly parallel instruction set
1.5.2
Hardware Debugging Support
¥ On-Chip Emulation (OnCEÔ) module
¥ Joint Test Action Group (JTAG) test access port (TAP)
¥ Address trace mode reflects internal program RAM accesses at the external port
1.5.3
Reduced Power Dissipation
¥ Very low-power CMOS design
¥ Wait and stop low-power standby modes
¥ Fully-static logic, operation frequency down to 0 Hz (dc)
¥ Optimized cycle-by-cycle power management circuitry (instruction-dependent,
peripheral-dependent, and mode-dependent)
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DSP56309 Overview
DSP56300 Core Functional Blocks
1.6
DSP56300 CORE FUNCTIONAL BLOCKS
The DSP56300 core provides the following functional blocks:
¥ Data ALU
¥ AGU
¥ PCU
¥ PLL and Clock Oscillator
¥ JTAG TAP and OnCE module
¥ Memory
In addition, the DSP56309 provides a set of on-chip peripherals, described in
Section 1.10.
1.6.1
Data ALU
The Data ALU performs all the arithmetic and logical operations on data operands in the
DSP56300 core. The components of the Data ALU are as follows:
¥ Fully pipelined 24 ´ 24-bit parallel multiplier-accumulator (MAC)
¥ Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and
normalization; bit stream generation and parsing)
¥ Conditional ALU instructions
¥ 24-bit or 16-bit arithmetic support under software control
¥ Four 24-bit input general-purpose registers: X1, X0, Y1, and Y0
¥ Six Data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two
general-purpose, 56-bit accumulators, A and B, accumulator shifters
¥ Two data bus shifter/limiter circuits
1.6.1.1
Data ALU Registers
The Data ALU registers can be read or written over the X data bus (XDB) and the Y data
bus (YDB) as 16- or 32-bit operands. The source operands for the Data ALU, which can
be 16, 32, or 40 bits, always originate from Data ALU registers. The results of all
Data ALU operations are stored in an accumulator.
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DSP56309 Overview
DSP56300 Core Functional Blocks
All the Data ALU operations are performed in two clock cycles in pipeline fashion so
that a new instruction can be initiated in every clock, yielding an effective execution rate
of one instruction per clock cycle. The destination of every arithmetic operation can be
used as a source operand for the immediately following operation without penalty.
1.6.1.2
Multiplier-Accumulator (MAC)
The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and
performs all of the calculations on data operands. For arithmetic instructions, the unit
accepts as many as three input operands and outputs one 56-bit result of the following
form, Extension:Most Significant Product:Least Significant Product (EXT:MSP:LSP).
The multiplier executes 24-bit ´ 24-bit, parallel, fractional multiplies between
twos-complement signed, unsigned, or mixed operands. The 48-bit product is
right-justified and added to the 56-bit contents of either the A or B accumulator. A 56-bit
result can be stored as a 24-bit operand. The LSP can either be truncated or rounded into
the MSP. Rounding is performed if specified.
1.6.2
Address Generation Unit (AGU)
The AGU performs the effective address calculations using integer arithmetic necessary
to address data operands in memory and contains the registers that generate the
addresses. It implements four types of arithmetic: linear, modulo, multiple wrap-around
modulo, and reverse-carry. The AGU operates in parallel with other chip resources to
minimize address-generation overhead.
The AGU is divided into two halves, each with its own address arithmetic logic unit
(Address ALU). Each Address ALU has four sets of register triplets, and each register
triplet is composed of an address register, an offset register, and a modifier register. The
two Address ALUs are identical. Each contains a 16-bit full adder (called an offset
adder).
A second full adder (called a modulo adder) adds the summed result of the first full
adder to a modulo value that is stored in its respective modifier register. A third full
adder (called a reverse-carry adder) is also provided.
The offset adder and the reverse-carry adder are in parallel and share common inputs.
The only difference between them is that they carry propagates in opposite directions.
Test logic determines which of the three summed results of the full adders is output.
Each Address ALU can update one address register from its respective address register
file during one instruction cycle. The contents of the associated modifier register
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DSP56309 Overview
DSP56300 Core Functional Blocks
specifies the type of arithmetic to be used in the address register update calculation. The
modifier value is decoded in the Address ALU.
1.6.3
Program Control Unit (PCU)
The PCU performs instruction prefetch, instruction decoding, hardware DO loop
control, and exception processing. The PCU implements a seven-stage pipeline and
controls the different processing states of the DSP56300 core. The PCU consists of three
hardware blocks:
¥ Program decode controller (PDC)
¥ Program address generator (PAG)
¥ Program interrupt controller
The PDC decodes the 24-bit instruction loaded into the instruction latch and generates
all signals necessary for pipeline control. The PAG contains all the hardware needed for
program address generation, system stack, and loop control. The PIC arbitrates among
all interrupt requests (internal interrupts, as well as the five external requests IRQA,
IRQB, IRQC, IRQD, and NMI) and generates the appropriate interrupt vector address.
PCU features include the following:
¥ Position Independent Code (PIC) support
¥ Addressing modes optimized for DSP applications (including immediate offsets)
¥ On-chip instruction cache controller
¥ On-chip memory-expandable hardware stack
¥ Nested hardware DO loops
¥ Fast auto-return interrupts
The PCU implements its functions using the following registers:
¥ PCÑprogram counter register
¥ SRÑstatus register
¥ LAÑloop address register
¥ LCÑloop counter register
¥ VBAÑvector base address register
¥ SZÑsize register
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DSP56300 Core Functional Blocks
¥ SPÑstack pointer
¥ OMRÑoperating mode register
¥ SCÑstack counter register
The PCU also includes a hardware system stack (SS).
1.6.4
PLL and Clock Oscillator
The clock generator in the DSP56300 core is composed of two main blocks: the PLL,
which performs clock input division, frequency multiplication, and skew elimination;
and the clock generator (CLKGEN), which performs low-power division and clock pulse
generation.
¥ Allows change of low-power divide factor (DF) without loss of lock
¥ Output clock with skew elimination
The PLL allows the processor to operate at a high internal clock frequency using a
low-frequency clock input, a feature that offers two immediate benefits:
¥ A lower-frequency clock input reduces the overall electromagnetic interference
generated by a system.
¥ The ability to oscillate at different frequencies reduces costs by eliminating the
need to add additional oscillators to a system.
1.6.5
JTAG TAP and OnCE Module
The DSP56300 core provides a dedicated user-accessible Test Access Port (TAP) that is
fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture. Problems associated with testing high density circuit boards have led to
development of this standard under the sponsorship of the Test Technology Committee
of IEEE and the Joint Test Action Group (JTAG). The DSP56300 core implementation
supports circuit-board test strategies based on this standard.
The test logic includes a TAP consisting of four dedicated signals, a 16-state controller,
and three test data registers. A boundary scan register links all device signals into a
single shift register. The test logic, implemented utilizing static logic design, is
independent of the device system logic. More information on the JTAG port is provided
in Section 11ÑJTAG Port.
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DSP56300 Core Functional Blocks
The OnCE module provides a means of interacting with the DSP56300 core and its
peripherals non-intrusively so that a user can examine registers, memory, or on-chip
peripherals. This facilitates hardware and software development on the DSP56300 core
processor. OnCE module functions are provided through the JTAG TAP signals. More
information about the OnCE module is provided in Section 10ÑOn-Chip Emulation
Module.
1.6.6
On-Chip Memory
The memory space of the DSP56300 core is partitioned into program memory space,
X data memory space, and Y data memory space. The data memory space is divided into
X data memory and Y data memory in order to work with the two Address ALUs and to
feed two operands simultaneously to the Data ALU. Memory space includes internal
RAM and ROM and can be expanded off-chip under software control. More information
about the internal memory is provided in Section 3ÑMemory Configuration.
Program RAM, instruction cache, X data RAM, and Y data RAM size are programmable,
as indicated in Table 1-2.
Table 1-2 On Chip Memory
Instruction
Cache
Switch Program RAM Instruction
X Data RAM
Size
Y Data RAM
Size
Mode
Size
Cache Size
disabled
enabled
disabled
enabled
disabled
disabled
enabled
enabled
20K ´ 24-bit
19K´ 24-bit
24K ´ 24-bit
23K ´ 24-bit
0
7K ´ 24-bit
7K ´ 24-bit
5K ´ 24-bit
5K ´ 24-bit
7K ´ 24-bit
7K ´ 24-bit
5K ´ 24-bit
5K ´ 24-bit
1K ´ 24-bit
0
1K ´ 24-bit
There is an on-chip 192 x 24-bit bootstrap ROM.
1.6.7
Off-Chip Memory Expansion
Memory can be expanded off-chip to do the following:
¥ Data memory expansion to two 256K ´ 24-bit word memory spaces (or up to two4
M ´ 24-bit word memory spaces by using the address attribute AA0ÐAA3 signals)
¥ Program memory expansion to one 256K ´ 24-bit words memory space (or up to
one 4 M ´ 24-bit word memory space by using the address attribute AA0ÐAA3 signals)
Additional features of off-chip memory include the following:
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Internal Buses
¥ External memory expansion port
¥ Simultaneous glueless interface to static random access memory (SRAM) and
dynamic random access memory (DRAM)
¥ Supports interleaved, non-interfering access to both types of memory without
losing in-page DRAM access, including DMA-driven access
1.7
INTERNAL BUSES
The following buses provide data exchange between the functional blocks of the core:
¥ Peripheral I/O expansion bus (PIO_EB) to peripherals
¥ Program memory expansion bus (PM_EB) to Program RAM
¥ X memory expansion bus (XM_EB) to X memory
¥ Y memory expansion bus (YM_EB) to Y memory
¥ Global data bus (GDB) between PCU and other core structures
¥ Program data bus (PDB) for carrying program data throughout the core
¥ X memory data bus (XDB) for carrying X data throughout the core
¥ Y memory data bus (YDB) for carrying Y data throughout the core
¥ Program address bus (PAB) for carrying program memory addresses throughout
the core
¥ X memory address bus (XAB) for carrying X memory addresses throughout the
core
¥ Y memory address bus (YAB) for carrying Y memory addresses throughout the
core
All internal buses on the DSP56300 family members are 16-bit buses except the PDB,
which is a 24-bit bus. Figure 1-1 shows a block diagram of the DSP56309.
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DSP56309 Block Diagram
1.8
DSP56309 BLOCK DIAGRAM
16
6
6
3
Memory Expansion Area
Program
RAM
Y Data
RAM
Host
Interface
HI08
X Data
RAM
Triple
Timer
SCI
Interface
ESSI
Interface
Peripheral
Expansion Area
YAB
XAB
PAB
External
Address
Bus
18
Address
Generation
Unit
ADDRESS
Switch
DAB
Six Channel
DMA Unit
External
Bus
24-Bit
DSP56300
Core
13
Interface
&
Boot-
strap
ROM
I - Cache
Control
CONTROL
DDB
YDB
XDB
PDB
GDB
External
Data Bus
Switch
24
Internal
Data
Bus
DATA
Switch
Power
EXTAL
XTAL
Clock
Generator
Mgmt
Data ALU
Program
Interrupt
Controller
Program
Decode
Program
Address
Generator
6
+
®
56-bit MAC
24 ´ 24 56
JTAG
Two 56-bit Accumulators
56-bit Barrel Shifter
PLL
2
Controller
OnCEª
MODD/IRQA
MODC/IRQB
MODB/IRQC
MODA/IRQD
RESET
PINIT/NMI
AA0456
Figure 1-1 DSP56309 Block Diagram
See Section 1.6.6 On-Chip Memory on page 1-12 for details on memory size.
Note:
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Direct Memory Access (DMA)
1.9
DIRECT MEMORY ACCESS (DMA)
The DMA block has the following features:
¥ Six DMA channels supporting internal and external accesses
¥ One-, two-, and three-dimensional transfers (including circular buffering)
¥ End-of-block-transfer interrupts
¥ Triggering from interrupt lines, all peripherals, and DMA channels
1.10 DSP56309 ARCHITECTURE OVERVIEW
The DSP56309 performs a wide variety of fixed-point digital signal processing functions.
In addition to the core features previously discussed, the DSP56309 provides the
following peripherals:
¥ Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of
buses (e.g., industry standard architecture) and provides glueless connection to a
number of industry standard microcomputers, microprocessors, and DSPs
¥ Two enhanced synchronous serial interfaces (ESSI0 and ESSI1), each with one
receiver and three transmitters (allows six-channel home theater)
¥ Serial communications interface (SCI) with baud rate generator
¥ Triple timer module
¥ Up to 34 programmable general purpose input/output (GPIO) pins, depending
on which peripherals are enabled
1.10.1
GPIO Functionality
The GPIO port consists of as many as thirty-four programmable signals, all of which are
also used by the peripherals (HI08, ESSI, SCI, and timer). There are no dedicated GPIO
signals. Peripheral pins are configured as GPIO inputs after any reset. (Data in the port
data register is not affected by a reset.) The GPIO functionality for each peripheral is
controlled by three memory-mapped registers per peripheral. The techniques for
register programming for all GPIO functionality is very similar between these interfaces.
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DSP56309 Architecture Overview
1.10.2
Host Interface (HI08)
The HI08 is a byte-wide, full-duplex, double-buffered, parallel port that can connect
directly to the data bus of a host processor. The HI08 supports a variety of buses and
connects to a number of industry-standard DSPs, microcomputers, and microprocessors
without requiring additional logic.
The DSP core treats the HI08 as a memory-mapped peripheral occupying eight 24-bit
words in data memory space. The DSP can use the HI08 as a memory-mapped
peripheral, using either standard polled or interrupt programming techniques. Separate
transmit and receive data registers are double-buffered to allow the DSP and host
processor to transfer data efficiently at high speed. Memory mapping allows DSP core
communication with the HI08 registers using standard instructions and addressing
modes.
1.10.3
Enhanced Synchronous Serial Interface (ESSI)
On the DSP56309 are two independent and identical ESSIs. Each ESSI has a full-duplex
serial port for communication with a variety of serial devices, including one or more
industry-standard codecs, other DSPs, microprocessors, and peripherals that implement
the Motorola SPI. The ESSI consists of independent transmitter and receiver sections and
a common ESSI clock generator.
The capabilities of the ESSI include the following:
¥ Independent (asynchronous) or shared (synchronous) transmit and receive
sections with separate or shared internal/external clocks and frame syncs
¥ Normal mode operation using frame sync
¥ Network mode operation with as many as 32 time slots
¥ Programmable word length (8, 12, or 16 bits)
¥ Program options for frame synchronization and clock generation
¥
One receiver and three transmitters per ESSI allows six-channel home theater
1.10.4
Serial Communications Interface (SCI)
The DSP56309Õs SCI provides a full-duplex port for serial communication with other
DSPs, microprocessors, or peripherals such as modems. The SCI interfaces without
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DSP56309 Architecture Overview
additional logic to peripherals that use TTL-level signals. With a small amount of
additional logic, the SCI can connect to peripheral interfaces that have non-TTL level
signals, such as the RS-232C, RS-422, etc.
This interface uses three dedicated signals: transmit data (TXD), receive data (RXD), and
SCI serial clock (SCLK). It supports industry-standard asynchronous bit rates and
protocols, as well as high-speed synchronous data transmission (up to 8.25 Mbps for a
66 MHz clock). The asynchronous protocols supported by the SCI include a multidrop
mode for master/slave operation with wakeup on idle line and wakeup on address bit
capability. This mode allows the DSP56309 to share a single serial line efficiently with
other peripherals.
The SCI consists of separate transmit and receive sections that can operate
asynchronously with respect to each other. A programmable baud-rate generator
provides the transmit and receive clocks. An enable vector and an interrupt vector have
been included so that the baud-rate generator can function as a general purpose timer
when it is not being used by the SCI or when the interrupt timing is the same as that
used by the SCI.
1.10.5
Timer Module
The triple timer module is composed of a common 21-bit prescaler and three
independent and identical general-purpose 24-bit timer/event counters, each with its
own memory-mapped register set.
Each timer has a single signal that can function as a GPIO signal or as a timer signal.
Each timer can use internal or external clocking and can interrupt the DSP after a
specified number of events (clocks) or can signal an external device after counting
internal events. Each timer connects to the external world through one bidirectional
signal. When this signal is configured as an input, the timer can function as an external
event counter or measures external pulse width/signal period. When the signal is used
as an output, the timer can function as either a timer, a watchdog, or a Pulse Width
Modulator (PWM).
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DSP56309 Architecture Overview
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SECTION 2
SIGNAL/CONNECTION DESCRIPTIONS
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Signal/Connection Descriptions
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
SIGNAL GROUPINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
GROUND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
PHASE-LOCKED LOOP (PLL) . . . . . . . . . . . . . . . . . . . . . . . 2-8
EXTERNAL MEMORY EXPANSION PORT (PORT A). . . . . 2-9
INTERRUPT AND MODE CONTROL . . . . . . . . . . . . . . . . . 2-14
HOST INTERFACE (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
ENHANCED SYNCHRONOUS SERIAL INTERFACE . . . . 2-24
SERIAL COMMUNICATION INTERFACE (SCI). . . . . . . . . 2-32
TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
ONCE/JTAG INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
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Signal/Connection Descriptions
Signal Groupings
2.1
SIGNAL GROUPINGS
The DSP56309 input and output signals are organized into functional groups, as shown
in Table 2-1 and as illustrated in Figure 2-1.
The DSP56309 is operated from a 3 V supply.
Table 2-1 DSP56309 Functional Signal Groupings
Number of
Signals
Detailed
Description
Functional Group
Power (V
)
20
Table 2-2
CC
Ground (GND)
Clock
19
2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 2-9
Table 2-11
PLL
3
Address Bus
Data Bus
18
24
13
5
1
Port A
Bus Control
Interrupt and Mode Control
Host Interface (HI08)
2
16
Port B
Enhanced Synchronous Serial Interface
(ESSI)
Ports C and
12
Table 2-12
and
Table 2-13
3
D
4
Serial Communication Interface (SCI)
3
Table 2-14
Port E
Timer
3
6
Table 2-15
Table 2-16
OnCE/JTAG Port
Note: 1. Port A signals define the external memory interface port, including the external
address bus, data bus, and control signals.
2. Port B signals are the HI08 port signals multiplexed with the GPIO signals.
3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.
4. Port E signals are the SCI port signals multiplexed with the GPIO signals.
Figure 2-1 is a diagram of DSP56309 signals by functional group.
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Signal/Connection Descriptions
Signal Groupings
fs
After Reset
IRQA
IRQB
During Reset
MODA
MODB
DSP56309
MODC
MODD
RESET
IRQC
IRQD
RESET
V
PLL
Core Logic
I/O
Address Bus
Data Bus
Bus Control
HI08
CCP
4
3
3
4
2
V
CCQL
V
CCQH
1
Host Interface (H108)
Non-Multiplexed Multiplexed
Bus
H0ÐH7
HA0
HA1
V
CCA
Port B
GPIO
V
V
V
CCD
CCC
CCH
Bus
8
HAD0ÐHAD7 PB0ÐPB7
HAS/HAS
HA8
PB8
PB9
2
V
ESSI/SCI/Timer
CCS
HA2
HA9
HA10
PB10
PB13
HCS/HCS
Single DS
HRW
HDS/HDS
Single HR
HREQ/HREQ
HACK/HACK
PLL
PLL
GND
P
Double DS
HRD/HRD
HWR/HWR
Double HR
HTRQ/HTRQ PB14
HRRQ/HRRQ PB15
GND
P1
4
PB11
PB12
Internal Logic
Address Bus
Data Bus
Bus Control
HI08
GND
GND
GND
GND
GND
Q
4
4
2
A
D
C
H
2
Enhanced Synchronous Serial Interface (ESSI0)
Port C GPIO
ESSI/SCI/Timer
GND
S
3
SC00ÐSC02
SCK0
PC0ÐPC2
PC3
EXTAL
XTAL
SRD0
PC4
STD0
PC5
CLKOUT
PCAP
After
Enhanced Synchronous Serial Interface (ESSI1)
Port D GPIO
3
PD0ÐPD2
PD3
SC10ÐSC12
SCK1
During
Reset
PINIT
Reset
NMI
PD4
SRD1
PD5
STD1
EXTERNAL MEMORY INTERFACE
2
Serial Communications Interface (SCI)
Port E GPIO
18
A0ÐA17
PE0
PE1
PE2
RXD
TXD
SCLK
24
D0ÐD23
AA0ÐAA3/
4
3
GPIO
TIO0
TIO1
TIO2
Timers
TIO0
TIO1
RAS0ÐRAS3
RD
WR
TA
TIO2
BR
BG
BB
CAS
BCLK
BCLK
TCK
TDI
TDO
TMS
TRST
DE
Notes:
1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or
double Host Request (HR) configurations. Since each of these modes is configured independently, any combination
of these modes is possible. These HI08 signals can also be configured alternately as GPIO signals (PB0ÐPB15).
Signals with dual designations (e.g., HAS/HAS) have configurable polarity.
2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC0ÐPC5), Port D GPIO signals
(PD0ÐPD5), and Port E GPIO signals (PE0ÐPE2), respectively.
AA0601
3. TIO0ÐTIO2 can be configured as GPIO signals.
Figure 2-1 Signals Identified by Functional Group
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Signal/Connection Descriptions
Power
2.2
POWER
Power input descriptions for the DSP56309 are listed in Table 2-2.
Table 2-2 Power Inputs
Power Name
Description
V
PLL PowerÑV
CCP
is power dedicated for phase-locked loop (PLL) use.
CCP
The voltage should be well regulated, and the input should be provided
with an extremely low impedance path to the V power rail. V
CC
CCP
should be bypassed to GND by a stabilizing capacitor located as close
P
as possible to the chip package. There is one V
input.
CCP
V
V
(4)
(3)
Quiet Core (Low) PowerÑV
processing logic. This input must be isolated externally from all other
chip power inputs. The user must provide adequate external decoupling
is an isolated power for the core
CCQL
CCQL
CCQH
capacitors. There are four V
inputs.
CCQL
Quiet External (High) PowerÑV
is a quiet power source for I/O
CCQH
lines. This input must be tied externally to all other chip power inputs,
except V . The user must provide adequate external decoupling
CCQL
capacitors. There are three V
inputs.
CCQH
V
(3)
Address Bus PowerÑV
is an isolated power for sections of the
CCA
CCA
address bus I/O drivers. This input must be tied externally to all other
chip power inputs except V . The user must provide adequate
CCQL
external decoupling capacitors. There are three V
inputs.
CCA
V
V
(4)
Data Bus PowerÑV
I/O drivers. This input must be tied externally to all other chip power
inputs. The user must provide adequate external decoupling capacitors.
is an isolated power for sections of the data bus
CCD
CCD
CCC
There are four V
inputs.
CCD
(2)
Bus Control PowerÑV
is an isolated power for the bus control I/O
CCC
drivers. This input must be tied externally to all other chip power inputs
except V . The user must provide adequate external decoupling
CCQL
capacitors. There are two V
inputs.
CCC
V
Host PowerÑV
is an isolated power for the HI08 I/O drivers. This
CCH
CCH
input must be tied externally to all other chip power inputs except
. The user must provide adequate external decoupling capacitors.
V
CCQL
There is one V
input.
CCH
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Signal/Connection Descriptions
Ground
Table 2-2 Power Inputs (Continued)
Power Name
(2)
Description
V
ESSI, SCI, and Timer PowerÑV
is an isolated power for the ESSI,
CCS
CCS
SCI, and timer I/O drivers. This input must be tied externally to all
other chip power inputs except V . The user must provide adequate
CCQL
external decoupling capacitors. There are two V
inputs.
CCS
Note:
These designations are package-dependent. Some packages connect all V inputs except V
to
CCP
CC
each other internally. On those packages, all power input, except V
, are labeled V . The number
CCP
CC
of connections indicated in this table are minimum values; the total V connections are
CC
package-dependent.
2.3
GROUND
Ground descriptions for the DSP56309 are listed in Table 2-3.
Table 2-3 Grounds
Ground Name
Description
GND
PLL GroundÑGND is a ground dedicated for PLL use. The connection
P
P
should be provided with an extremely low-impedance path to ground.
V
should be bypassed to GND by a 0.47 mF capacitor located as
CCP
P
close as possible to the chip package. There is one GND connection.
P
GND
PLL Ground 1ÑGND is a ground dedicated for PLL use. The
P1
P1
connection should be provided with an extremely low-impedance path
to ground. There is one GND connection.
P1
GND (4)
Quiet GroundÑGND is an isolated ground for the internal processing
Q
Q
logic. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling
capacitors. There are four GND connections.
Q
GND (4)
Address Bus GroundÑGND is an isolated ground for sections of the
A
A
address bus I/O drivers. This connection must be tied externally to all
other chip ground connections. The user must provide adequate
external decoupling capacitors. There are four GND connections.
A
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Signal/Connection Descriptions
Clock
Table 2-3 Grounds (Continued)
Ground Name
GND (4)
Description
Data Bus GroundÑGND is an isolated ground for sections of the data
D
D
bus I/O drivers. This connection must be tied externally to all other chip
ground connections. The user must provide adequate external
decoupling capacitors. There are four GND connections.
D
GND (2)
Bus Control GroundÑGND is an isolated ground for the bus control
C
C
I/O drivers. This connection must be tied externally to all other chip
ground connections. The user must provide adequate external
decoupling capacitors. There are two GND connections.
C
GND
Host GroundÑGND is an isolated ground for the HI08 I/O drivers.
H
H
This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling
capacitors. There is one GND connection.
H
GND (2)
ESSI, SCI, and Timer GroundÑGND is an isolated ground for the
S
S
ESSI, SCI, and timer I/O drivers. This connection must be tied externally
to all other chip ground connections. The user must provide adequate
external decoupling capacitors. There are two GND connections.
S
Note:
These designations are package-dependent. Some packages connect all GND inputs, except GND
P
and GND , to each other internally. On those packages, all ground connections, except GND and
P1
P
GND , are labeled GND. The number of connections indicated in this table are minimum values; the
P1
total GND connections are package-dependent.
2.4
CLOCK
Clock Signal descriptions for the DSP56309 are listed in Table 2-4.
Table 2-4 Clock Signals
State
During
Reset
Signal
Name
Type
Signal Description
EXTAL
Input
Input
External Clock/Crystal InputÑEXTAL interfaces the
internal crystal oscillator input to an external crystal
or an external clock.
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Signal/Connection Descriptions
Phase-Locked Loop (PLL)
Table 2-4 Clock Signals (Continued)
State
During
Reset
Signal
Type
Signal Description
Name
XTAL
Output Chip-driven Crystal OutputÑXTAL connects the internal crystal
oscillator output to an external crystal. If an external
clock is used, leave XTAL unconnected.
2.5
PHASE-LOCKED LOOP (PLL)
Phase-locked loop signal descriptions are listed in Table 2-5.
Table 2-5 Phase-Locked Loop Signals
Signal
Name
State During
Reset
Type
Signal Description
PCAP
Input
Input
PLL CapacitorÑPCAP is an input connecting an
off-chip capacitor to the PLL filter. Connect one
capacitor terminal to PCAP and the other terminal
to V
.
CCP
If the PLL is not used, PCAP can be tied to V
tied to GND, or left floating.
,
CC
CLKOUT
Output Chip-driven
Clock OutputÑCLKOUT provides an output
clock synchronized to the internal core clock
phase.
If the PLL is enabled and both the multiplication
and division factors equal one, then CLKOUT is
also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is
half the frequency of EXTAL.
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External Memory Expansion Port (Port A)
Table 2-5 Phase-Locked Loop Signals (Continued)
Signal
Name
State During
Reset
Type
Signal Description
PINIT/
NMI
Input
Input
PLL Initial/Non-Maskable InterruptÑDuring
assertion of RESET, the value of PINIT/NMI is
written into the PLL Enable (PEN) bit of the PLL
control register, determining whether the PLL is
enabled or disabled. After RESET deassertion and
during normal instruction processing, the
PINIT/NMI Schmitt-trigger input is a
negative-edge-triggered Non-Maskable Interrupt
(NMI) request internally synchronized to
CLKOUT.
2.6
EXTERNAL MEMORY EXPANSION PORT (PORT A)
When the DSP56309 enters a low-power standby mode (stop or wait), it releases bus
mastership and tri-states the relevant Port A signals: A0ÐA17, D0ÐD23,
AA0/RAS0ÐAA3/RAS3, RD, WR, BB, CAS, BCLK, BCLK.
2.6.1
External Address Bus
External address bus signals for the DSP56309 are listed in Table 2-6.
Table 2-6 External Address Bus Signals
State
During
Reset
Signal
Name
Type
Signal Description
A0ÐA17
Output
Tri-stated
Address BusÑWhen the DSP is the bus master,
A0ÐA17 are active-high outputs that specify the
address for external program and data memory
accesses. Otherwise, the signals are tri-stated.
To minimize power dissipation, A0ÐA17 do not
change state when external memory spaces are
not being accessed.
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External Memory Expansion Port (Port A)
2.6.2
External Data Bus
External data bus signals for the DSP56309 are listed in Table 2-7.
Table 2-7 External Data Bus Signals
State
During
Reset
Signal
Name
Type
Signal Description
D0ÐD23
Input/
Output
weakly
driven by
bus keeper
Data BusÑWhen the DSP is the bus master,
D0ÐD23 are active-high, bidirectional
input/outputs that provide the bidirectional
data bus for external program and data
memory accesses. Otherwise, D0ÐD23 are
weakly driven by the bus keeper.
2.6.3
External Bus Control
External bus control signal descriptions for the DSP56309 are listed in Table 2-8.
Table 2-8 External Bus Control Signals
State
During
Reset
Signal
Name
Type
Signal Description
AA0Ð
Output Tri-stated
Address Attribute or Row Address StrobeÑWhen
defined as AA, these signals can be used as chip
selects or additional address lines. When defined as
RAS, these signals can be used as RAS for DRAM
interface. These signals are tri-statable outputs with
programmable polarity.
AA3/
RAS0Ð
RAS3
RD
Output Tri-stated
Output Tri-stated
Read EnableÑWhen the DSP is the bus master, RD
is an active-low output that is asserted to read
external memory on the data bus (D0ÐD23).
Otherwise, RD is tri-stated.
WR
Write EnableÑWhen the DSP is the bus master, WR
is an active-low output that is asserted to write
external memory on the data bus (D0ÐD23).
Otherwise, the signals are tri-stated.
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External Memory Expansion Port (Port A)
Table 2-8 External Bus Control Signals (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
TA
Input
Ignored
Input
Transfer AcknowledgeÑIf the DSP56309 is the bus
master and there is no external bus activity, or the
DSP56309 is not the bus master, the TA input is
ignored. The TA input is a data transfer
acknowledge (DTACK) function that can extend an
external bus cycle indefinitely. Any number of wait
states (1, 2,..., infinity) can be added to the wait states
inserted by the BCR by keeping TA deasserted. In
typical operation, TA is deasserted at the start of a
bus cycle, is asserted to enable completion of the bus
cycle, and is deasserted before the next bus cycle.
The current bus cycle completes one clock period
after TA is asserted synchronous to CLKOUT. The
number of wait states is determined by the TA input
or by the BCR, whichever is longer. The BCR can be
used to set the minimum number of wait states in
external bus cycles.
In order to use the TA functionality, the BCR must be
programmed to at least one wait state. A zero wait
state access cannot be extended by TA deassertion;
otherwise, improper operation can result. TA can
operate synchronously or asynchronously
depending on the setting of the TAS bit in the OMR.
You must not use TA functionality while performing
DRAM type accesses; otherwise, improper operation
can result.
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External Memory Expansion Port (Port A)
Table 2-8 External Bus Control Signals (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
BR
Output Output
Bus RequestÑBR is an active-low output, never
(deasserted) tri-stated. BR is asserted when the DSP requests bus
mastership. BR is deasserted when the DSP no
longer needs the bus. BR can be asserted or
deasserted independent of whether the DSP56309 is
a bus master or a bus slave. Bus ÒparkingÓ allows BR
to be deasserted even though the DSP56309 is the
bus master; see the description of bus ÒparkingÓ in
the BB signal description. The bus request hole
(BRH) bit in the BCR allows BR to be asserted under
software control even though the DSP does not need
the bus. BR is typically sent to an external bus
arbitrator that controls the priority, parking, and
tenure of each master on the same external bus. BR is
only affected by DSP requests for the external bus,
never for the internal bus. During hardware reset,
BR is deasserted and the arbitration is reset to the
bus slave state.
BG
Input
Ignored
Input
Bus GrantÑBG is an active-low input. BG must be
asserted/deasserted synchronous to CLKOUT for
proper operation. BG is asserted by an external bus
arbitration circuit when the DSP56309 becomes the
next bus master. When BG is asserted, the DSP56309
must wait until BB is deasserted before taking bus
mastership. When BG is deasserted, bus mastership
is typically given up at the end of the current bus
cycle. This can occur in the middle of an instruction
that requires more than one external bus cycle for
execution.
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External Memory Expansion Port (Port A)
Table 2-8 External Bus Control Signals (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
BB
Input/
Output
Input
Bus BusyÑBB is a bidirectional active-low
input/output and must be asserted and deasserted
synchronous to CLKOUT. BB indicates that the bus
is active. Only after BB is deasserted can the pending
bus master become the bus master (and then assert
the signal again). The bus master can keep BB
asserted after ceasing bus activity regardless of
whether BR is asserted or deasserted. This is called
Òbus parkingÓ and allows the current bus master to
reuse the bus without rearbitration until another
device requires the bus. The deassertion of BB is
done by an Òactive pull-upÓ method (i.e., BB is
driven high and then released and held high by an
external pull-up resistor).
BB requires an external pull-up resistor.
CAS
Output Tri-stated
Output Tri-stated
Column Address StrobeÑWhen the DSP is the bus
master, CAS is an active-low output used by DRAM
to strobe the column address. Otherwise, if the Bus
Mastership Enable (BME) bit in the DRAM Control
Register is cleared, the signal is tri-stated.
BCLK
Bus ClockÑWhen the DSP is the bus master, BCLK
is an active-high output. BCLK is active as a
sampling signal when the program address tracing
mode is enabled (by setting the ATE bit in the OMR).
When BCLK is active and synchronized to CLKOUT
by the internal PLL, BCLK precedes CLKOUT by 1/4
of a clock cycle. The BCLK rising edge can be used to
sample the internal program memory access on the
A0ÐA23 address lines.
BCLK
Output Tri-stated
Bus Clock NotÑWhen the DSP is the bus master,
BCLK is an active-low output and is the inverse of
the BCLK signal. Otherwise, the signal is tri-stated.
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Signal/Connection Descriptions
Interrupt and Mode Control
2.7
INTERRUPT AND MODE CONTROL
The interrupt and mode control signals select the chipÕs operating mode as it comes out
of hardware reset. After RESET is deasserted, these inputs are hardware interrupt
request lines.
Table 2-9 Interrupt and Mode Control
State
During
Reset
Signal Name
Type
Signal Description
RESET
Input
Input
ResetÑRESET is an active-low, Schmitt-trigger
input. Deassertion of RESET is internally
synchronized to the clock out (CLKOUT). When
asserted, the chip is placed in the Reset state and
the internal phase generator is reset. The
Schmitt-trigger input allows a slowly rising input
(such as a capacitor charging) to reset the chip
reliably. If RESET is deasserted synchronous to
CLKOUT, exact start-up timing is guaranteed,
allowing multiple processors to start
synchronously and operate together in lock-step.
When the RESET signal is deasserted, the initial
chip operating mode is latched from the MODA,
MODB, MODC, and MODD inputs. The RESET
signal must be asserted after power up.
MODA
IRQA
Input
Input
Mode Select AÑMODA is an active-low
Schmitt-trigger input, internally synchronized to
CLKOUT. MODA, MODB, MODC, and MODD
select one of 16 initial chip operating modes,
latched into the OMR when the RESET signal is
deasserted.
External Interrupt Request AÑAfter reset, this
signal becomes a level-sensitive or
negative-edge-triggered, maskable interrupt
request input during normal instruction
processing. If IRQA is asserted synchronous to
CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and
asserting IRQA to exit the wait state. If the
processor is in the stop standby state and IRQA is
asserted, the processor exits the stop state.
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Interrupt and Mode Control
Table 2-9 Interrupt and Mode Control (Continued)
State
During
Reset
Signal Name
Type
Signal Description
MODB
Input
Input
Mode Select BÑMODB is an active-low
Schmitt-trigger input, internally synchronized to
CLKOUT. MODA, MODB, MODC, and MODD
select one of 16 initial chip operating modes,
latched into OMR when the RESET signal is
deasserted.
IRQB
External Interrupt Request BÑAfter hardware
reset, this signal becomes a level-sensitive or
negative-edge-triggered, maskable interrupt
request input during normal instruction
processing. If IRQB is asserted synchronous to
CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and
asserting IRQB to exit the wait state.
MODC
IRQC
Input
Input
Mode Select CÑMODC is an active-low
Schmitt-trigger input, internally synchronized to
CLKOUT. MODA, MODB, MODC, and MODD
select one of 16 initial chip operating modes,
latched into OMR when the RESET signal is
deasserted.
External Interrupt Request CÑAfter hardware
reset, this signal becomes a level-sensitive or
negative-edge-triggered, maskable interrupt
request input during normal instruction
processing. If IRQC is asserted synchronous to
CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and
asserting IRQC to exit the wait state.
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Signal/Connection Descriptions
Host Interface (HI08)
Table 2-9 Interrupt and Mode Control (Continued)
State
During
Reset
Signal Name
Type
Signal Description
MODD
Input
Input
Mode Select DÑMODD is an active-low
Schmitt-trigger input, internally synchronized to
CLKOUT. MODA, MODB, MODC, and MODD
select one of 16 initial chip operating modes,
latched into OMR when the RESET signal is
deasserted.
IRQD
External Interrupt Request DÑAfter hardware
reset, this signal becomes a level-sensitive or
negative-edge-triggered, maskable interrupt
request input during normal instruction
processing. If IRQD is asserted synchronous to
CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and
asserting IRQD to exit the wait state.
2.8
HOST INTERFACE (HI08)
The HI08 provides a fast parallel 8-bit port, which can connect directly to the host bus.
The HI08 supports a variety of standard buses and can be directly connected to a
number of industry standard microcomputers, microprocessors, DSPs, and DMA
hardware.
2.8.1
Host Port Usage Considerations
When reading multiple-bit registers that are written by another asynchronous system,
you must synchronize carefully. This problem commonly occurs when two
asynchronous systems are connected (as they are in the host port). The considerations
for proper operation are discussed in Table 2-10.
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Host Interface (HI08)
Table 2-10 Host Port Usage Considerations
Action
Description
Asynchronous read of
receive byte registers
When reading the receive byte registers, receive register high
(RXH), receive register middle (RXM), or receive register low
(RXL), use interrupts or poll the receive register data full
(RXDF) flag which indicates that data is available. This assures
that the data in the receive byte registers is valid.
Asynchronous write to
transmit byte registers
Do not write to the transmit byte registers, transmit register
high (TXH), transmit register middle (TXM), or transmit
register low (TXL), unless the transmit register data empty
(TXDE) bit is set indicating that the transmit byte registers are
empty. This guarantees that the transmit byte registers transfer
valid data to the host receive (HRX) register.
Asynchronous write to
host vector
Change the host vector (HV) register only when the host
command bit (HC) is clear. This guarantees that the DSP
interrupt control logic receives a stable vector.
2.8.2
Host Port Configuration
The functions of the signals associated with the HI08 vary according to the programmed
configuration of the interface as determined by the HI08 Port Control Register (HPCR).
Refer to Section 6ÑHost Interface (HI08) for detailed descriptions of this and the other
configuration registers used with the HI08.
Host interface signal descriptions for the DSP56309 are listed in Table 2-11.
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Host Interface (HI08)
Table 2-11 Host Interface
State
During
Reset
Signal
Name
Type
Signal Description
H0ÐH7
Input/
Output
Tri-stated
Host DataÑWhen the HI08 is programmed
to interface a non-multiplexed host bus and
the HI function is selected, these signals are
lines 0Ð7 of the data bidirectional, tri-state
bus.
HAD0Ð
HAD7
Input/
Output
Host AddressÑWhen HI08 is programmed
to interface a multiplexed host bus and the
HI function is selected, these signals are lines
0Ð7 of the address/data bidirectional,
multiplexed, tri-state bus.
Input or
Output
PB0ÐPB7
Port B 0Ð7ÑWhen the HI08 is configured as
GPIO through the HPCR, these signals are
individually programmed as inputs or
outputs through the HI08 data direction
register (HDDR).
HA0
Input
Input
Input
Host Address Input 0ÑWhen the HI08 is
programmed to interface a non-multiplexed
host bus and the HI function is selected, this
signal is line 0 of the host address input bus.
HAS/HAS
Host Address StrobeÑWhen HI08 is
programmed to interface a multiplexed host
bus and the HI function is selected, this
signal is the host address strobe (HAS)
Schmitt-trigger input. The polarity of the
address strobe is programmable but is
configured active-low (HAS) following reset.
PB8
Input or
Output
Port B 8ÑWhen the HI08 is configured as
GPIO through the HPCR, this signal is
individually programmed as an input or
output through the HDDR.
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Host Interface (HI08)
Table 2-11 Host Interface (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
HA1
Input
Input
Host Address Input 1ÑWhen the HI08 is
programmed to interface a non-multiplexed
host bus and the HI function is selected, this
signal is line 1 of the host address (HA1)
input bus.
HA8
Input
Host Address 8ÑWhen HI08 is programmed
to interface a multiplexed host bus and the
HI function is selected, this signal is line 8 of
the host address (HA8) input bus.
PB9
Input or
Output
Port B 9ÑWhen the HI08 is configured as
GPIO through the HPCR, this signal is
individually programmed as an input or
output through the HDDR.
HA2
Input
Input
Input
Host Address Input 2ÑWhen the HI08 is
programmed to interface a non-multiplexed
host bus and the HI function is selected, this
signal is line 2 of the host address (HA2)
input bus.
HA9
PB10
Host Address 9ÑWhen HI08 is programmed
to interface a multiplexed host bus and the
HI function is selected, this signal is line 9 of
the host address (HA9) input bus.
Input or
Output
Port B 10ÑWhen the HI08 is configured as
GPIO through the HPCR, this signal is
individually programmed as an input or
output through the HDDR.
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Host Interface (HI08)
Table 2-11 Host Interface (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
HRW
Input
Input
Host Read/WriteÑWhen HI08 is
programmed to interface a single-data-strobe
host bus and the HI function is selected, this
signal is the host read/write (HRW) input.
HRD/HRD
Input
Host Read DataÑWhen HI08 is
programmed to interface a
double-data-strobe host bus and the HI
function is selected, this signal is the host
read data strobe (HRD) Schmitt-trigger
input. The polarity of the data strobe is
programmable, but is configured as
active-low (HRD) after reset.
PB11
Input or
Output
Port B 11ÑWhen the HI08 is configured as
GPIO through the HPCR, this signal is
individually programmed as an input or
output through the HDDR.
HDS/HDS
Input
Input
Host Data StrobeÑWhen HI08 is
programmed to interface a single-data-strobe
host bus and the HI function is selected, this
signal is the host data strobe (HDS)
Schmitt-trigger input. The polarity of the
data strobe is programmable, but is
configured as active-low (HDS) following
reset.
HWR/
HWR
Input
Host Write DataÑWhen HI08 is
programmed to interface a
double-data-strobe host bus and the HI
function is selected, this signal is the host
write data strobe (HWR) Schmitt-trigger
input. The polarity of the data strobe is
programmable, but is configured as
active-low (HWR) following reset.
Input or
Output
PB12
Port B 12ÑWhen the HI08 is configured as
GPIO through the HPCR, this signal is
individually programmed as an input or
output through the HDDR.
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Host Interface (HI08)
Table 2-11 Host Interface (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
HCS
Input
Input
Host Chip SelectÑWhen HI08 is
programmed to interface a non-multiplexed
host bus and the HI function is selected, this
signal is the host chip select (HCS) input. The
polarity of the chip select is programmable,
but is configured active-low (HCS) after
reset.
HA10
PB13
Input
Host Address 10ÑWhen HI08 is
programmed to interface a multiplexed host
bus and the HI function is selected, this
signal is line 10 of the host address (HA10)
input bus.
Input or
Output
Port B 13ÑWhen the HI08 is configured as
GPIO through the HPCR, this signal is
individually programmed as an input or
output through the HDDR.
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Host Interface (HI08)
Table 2-11 Host Interface (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
HREQ/
HREQ
Output
Output
Input
Host RequestÑWhen HI08 is programmed
to interface a single host request host bus and
the HI function is selected, this signal is the
host request (HREQ) output. The polarity of
the host request is programmable, but is
configured as active-low (HREQ) following
reset. The host request can be programmed
as a driven or open-drain output.
HTRQ/
HTRQ
Transmit Host RequestÑWhen HI08 is
programmed to interface a double host
request host bus and the HI function is
selected, this signal is the transmit host
request (HTRQ) output. The polarity of the
host request is programmable, but is
configured as active-low (HTRQ) following
reset. The host request can be programmed
as a driven or open-drain output.
PB14
Input or
Output
Port B 14ÑWhen the HI08 is programmed to
interface a multiplexed host bus and the
signal is configured as GPIO through the
HPCR, this signal is individually
programmed as an input or output through
the HDDR.
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Host Interface (HI08)
Table 2-11 Host Interface (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
HACK/
HACK
Input
Input
Host AcknowledgeÑWhen HI08 is
programmed to interface a single host
request host bus and the HI function is
selected, this signal is the host acknowledge
(HACK) Schmitt-trigger input. The polarity
of the host acknowledge is programmable,
but is configured as active-low (HACK) after
reset.
HRRQ/
HRRQ
Output
Receive Host RequestÑWhen HI08 is
programmed to interface a double host
request host bus and the HI function is
selected, this signal is the receive host request
(HRRQ) output. The polarity of the host
request is programmable, but is configured
as active-low (HRRQ) after reset. The host
request can be programmed as a driven or
open-drain output.
Input or
Output
PB15
Port B 15ÑWhen the HI08 is configured as
GPIO through the HPCR, this signal is
individually programmed as an input or
output through the HDDR.
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Signal/Connection Descriptions
Enhanced Synchronous Serial Interface
2.9
ENHANCED SYNCHRONOUS SERIAL INTERFACE
Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for
serial communication with a variety of serial devices, including one or more
industry-standard codecs, other DSPs, microprocessors, and peripherals which
implement the Motorola SPI.
2.9.1
ESSI0
The ESSI0 signal descriptions for the DSP56309 are listed in Table 2-12.
Table 2-12 Enhanced Synchronous Serial Interface 0 (ESSI0)
State
During
Reset
Signal
Name
Type
Signal Description
SC00
Input or
Output
Input
Serial Control 0ÑThe function of SC00 is
determined by the selection of either
synchronous or asynchronous mode. For
asynchronous mode, this signal is used for
the receive clock I/O (Schmitt-trigger input).
For synchronous mode, this signal is used
either for Transmitter 1 output or for Serial
I/O Flag 0.
This signal is driven by a weak keeper after
reset.
PC0
Port C 0ÑThe default configuration
following reset is GPIO input PC0. When this
port is configured as PC0, signal direction is
controlled through the Port C direction
register (PRR0). The signal can be configured
as ESSI signal SC00 through the Port C
control register (PCR0).
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Enhanced Synchronous Serial Interface
Table 2-12 Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
SC01
Input/
Output
Input
Serial Control 1ÑThe function of this signal
is determined by the selection of either
synchronous or asynchronous mode. For
Asynchronous mode, this signal is the
receiver frame sync I/O. For synchronous
mode, this signal is used either for
Transmitter 2 output or for Serial I/O Flag 1.
This signal is driven by a weak keeper after
reset.
PC1
Input or
Output
Port C 1ÑThe default configuration
following reset is GPIO input PC1. When this
port is configured as PC1, signal direction is
controlled through PRR0. The signal can be
configured as an ESSI signal SC01 through
PCR0.
SC02
Input/
Output
Input
Serial Control Signal 2ÑSC02 is used for
frame sync I/O. SC02 is the frame sync for
both the transmitter and receiver in
synchronous mode and for the transmitter
only in asynchronous mode. When
configured as an output, this signal is the
internally generated frame sync signal. When
configured as an input, this signal receives an
external frame sync signal for the transmitter
(and the receiver in synchronous operation).
This signal is driven by a weak keeper after
reset.
PC2
Input or
Output
Port C 2ÑThe default configuration
following reset is GPIO input PC2. When this
port is configured as PC2, signal direction is
controlled through PRR0. The signal can be
configured as an ESSI signal SC02 through
PCR0.
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Signal/Connection Descriptions
Enhanced Synchronous Serial Interface
Table 2-12 Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
SCK0
Input/
Output
Input
Serial ClockÑSCK0 is a bidirectional
Schmitt-trigger input signal providing the
serial bit rate clock for the ESSI interface. The
SCK0 is a clock input or output used by both
the transmitter and receiver in synchronous
modes or by the transmitter in asynchronous
modes.
Although an external serial clock can be
independent of and asynchronous to the DSP
system clock, it must exceed the minimum
clock cycle time of 6 T (i.e., the system clock
frequency must be at least three times the
external ESSI clock frequency). The ESSI
needs at least three DSP phases inside each
half of the serial clock.
This signal is driven by a weak keeper after
reset.
PC3
Input or
Output
Port C 3ÑThe default configuration
following reset is GPIO input PC3. When this
port is configured as PC3, signal direction is
controlled through PRR0. The signal can be
configured as an ESSI signal SCK0 through
PCR0.
SRD0
Input/
Output
Input
Serial Receive DataÑSRD0 receives serial
data and transfers the data to the ESSI receive
shift register. SRD0 is an input when data is
being received.
This signal is driven by a weak keeper after
reset.
PC4
Input or
Output
Port C 4ÑThe default configuration
following reset is GPIO input PC4. When this
port is configured as PC4, signal direction is
controlled through PRR0. The signal can be
configured as an ESSI signal SRD0 through
PCR0.
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Signal/Connection Descriptions
Enhanced Synchronous Serial Interface
Table 2-12 Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
STD0
Input/
Output
Input
Serial Transmit DataÑSTD0 is used for
transmitting data from the serial Transmit
shift register. STD0 is an output when data is
being transmitted.
This signal is driven by a weak keeper after
reset.
PC5
Input or
Output
Port C 5ÑThe default configuration
following reset is GPIO input PC5. When this
port is configured as PC5, signal direction is
controlled through PRR0. The signal can be
configured as an ESSI signal STD0 through
PCR0.
2.9.2
ESSI1
The ESSI1 signal descriptions for the DSP56309 are listed in Table 2-13.
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Enhanced Synchronous Serial Interface
Table 2-13 Enhanced Synchronous Serial Interface 1 (ESSI1)
State
During
Reset
Signal
Name
Type
Signal Description
SC10
Input or
Output
Input
Serial Control 0ÑThe function of SC10 is
determined by the selection of either
synchronous or asynchronous mode. For
asynchronous mode, this signal is used for
the receive clock I/O (Schmitt-trigger input).
For synchronous mode, this signal is used
either for Transmitter 1 output or for Serial
I/O Flag 0.
This signal is driven by a weak keeper after
reset.
PD0
Port D 0ÑThe default configuration
following reset is GPIO input PD0. When this
port is configured as PD0, signal direction is
controlled through the Port D direction
register (PRR1). The signal can be configured
as an ESSI signal SC10 through the Port D
control register (PCR1).
SC11
Input/
Output
Input
Serial Control 1ÑThe function of this signal
is determined by the selection of either
synchronous or asynchronous mode. For
asynchronous mode, this signal is the
receiver frame sync I/O. For synchronous
mode, this signal is used either for
Transmitter 2 output or for Serial I/O Flag 1.
This signal is driven by a weak keeper after
reset.
PD1
Input or
Output
Port D 1ÑThe default configuration
following reset is GPIO input PD1. When this
port is configured as PD1, signal direction is
controlled through PRR1. The signal can be
configured as an ESSI signal SC11 through
PCR1.
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Signal/Connection Descriptions
Enhanced Synchronous Serial Interface
Table 2-13 Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
SC12
Input/
Output
Input
Serial Control Signal 2ÑSC12 is used for
frame sync I/O. SC12 is the frame sync for
both the transmitter and receiver in
synchronous mode and for the transmitter
only in asynchronous mode. When
configured as an output, this signal is the
internally generated frame sync signal. When
configured as an input, this signal receives an
external frame sync signal for the transmitter.
The receiver receives an external frame sync
signal as well when in synchronous
operation).
This signal is driven by a weak keeper after
reset.
PD2
Input or
Output
Port D 2ÑThe default configuration
following reset is GPIO input PD2. When this
port is configured as PD2, signal direction is
controlled through PRR1. The signal can be
configured as an ESSI signal SC12 through
PCR1.
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Enhanced Synchronous Serial Interface
Table 2-13 Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
SCK1
Input/
Output
Input
Serial ClockÑSCK1 is a bidirectional
Schmitt-trigger input signal providing the
serial bit rate clock for the ESSI interface. The
SCK1 is a clock input or output used by both
the transmitter and receiver in synchronous
modes or by the transmitter in asynchronous
modes.
Although an external serial clock can be
independent of and asynchronous to the DSP
system clock, it must exceed the minimum
clock cycle time of 6T (i.e., the system clock
frequency must be at least three times the
external ESSI clock frequency). The ESSI
needs at least three DSP phases inside each
half of the serial clock.
This signal is driven by a weak keeper after
reset.
PD3
Input or
Output
Port D 3ÑThe default configuration
following reset is GPIO input PD3. When this
port is configured as PD3, signal direction is
controlled through PRR1. The signal can be
configured as an ESSI signal SCK1 through
PCR1.
SRD1
Input/
Output
Input
Serial Receive DataÑSRD1 receives serial
data and transfers the data to the ESSI receive
shift register. SRD1 is an input when data is
being received.
This signal is driven by a weak keeper after
reset.
PD4
Input or
Output
Port D 4ÑThe default configuration
following reset is GPIO input PD4. When this
port is configured as PD4, signal direction is
controlled through PRR1. The signal can be
configured as an ESSI signal SRD1 through
PCR1.
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Signal/Connection Descriptions
Enhanced Synchronous Serial Interface
Table 2-13 Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
STD1
Input/
Output
Input
Serial Transmit DataÑSTD1 is used for
transmitting data from the serial transmit
shift register. STD1 is an output when data is
being transmitted.
This signal is driven by a weak keeper after
reset.
PD5
Input or
Output
Port D 5ÑThe default configuration
following reset is GPIO input PD5. When this
port is configured as PD5, signal direction is
controlled through PRR1. The signal can be
configured as an ESSI signal STD1 through
PCR1.
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Signal/Connection Descriptions
Serial Communication Interface (SCI)
2.10 SERIAL COMMUNICATION INTERFACE (SCI)
SCI provides a full duplex port for serial communication to other DSPs, microprocessors,
or peripherals such as modems. SCI signal descriptions are listed in Table 2-14.
Table 2-14 Serial Communication Interface (SCI)
State
During
Reset
Signal
Name
Type
Signal Description
RXD
Input
Input
Serial Receive DataÑThis input receives
byte oriented serial data and transfers it to
the SCI receive shift register.
This signal is driven by a weak keeper after
reset.
PE0
Input or
Output
Port E 0ÑThe default configuration
following reset is GPIO input PE0. When this
port is configured as PE0, signal direction is
controlled through the SCI Port E direction
register (PRR). The signal can be configured
as an SCI signal RXD through the SCI Port E
control register (PCR).
TXD
PE1
Output
Input
Serial Transmit DataÑThis signal transmits
data from SCI transmit data register.
This signal is driven by a weak keeper after
reset.
Input or
Output
Port E 1ÑThe default configuration
following reset is GPIO input PE1. When this
port is configured as PE1, signal direction is
controlled through the SCI PRR. The signal
can be configured as an SCI signal TXD
through the SCI PCR.
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Signal/Connection Descriptions
Timers
Table 2-14 Serial Communication Interface (SCI) (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
SCLK
Input/
Output
Input
Serial ClockÑThis is the bidirectional
Schmitt-trigger input signal providing the
input or output clock used by the transmitter
and/or the receiver.
This signal is driven by a weak keeper after
reset.
PE2
Input or
Output
Port E 2ÑThe default configuration
following reset is GPIO input PE2. When this
port is configured as PE2, signal direction is
controlled through the SCI PRR. The signal
can be configured as an SCI signal SCLK
through the SCI PCR.
2.11 TIMERS
Three identical and independent timers are implemented in the DSP56309. Each timer
can use internal or external clocking; each timer can interrupt the DSP56309 after a
specified number of events (clocks) or can signal an external device after counting a
specific number of internal events. Triple timer signal descriptions are listed in
Table 2-15.
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Signal/Connection Descriptions
Timers
Table 2-15 Triple Timer Signals
State
During
Reset
Signal
Name
Type
Signal Description
TIO0
Input or
Output
Input
Timer 0 Schmitt-Trigger Input/OutputÑ
When timer 0 functions as an external event
counter or in measurement mode, TIO0 is
used as input. When timer 0 functions in
watchdog, timer, or pulse modulation mode,
TIO0 is used as output.
This signal is driven by a weak keeper after
reset.
The default mode after reset is GPIO input.
This can be changed to output or configured
as a timer input/output through the timer 0
control/status register (TCSR0).
TIO1
Input or
Output
Input
Timer 1 Schmitt-Trigger Input/OutputÑ
When Timer 1 functions as an external event
counter or in measurement mode, TIO1 is
used as input. When timer 1 functions in
watchdog, timer, or pulse modulation mode,
TIO1 is used as output.
This signal is driven by a weak keeper after
reset.
The default mode after reset is GPIO input.
This can be changed to output or configured
as a timer input/output through the timer 1
control/status register (TCSR1).
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Signal/Connection Descriptions
OnCE/JTAG Interface
Table 2-15 Triple Timer Signals (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
TIO2
Input or
Output
Input
Timer 2 Schmitt-Trigger Input/OutputÑ
When Timer 2 functions as an external event
counter or in measurement mode, TIO2 is
used as input. When timer 2 functions in
watchdog, timer, or pulse modulation mode,
TIO2 is used as output.
This signal is driven by a weak keeper after
reset.
The default mode after reset is GPIO input.
This can be changed to output or configured
as a timer input/output through the timer 2
control/status register (TCSR2).
2.12 OnCE/JTAG INTERFACE
OnCE/JTAG interface signal descriptions are listed in Table 2-16.
Table 2-16 OnCE/JTAG Interface
State
During
Reset
Signal
Name
Type
Signal Description
TCK
Input
Input
Test ClockÑTCK is a test clock input signal
used to synchronize the JTAG test logic. Its
pin has a pull-up resistor.
TDI
Input
Input
Test Data InputÑTDI is a test data serial
input signal used for test instructions and
data. TDI is sampled on the rising edge of
TCK and has an internal pull-up resistor.
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OnCE/JTAG Interface
Table 2-16 OnCE/JTAG Interface (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
TDO
Output
Tri-stated
Test Data OutputÑTDO is a test data serial
output signal used for test instructions and
data. TDO is tri-statable and is actively
driven in the shift-IR and shift-DR controller
states. TDO changes on the falling edge of
TCK.
TMS
Input
Input
Input
Input
Test Mode SelectÑTMS is an input signal
used to sequence the test controllerÕs state
machine. TMS is sampled on the rising edge
of TCK and has an internal pull-up resistor.
TRST
Test ResetÑTRST is an active-low
Schmitt-trigger input signal used to
asynchronously initialize the test controller.
TRST has an internal pull-up resistor. TRST
must be asserted after power up.
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OnCE/JTAG Interface
Table 2-16 OnCE/JTAG Interface (Continued)
State
During
Reset
Signal
Name
Type
Signal Description
DE
Input/
Output
Input
Debug EventÑDE is an open-drain,
bidirectional, active-low signal providing, as
an input, a means of entering debug mode of
operation from an external command
controller, and as an output, a means of
acknowledging that the chip has entered
debug mode. This signal, when asserted as
an input, causes the DSP56300 core to finish
the current instruction being executed, save
the instruction pipeline information, enter
debug mode, and wait for commands to be
entered from the debug serial input line. This
signal is asserted as an output for three clock
cycles when the chip enters debug mode as a
result of a debug request or as a result of
meeting a breakpoint condition. The DE has
an internal pull-up resistor.
This is not a standard part of the JTAG TAP
controller. The signal connects directly to the
OnCE module to initiate debug mode
directly or to provide a direct external
indication that the chip has entered debug
mode. All other interfacing with the OnCE
module must occur through the JTAG port.
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OnCE/JTAG Interface
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SECTION 3
MEMORY CONFIGURATION
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Memory Configuration
3.1
3.2
3.3
3.4
3.5
MEMORY SPACES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
RAM CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
MEMORY CONFIGURATIONS. . . . . . . . . . . . . . . . . . . . . . . 3-7
MEMORY MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
INTERNAL I/O MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . 3-18
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Memory Configuration
Memory Spaces
3.1
MEMORY SPACES
The DSP56309 provides three independent memory spaces:
¥ Program
¥ X data
¥ Y data
Each memory space uses 24-bit addressing by default. The program and data word
length is 24 bits. Moreover, this device supports remapping address attribute registers
Òon the fly,Ó thus allowing access to 16 M of memory.
The DSP56309 provides a sixteen-bit compatibility mode that effectively uses 16-bit
addressing for each memory space, allowing access to 64K each of memory. This mode
puts zeroes in the most significant byte of the usual (24-bit) program and data word; it
ignores the zeroed byte, thus effectively using 16-bit program and data words. The
sixteen-bit compatibility mode allows the DSP56309 to use 56000 object code without
change, thus minimizing system cost for applications that use the smaller address space.
See the DSP56300 Family Manual for further information.
3.1.1
Program Memory Space
Program memory space consists of the following:
¥ Internal program memory (Program RAM, 20K by default)
¥ Bootstrap Program ROM (192 x 24-bit)
¥ (Optionally) off-chip memory expansion (as much as 16 M in 24-bit mode and
64K in 16-bit mode)
¥ (Optionally) instruction cache (1K) formed from Program RAM
Program memory space at locations $FF00C0 to $FFFFFF is reserved and should not be
accessed.
3.1.2
Data Memory Spaces
Data memory space is divided into X data memory and Y data memory to match the
natural partitioning of DSP algorithms. The data memory partitioning allows the
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Memory Configuration
Memory Spaces
DSP56309 to feed two operands to the Data ALU simultaneously, enabling it to perform
a multiply-accumulate operation in one clock cycle.
X and Y data memory are identical in structure and functionality except for the upper
128 words of each space. The upper 128 words of X data memory are reserved for
internal I/O. We recommend that the programmer reserve the upper 128 words of Y
data memory for external I/O. (For further information, see Section 3.1.2.1 X Data
Memory Space and Section 3.1.2.2 Y Data Memory Space.)
X and Y data memory space each consist of the following:
¥ Internal data memory (X data RAM and Y data RAM, the default size of each is
7K, but they can be switched to 5K each)
¥ (Optionally) Off-chip memory expansion (up to 16 M in the 24-bit address mode
and 64K in the 16-bit address mode)
3.1.2.1
X Data Memory Space
The on-chip peripheral registers and some of the DSP56309 core registers occupy the top
128 locations of X data memory ($FFFF80Ð$FFFFFF in the 24-bit Address mode or
$FF80Ð$FFFF in the 16-bit Address mode). This area is called X-I/O space, and it can be
accessed by MOVE and MOVEP instructions and by bit oriented instructions (BCHG,
BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR, and JSSET). For
a listing of the contents of this area, see the programming sheets in
Appendix DÑProgramming Reference.
The X memory space at locations $FF0000 to $FFEFFF is reserved and should not be
accessed by the programmer.
3.1.2.2
Y Data Memory Space
The off-chip peripheral registers should be mapped into the top 128 locations of Y data
memory ($FFFF80Ð$FFFFFF in the 24-bit address mode or $FF80Ð$FFFF in the 16-bit
address mode) to take advantage of the move peripheral data (MOVEP) instruction and
the bit oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET,
JCLR, JSET, JSCLR, and JSSET).
The Y memory space at locations $FF0000 to $FFEFFF is reserved and should not be
accessed by the programmer.
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Memory Configuration
RAM Configuration
3.1.3
Memory Space Configuration
Memory space addressing is 24-bit by default. The DSP56309 switches to sixteen-bit
address compatibility mode by setting the sixteen-bit compatibility (SC) bit in the Status
Register (SR).
Table 3-1 Memory Space Configuration Bit Settings for the DSP56309
Bit
Cleared = 0
Effect (Default)
Bit Name
Bit Location
Set = 1 Effect
Abbreviation
SC
Sixteen-bit
Compatibility
SR 13
16M word
address space
64K word
address space
(24-bit address) (16-bit address)
Memory maps for the different configurations are shown in Figure 3-1 through
Figure 3-8.
3.2
RAM CONFIGURATION
The DSP56309 contains 34K of RAM, divided by default into the following:
¥ Program RAM (20K)
¥ X data RAM (7K)
¥ Y data RAM (7K)
RAM configuration depends on two bits: the Cache Enable (CE) of the SR and the
Memory Select (MS) of the Operating Mode Register (OMR).
Table 3-2 RAM Configuration Bit Settings for the DSP56309
Bit
Bit
Location
Cleared = 0 Effect
(Default)
Bit Name
Set = 1 Effect
Abbreviation
CE
Cache
Enable
SR 19
Cache Disabled
Cache Enabled
1K
MS
Memory
Switch
OMR 7
Program RAM 20K Program RAM 24K
X data RAM 7K
Y data RAM 7K
X data RAM 5K
Y data RAM 5K
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Memory Configuration
RAM Configuration
Memory maps for the different configurations are shown in Figure 3-1 through
Figure 3-8.
Note:
The MS bit cannot be changed when CE is set. The instruction cache occupies
the top 1K of what would otherwise be Program RAM; if you switch memory
into or out of Program RAM when the cache is enabled, the switch causes
conflicts. To change the MS bit when CE is set, do the following:
1. Clear CE.
2. Change MS.
3. Set CE.
3.2.1
On-Chip Program Memory (Program RAM)
The on-chip Program RAM consists of 24-bit wide, high-speed, internal Static RAM
occupying the lowest 20K (default), 23K, 24K, or 19K locations in the program memory
space (depending on the settings of the MS and CE bits). The Program RAM default
organization is 80 banks of 256 24-bit words (20K). The upper eight banks of both X data
RAM and Y data RAM can be configured as Program RAM by setting the MS bit. When
the CE is set, the upper 1K of Program RAM is used as an internal Instruction Cache.
CAUTION
While the contents of Program RAM are unaffected by toggling the
MS bit, the location of program data placed in the Program
RAM/Instruction Cache area changes after the MS bit is toggled, since
the cache always occupies the top-most 1K Program RAM addresses.
To preserve program data integrity, do not set or clear the MS bit
when the CE bit is set. See Section 3.2 on page 3-5 for the correct
procedure.
3.2.2
On-Chip X Data Memory (X Data RAM)
The on-chip X data RAM consists of 24-bit wide, high-speed, internal Static RAM
occupying the lowest 7K (default) or 5K locations in the X memory space. The size of the
X data RAM depends on the setting of the MS bit (default: MS is cleared). The X data
RAM default organization is 28 banks of 256 (7K) 24-bit words. Eight banks of RAM can
be switched from the X data RAM to the Program RAM by setting the MS bit (leaving 5K
of X data RAM).
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Memory Configuration
Memory Configurations
3.2.3
On-Chip Y Data Memory (Y Data RAM)
The on-chip Y data RAM consists of 24-bit wide, high-speed, internal Static RAM
occupying the lowest 7K (default) or 5K locations in the Y memory space. The size of the
Y data RAM is dependent on the setting of the MS bit (default: MS is cleared). The Y data
RAM default organization is 28 banks of 256 (7K) 24-bit words. Eight banks of RAM can
be switched from the Y data RAM to the Program RAM by setting the MS bit (leaving 5K
of Y data RAM).
3.2.4
Bootstrap ROM
The bootstrap code is accessed at addresses $FF0000 to $FFF0BF (192 words) in program
memory space. The bootstrap ROM cannot be accessed in 16-bit address compatibility
mode. See Appendix AÑBootstrap Programs for a complete listing of the bootstrap
code.
3.3
MEMORY CONFIGURATIONS
Memory configuration determines the size and address range for addressable memory,
as well as the amount of memory allocated to Program RAM, data RAM, and the
instruction cache.
3.3.1
Memory Space Configurations
The memory space configurations are listed in Table 3-3.
Table 3-3 Memory Space Configurations for the DSP56309
SC Bit
Setting
Addressable
Memory Size
Number of
Address Bits
Address Range
0
1
16M words
64K words
$000000Ð
$FFFFFF
24
16
$0000Ð$FFFF
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Memory Configuration
Memory Configurations
3.3.2
RAM Configurations
The RAM configurations for the DSP56309 appear in Table 3-4.
Table 3-4 RAM Configurations for the DSP56309
Bit Settings
Memory Sizes (in K)
Program
RAM
X data
RAM
Y data
RAM
MS
CE
Cache
0
0
1
1
0
1
0
1
20
19
24
23
7
7
5
5
7
7
5
5
0
1
0
1
The actual memory locations for Program RAM and the instruction cache in the Program
memory space are determined by the MS and CE bits. Their addresses appear in
Table 3-5.
Table 3-5 Memory Locations for Program RAM and Instruction Cache
Program RAM
MS
CE
Cache Location
Location
0
0
1
1
0
1
0
1
$0000Ð$4FFF
$0000Ð$4BFF
$0000Ð$5FFF
$0000Ð$5BFF
N/A
$4C00Ð$4FFF
N/A
$5C00Ð$5FFF
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Memory Configuration
Memory Maps
The actual memory locations for both X and Y data RAM in their own memory space are
determined by the MS bit. Their addresses appear in Table 3-6.
Table 3-6 Memory Locations for Data RAM
Data RAM
Location
MS
0
1
$0000Ð$1BFF
$0000Ð$13FF
3.4
MEMORY MAPS
Figure 3-1 through Figure 3-8 illustrate each of the memory space and RAM
configurations defined by the settings of the SC, MS, and CE bits. The figures show the
configuration, and the accompanying tables show the bit settings, memory sizes, and
memory locations.
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Memory Configuration
Memory Maps
Program
X Data
Y Data
$FFFFFF
$FFFFFF
$FFFF80
$FFFFFF
$FFFF80
Internal I/O
External
External I/O
External
$FFF000
$FFF000
Internal
Reserved
Internal
Reserved
Internal
Reserved
$FFF0C0
$FF0000
Bootstrap ROM
External
$FF0000
$FF0000
External
External
$005000
Internal
Program RAM
20K
$001C00
$000000
$001C00
$000000
Internal
X data RAM
7K
Internal
Y data RAM
7K
$000000
Bit Settings
Memory Configuration
X Data RAM Y Data RAM Cache
7K 7K None
Program
RAM
Addressable
Memory Size
SC MS CE
0
0
0
20K
16M
$0000Ð$4FFF $0000Ð$1BFF $0000Ð$1BFF
AA0557
Figure 3-1 Default Settings (0, 0, 0)
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Memory Configuration
Memory Maps
Program
X Data
Y Data
$FFFFFF
$FFFF80
$FFF000
$FFFFFF
$FFFF80
$FFF000
$FFFFFF
Internal I/O
External
External I/O
External
Internal
Reserved
Internal
Reserved
Internal
Reserved
$FFF0C0
$FF0000
Bootstrap ROM
External
$FF0000
$FF0000
External
External
$005000
$004C00
I-Cache
1K
$001C00
$000000
$001C00
$000000
Internal
Program RAM
19K
Internal
X data RAM
7K
Internal
Y data RAM
7K
$000000
Bit Settings
Memory Configuration
Program
RAM
X Data
RAM
Y Data
RAM
Addressable
Memory Size
SC MS CE
Cache
0
0
1
19K
$0000Ð
$4BFF
7K
$0000Ð
$1BFF
7K
$0000Ð
$1BFF
1K
$4C00Ð
$4FFF
16 M
AA0561
Figure 3-2 Instruction Cache Enabled (0, 0, 1)
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Memory Configuration
Memory Maps
Program
X Data
Y Data
$FFFFFF
$FFFFFF
$FFFF80
$FFF000
$FFFFFF
$FFFF80
$FFF000
Internal I/O
External
External I/O
External
Internal
Reserved
Internal
Reserved
Internal
Reserved
$FFF0C0
$FF0000
Bootstrap ROM
External
$FF0000
$FF0000
External
External
$001400
$000000
$001400
$000000
$006000
$000000
Internal
X data RAM
5K
Internal
Y data RAM
5K
Internal
Program RAM
24K
Bit Settings
Memory Configuration
Program
RAM
X Data
RAM
Y Data
RAM
Addressable
Memory Size
SC MS CE
Cache
0
1
0
24K
$0000Ð
$5FFF
5K
$0000Ð
$13FF
5K
$0000Ð
$13FF
None
16 M
AA0559
Figure 3-3 Switched Program RAM (0, 1, 0)
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Memory Configuration
Memory Maps
Program
X Data
Y Data
$FFFFFF
$FFFFFF
$FFFF80
$FFFFFF
$FFFF80
Internal I/O
External
External I/O
External
$FFF000
$FFF000
Internal
Reserved
Internal
Reserved
Internal
Reserved
$FFF0C0
$FF0000
Bootstrap ROM
External
$FF0000
$001400
$FF0000
$001400
External
External
$006000
$005C00
I-Cache
1K
Internal
Program
RAM 23K
Internal
X data RAM
5K
Internal
Y data RAM
5K
$000000
$000000
$000000
Bit Settings
Memory Configuration
Program
RAM
X Data
RAM
Y Data
RAM
Addressable
Memory Size
SC MS CE
Cache
0
1
1
23K
$0000Ð
$5BFF
5K
$0000Ð
$13FF
5K
$0000Ð
$13FF
1K
$5C00Ð
$5FFF
16 M
AA0563
Figure 3-4 Switched Program RAM and Instruction Cache Enabled (0, 1, 1)
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Memory Configuration
Memory Maps
Program
X Data
Y Data
$FFFF
$FF80
$FFFF
$5000
$0000
$FFFF
$FF80
Internal I/O
External I/O
External
External
External
Internal
Program RAM
20K
$1C00
$0000
$1C00
$0000
Internal
X data RAM
7K
Internal
Y data RAM
7K
Bit Settings
Memory Configuration
Program
RAM
X Data
RAM
Y Data
RAM
Addressable
Memory Size
SC MS CE
Cache
1
0
0
20K
$0000Ð
$4FFF
7K
$0000Ð
$1BFF
7K
$0000Ð
$1BFF
None
64K
AA0558
Figure 3-5 16-bit Space with Default RAM (1, 0, 0)
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Memory Configuration
Memory Maps
Program
X Data
Y Data
$FFFF
$FFFF
$FF80
$FFFF
$FF80
Internal I/O
External I/O
External
External
External
$5000
$4C00
I-Cache
1K
$1C00
$0000
$1C00
$0000
Internal
Program RAM
19K
Internal
X data RAM
7K
Internal
Y data RAM
7K
$0000
Bit Settings
Memory Configuration
Program
RAM
X Data
RAM
Y Data
RAM
Addressable
Memory Size
SC MS CE
Cache
1
0
1
19K
$0000Ð
$4BFF
7K
$0000Ð
$1BFF
7K
$0000Ð
$1BFF
1K
$4C00Ð
$4FFF
64K
AA0562
Figure 3-6 16-bit Space with Instruction Cache Enabled (1, 0, 1)
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Memory Configuration
Memory Maps
Program
X Data
Y Data
$FFFF
$FFFF
$FF80
$FFFF
$FF80
Internal I/O
External I/O
External
External
External
$1400
$0000
$1400
$0000
$6000
$0000
Internal
X data RAM
5K
Internal
Y data RAM
5K
Internal
Program RAM
24K
Bit Settings
Memory Configuration
Program
RAM
X Data
RAM
Y Data
RAM
Addressable
Memory Size
SC MS CE
Cache
1
1
0
24K
$0000Ð
$5FFF
5K
$0000Ð
$13FF
5K
$0000Ð
$13FF
None
64K
AA0560
Figure 3-7 16-bit Space with Switched Program RAM (1, 1, 0)
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Memory Configuration
Memory Maps
Program
X Data
Y Data
$FFFF
$FFFF
$FF80
$FFFF
$FF80
Internal I/O
External I/O
External
External
External
$1400
$0000
$1400
$0000
$6000
$5C00
$0000
I-Cache
1K
Internal
X data RAM
5K
Internal
Y data RAM
5K
Internal
Program
RAM 23K
Bit Settings
Memory Configuration
Program
RAM
X Data
RAM
Y Data
RAM
Addressable
Memory Size
SC MS CE
Cache
1
1
1
23K
$0000Ð
$5FFF
5K
$0000Ð
$13FF
5K
$0000Ð
$13FF
1K
$5C00Ð
$5FFF
64K
AA0564
Figure 3-8 16-bit Space, Switched Program RAM, Instruction Cache
Enabled (1, 1, 1)
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Memory Configuration
Internal I/O Memory Map
3.5
INTERNAL I/O MEMORY MAP
The DSP56309 internal X-I/O space (the top 128 locations of the X data memory space) is
listed in Table D-2 on page D-11 of Appendix DÑInterrupt Sources.
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SECTION 4
CORE CONFIGURATION
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Core Configuration
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
BOOTSTRAP PROGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
INTERRUPT SOURCES AND PRIORITIES . . . . . . . . . . . . . 4-9
DMA REQUEST SOURCES . . . . . . . . . . . . . . . . . . . . . . . . 4-16
OPERATING MODE REGISTER (OMR). . . . . . . . . . . . . . . 4-17
PLL CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . 4-18
DEVICE IDENTIFICATION REGISTER (IDR). . . . . . . . . . . 4-18
AA CONTROL REGISTERS (AAR0ÐAAR3) . . . . . . . . . . . . 4-19
JTAG BOUNDARY SCAN REGISTER (BSR). . . . . . . . . . . 4-20
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Core Configuration
Introduction
4.1
INTRODUCTION
This chapter presents details on core configuration specific to the DSP56309. These
configuration details include the following:
¥ Operating modes
¥ Bootstrap program
¥ Interrupt sources and priorities
¥ DMA request sources
¥ Operating Mode Register
¥ PLL control register
¥ AA control registers
¥ JTAG Boundary Scan Register
For information on specific registers or modules in the DSP56300 core, refer to the
DSP56300 Family Manual (DSP56300FM/AD).
4.2
OPERATING MODES
The DSP56309 begins operation by leaving Reset state and going into one of eight
operating modes. As the DSP56309 exits the Reset state, it loads the values of MODA,
MODB, MODC, and MODD into bits MA, MB, MC, and MD of the Operating Mode
Register (OMR). These bit settings select the operating mode, which determines the
bootstrap program option the microprocessor uses to start up.
The MAÐMD bits of the OMR can also be set directly by software. A jump directly to the
bootstrap program entry point ($FF0000) after the OMR bits are set causes the DSP56309
to execute the specified bootstrap program option (except modes 0 and 8).
Table 4-1 shows the DSP56309 bootstrap operation modes, the corresponding settings of
the external operational mode signal lines (the mode bits MAÐMD in the OMR), and the
reset vector address to which the DSP56309 jumps once it leaves the Reset state.
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Core Configuration
Bootstrap Program
4.3
BOOTSTRAP PROGRAM
Bootstrap operating mode descriptions for the DSP56309 are listed in Table 4-1.
Table 4-1 DSP56309 Operating Modes
Mode MODD MODC MODB MODA Reset Vector
Description
0
0
0
0
0
$C00000
Expanded mode: address
$C00000 is reflected as $00000
on Port A signals A0-A17
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
$FF0000
$FF0000
$FF0000
$FF0000
$FF0000
$FF0000
$FF0000
$008000
$FF0000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Expanded mode
Bootfrombyte-widememory
at $D00000
A
B
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
$FF0000
$FF0000
$FF0000
$FF0000
Boot through SCI
Reserved
C
D
HI08 boot in ISA mode
HI08 boot in HC11
non-multiplexed mode
E
F
1
1
1
1
1
1
0
1
$FF0000
$FF0000
HI08 boot in 8051
multiplexed bus mode
HI08 boot in MC68302 mode
The bootstrap program is factory-programmed in an internal, 192-word by 24-bit
bootstrap ROM located in program memory space at locations $FF0000Ð$FF00BF. The
bootstrap program can load any Program RAM segment from an external byte-wide
EPROM, the SCI, or the host port. The bootstrap program code is listed in
Appendix AÑBootstrap Programs.
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Core Configuration
Bootstrap Program
On exiting the reset state, the DSP56309 does the following:
1. Samples the MODA, MODB, MODC, and MODD signal lines.
2. Loads their values into bits MA, MB, MC, and MD in the OMR.
The contents of the MA, MB, MC, and MD bits determine which bootstrap mode the
DSP56309 enters:
1. If MA, MB, MC, and MD are all cleared (Bootstrap mode 0), the program bypasses
the bootstrap ROM, and the DSP56309 starts loading instructions from external
program memory location $C00000.
2. If MA, MB, and MC are cleared and MD is set (Bootstrap mode 8), the program
bypasses the bootstrap ROM, and the DSP56309 starts loading in instruction
values from external program memory location $008000.
3. Otherwise (Bootstrap modes 1Ð7), the DSP56309 jumps to the bootstrap program
entry point at $FF0000.
If the bootstrap program is loading via the host interface (HI08), setting the HF0 bit in
the host status register (HSR) causes the DSP56309 to stop loading and begin executing
the loaded program at the specified start address.
See Table 4-1 for a tabular description of the mode bit settings for the operating modes.
The bootstrap program options (except modes 0 and 8) can be invoked at any time by
setting the MA, MB, MC, and MD bits in the OMR and jumping to the bootstrap
program entry point, $FF0000. Software can directly set the mode selection bits in the
OMR.
Bootstrap modes 0 and 8 are the normal functioning modes for the DSP56309. Bootstrap
modes 1Ð7 are the bootstrap modes proper.
Bootstrap modes 9, A, C, D, E, F select different, specific devices for loading the
bootstrap source. In those bootstrap modes, the bootstrap program expects the following
data sequence when downloading the user program through an external port:
1. Three bytes defining the number of (24-bit) program words to be loaded
2. Three bytes defining the (24-bit) start address to which the user program loads in
the DSP56309 program memory
3. The user program (three bytes for each 24-bit program word)
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Core Configuration
Bootstrap Program
The three bytes for each data sequence must be loaded with the least significant byte
first. Once the bootstrap program completes loading the specified number of words, it
jumps to the specified starting address and executes the loaded program.
4.3.1
Mode 0: Expanded Mode
Reset
Vector
Mode MODD MODC MODB MODA
Description
0
0
0
0
0
$C00000 Expanded mode
The bootstrap ROM is bypassed and the DSP56309 starts fetching instructions beginning
at address $C00000. Memory accesses are performed using SRAM memory access type
with 31 wait states and no address attributes selected (by default).
4.3.2
Modes 1 to 7: Reserved
These modes are reserved for future use.
4.3.3
Mode 8: Expanded Mode
Reset
Vector
Mode MODD MODC MODB MODA
Description
8
1
0
0
0
$008000 Expanded mode
The bootstrap ROM is bypassed and the DSP56309 starts fetching instructions beginning
at address $008000. Memory accesses are performed using SRAM memory access type
with 31 wait states and no address attributes selected.
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Core Configuration
Bootstrap Program
4.3.4
Mode 9: Boot from Byte-Wide External Memory
Reset
Vector
Mode MODD MODC MODB MODA
Description
9
1
0
0
1
$FF0000 Boot from byte-wide
memory (at $D00000)
The bootstrap program loads instructions through Port A from external byte-wide
memory, starting at P:$D00000. The SRAM memory access type is selected by the values
in address attribute register 1 (AAR1). Thirty-one wait states are inserted between each
memory access. Address $D00000 is reflected as address $00000 on Port A signals
HA0-HA17.
4.3.5
Mode A: Boot from SCI
Reset
Vector
Mode MODD MODC MODB MODA
Description
A
1
0
1
0
$FF0000 Boot through SCI
Instructions are loaded through the SCI. The bootstrap program sets the SCI to operate
in 10-bit asynchronous mode, with one start bit, eight data bits, one stop bit and no
parity. Data is received in this order; start bit, eight data bits (LSB first), and one stop bit.
Data is aligned in the SCI receive data register with the LSB of the least significant byte
of the received data appearing at bit 0. The user must provide an external clock source
with a frequency at least 16 times the transmission data rate. Each byte received by the
SCI is echoed back through the SCI transmitter to the external transmitter.
4.3.6
Mode B: Reserved
Reset
Vector
Mode MODD MODC MODB MODA
Description
B
1
0
1
1
$FF0000 Reserved
This mode is reserved for future use.
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Core Configuration
Bootstrap Program
4.3.7
Modes C, D, E, F: Boot from HI08
Modes C, D, E, and F enable the programmer to boot through the host interface (HI08) in
various ways.
4.3.7.1
Mode C: In ISA/DSP5630X Mode (8-Bit Bus)
Reset
Vector
Mode MODD MODC MODB MODA
Description
C
1
1
0
0
$FF0000 HI08 Bootstrap in
ISA/DSP5630X
In mode C: boot from HI08 in ISA/DSP5630x with an 8-bit wide bus, the HI08 is
configured to interface with an ISA bus or with the memory expansion port of a master
DSP5630n processor.
If the host processor sets host flag 0 (HF0) in the HI08 interface control register (HCR)
while writing the initialization program, the bootstrap program stops loading
instructions, jumps to the starting address specified, and executes the loaded program.
4.3.7.2
Mode D: In HC11 Non-multiplexed Mode
Reset
Vector
Mode MODD MODC MODB MODA
Description
D
1
1
0
1
$FF0000 HI08 Bootstrap in HC11
non-multiplexed
In mode D: boot from HI08 in HC11 non-multiplexed mode, the bootstrap program sets
the host interface to interface with the Motorola HC11 microcontroller.
If the host processor sets host flag 0 (HF0) in the HCR while writing the initialization
program, the bootstrap program stops loading instructions, jumps to the starting
address specified, and executes the loaded program.
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Core Configuration
Interrupt Sources and Priorities
4.3.7.3
Mode E: In 8051 Multiplexed Bus Mode
Reset
Vector
Mode MODD MODC MODB MODA
Description
E
1
1
1
0
$FF0000 HI08 Bootstrap in 8051
multiplexed bus
In mode E: boot from HI08 in 8051 multiplexed bus mode, the bootstrap program sets
Ò
the host interface to interface with the Intel 8051 bus.
If the host processor sets host flag 0 (HF0) in the HCR while writing the initialization
program, the bootstrap program stops loading instructions, jumps to the starting
address specified, and executes the loaded program.
4.3.7.4
Mode F: In 68302/68360 Bus Mode
Reset
Vector
Mode MODD MODC MODB MODA
Description
F
1
1
1
1
$FF0000 HI08 Bootstrap in 68302 bus
In mode F: boot from HI08 in 68302/68360 Bus mode, the bootstrap program sets the
host interface to interface with the Motorola 68302 or 68360 bus.
If the host processor sets host flag 0 (HF0) in the HCR while writing the initialization
program, the bootstrap program stops loading instructions, jumps to the starting
address specified, and executes the loaded program.
4.4
INTERRUPT SOURCES AND PRIORITIES
DSP56309 interrupt handling, like that of all DSP56300 family members, has been
optimized for DSP applications. Refer to Section 7 of the DSP56300 Family Manual. The
interrupt table is located in the 256 locations of program memory to which the vector
base address (VBA) register in the program control unit (PCU) points.
4.4.1
Interrupt Sources
Each interrupt is allocated two instructions in the table, so there are 128 table entries for
interrupt handling. Table 4-2 shows the table entry address for each interrupt source.
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Core Configuration
Interrupt Sources and Priorities
The DSP56309 initialization program loads the table entry for each interrupt serviced
with two interrupt servicing instructions.
In the DSP56309, only 46 of the 128 vector addresses are used for specific interrupt
sources. The remaining 82 are reserved. If you know that certain interrupts will not be
used, those interrupt vector locations can be used for program or data storage.
Table 4-2 Interrupt Sources
Interrupt
Interrupt
Priority
Level
Range
Starting
Address
Interrupt Source
VBA:$00
VBA:$02
VBA:$04
VBA:$06
VBA:$08
VBA:$0A
VBA:$0C
VBA:$0E
VBA:$10
VBA:$12
VBA:$14
VBA:$16
VBA:$18
VBA:$1A
VBA:$1C
VBA:$1E
VBA:$20
VBA:$22
VBA:$24
VBA:$26
VBA:$28
VBA:$2A
VBA:$2C
VBA:$2E
3
Hardware RESET
Stack Error
3
3
Illegal Instruction
3
Debug Request Interrupt
Trap
3
3
Non-Maskable Interrupt (NMI)
Reserved
3
3
Reserved
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
IRQA
IRQB
IRQC
IRQD
DMA Channel 0
DMA Channel 1
DMA Channel 2
DMA Channel 3
DMA Channel 4
DMA Channel 5
TIMER 0 Compare
TIMER 0 Overflow
TIMER 1 Compare
TIMER 1 Overflow
TIMER 2 Compare
TIMER 2 Overflow
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Core Configuration
Interrupt Sources and Priorities
Table 4-2 Interrupt Sources (Continued)
Interrupt
Priority
Level
Interrupt
Starting
Address
Interrupt Source
Range
VBA:$30
VBA:$32
VBA:$34
VBA:$36
VBA:$38
VBA:$3A
VBA:$3C
VBA:$3E
VBA:$40
VBA:$42
VBA:$44
VBA:$46
VBA:$48
VBA:$4A
VBA:$4C
VBA:$4E
VBA:$50
VBA:$52
VBA:$54
VBA:$56
VBA:$58
VBA:$5A
VBA:$5C
VBA:$5E
VBA:$60
VBA:$62
VBA:$64
VBA:$66
:
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
:
ESSI0 Receive Data
ESSI0 Receive Data With Exception Status
ESSI0 Receive Last Slot
ESSI0 Transmit Data
ESSI0 Transmit Data With Exception Status
ESSI0 Transmit Last Slot
Reserved
Reserved
ESSI1 Receive Data
ESSI1 Receive Data With Exception Status
ESSI1 Receive Last Slot
ESSI1 Transmit Data
ESSI1 Transmit Data With Exception Status
ESSI1 Transmit Last Slot
Reserved
Reserved
SCI Receive Data
SCI Receive Data With Exception Status
SCI Transmit Data
SCI Idle Line
SCI Timer
Reserved
Reserved
Reserved
Host Receive Data Full
Host Transmit Data Empty
Host Command (Default)
Reserved
:
VBA:$FE
0Ð2
Reserved
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Core Configuration
Interrupt Sources and Priorities
4.4.2
Interrupt Priority Levels
The DSP56309 has a four-level interrupt priority structure. Each interrupt has two
interrupt priority level bits (IPL[1:0]) that determine its interrupt priority level. Level 0 is
the lowest priority; Level 3 is the highest-level priority and is non-maskable. Table 4-3
defines the IPL bits.
Table 4-3 Interrupt Priority Level Bits
IPL bits
Interrupt
Priority
Level
Interrupts
Enabled
Interrupts
Masked
xxL1 xxL0
0
0
1
1
0
1
0
1
No
Yes
Yes
Yes
Ñ
0
0
1
2
3
0, 1
0, 1, 2
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Core Configuration
Interrupt Sources and Priorities
There are two interrupt priority registers in the DSP56309. The IPRÐC is dedicated to
DSP56300 core interrupt sources, and IPRÐP is dedicated to DSP56309 peripheral
interrupt sources. IPRÐC is shown in Figure 4-1 and IPRÐP is shown in Figure 4-2.
11
10
9
7
6
5
4
3
2
1
0
8
IDL2
IDL1 IDL0 ICL2 ICL1 ICL0 IBL2 IBL1 IBL0 IAL2 IAL1 IAL0
IRQA IPL
IRQA mode
IRQB IPL
IRQB mode
IRQC IPL
IRQC mode
IRQD IPL
IRQD mode
22
23
21
20
19
18
17
16
15
14
13
12
D5L1 D5L0 D4L1 D4L0 D3L1 D3L0 D2L1 D2L0 D1L1 D1L0 D0L1 D0L0
DMA0 IPL
DMA1 IPL
DMA2 IPL
DMA3 IPL
DMA4 IPL
DMA5 IPL
Figure 4-1 Interrupt Priority Register C (IPR-C) (X:$FFFFFF)
11
10
9
7
6
5
4
3
2
1
0
8
T0L1
T0L0 SCL1 SCL0 S1L1 S1L0 S0L1 S0L0 HPL1 HPL0
HI08 IPL
ESSI0 IPL
ESSI1 IPL
SCI IPL
TRIPLE TIMER IPL
reserved
22
23
21
20
19
18
17
16
15
14
13
12
reserved
Figure 4-2 Interrupt Priority Register P (IPR-P) (X:$FFFFFE)
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Core Configuration
Interrupt Sources and Priorities
4.4.3
Interrupt Source Priorities Within an IPL
If more than one interrupt request is pending when an instruction executes, the interrupt
source with the highest IPL is serviced first. When several interrupt requests having the
same IPL are pending, another fixed-priority structure within that IPL determines which
interrupt source is serviced first. This fixed priority list of interrupt sources within an
IPL is shown in Table 4-4.
Table 4-4 Interrupt Source Priorities within an IPL
Priority
Interrupt Source
Level 3 (Nonmaskable)
Hardware RESET
Highest
Ñ
Stack Error
Ñ
Illegal Instruction
Ñ
Debug Request Interrupt
Trap
Ñ
Lowest
Non-Maskable Interrupt
Levels 0, 1, 2 (Maskable)
Highest
Ñ
IRQA (External Interrupt)
IRQB (External Interrupt)
IRQC (External Interrupt)
IRQD (External Interrupt)
DMA Channel 0 Interrupt
DMA Channel 1 Interrupt
DMA Channel 2 Interrupt
DMA Channel 3 Interrupt
DMA Channel 4 Interrupt
DMA Channel 5 Interrupt
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
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Core Configuration
Interrupt Sources and Priorities
Table 4-4 Interrupt Source Priorities within an IPL (Continued)
Priority
Interrupt Source
Host Command Interrupt
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Host Transmit Data Empty
Host Receive Data Full
ESSI0 RX Data with Exception Interrupt
ESSI0 RX Data Interrupt
ESSI0 Receive Last Slot Interrupt
ESSI0 TX Data With Exception Interrupt
ESSI0 Transmit Last Slot Interrupt
ESSI0 TX Data Interrupt
ESSI1 RX Data With Exception Interrupt
ESSI1 RX Data Interrupt
ESSI1 Receive Last Slot Interrupt
ESSI1 TX Data With Exception Interrupt
ESSI1 Transmit Last Slot Interrupt
ESSI1 TX Data Interrupt
SCI Receive Data With Exception Interrupt
SCI Receive Data
SCI Transmit Data
SCI Idle Line
SCI Timer
TIMER0 Overflow Interrupt
TIMER0 Compare Interrupt
TIMER1 Overflow Interrupt
TIMER1 Compare Interrupt
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Core Configuration
DMA Request Sources
Table 4-4 Interrupt Source Priorities within an IPL (Continued)
Priority
Interrupt Source
Ñ
TIMER2 Overflow Interrupt
TIMER2 Compare Interrupt
Lowest
4.5
DMA REQUEST SOURCES
The DMA request source bits (DRS[4:0]) in the DMA control/status registers) encode the
source of DMA requests used to trigger DMA transfers. The DMA request sources can
be internal peripherals or external devices requesting service through the IRQA, IRQB,
IRQC, or IRQD signals. Table 4-5 describes the meanings of the DRS bits.
Table 4-5 DMA Request Sources
DMA Request Source Bits
Requesting Device
DRS4... DRS0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
External (IRQA signal)
External (IRQB signal)
External (IRQC signal)
External (IRQD signal)
Transfer done from DMA channel 0
Transfer done from DMA channel 1
Transfer done from DMA channel 2
Transfer done from DMA channel 3
Transfer done from DMA channel 4
Transfer done from DMA channel 5
ESSI0 Receive Data (RDF0 = 1)
ESSI0 Transmit Data (TDE0 = 1)
ESSI1 Receive Data (RDF1 = 1)
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Core Configuration
Operating Mode Register (OMR)
Table 4-5 DMA Request Sources (Continued)
DMA Request Source Bits
Requesting Device
DRS4... DRS0
01101
01110
ESSI1 Transmit Data (TDE1 = 1)
SCI Receive Data (RDRF = 1)
SCI Transmit Data (TDRE = 1)
Timer0 (TCF0 = 1)
01111
10000
10001
Timer1 (TCF1 = 1)
10010
Timer2 (TCF2 = 1)
10011
Host Receive Data Full (HRDF = 1)
Host Transmit Data Empty (HTDE = 1)
Reserved
10100
10101Ð11111
4.6
OPERATING MODE REGISTER (OMR)
The OMR is a 24-bit, read/write register divided into three byte-sized units. The first
two bytes (COM and EOM) control the chipÕs operating mode. The third byte (SCS)
controls and monitors the stack extension. The OMR control bits are shown in
Figure 4-3. Refer to the DSP56300 Family Manual for a complete description of the OMR.
SCS
EOM
COM
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PEN
SENWRPEOV EUN XYS ATE APD ABE BRT TAS BE CDP1:0 MS SD
EBD MD MC MB MA
PENÑPatch Enable
ATEÑAddress Tracing Enable
APDÑAddress Priority Disable
MSÑMemory Switch Mode
SDÑStop Delay
SENÑStack Extension Enable
WRPÑExtended Stack Wrap Flag
EOVÑExtended Stack Overflow Flag
EUNÑExtended Stack Underflow Flag
XYSÑStack Extension Space Select
ABEÑAsynch. Bus Arbitration Enable
BRTÑBus Release Timing
TASÑTA Synchronize Select
BEÑBurst Mode Enable
EBDÑExternal Bus Disable
MDÑOperating Mode D
MCÑOperating Mode C
MBÑOperating Mode B
MAÑOperating Mode A
CDP1ÑCore-DMA Priority 1
CDP0ÑCore-DMA Priority 0
- Reserved bit. Read as zero, should be written with zero for future compatibility.
Figure 4-3 DSP56309 Operating Mode Register (OMR)
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Core Configuration
PLL Control Register
4.7
PLL CONTROL REGISTER
The PLL Control (PCTL) register is an X-I/O mapped, 24-bit, read/write register that
directs the operation of the on-chip PLL. The PCTL control bits are shown in Figure 4-4.
Refer to the DSP56300 Family Manual for a full description of the PCTL.
11
10
9
8
7
6
5
4
3
2
1
0
MF11 MF10
MF9
21
MF8
20
MF7
19
MF6
18
MF5
17
MF4
16
MF3
15
MF2
14
MF1
13
MF0
12
23
22
PD3
PD2
PD1
PD0
COD
PEN
PSTP XTLD XTLR
DF2
DF1
DF0
AA0852
Figure 4-4 PLL Control (PCTL) Register
4.7.1
PCTL PLL Multiplication Factor Bits 0Ð11
The multiplication factor bits (MF[11:0]) define the Multiplication Factor (MF) that is
applied to the PLL input frequency. The MF bits are cleared during a DSP56309
hardware reset, which corresponds to an MF of one.
4.7.2
PCTL XTAL Disable Bit (XTLD) Bit 16
The XTAL disable bit (XTLD) controls the on-chip crystal oscillator XTAL output. The
XTLD bit is cleared during a DSP56309 hardware reset, which means that the XTAL
output signal is active, permitting normal operation of the crystal oscillator.
4.7.3
PCTL Predivider Factor Bits (PD0ÐPD3) Bits 20Ð23
The predivider factor bits (PD0ÐPD3) define the predivision factor (PDF) to be applied to
the PLL input frequency. The PD0ÐPD3 bits are cleared during a DSP56309 hardware
reset, which corresponds to a PDF of one.
4.8
DEVICE IDENTIFICATION REGISTER (IDR)
The device identification register (IDR) is a 24-bit, read-only factory programmed
register that identifies DSP56300 family members. It specifies the derivative number and
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AA Control Registers (AAR0ÐAAR3)
revision number of the device. This information can be used in testing or by software.
shows the contents of the IDR.
Revision numbers are assigned as follows: $0 is revision 0, $1 is revision A, and so on.
Because the DSP56309 is based on the DSP56302, its identification number is based on
the derivative number and revision number of that device.
23
16 15
12 11
0
Reserved
Revision Number
Derivative Number
$00
$2
$302
Figure 4-5 Identification Register Configuration (Revision 0)
4.9
AA CONTROL REGISTERS (AAR0ÐAAR3)
The address attribute register (AAR) appears in Figure 4-6. There are four of these
registers in the DSP56309 (AAR0ÐAAR3), one for each AA signal.
For a full description of the address attribute registers see the DSP56300 Family Manual.
Address multiplexing is not supported by the DSP56309. Bit 6 (BAM) of the AARs is
reserved and should have only 0 written to it.
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Core Configuration
JTAG Boundary Scan Register (BSR)
11
10
9
8
7
6
5
4
3
2
1
0
BPAC
BNC2 BNC1
BNC3
BNC0
BYEN BXEN BPEN BAAP BAT1 BAT0
External access type
AA pin polarity
Program space enable
X data space enable
Y data space enable
Reserved
Packing enable
Number of address bit to
compare
23
22
21
20
19
18
17
16
15
14
13
12
BAC3 BAC2
BAC11 BAC10 BAC9 BAC8
BAC5
BAC6
BAC4
BAC1
BAC7
BAC0
Address to compare
- Reserved Bit
Figure 4-6 Address Attribute Registers (AAR0ÐAAR3)
(X:$FFFFF9Ð$FFFFF6)
4.10 JTAG BOUNDARY SCAN REGISTER (BSR)
The BSR in the DSP56309 JTAG implementation contains bits for all device signal and
clock pins and associated control signals. All DSP56309 bidirectional pins have a
corresponding register bit in the BSR for pin data and are controlled by an associated
control bit in the BSR. The BSR is documented in Section 11.5ÑDSP56309 Boundary
Scan Register on page 11-13. The JTAG code is listed in Appendix CÑDSP56309 BSDL
Listing.
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SECTION 5
GENERAL-PURPOSE I/O
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General-Purpose I/O
5.1
5.2
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
PROGRAMMING MODEL. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
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General-Purpose I/O
Introduction
5.1
INTRODUCTION
The DSP56309 provides thirty-four bidirectional signals that can be configured as GPIO
signals or as dedicated peripheral signals. No dedicated GPIO signals are provided. All
of these signals are GPIO by default after reset. The control register settings of the
DSP56309Õs peripherals determine whether these signals function as GPIO or as
dedicated peripheral signals. This section describes how signals can function as GPIO.
5.2
PROGRAMMING MODEL
Section 2ÑSignal/Connection Descriptions of this manual documents the special uses
of these signals in detail. There are five groups of these signals. They can be controlled
separately or as groups. The groups include the following signals:
¥ Port B: sixteen GPIO signals (shared with the HI08 signals)
¥ Port C: six GPIO signals (shared with the ESSI0 signals)
¥ Port D: six GPIO signals (shared with the ESSI1 signals)
¥ Port E: three GPIO signals (shared with the SCI signals)
¥ Timers: three GPIO signals (shared with the Triple Timer signals)
5.2.1
Port B Signals and Registers
Each of the 16 Port B signals not used as a HI08 signal can be configured as a GPIO
signal. The GPIO functionality of Port B is controlled by three registers: host control
register (HCR), host port GPIO data register (HDR), and host port GPIO direction
register (HDDR). These registers are documented in Section 6ÑHost Interface (HI08) of
this manual.
5.2.2
Port C Signals and Registers
Each of the six Port C signals not used as an ESSI0 signal can be configured as a GPIO
signal. The GPIO functionality of Port C is controlled by three registers: Port C control
register (PCRC), Port C direction register (PRRC), and Port C data register (PDRC).
These registers are documented in Section 7ÑEnhanced Synchronous Serial Interface
(ESSI) of this manual.
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General-Purpose I/O
Programming Model
5.2.3
Port D Signals and Registers
Each of the six Port D signals not used as a ESSI1 signal can be configured as a GPIO
signal. The GPIO functionality of Port D is controlled by three registers: Port D control
register (PCRD), Port D direction register (PRRD) and Port D data register (PDRD).
These registers are also documented in Section 7ÑEnhanced Synchronous Serial
Interface (ESSI) of this manual.
5.2.4
Port E Signals and Registers
Each of the three Port E signals not used as a SCI signal can be configured as a GPIO
signal. The GPIO functionality of Port E is controlled by three registers: Port E control
register (PCRE), Port E direction register (PRRE) and Port E data register (PDRE). These
registers are documented in Section 8ÑSerial Communication Interface (SCI) of this
manual.
5.2.5
Triple Timer Signals
Each of the three triple timer interface signals (TIO0ÐTIO2) not used as a timer signal can
be configured as a GPIO signal. Each signal is controlled by the appropriate timer
control status register (TCSR0ÐTCSR2). These registers are documented in
Section 9ÑTriple Timer Module of this manual.
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SECTION 6
HOST INTERFACE (HI08)
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Host Interface (HI08)
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
HI08 FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
HI08 HOST PORT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . 6-6
HI08 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
HI08 DSP SIDE PROGRAMMERÕS MODEL. . . . . . . . . . . . . 6-8
HI08-EXTERNAL HOST PROGRAMMERÕS MODEL . . . . . 6-20
SERVICING THE HOST INTERFACE . . . . . . . . . . . . . . . . 6-31
HI08 PROGRAMMING MODEL QUICK REFERENCE. . . . 6-34
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Host Interface (HI08)
Introduction
6.1
INTRODUCTION
The Host Interface (HI08) is a byte-wide, full-duplex, double-buffered parallel port that
can connect directly to the data bus of a host processor. The HI08 supports a variety of
buses and provides glueless connection with a number of industry-standard
microcomputers, microprocessors, and DSPs.
The host bus can operate asynchronously to the DSP core clock, so the HI08 registers are
divided into two banks. The host register bank is accessible to the external host and the
DSP register bank is accessible to the DSP core.
The HI08 supports two classes of interfaces:
¥ Host Processor/Microcontroller (MCU) connection interface
¥ GPIO port
Signals not used as HI08 port signals can be configured as GPIO signals, up to a total of
16.
6.2
HI08 FEATURES
This section lists the features of the host-to-DSP and DSP-to-host interfaces. Further
details are given in Section 6.5ÑHI08 DSP Side ProgrammerÕs Model and
Section 6.8ÑHI08 Programming Model Quick Reference. Also, see Table 6-13 on
page 6-34.
6.2.1
Host to DSP Core Interface
¥ Mapping:
Ð Registers are directly mapped into eight internal X data memory locations
¥ Data word:
Ð DSP56309 24-bit (native) data words are supported, as are 8-bit and 16-bit
words
¥ Transfer modes:
Ð DSP-to-host
Ð Host-to-DSP
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Host Interface (HI08)
HI08 Features
Ð Host command
¥ Handshaking protocols:
Ð Software polled
Ð Interrupt driven
Ð Core DMA accesses
¥ Instructions:
Ð Memory-mapped registers allow the standard MOVE instruction to be used to
transfer data between the DSP56309 and external hosts.
Ð Special MOVEP instruction provides for I/O service capability using fast
interrupts.
Ð Bit addressing instructions (e.g., BCHG, BCLR, BSET, BTST, JCLR, JSCLR,
JSET, JSSET) simplify I/O service routines.
6.2.2
HI08-to-Host Processor Interface
¥ Sixteen signals support non-multiplexed or multiplexed buses:
Ð H0ÐH7/HAD0ÐHAD7 host data bus (H0ÐH7) or host multiplexed
address/data bus (HAD0ÐHAD7)
Ð HAS/HA0 address strobe (HAS) or host address line (HA0)
Ð HA8/HA1 host address line (HA8) or host address line (HA1)
Ð HA9/HA2 host address line (HA9) or host address line (HA2)
Ð HRW/HRD read/write select (HRW) or read strobe (HRD)
Ð HDS/HWR data strobe (HDS) or write strobe (HWR)
Ð HCS/HA10 host chip select (HCS) or host address line (HA10)
Ð HREQ/HTRQ host request (HREQ) or host transmit request (HTRQ)
Ð HACK/HRRQ host acknowledge (HACK) or host receive request (HRRQ)
¥ Mapping:
Ð HI08 registers are mapped into eight consecutive locations in external bus
address space.
Ð The HI08 acts as a memory or I/O-mapped peripheral for microprocessors,
microcontrollers, etc.
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Host Interface (HI08)
HI08 Features
¥ Data word: 8-bit
¥ Transfer modes:
Ð Mixed 8-bit, 16-bit, and 24-bit data transfers
¥ DSP-to-host
¥ Host-to-DSP
Ð Host command
¥ Handshaking protocols:
Ð Software polled
Ð Interrupt-driven (Interrupts are compatible with most processors, including
the MC68000, 8051, HC11, and Hitachi H8.)
¥ Dedicated interrupts:
Ð Separate interrupt lines for each interrupt source
Ð Special host commands force DSP core interrupts under host processor
control. These commands are useful for these purposes:
¥ Real-time production diagnostics
¥ Creating a debugging window for program development
¥ Host control protocols
¥ Interface capabilities:
Ð Glueless interface (no external logic required) to these devices:
¥ Motorola HC11
¥ Hitachi H8
¥ 8051 family
¥ Thomson P6 family
Ð Minimal glue-logic (pullups, pulldowns) required to interface these devices:
¥ ISA bus
¥ Motorola 68K family
Ò
¥ Intel X86 family
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Host Interface (HI08)
HI08 Host Port Signals
6.3
HI08 HOST PORT SIGNALS
The host port signals are documented in Section 2.8ÑHost Interface (HI08). Each host
port signal can be programmed as a host port signal or as a GPIO signal, PB0ÐPB15, as in
Table 6-1 through Table 6-3.
Table 6-1 HI08 Signal Definitions for Various Operational Modes
HI08 Port
Signal
Multiplexed Address/Data
Bus Mode
Non-Multiplexed Bus
Mode
GPIO
Mode
HAD0ÐHAD7
HAS/HA0
HA8/HA1
HA9/HA2
HCS/HA10
HAD0ÐHAD7
HAS/HAS
HA8
H0ÐH7
HA0
PB0ÐPB7
PB8
HA1
PB9
HA9
HA2
PB10
PB13
HA10
HCS/HCS
Table 6-2 HI08 Data Strobe Signals
HI08 Port
Signal
Single Strobe Bus
Dual Strobe Bus
GPIO Mode
HRW/HRD
HDS/HWR
HRW
HRD/HRD
HWR/HWR
PB11
PB12
HDS/HDS
Table 6-3 HI08 Host Request Signals
HI08 Port
Signal
Vector Required
No Vector Required
GPIO Mode
HREQ/
HTRQ
HREQ/HREQ
HTRQ/HTRQ
PB14
HACK/
HRRQ
HACK/HACK
HRRQ/HRRQ
PB15
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Host Interface (HI08)
HI08 Block Diagram
6.4
HI08 BLOCK DIAGRAM
Figure 6-1 shows the HI08 registers. The top row of registers are for access by the DSP
core. The bottom row of registers are for access by the host processor.
HCR = Host Control Register
HSR = Host Status Register
HPCR = Host Port Control Register
HBAR = Host Base Address register
HTX = Host Transmit register
HRX = Host Receive register
HDDR = Host Data Direction Register
HDR = Host Data Register
Core DMA Data Bus
DSP Peripheral Data Bus
24
HCR
24
HSR
24
HDDR
24
HDR
24
24
HPCR
24
24 24
24
HBAR
HTX
HRX
Address
Comparator
24
24
5
3
ISR
8
ICR
CVR
8
IVR
Latch
8
RXH RXM RXL
TXH TXM TXL
8
8
3
8
8
8
8
8
8
HOST Bus
ICR = Interface Control Register
CVR = Command Vector Register
ISR = Interface Status Register
IVR = Interrupt Vector Register
RXH = Receive Register High
RXM = Receive Register Middle
RXL = Receive Register Low
TXH = Transmit Register High
TXM = Transmit Register Middle
TXL = Transmit Register High
AA0657
Figure 6-1 HI08 Block Diagram
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HI08 DSP Side ProgrammerÕs Model
6.5
HI08 DSP SIDE PROGRAMMERÕS MODEL
The DSP56309 core treats the HI08 as a memory-mapped peripheral occupying eight
24-bit words in X data memory space. The DSP treats the HI08 as a normal
memory-mapped peripheral, employing either standard polled or interrupt-driven
programming techniques. Separate transmit and receive data registers are
double-buffered to allow the DSP and host processor to transfer data efficiently at high
speed. Direct memory mapping allows the DSP56309 core to communicate with the HI08
registers using standard instructions and addressing modes. In addition, the MOVEP
instruction allows direct data transfers between DSP56309 internal memory and the
HI08 registers or vice versa.
There are two kinds of host processor registers, data and control, with eight registers in
all. All eight registers can be accessed by the DSP core but not by the external host.
Data registers are 24-bit registers used for high-speed data transfer to and from the DSP.
¥ Host data receive register (HRX)
¥ Host data transmit register (HTX)
The DSP side control registers are 16-bit registers that control DSP functions. The eight
MSBs in the DSP side control registers are read by the DSP56309 as 0. Those registers are
as follows:
¥ Host control register (HCR)
¥ Host status register (HSR)
¥ Host base address register (HBAR)
¥ Host port control register (HPCR)
¥ Host GPIO data direction register (HDDR)
¥ Host GPIO data register (HDR)
Both hardware RESET signals and software RESET instructions disable the HI08. After
reset, the HI08 signals are configured to GPIO and disconnected from the DSP56309 core
(i.e., the signals are left floating).
6.5.1
Host Receive Data Register (HRX)
The HRX register handles host-to-DSP data transfers. The DSP56309 views it as a 24-bit
read-only register. Its address is X:$FFFFC6. It is loaded with 24-bit data from the
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transmit data registers (TXH:TXM:TXL on the host side) when both the hostÕs transmit
data register empty (ISR:TXDE) bit and the DSPÕs host receive data full (HSR:HRDF) bits
are cleared. The transfer operation sets both the TXDE and HRDF bits. When the HRDF
bit is set, the HRX register contains valid data. The DSP56309 sets the HRIE bit (HCR, bit
0) to cause a host receive data interrupt when HRDF is set. When the DSP56309 reads the
HRX register, the HRDF bit is cleared.
6.5.2
Host Transmit Data Register (HTX)
The HTX register handles for DSP-to-host data transfers. The DSP56309 views it as a
24-bit write-only register. Its address is X:$FFFFC7. Writing to the HTX register clears
the DSPÕs host transfer data empty (HSR:HTDE) bit. The contents of the HTX register are
transferred as 24-bit data to the receive byte registers (RXH:RXM:RXL) when both the
HTDE and the hostÕs receive data full (ISR:RXDF) bits are cleared. This transfer
operation sets the HTDE and RXDF bits. The DSP56309 sets the HTIE bit to cause a host
transmit data interrupt when HTDE is set. To prevent the previous data from being
overwritten, data should not be written to the HTX until the HTDE bit is set.
Note:
During data writes to a peripheral device, there is a two-cycle pipeline delay
until any status bits affected by this operation are updated. If you read any of
those status bits within the next two cycles, the bit does not reflect its current
status. See the DSP56300 Family Manual, Appendix B, Polling a Peripheral
Device for Write for further details.
6.5.3
Host Control Register (HCR)
The HCR is a 16-bit, read/write control register by which the DSP core controls the HI08
operating mode. Initialization values for HCR bits are documented in
Section 6.5.9ÑDSP Side Registers After Reset. Reserved bits are read as 0 and should
be written with 0 for future compatibility.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HF3 HF2 HCIE HTIE HRIE
ÑReserved bit, read as 0, should be written with 0 for future compatibility.
AA0658
Figure 6-2 Host Control Register (HCR) (X:$FFFFC2)
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6.5.3.1
HCR Host Receive Interrupt Enable (HRIE) Bit 0
The HRIE bit generates a host receive data interrupt request if the host receive data full
(HRDF) bit in the host status register (HSR, Bit 0), is set. The HRDF bit is set when data is
written to the HRX. If HRIE is cleared, HRDF interrupts are disabled.
6.5.3.2
HCR Host Transmit Interrupt Enable (HTIE) Bit 1
The HTIE bit generates a host transmit data interrupt request if the host transmit data
empty (HTDE) bit in the HSR is set. The HTDE bit is set when data is read from the HTX.
If HTIE is cleared, HTDE interrupts are disabled.
6.5.3.3
HCR Host Command Interrupt Enable (HCIE) Bit 2
The HCIE bit generates a host command interrupt request if the host command pending
(HCP) status bit in the HSR is set. If HCIE is cleared, HCP interrupts are disabled. The
interrupt address is determined by the host command vector register (CVR).
Note:
If more than one interrupt request source is asserted and enabled (e.g., HRDF
is set, HCP is set, HRIE is set, and HCIE is set), the HI08 generates interrupt
requests according to priorities shown in Table 6-4.
Table 6-4 Host Command Interrupt Priority List
Priority
Interrupt Source
Highest
Host Command (HCP = 1)
Transmit Data (HTDE = 1)
Receive Data (HRDF = 1)
Lowest
6.5.3.4
HCR Host Flags 2,3 (HF[3:2]) Bits 3, 4
HF[3:2] bits are general-purpose flags for DSP-to-host communication. The DSP core sets
and clears them. The values of HF[3:2] are reflected in the interface status register (ISR);
that is, if they are modified by the DSP software, the host processor can read the
modified values by reading the ISR.
These two flags can be used individually or as encoded pairs in a simple DSP-to-host
communication protocol, implemented in both the DSP and the host processor software.
6.5.3.5
HCR Reserved Bits 5-15
These bits are reserved. They are read as 0 and should be written with 0.
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6.5.4
Host Status Register (HSR)
The HSR is a 16-bit, read-only status register by which the DSP reads the HI08 status and
flags. The host processor cannot access it directly. Reserved bits are read as 0 and should
be written with 0. The initialization values for the HSR bits are described in
Section 6.5.9ÑDSP Side Registers After Reset on page 6-18.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HF1
HF0
HCP HTDE HRDF
ÑReserved bit, read as 0, should be written with 0 for future compatibility.
AA0659
Figure 6-3 Host Status Register (HSR) (X:$FFFFC3)
6.5.4.1
HSR Host Receive Data Full (HRDF) Bit 0
The HRDF bit indicates that the host receive data register (HRX) contains data from the
host processor. HRDF is set when data is transferred from the TXH:TXM:TXL registers
to the HRX register. If HRDF is set, the HI08 generates a receive data full DMA request.
HRDF is cleared when the DSP core reads the HRX. HRDF is also cleared when the host
processor uses the initialize function.
6.5.4.2
HSR Host Transmit Data Empty (HTDE) Bit 1
The HTDE bit indicates that the host transmit data register (HTX) is empty and can be
written by the DSP core. HTDE is set when the HTX register is transferred to the
RXH:RXM:RXL registers. HTDE is also set when the host processor uses the initialize
function. If HTDE is set, the HI08 generates a transmit data full DMA request. HTDE is
cleared when HTX is written by the DSP core.
6.5.4.3
HSR Host Command Pending (HCP) Bit 2
The HCP bit indicates that the host has set the HC bit and that a host command interrupt
is pending. The HCP bit reflects the status of the HC bit in the CVR. HC and HCP are
cleared by the HI08 hardware when the interrupt request is serviced by the DSP core. If
the host clears HC, HCP is also cleared.
6.5.4.4
HSR Host Flags 0, 1 (HF[1:0]) Bits 3, 4
HF[1:0] bits are used as general-purpose flags for host-to-DSP communication. HF[1:0]
can be set or cleared by the host. These bits reflect the status of host flags HF[1:0] in the
ICR on the host side. They can be used individually or as encoded pairs in a simple
host-to-DSP communication protocol implemented in both the DSP and the host
processor software.
6.5.4.5
HSR Reserved Bits 5-15
These bits are reserved. They are read as 0 and should be written with 0.
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6.5.5
Host Base Address Register (HBAR)
The HBAR is used in multiplexed bus modes. This register, illustrated in Figure 6-4,
selects the base address where the host side registers are mapped into the bus address
space. The address from the host bus is compared with the base address as programmed
in the base address register. If the addresses match, an internal chip select is generated.
The use of this register by the chip select logic is described in Figure 6-5.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BA10 BA9
BA8
BA7
BA6
BA5
BA4
BA3
AA0665
Figure 6-4 Host Base Address Register (HBAR) (X:$FFFFC5)
6.5.5.1
HBAR Base Address (BA[10:3]) Bits 0-7
These bits reflect the base address where the host-side registers are mapped into the bus
address space.
6.5.5.2
HBAR Reserved Bits 8-15
These bits are reserved. They are read as 0 and should be written with 0.
HAD[0Ð7]
Latch
A[3:7]
HAS
HA[8:10]
Chip select
Base
Address
Register
8 bits
DSP Peripheral
Data Bus
AA0666
Figure 6-5 Self Chip Select Logic
6.5.6
Host Port Control Register (HPCR)
The HPCR is a 16-bit, read/write control register by which the DSP controls the HI08
operating mode. Reserved bits are read as 0 and should be written with 0 for future
compatibility. The initialization values for the HPCR bits are described in
Section 6.5.9ÑDSP Side Registers After Reset. The HPCR bits are illustrated in
Figure 6-6.
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1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
HAP HRP HCSP HDDS HMUX HASP HDSP HROD
HEN HAEN HREN HCSEN HA9EN HA8EN HGEN
ÑReserved bit, read as 0, should be written with 0 for future compatibility.
AA0660
Figure 6-6 Host Port Control Register (HPCR) (X:$FFFFC4)
Note:
To assure proper operation of the DSP56309, the HPCR bits HAP, HRP, HCSP,
HDDS, HMUX, HASP, HDSP, HROD, HAEN, and HREN should be changed
only if HEN is cleared.
To assure proper operation of the DSP56309, the HPCR bits HAP, HRP, HCSP,
HDDS, HMUX, HASP, HDSP, HROD, HAEN, HREN, HCSEN, HA9EN, and
HA8EN should not be set when HEN is set or simultaneously with setting
HEN.
6.5.6.1
HPCR Host GPIO Port Enable (HGEN) Bit 0
If HGEN is set, signals configured as GPIO are enabled. If this bit is cleared, signals
configured as GPIO are disconnected; outputs are high impedance, and inputs are
electrically disconnected. Signals configured as HI08 are not affected by the value of
HGEN.
6.5.6.2
HPCR Host Address Line 8 Enable (HA8EN) Bit 1
If HA8EN is set and the HI08 is in multiplexed bus mode, then HA8/A1 acts as host
address line 8 (HA8). If this bit is cleared and the HI08 is in multiplexed bus mode, then
HA8/HA1 acts as a GPIO signal according to the value of the HDDR and HDR.
Note:
HA8EN is ignored when the HI08 is not in the multiplexed bus mode (HMUX
is cleared).
6.5.6.3
HPCR Host Address Line 9 Enable (HA9EN) Bit 2
If HA9EN is set and the HI08 is in multiplexed bus mode, then HA9/HA2 acts as host
address line 9 (HA9). If this bit is cleared, and the HI08 is in multiplexed bus mode, then
HA9/HA2 is configured as a GPIO signal according to the value of the HDDR and HDR.
Note:
HA9EN is ignored when the HI08 is not in the multiplexed bus mode (HMUX
is cleared).
6.5.6.4
HPCR Host Chip Select Enable (HCSEN) Bit 3
If the HCSEN bit is set, then HCS/HA10 is used as host chip select (HCS) in the
non-multiplexed bus mode (HMUX is cleared), and as host address line 10 (HA10) in the
multiplexed bus mode (HMUX is set). If this bit is cleared, then HCS/HA10 is
configured as a GPIO signal according to the value of the HDDR and HDR.
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6.5.6.5
HPCR Host Request Enable (HREN) Bit 4
The HREN bit controls the host request signals. If HREN is set and the HI08 is in the
single host request mode (HDRQ is cleared in the host interface control register (ICR)),
HREQ/HTRQ is configured as the host request (HREQ) output. If HREN is cleared,
HREQ/HTRQ and HACK/HRRQ are configured as GPIO signals according to the value
of the HDDR and HDR.
If HREN is set in the double host request mode (HDRQ is set in the ICR), HREQ/HTRQ
is configured as the host transmit request (HTRQ) output and HACK/HRRQ as the host
receive request (HRRQ) output. If HREN is cleared, HREQ/HTRQ and HACK/HRRQ
are configured as GPIO signals according to the value of the HDDR and HDR.
6.5.6.6
HPCR Host Acknowledge Enable (HAEN) Bit 5
The HAEN bit controls the HACK signal. In the single host request mode (HDRQ is
cleared in the ICR), if HAEN and HREN are both set, HACK/HRRQ is configured as the
host acknowledge (HACK) input. If HAEN or HREN is cleared, HACK/HRRQ is
configured as a GPIO signal according to the value of the HDDR and HDR. In the double
host request mode (HDRQ is set in the ICR), HAEN is ignored.
6.5.6.7
HPCR Host Enable (HEN) Bit 6
If HEN is set, the HI08 operates as the host interface. If HEN is cleared, the HI08 is not
active, and all the HI08 signals are configured as GPIO signals according to the value of
the HDDR and HDR.
6.5.6.8
HPCR Reserved Bit 7
This bit is reserved. It is read as 0 and should be written as 0.
6.5.6.9
HPCR Host Request Open Drain (HROD) Bit 8
The HROD bit controls the output drive of the host request signals. In the single host
request mode (HDRQ is cleared in ICR), if HROD is cleared and host requests are
enabled (HREN is set and HEN is set in HPCR), the HREQ signal is always driven by the
HI08. If HROD is set and host requests are enabled, the HREQ signal is an open drain
output. In the double host request mode (HDRQ is set in the ICR), if HROD is cleared
and host requests are enabled (HREN is set and HEN is set in the HPCR), the HTRQ and
HRRQ signals are always driven. If HROD is set and host requests are enabled, the
HTRQ and HRRQ signals are open drain outputs.
6.5.6.10
HPCR Host Data Strobe Polarity (HDSP) Bit 9
If HDSP is cleared, the data strobe signals are configured as active low inputs, and data
is transferred when the data strobe is low. If HDSP is set, the data strobe signals are
configured as active high inputs, and data is transferred when the data strobe is high.
The data strobe signals are either HDS by itself or both HRD and HWR together.
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6.5.6.11
HPCR Host Address Strobe Polarity (HASP) Bit 10
If HASP is cleared, the host address strobe (HAS) signal is an active low input, and the
address on the host address/data bus is sampled when the HAS signal is low. If HASP is
set, HAS is an active high address strobe input, and the address on the host address or
data bus is sampled when the HAS signal is high.
6.5.6.12
HPCR Host Multiplexed Bus (HMUX) Bit 11
If HMUX is set, the HI08 latches the lower portion of a multiplexed address/data bus. In
this mode the internal address line values of the host registers are taken from the
internal latch. If HMUX is cleared, it indicates that the HI08 is connected to a
non-multiplexed type of bus. The values of the address lines are then taken from the
HI08 input signals.
6.5.6.13
HPCR Host Dual Data Strobe (HDDS) Bit 12
If the HDDS bit is cleared, the HI08 operates in the single-strobe bus mode. In this mode,
the bus has a single data strobe signal for both reads and writes. If set, the HI08 operates
in the dual-strobe bus mode. In this mode, the bus has two separate data strobes, one for
data reads, the other for data writes. See Figure 6-7 and Figure 6-8 for more information
on the two types of buses.
.
HRW
HDS
In a single-strobe bus, a DS (data strobe) signal qualifies the access, while a R/W (Read-Write)
signal specifies the direction of the access.
AA0661
Figure 6-7 Single Strobe Bus
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HI08 DSP Side ProgrammerÕs Model
Data
Write Data In
HWR
Write Cycle
Data
Read Data Out
HRD
Read Cycle
In dual strobe bus, there are separate HRD and HWR signals that specify the access as being
a read or write access, respectively.
AA0662
Figure 6-8 Dual Strobe Bus
6.5.6.14
HPCR Host Chip Select Polarity (HCSP) Bit 13
If the HCSP bit is cleared, the host chip select (HCS) signal is configured as an active low
input and the HI08 is selected when the HCS signal is low. If the HCSP signal is set, HCS
is configured as an active high input, and the HI08 is selected when the HCS signal is
high.
6.5.6.15
HPCR Host Request Polarity (HRP) Bit 14
The HRP bit controls the polarity of the host request signals. In the single-host request
mode (HDRQ is cleared in the ICR), if HRP is cleared, and host requests are enabled
(HREN is set and HEN is set), the HREQ signal is an active low output. If HRP is set and
host requests are enabled, the HREQ signal is an active high output.
In the double-host request mode (HDRQ is set in the ICR), if HRP is cleared, and host
requests are enabled (HREN is set and HEN is set), the HTRQ and HRRQ signals are
active low outputs. If HRP is set, and host requests are enabled, the HTRQ and HRRQ
signals are active high outputs.
6.5.6.16
HPCR Host Acknowledge Polarity (HAP) Bit 15
If the HAP bit is cleared, the host acknowledge (HACK) signal is configured as an active
low input. The HI08 drives the contents of the IVR onto the host bus when the HACK
signal is low. If the HAP bit is set, the HACK signal is configured as an active high input.
The HI08 outputs the contents of the IVR when the HACK signal is high.
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HI08 DSP Side ProgrammerÕs Model
6.5.7
Host Data Direction Register (HDDR)
The HDDR controls the direction of the data flow for each of the HI08 signals configured
as GPIO. It is illustrated in Figure 6-9. Even when the HI08 functions as the host
interface, its unused signals can be configured as GPIO signals. For information on the
HI08 GPIO configuration options, see Section 6.6.8ÑGeneral-Purpose I/O on page 6-30.
If bit DRxx is set, the corresponding HI08 signal is configured as an output signal. If bit
DRxx is cleared, the corresponding HI08 signal is configured as an input signal.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DR15 DR14 DR13 DR12 DR11 DR10 DR9
DR8
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
AA0663
Figure 6-9 Host Data Direction Register (HDDR) (X:$FFFFC8)
6.5.8
Host Data Register (HDR)
The HDR register holds the data value of the corresponding bits of the HI08 signals
configured as GPIO signals. It is illustrated in Figure 6-10. The functionality of the Dxx
bit depends on the corresponding HDDR bit (DRxx), as in Table 6-5. The HDR cannot be
accessed by the host processor.
15
D15
14
D14
13
D13
12
D12
11
D11
10
D10
9
D9
8
D8
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
AA0664
Figure 6-10 Host Data Register (HDR) (X:$FFFFC9)
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Table 6-5 HDR and HDDR Functionality
HDDR
HDR
Dxx
DRxx
Configured as GPIO signal
Configured as non-GPIO signal
0
Read only bitÑ The value read is the
binary value of the signal. The
corresponding signal is configured as
an input.
Read only bitÑDoes not contain
significant data.
1
Read/write bitÑ The value written is
the value read. The corresponding
signal is configured as an output, and
is driven with the data written to Dxx.
Read/write bitÑ The value written is
the value read.
6.5.9
DSP Side Registers After Reset
Table 6-6 shows the results of the four reset types on the bits in each of the HI08 registers
accessible by the DSP56309. Reset types are as follows:
¥ Hardware reset (HW)Ñcaused by the RESET signal
¥ Software reset (SW)Ñcaused by executing the RESET instruction
¥ Individual reset (IR)Ñcaused by clearing the HPCR:HEN
¥ Stop reset (ST)Ñcaused by executing the STOP instruction.
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Table 6-6 DSP Side Registers after Reset
Reset Type
Register
Name
Register
Data
HW
Reset
SW
Reset
IR
ST
Reset
Reset
HCR
All bits
0
0
bit value
indeterminate
Ñ
after reset
HPCR
HSR
All bits
HF[1:0]
HCP
0
0
Ñ
Ñ
0
0
Ñ
Ñ
0
0
0
1
0
1
HTDE
1
0
1
0
HRDF
0
0
HBAR
HDDR
HDR
BA[10:3]
DR[15:0]
D[15:0]
$80
0
$80
0
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
HRX
HRX [23:0]
HTX [23:0]
empty
empty
empty
empty
empty
empty
empty
empty
HTX
6.5.10
Host Interface DSP Core Interrupts
The HI08 can request interrupt service from either the DSP56309 or the host processor.
The DSP56309 interrupts are internal and do not require the use of an external interrupt
signal. When the appropriate interrupt enable bit in the HCR is set, an interrupt
condition caused by the host processor sets the appropriate bit in the HSR, generating an
interrupt request to the DSP56309. (See Figure 6-11.) The DSP56309 acknowledges
interrupts caused by the host processor by jumping to the appropriate interrupt service
routine. There are three possible interrupts:
¥ Host command
¥ Transmit data register empty
¥ Receive data register full
Although there is a set of vectors reserved for host command use, the host command can
access any interrupt vector in the interrupt vector table. The DSP interrupt service
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HI08-External Host ProgrammerÕs Model
routine must read or write the appropriate HI08 register (e.g., clearing HRDF or HTDE)
to clear the interrupt. For host command interrupts, the interrupt acknowledge from the
DSP56309 program controller clears the pending interrupt condition.
Enable
15
0
X:HCR
HF3
HF2 HCIE HTIE HRIE HCR
DSP Core Interrupts
Receive Data Full
Transmit Data Empty
Host Command
15
0
X:HSR
HF1
HF0
HCP HTDE HRDF HSR
Status
AA0667
Figure 6-11 HSR-HCR Operation
6.6
HI08-EXTERNAL HOST PROGRAMMERÕS MODEL
The HI08 is a simple, high speed interface to a host processor. To the host bus, the HI08
appears to be eight byte-wide registers. Separate transmit and receive data registers are
double-buffered to allow the DSP core and host processor to transfer data efficiently at
high speed. The host can access the HI08 asynchronously by using polling techniques or
interrupt-based techniques.
The HI08 appears to the host processor as a memory-mapped peripheral occupying
eight bytes in the host processor address space, as in Table 6-7 on page 6-22. The eight
HI08 registers include the following:
¥ A control register (ICR)
¥ A status register (ISR)
¥ Three data registers (RXH/TXH, RXM/TXM, and RXL/TXL)
¥ Two vector registers (IVR and CVR)
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HI08-External Host ProgrammerÕs Model
The CVR is a special command register by which the host processor issues commands to
the DSP56309. Only the host processor can access this register.
Host processors can use standard host processor instructions (e.g., byte move) and
addressing modes to communicate with the HI08 registers. The HI08 registers are
aligned so that 8-bit host processors can use 8/16/24-bit load and store instructions for
data transfers. The HREQ/HTRQ and HACK/HRRQ handshake flags are provided for
polled or interrupt-driven data transfers with the host processor. Because of the speed of
the DSP56309 interrupt response, most host microprocessors can load or store data at
their maximum programmed I/O instruction rate without testing the handshake flags
for each transfer. If full handshake is not needed, the host processor can treat the
DSP56309 as a fast device, and data can be transferred between the host processor and
the DSP56309 at the fastest host processor data rate.
One of the most innovative features of the host interface is the host command feature.
With this feature, the host processor can issue vectored interrupt requests to the
DSP56309. The host can select any of 128 DSP interrupt routines for execution by writing
a vector address register in the HI08. This flexibility allows the host processor to execute
up to 128 pre-programmed functions inside the DSP56309. For example, use of the
DSP56309 host interrupts can allow the host processor to read or write DSP registers (X,
Y, or program memory locations), force interrupt handlers (e.g., SSI, SCI, IRQA, IRQB
interrupt routines), and perform control and debugging operations.
Note:
When the DSP enters stop mode, the HI08 signals are electrically disconnected
internally, thus disabling the HI08 until the core leaves stop mode. While the
HI08 configuration remains unchanged in stop mode, the core cannot be
restarted via the HI08 interface.
Do not issue a STOP command to the DSP via the HI08 unless some other
mechanism for exiting stop mode is provided.
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Table 6-7 Host Side Register Map
Host
Address
Big Endian
HLEND = 0
Little Endian
HLEND = 1
0
1
2
3
4
5
6
7
ICR
CVR
ICR
CVR
Interface Control
Command Vector
Interface Status
Interrupt Vector
Unused
ISR
ISR
IVR
IVR
00000000
RXH/TXH
RXM/TXM
RXL/TXL
00000000
RXL/TXL
RXM/TXM
RXH/TXH
Receive/Transmit
Bytes
Host Data Bus
H0 - H7
Host Data Bus
H0 - H7
6.6.1
Interface Control Register (ICR)
The ICR is an 8-bit, read/write control register by which the host processor controls the
HI08 interrupts and flags. It is illustrated in Figure 6-12. The DSP core cannot access the
ICR. The ICR is a read/write register, which allows the use of bit manipulation
instructions on control register bits. The control bits are described in the following
paragraphs.
7
6
5
4
3
2
1
0
INIT
HLEND HF1
HF0
HDRQ TREQ RREQ
ÑReserved bit. Read as 0. Should be written with 0, for future compatibility.
AA0668
Figure 6-12 Interface Control Register
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6.6.1.1
ICR Receive Request Enable (RREQ) Bit 0
The RREQ bit controls the HREQ signal for host receive data transfers. RREQ enables
host requests via the host request (HREQ or HRRQ) signal when the receive data register
full (RXDF) status bit in the ISR is set. If RREQ is cleared, RXDF interrupts are disabled.
If RREQ and RXDF are set, the host request signal (HREQ or HRRQ) is asserted.
6.6.1.2
ICR Transmit Request Enable (TREQ) Bit 1
TREQ enables host requests via the host request (HREQ or HTRQ) signal when the
transmit data register empty (TXDE) status bit in the ISR is set. If TREQ is cleared, TXDE
interrupts are disabled. If TREQ and TXDE are set, the host request signal is asserted.
Table 6-8 and Table 6-9 summarize the effect of RREQ and TREQ on the HREQ and
HRRQ signals.
Table 6-8 TREQ and RREQ modes (HDRQ = 0)
TREQ
RREQ
HREQ Signal
0
0
1
1
0
1
0
1
No Interrupts (Polling)
RXDF Request (Interrupt)
TXDE Request (Interrupt)
RXDF and TXDE Request (Interrupts)
Table 6-9 TREQ and RREQ modes (HDRQ = 1)
TREQ
RREQ
HTRQ Single
HRRQ Signal
0
0
1
1
0
1
0
1
No Interrupts (Polling)
No Interrupts (Polling)
TXDE Request (Interrupt)
TXDE Request (Interrupt)
No Interrupts (Polling)
RXDF Request (Interrupt)
No Interrupts (Polling)
RXDF Request (Interrupt)
6.6.1.3
ICR Double Host Request (HDRQ) Bit 2
If cleared, the HDRQ bit configures HREQ/HTRQ and HACK/HRRQ as HREQ and
HACK, respectively. If HDRQ is set, HREQ/HTRQ and HACK/HRRQ are configured
as HTRQ and HRRQ, respectively.
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6.6.1.4
ICR Host Flag 0 (HF0) Bit 3
The HF0 bit is a general-purpose flag for host-to-DSP communication. The host
processor can set or clear HF0, and the DSP56309 cannot change this bit. HF0 is reflected
in the HSR on the DSP side of the HI08.
6.6.1.5
ICR Host Flag 1 (HF1) Bit 4
The HF1 bit is a general-purpose flag for host-to-DSP communication. The host
processor can set or clear HF1, and the DSP56309 cannot change this bit. HF1 is reflected
in the HSR on the DSP side of the HI08.
6.6.1.6
ICR Host Little Endian (HLEND) Bit 5
If the HLEND bit is cleared, the host can access the HI08 in big endian byte order. If set,
the host can access the HI08 in little endian byte order. If the HLEND bit is cleared the
RXH/TXH register is located at address $5, the RXM/TXM register at $6, and the
RXL/TXL register at $7. If the HLEND bit is set, the RXH/TXH register is located at
address $7, the RXM/TXM register at $6, and the RXL/TXL register at $5.
6.6.1.7
ICR Reserved Bit 6
This bit is reserved. It is read as 0 and should be written with 0.
6.6.1.8
ICR Initialize Bit (INIT) Bit 7
The host processor uses the INIT bit to force initialization of the HI08 hardware. During
initialization, the HI08 transmit and receive control bits are configured. Using the INIT
bit to initialize the HI08 hardware may or may not be necessary, depending on the
software design of the interface.
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The tÒype of initialization done when the INIT bit is set depends on the state of TREQ
and RREQ in the HI08. The INIT command, which is local to the HI08, can conveniently
configure the HI08 into the desired data transfer mode. The effect of the INIT command
is described in Table 6-10. When the host sets the INIT bit, the HI08 hardware executes
the INIT command. The interface hardware clears the INIT bit after the command has
been executed.
Table 6-10 INIT Command Effects
Transfer Direction
TREQ RREQ
After INIT Execution
Initialized
0
0
1
1
0
1
0
1
INIT = 0
None
INIT = 0; RXDF = 0; HTDE = 1
INIT = 0; TXDE = 1; HRDF = 0
DSP to Host
Host to DSP
INIT = 0; RXDF = 0; HTDE = 1; TXDE = 1;
HRDF = 0
Host to/from DSP
6.6.2
Command Vector Register (CVR)
The host processor uses the CVR to cause the DSP56309 to execute an interrupt. The host
command feature is independent of any of the data transfer mechanisms in the HI08. It
can cause any of the 128 possible interrupt routines in the DSP core to be executed. This
register is illustrated in Figure 6-13.
7
6
5
4
3
2
1
0
HC
HV6
HV5
HV4
HV3
HV2
HV1
HV0
AA0669
Figure 6-13 Command Vector Register (CVR)
6.6.2.1
CVR Host Vector (HV[6:0]) Bits 0Ð6
The seven HV bits select the host command interrupt address to be used by the host
command interrupt logic. When the host command interrupt is recognized by the DSP
interrupt control logic, the address of the interrupt routine taken is 2 ´ HV. The host can
write HC and HV in the same write cycle.
The host processor can select any of the 128 possible interrupt routine starting addresses
in the DSP by writing the interrupt routine address divided by two into the HV bits. This
means that the host processor can force any of the existing interrupt handlers (SSI, SCI,
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IRQA, IRQB, etc.) and can use any of the reserved or otherwise unused addresses
(provided they have been pre-programmed in the DSP). HV is set to $32 (vector location
$0064) by a hardware RESET signal, software RESET instruction, individual reset, or a
STOP instruction.
6.6.2.2
CVR Host Command Bit (HC) Bit 7
The host processor uses the HC bit to handshake the execution of host command
interrupts. Normally, the host processor sets HC to request a host command interrupt
from the DSP56309. When the DSP56309 acknowledges the host command interrupt, the
HI08 hardware clears the HC bit. The host processor can read the state of HC to
determine when the host command has been accepted. After setting HC, the host must
not write to the CVR again until the HI08 hardware clears HC. Setting the HC bit causes
host command pending (HCP) to be set in the HSR. The host can write to the HC and HV
bits in the same write cycle.
6.6.3
Interface Status Register (ISR)
The interface status register (ISR) is an 8-bit, read-only status register used by the host
processor to interrogate the status and flags of the HI08. The host processor can write to
this address without affecting the internal state of the HI08. The DSP core cannot access
the ISR. The ISR bits are described in the following paragraphs. This register is
illustrated in Figure 6-14.
7
6
5
4
3
2
1
0
HREQ
HF3
HF2
TRDY TXDE RXDF
ÑReserved bit. Read as 0. Should be written with 0, for future compatibility.
AA0670
Figure 6-14 Interface Status Register
6.6.3.1
ISR Receive Data Register Full (RXDF) Bit 0
The RXDF bit indicates that the receive byte registers (RXH:RXM:RXL) contain data
from the DSP56309 and can be read by the host processor. RXDF is set when the HTX is
transferred to the receive byte registers. RXDF is cleared when the receive data (RXL or
RXH according to HLEND bit) register is read by the host processor. RXDF can be
cleared by the host processor using the initialize function. RXDF can assert the external
HREQ signal if the RREQ bit is set. Regardless of whether the RXDF interrupt is enabled,
RXDF indicates whether the RX registers are full and data can be latched out so that the
host processor can use polling techniques.
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6.6.3.2
ISR Transmit Data Register Empty (TXDE) Bit 1
The TXDE bit indicates that the transmit byte registers (TXH:TXM:TXL) are empty and
can be written by the host processor. TXDE is set when the contents of the transmit byte
registers are transferred to the HRX register. TXDE is cleared when the transmit (TXL or
TXH according to HLEND bit) register is written by the host processor. The host
processor can set TXDE using the initialize function. TXDE can assert the external HTRQ
signal if the TREQ bit is set. Regardless of whether the TXDE interrupt is enabled, TXDE
indicates whether the TX registers are full and data can be latched in so that the host
processor can use polling techniques.
6.6.3.3
ISR Transmitter Ready (TRDY) Bit 2
The TRDY status bit indicates that TXH:TXM:TXL, and the HRX registers are empty.
TRDY = TXDE and HRDF
If TRDY is set, the data that the host processor writes to TXH:TXM:TXL is immediately
transferred to the DSP side of the HI08. This feature has many applications. For example,
if the host processor issues a host command which causes the DSP56309 to read the
HRX, the host processor can be guaranteed that the data it just transferred to the HI08 is
that being received by the DSP56309.
6.6.3.4
ISR Host Flag 2 (HF2) Bit 3
HF2 indicates the state of host flag 2 in the HCR on the DSP side. HF2 can be changed
only by the DSP56309, as documented in Section 6.5.3.4ÑHCR Host Flags 2,3 (HF[3:2])
Bits 3, 4 on page 6-10.
6.6.3.5
ISR Host Flag 3 (HF3) Bit 4
HF3 indicates the state of Host Flag 3 in the HCR on the DSP side. HF3 can be changed
only by the DSP56309, as documented in Section 6.5.3.4ÑHCR Host Flags 2,3 (HF[3:2])
Bits 3, 4 on page 6-10.
6.6.3.6
ISR Reserved Bits 5, 6
These bits are reserved. They are read as 0 and should be written with 0.
6.6.3.7
ISR Host Request (HREQ) Bit 7
HREQ indicates the status of the external transmit and receive request output signals
(HTRQ and HRRQ) if HDRQ is set. If HDRQ is cleared, it indicates the status of the
external host request output signal (HREQ). Table 6-11 shows possible settings of
HRDQ and HDEQ and their effects.
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Table 6-11 HREQ and HDRQ Settings
HDRQ HREQ
Effect
0
0
1
0
1
0
HREQ is cleared; no host processor interrupts are requested.
HREQ is set; an interrupt is requested.
HTRQ and HRRQ are cleared, no host processor interrupts are
requested.
1
1
HTRQ or HRRQ are set; an interrupt is requested.
The HREQ is set from either or both of two conditionsÑeither the receive byte registers
are full or the transmit byte registers are empty. These conditions are indicated by the
ISR RXDF and TXDE status bits, respectively. If the interrupt source has been enabled by
the associated request enable bit in the ICR, HREQ is set if one or more of the two
enabled interrupt sources is set.
6.6.4
Interrupt Vector Register (IVR)
The IVR is an 8-bit, read/write register which typically contains the interrupt vector
number used with MC68000 family processor vectored interrupts. Only the host
processor can read and write this register. The contents of the IVR are placed on the host
data bus, H[7:0], when both the HREQ and HACK signals are asserted. The contents of
this register are initialized to $0F by a hardware RESET signal or software RESET
instruction. This value corresponds to the uninitialized interrupt vector in the MC68000
family. This register is illustrated in Figure 6-15.
7
6
5
4
3
2
1
0
IV7
IV6
IV5
IV4
IV3
IV2
IV1
IV0
AA0671
Figure 6-15 Interrupt Vector Register (IVR)
6.6.5
Receive Byte Registers (RXH: RXM: RXL)
The receive byte registers are viewed by the host processor as three 8-bit, read-only
registers. These registers are the receive high register (RXH), the receive middle register
(RXM), and the receive low register (RXL). They receive data from the high, middle, and
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low bytes, respectively, of the HTX register and are selected by the external host address
inputs (HA[2:0]) during a host processor read operation.
The memory address of the receive byte registers is set by the HLEND bit in the ICR. If
the HLEND bit is set, the RXH is located at address $7, RXM at $6, and RXL at $5. If the
HLEND bit is cleared, the RXH is located at address $5, RXM at $6, and RXL at $7.
When data is written to the receive byte register at host address $7, the receive data
register full (RXDF) bit is set. The host processor can program the RREQ bit to assert the
external HREQ signal when RXDF is set. This indicates that the HI08 has a full word
(either 8, 16, or 24 bits) for the host processor. The host processor can program the RREQ
bit to assert the external HREQ signal when RXDF is set. Asserting the HREQ signal
informs the host processor that the receive byte registers have data to be read. When the
host reads the receive byte register at host address $7, the RXDF bit is cleared.
6.6.6
Transmit Byte Registers (TXH:TXM:TXL)
The host processor views the transmit byte registers as three 8-bit, write-only registers.
These registers are the transmit high register (TXH), the transmit middle register (TXM),
and the transmit low register (TXL). These registers send data to the high, middle, and
low bytes, respectively, of the HRX register and are selected by the external host address
inputs, HA[2:0], during a host processor write operation.
If the HLEND bit in the ICR is set, the TXH register is located at address $7, the TXM
register at $6 and the TXL register at $5. If the HLEND bit in the ICR is cleared, the TXH
register is located at address $5, the TXM register at $6, and the TXL register at $7.
Data is written into the transmit byte registers when the transmit data register empty
(TXDE) bit is set. The host processor programs the TREQ bit to assert the external
HREQ/HTRQ signal when TXDE is set. This informs the host processor that the
transmit byte registers are empty. Writing to the data register at host address $7 clears
the TXDE bit. The contents of the transmit byte registers are transferred as 24-bit data to
the HRX register when both the TXDE and the HRDF bit are cleared. This transfer
operation sets TXDE and HRDF.
Note:
When data is written to a peripheral device, there is a two-cycle pipeline delay
until any status bits affected by this operation are updated. If you read any of
those status bits within the next two cycles, the bit does not reflect its current
status. See the DSP56300 Family Manual, Appendix B, Polling a Peripheral
Device for Write for further details.
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6.6.7
Host Side Registers After Reset
Table 6-12 shows the result of the four kinds of reset on bits in each of the HI08 registers
seen by the host processor. The hardware reset is caused by asserting the RESET signal.
The software reset is caused by executing the RESET instruction. The individual reset is
caused by clearing the HEN bit in the HPCR. The stop reset is caused by executing the
STOP instruction.
Table 6-12 Host Side Registers After Reset
Reset Type
Register
Name
Register
Data
HW
SW
IR
ST
Reset
Reset
Reset
Reset
ICR
All Bits
HC
0
0
0
0
Ñ
0
Ñ
0
CVR
HV[0:6]
HREQ
$32
0
$32
0
Ñ
Ñ
ISR
1 if TREQ is set;
0 otherwise
1 if TREQ is set;
0 otherwise
HF3 -HF2
TRDY
0
1
0
1
Ñ
Ñ
1
1
1
1
TXDE
1
1
RXDF
0
0
0
0
IVR
RX
TX
IV[0:7]
$0F
$0F
Ñ
Ñ
RXH: RXM:RXL
TXH: TXM:TXL
empty empty
empty empty
empty
empty
empty
empty
6.6.8
General-Purpose I/O
When configured as GPIO, the HI08 is viewed by the DSP56309 as memory-mapped
registers, as documented in Section 6.5ÑHI08 DSP Side ProgrammerÕs Model on
page 6-8. Those memory-mapped registers control up to 16 I/O signals. Software RESET
instructions and hardware RESET signals clear all DSP side control registers and
configure the HI08 as GPIO with all 16 signals disconnected. External circuitry
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Servicing the Host Interface
connected to the HI08 may need external pull-up/pull-down resistors until the signals
are configured for operation. The registers cleared are the HPCR, HDDR, and HDR.
Selection between GPIO and HI08 is made by clearing HPCR bits 6 through 1 for GPIO
or setting these bits for HI08 functionality. If the HI08 is in GPIO mode, the HDDR
configures each corresponding signal in the HDR as an input signal if the HDDR bit is
cleared or as an output signal if the HDDR bit is set. (See Section 6.5.7ÑHost Data
Direction Register (HDDR) on page 6-17 and Section 6.5.8ÑHost Data Register (HDR)
also on page 6-17.)
6.7
SERVICING THE HOST INTERFACE
The HI08 can be serviced by using one of the following protocols:
¥ Polling
¥ Interrupts
The host processor writes to the appropriate HI08 register to reset the control bits and
configure the HI08 for proper operation.
6.7.1
HI08 Host Processor Data Transfer
To the host processor, the HI08 looks like a contiguous block of Static RAM. To transfer
data between itself and the HI08, the host processor performs the following steps:
1. asserts the HI08 address to select the register to be read or written
2. selects the direction of the data transfer
(If it is writing, the host processor sources the data on the bus.)
3. strobes the data transfer
6.7.2
Polling
In polling mode, the HREQ/HTRQ signal is not connected to the host processor and
HACK must be deasserted to insure IVR data is not being driven on H[7:0] when other
registers are being polled. (If the HACK function is not needed, the HACK signal can be
configured as a GPIO signal, as documented in Section 6.5.6ÑHost Port Control
Register (HPCR) on page 6-12.)
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The host processor first performs a data read transfer to read the ISR, as in Figure 6-16.
This convention allows the host processor to assess the status of the HI08 and perform
the appropriate actions.
Generally, after the appropriate data transfer has been made, the corresponding status
bit is updated to reflect the transfer.
¥ If RXDF is set, the receive data register is full, and the host processor can perform
a data read.
¥ If TXDE is set, the transmit data register is empty, and the host processor can
perform a data write.
¥ If TRDY is set, the transmit data register is empty. This implies that the receive
data register on the DSP side is also empty. Data written by the host processor to
the HI08 is transferred directly to the DSP side.
¥ If (HF2 and HF3) ¹ 0, depending on how the host flags have been used, this may
indicate that an application-specific state within the DSP56309 has been reached.
Intervention by the host processor may be required.
¥ If HREQ is set, the HREQ/TRQ signal has been asserted, and the DSP56309 is
requesting the attention of the host processor. One of the previous four conditions
exists.
After the appropriate data transfer has been made, the corresponding status bit is
updated to reflect the transfer.
If the host processor has issued a command to the DSP56309 by writing to the CVR and
setting the HC bit, it can read the HC bit in the CVR to determine whether the command
has been accepted by the interrupt controller in the DSP core. When the command has
been accepted for execution, the HC bit is cleared by the interrupt controller in the DSP
core.
6.7.3
Servicing Interrupts
If either HREQ/HTRQ or the HRRQ signal or both are connected to the host processorÕs
interrupt input, the HI08 can request service from the host processor by asserting one of
these signals. The HREQ/HTRQ and/or the HRRQ signal is asserted when TXDE is set
and/or RXDF is set and the corresponding enable bit (TREQ or RREQ, respectively) is
set. This situation appears in Figure 6-16.
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Status
TXDE RXDF ISR
7
0
$2
HREQ
0
0
HF3
HF2 TRDY
Host Request
Asserted
HRRQ
HREQ
HTRQ
7
0
$0 INIT
0
0
HF1
HF0 HBEND TREQ RREQ ICR
Enable
AA0672
Figure 6-16 HI08 Host Request Structure
HREQ is normally connected to the maskable interrupt input of the host processor. The
host processor acknowledges host interrupts by executing an interrupt service routine.
The host processor can test the two LSBs (RXDF and TXDE) of the ISR register to
determine the interrupt source, as in Figure 6-16. The host processor interrupt service
routine must read or write the appropriate HI08 data register to clear the interrupt.
HREQ/HTRQ and/or HRRQ is deasserted under either of the following conditions:
¥ The enabled request is cleared or masked.
¥ The DSP is reset.
If the host processor is a member of the MC68000 family, there is no need for the
additional step when the host processor reads the ISR to determine how to respond to an
interrupt generated by the DSP56309. Instead, the DSP56309 automatically sources the
contents of the IVR on the data bus when the host processor acknowledges the interrupt
by asserting HACK. The contents of the IVR are placed on the host data bus while
HREQ/TRQ (or HRRQ) and HACK are simultaneously asserted. The IVR data tells the
MC680XX host processor which interrupt routine to execute to service the DSP56309.
Table 6-13 shows the HI08 programming model.
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HI08 Programming Model Quick Reference
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SECTION 7
ENHANCED SYNCHRONOUS SERIAL
INTERFACE (ESSI)
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Enhanced Synchronous Serial Interface (ESSI)
7.1
7.2
7.3
7.4
7.5
7.6
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
ENHANCEMENTS TO THE ESSI . . . . . . . . . . . . . . . . . . . . . 7-3
ESSI DATA AND CONTROL SIGNALS . . . . . . . . . . . . . . . . 7-4
ESSI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . 7-8
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
GPIO SIGNALS AND REGISTERS. . . . . . . . . . . . . . . . . . . 7-43
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Enhanced Synchronous Serial Interface (ESSI)
Introduction
7.1
INTRODUCTION
The Enhanced Synchronous Serial Interface (ESSI) provides a full-duplex serial port for
serial communication with a variety of serial devices, including one or more
industry-standard codecs, other DSPs, microprocessors, and peripherals that implement
the Motorola Serial Peripheral Interface (SPI). The ESSI consists of independent
transmitter and receiver sections and a common ESSI clock generator.
There are two independent and identical ESSIs in the DSP56309: ESSI0 and ESSI1. For
the sake of simplicity, a single generic ESSI is described.
The ESSI block diagram appears in Figure 7-1 on page 7-5. This interface is synchronous
because all serial transfers are synchronized to a clock.
Note:
This should not be confused with the asynchronous mode of the ESSI, in
which separate clocks are used for the receiver and transmitter. In this mode,
the ESSI is still a synchronous device, because all transfers are synchronized to
these clocks.
Additional synchronization signals are used to delineate the word frames. Normal mode
is used to transfer data at a periodic rate, one word per period. Network mode is similar
in that it is also intended for periodic transfers; however, it supports up to 32 words
(time slots) per period. Network mode can be used to build time division multiplexed
(TDM) networks. In contrast, on-demand mode is intended for non-periodic transfers of
data. This mode can be used to transfer data serially at high speed when the data become
available. This mode offers a subset of the SPI protocol.
Since each ESSI unit can be configured with one receiver and three transmitters, the two
units can be used together for surround sound applications (which need two digital
input channels and six digital output channels).
7.2
ENHANCEMENTS TO THE ESSI
The synchronous serial interface (SSI) used in the DSP56000 family has been enhanced in
the following ways to make the ESSI:
¥ Network enhancements
Ð Time slot mask registers (receive and transmit) added
Ð End-of-frame interrupt added
Ð Drive enable signal added (to be used with transmitter 0)
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Enhanced Synchronous Serial Interface (ESSI)
ESSI Data and Control Signals
¥ Audio enhancements
Ð Three transmitters per ESSI (for six-channel surround sound)
¥ General enhancements
Ð Can trigger DMA interrupts (receive or transmit)
Ð Separate exception enable bits
¥ Other Changes
Ð One divide by 2 removed from the internal clock source chain
Ð CRA (PSR) bit definition is reversed
Ð Gated clock mode not available
7.3
ESSI DATA AND CONTROL SIGNALS
Three to six signals are required for ESSI operation, depending on the operating mode
selected. The serial transmit data (STD) signal and serial control (SC0 and SC1) signals
are fully synchronized to the clock if they are programmed as transmit-data signals.
7.3.1
Serial Transmit Data (STD) Signal
The STD signal is used for transmitting data from the TX0 serial transmit shift register.
STD is an output when data is being transmitted from the TX0 shift register. With an
internally generated bit clock, the STD signal becomes a high impedance output signal
for a full clock period after the last data bit has been transmitted. If sequential data
words are being transmitted, the STD signal does not assume a high-impedance state.
The STD signal can be programmed as a GPIO signal (P5) when the ESSI STD function is
not being used.
7.3.2
Serial Receive Data Signal (SRD)
The SRD signal receives serial data and transfers the data to the ESSI receive shift
register. SRD can be programmed as a GPIO signal (P4) when the ESSI SRD function is
not being used.
The ESSI block diagram is shown in Figure 7-1.
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Enhanced Synchronous Serial Interface (ESSI)
ESSI Data and Control Signals
GDB
DDB
RCLK
SRD
STD
RX SHIFT REG
RX
RSMA
RSMB
TCLK
TSMA
TSMB
TX0 SHIFT REG
TX0
CRA
CRB
TX1 SHIFT REG
TX1
SC0
SC1
TSR
TX2 SHIFT REG
TX2
SSISR
Interrupts
Clock/Frame Sync Generators and Control Logic
SC2
SCK
AA0678
Figure 7-1 ESSI Block Diagram
7.3.3
Serial Clock (SCK)
The SCK signal is a bidirectional signal providing the serial bit rate clock for the ESSI
interface. The SCK signal is a clock input or output used by all the enabled transmitters
and receiver in synchronous modes or by all the enabled transmitters in asynchronous
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Enhanced Synchronous Serial Interface (ESSI)
ESSI Data and Control Signals
modes; see Table 7-1 on page 7-8. SCK can be programmed as a GPIO signal (P3) when
the ESSI SCK function is not being used.
Notes:
1. Although an external serial clock can be independent of and asynchronous
to the DSP system clock, the external ESSI clock frequency must not exceed
F
/3, and each ESSI phase must exceed the minimum of 1.5 CLKOUT
core
cycles.
2. The internally sourced ESSI clock frequency must not exceed F /4.
core
7.3.4
Serial Control Signal (SC0)
SC00 is a serial control signal for ESSI0, and SC10 is a serial control signal for ESSI1. They
are referred to collectively as SC0.
The function of this signal is determined by selecting either synchronous or
asynchronous mode; see Table 7-4 on page 7-24. In asynchronous mode, this signal is
used for the receive clock I/O. In synchronous mode, this signal is used as the
transmitter data out signal for transmit shift register 1 or for serial flag I/O. A typical
application of serial flag I/O would be multiple device selection for addressing in codec
systems.
If SC0 is configured as a serial flag signal, its direction is determined by the serial control
direction 0 (SCD0) bit in the ESSI control register B (CRB). When configured as an
output, its value is determined by the value of the serial output flag 0 (OF0) bit in the
CRB. When configured as an input, SC0 controls the state of serial input flag 0 (IF0) bit in
the ESSI status register (SSISR).
When SC0 is configured as a transmit data signal, it is always an output signal
regardless of the SCD0 bit value. SC0 is fully synchronized with the other transmit data
signals (STD and SC1).
In asynchronous mode, SC0 is configured as the receive clock. The direction of the SC0
in this mode is also determined by SCD0.
SC0 can be programmed as a GPIO signal (P0) when the ESSI SC0 function is not being
used.
Note:
The ESSI can operate with more than one active transmitter only in
synchronous mode.
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Enhanced Synchronous Serial Interface (ESSI)
ESSI Data and Control Signals
7.3.5
Serial Control Signal (SC1)
SC01 is a serial control signal for ESSI0, and SC11 is a serial control signal for ESSI1. They
are referred to collectively as SC1.
The function of this signal is determined by selecting either synchronous or
asynchronous mode; see Table 7-4 on page 7-24. In asynchronous mode (such as a single
codec with asynchronous transmit and receive), SC1 is the receiver frame sync I/O. In
synchronous mode, SC1 is used for the transmitter data out signal of transmit shift
register TX2, for the drive enable transmitter 0 signal, or for serial flag SC1.
When used as a serial flag signal, SC1 operates like the previously described SC0. SC0
and SC1 are independent flags but can be used together for multiple serial device
selection. SC0 and SC1 can be used unencoded to select up to two codecs or can be
decoded externally to select up to four codecs.
If SC1 is configured as a serial flag signal, its direction is determined by the SCD1 bit in
the CRB. When configured as an output, its value is determined by the value of the serial
output flag1 (OF1) bit in the CRB. When configured as an input, SC0 controls the stated
serial input flag 1 (IF1) bits in SSISR.
When SC1 is configured as a transmit data signal, it is always an output signal
regardless of the SCD1 bit value. As an output, it is fully synchronized with the other
ESSI transmit data signals (STD and SC0).
In asynchronous mode, SC1 is configured as the receive frame sync. The direction of SC1
in this mode is determined by SCD1.
SC1 can be programmed as a GPIO signal (P1) when the ESSI SC1 function is not being
used.
Table 7-1 summarizes ESSI clock sources, whether synchronous or asynchronous, and
shows the bit settings for the signals involved.
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ESSI Programming Model
Table 7-1 ESSI Clock Sources
RX
Clock
Out
R Clock
Source
T Clock
Source
SYN
SCKD
SCD0
TX Clock Out
Asynchronous
0
0
0
0
0
0
1
1
0
1
0
1
EXT, SC0
Ñ
SC0
Ñ
EXT, SCK
EXT, SCK
INT
Ñ
Ñ
INT
EXT, SC0
INT
SCK
SCK
SC0
INT
Synchronous
1
1
0
1
0/1
0/1
EXT, SCK
INT
Ñ
EXT, SCK
INT
Ñ
SCK
SCK
7.3.6
Serial Control Signal (SC2)
SC02 is a serial control signal for ESSI0, and SC12 is a serial control signal for ESSI1. They
are referred to collectively as SC2.
This signal is used for frame sync I/O. SC2 is the frame sync for both the transmitter and
receiver in synchronous mode and for the transmitter only in asynchronous mode. The
direction of this signal is determined by the SCD2 bit in the CRB. When configured as an
output, this signal outputs the internally generated frame sync signal. When configured
as an input, this signal receives an external frame sync signal for the transmitter in
asynchronous mode and for the receiver when in synchronous mode. SC2 can be
programmed as a GPIO signal (P2) when the ESSI SC2 function is not being used.
7.4
ESSI PROGRAMMING MODEL
The ESSI includes the following registers:
¥ Two control registers (CRA, CRB) illustrated in Figure 7-2 and Figure 7-3
¥ One status register (SSISR) illustrated in Figure 7-4
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ESSI Programming Model
¥ Three transmit data registers (TX0, TX1, TX2)
¥ One receive data register (RX)
¥ Two transmit slot mask registers (TSMA, TSMB) illustrated in Figure 7-5 and
Figure 7-6
¥ Two receive slot mask registers (RSMA, RSMB) illustrated in Figure 7-7 and
Figure 7-8
¥ One special-purpose time slot register (TSR)
The following paragraphs give detailed descriptions and operations of each of the bits in
the ESSI registers. The GPIO functionality of the ESSI is documented in
Section 7.6ÑGPIO Signals and Registers of this manual.
11
10
9
8
7
6
5
4
3
2
1
0
PSR
PM7
PM6
PM5
PM4
PM3
PM2
PM1
PM0
23
22
21
20
19
18
17
16
15
14
13
12
SSC1
WL2
WL1
WL0
ALC
DC4
DC3
DC2
DC1
DC0
AA0857
Figure 7-2 ESSI Control Register A (CRA)
(ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5)
11
10
9
8
7
6
5
4
3
2
1
0
CKP
FSP
FSR
FSL1
FSL0
SHFD
SCKD
SCD2
SCD1
SCD0
OF1
OF0
23
22
21
20
19
18
17
16
15
14
13
12
REIE
TEIE
RLIE
TLIE
RIE
TIE
RE
TE0
TE1
TE2
MOD
SYN
AA0858
Figure 7-3 ESSI Control Register B (CRB)
(ESSI0 X:$FFFFB6, ESSI1 X:$FFFFA6)
11
23
10
22
9
8
7
RDF
6
TDE
5
ROE
4
TUE
3
RFS
2
TFS
1
IF1
0
IF0
21
20
19
18
17
16
15
14
13
12
AA0859
Figure 7-4 ESSI Status Register (SSISR)
(ESSI0 X:$FFFFB7, ESSI1 X:$FFFFA7)
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ESSI Programming Model
11
10
9
8
7
6
5
4
3
2
1
0
TS11
TS10
TS9
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
23
22
21
20
19
18
17
16
15
14
13
12
TS15
TS14
TS13
TS12
AA0860
Figure 7-5 ESSI Transmit Slot Mask Register A (TSMA)
(ESSI0 X:$FFFFB4, ESSI1 X:$FFFFA4)
11
10
9
8
7
6
5
4
3
2
1
0
TS27
TS26
TS25
TS24
TS23
TS22
TS21
TS20
TS19
TS18
TS17
TS16
23
22
21
20
19
18
17
16
15
14
13
12
TS31
TS30
TS29
TS28
AA0861
Figure 7-6 ESSI Transmit Slot Mask Register B (TSMB)
(ESSI0 X:$FFFFB3, ESSI1 X:$FFFFA3)
11
10
9
8
7
6
5
4
3
2
1
0
RS11
RS10
RS9
RS8
RS7
RS6
RS5
RS4
RS3
RS2
RS1
RS0
23
22
21
20
19
18
17
16
15
14
13
12
RS15
RS14
RS13
RS12
AA0862
Figure 7-7 ESSI Receive Slot Mask Register A (RSMA)
(ESSI0 X:$FFFFB2, ESSI1 X:$FFFFA2)
11
10
9
8
7
6
5
4
3
2
1
0
RS27
RS26
RS25
RS24
RS23
RS22
RS21
RS20
RS19
RS18
RS17
RS16
23
22
21
20
19
18
17
16
15
14
13
12
RS31
RS30
RS29
RS28
Ð Reserved bit - read as zero should be written with zero for future compatibility
AA0863
Figure 7-8 ESSI Receive Slot Mask Register B (RSMB)
(ESSI0 X:$FFFFB1, ESSI1 X:$FFFFA1)
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ESSI Programming Model
7.4.1
ESSI Control Register A (CRA)
The ESSI control register A (CRA) is one of two 24-bit, read/write control registers used
to direct the operation of the ESSI. The CRA controls the ESSI clock generator bit and
frame sync rates, word length, and number of words per frame for the serial data. The
CRA control bits are described in the following paragraphs; see also Figure 7-2 on
page 7-9.
7.4.1.1
CRA Prescale Modulus Select PM[7:0] Bits 7Ð0
The PM[7:0] bits specify the divide ratio of the prescale divider in the ESSI clock
generator. A divide ratio from 1 to 256 (PM = $0 to $FF) can be selected. The bit clock
output is available at the transmit clock signal (SCK) and/or the receive clock (SC0)
signal of the DSP. The bit clock output is also available internally for use as the bit clock
to shift the transmit and receive shift registers. The ESSI clock generator functional
diagram is shown in Figure 7-9. F
is the DSP56309 core clock frequency (the same
core
frequency as the CLKOUT signal, when that signal is enabled). Careful choice of the
crystal oscillator frequency and the prescaler modulus allows generation of the
industry-standard codec master clock frequencies of 2.048 MHz, 1.544 MHz, and
1.536 MHz. Both the hardware RESET signal and the software RESET instruction clear
PM[7:0].
7.4.1.2
CRA Reserved Bits 8Ð10
These bits are reserved. They are read as 0 and should be written with 0.
7.4.1.3
CRA Prescaler Range (PSR) Bit 11
The PSR controls a fixed divide-by-eight prescaler in series with the variable prescaler.
This bit is used to extend the range of the prescaler for those cases where a slower bit
clock is desired. When PSR is set, the fixed prescaler is bypassed. When PSR is cleared,
the fixed divide-by-eight prescaler is operational; see Figure 7-9 on page 7-12.
Note:
This definition is reversed from that of the 560xx SSI.
The maximum allowed internally generated bit clock frequency is the internal DSP56309
clock frequency divided by 4; the minimum possible internally generated bit clock
frequency is the DSP56309 internal clock frequency divided by 4096. Both the hardware
RESET signal and the software RESET instruction clear PSR.
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ESSI Programming Model
Note:
The combination PSR = 1 and PM[7:0] = $00 (dividing F
synchronization problems and should not be used.
by 2) can cause
core
TX #1 or Flag0 Out
CRB(TE1) CRB(OF0)
(Sync Mode)
Flag0 In
SSISR(IF0)
(Sync Mode)
CRA(WL2:0)
RX
Word
Clock
/8, /12, /16, /24, /32
SCD0 = 0
SYN = 0
0
1
2
3
4,5
CRB(SYN) = 1
SCn0
SCKn
Sync:
RX Shift Register
TX #1, or
SYN = 0
SCD0 = 1
RCLOCK
SYN = 1
Flag0
Async:
RX clk
CRB(SCD0)
CRA(WL2:0)
TX
Word
Clock
TCLOCK
/8, /12, /16, /24, /32
4,5
0
1
2
3
Internal Bit Clock
Sync:
TX Shift Register
is the DSP56300 Core internal
TX/RX clk
Async:
TX clk
CRB(SCKD)
/2
Note: 1. F
CORE
clock frequency.
2. ESSI internal clock range:
CRA(PSR)
/1 or /8
CRA(PM7:0)
/1 to /256
min = F
/4096
OSC
max = F
/4
OSC
1
0
0
255
3. ÔnÕ in signal name is ESSI # (0 or 1)
F
(Opposite
from SSI)
CORE
AA0679
Figure 7-9 ESSI Clock Generator Functional Block Diagram
7.4.1.4
CRA Frame Rate Divider Control DC[4:0] Bits 16Ð12
The values of the DC[4:0] bits control the divide ratio for the programmable frame rate
dividers used to generate the frame clocks. In network mode, this ratio can be
interpreted as the number of words per frame minus one. In normal mode, this ratio
determines the word transfer rate.
The divide ratio can range from 1 to 32 (DC = 00000 to 11111) for normal mode and 2 to
32 (DC = 00001 to 11111) for network mode. A divide ratio of one (DC = 00000) in
network mode is a special case known as on-demand mode. In normal mode, a divide
ratio of one (DC = 00000) provides continuous periodic data word transfers. A bit-length
frame sync must be used in this case and is selected by setting the FSL[1:0] bits in the
CRA to (01). Both the hardware RESET signal and the software RESET instruction clear
DC[4:0].
The ESSI frame sync generator functional diagram is shown in Figure 7-10.
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ESSI Programming Model
CRB(FSL1)
CRB(FSR)
RX Word
Clock
CRA(DC4:0)
/1 to /32
Internal Rx Frame Sync
Sync
Type
CRB(SCD1)
SCn1
0
31
CRB(SCD1) = 1
SYN = 0
SYN = 1
CRB(SYN) = 0
Receive
Frame Sync
Receive
Control Logic
Sync:
SCD1 = 0
TX #2,
Flag1, or
drive enb.
SYN = 1
These signals are
identical in sync mode.
Async:
RX F.S.
Flag1 In
SSISR(IF1)
(Sync Mode)
CRB(FSL1:0)
CRB(FSR)
TX #2,
CRB(TE2) CRB(OF1)
Flag1 Out, or drive enb.
CRA(SSC1)
(Sync Mode)
TX Word
Clock
CRB(SCD2)
CRA(DC4:0)
/1 to /32
31
Internal TX Frame Sync
Sync
Type
SCn2
Sync:
TX/RX F.S.
0
Async:
TX F.S.
Transmit
Frame Sync
Transmit
Control Logic
AA0680
Figure 7-10 ESSI Frame Sync Generator Functional Block Diagram
7.4.1.5
CRA Reserved Bit 17
This bit is reserved. It is read as 0 and should be written with 0.
7.4.1.6 CRA Alignment Control (ALC) Bit 18
The ESSI is designed for 24-bit fractional data. Shorter data words are left aligned to the
MSB, Bit 23. For applications that use 16 bit fractional data, shorter data words are left
aligned to bit 15. The ALC bit supports shorter data words. If ALC is set, received words
are left aligned to bit 15 in the receive shift register. Transmitted words must be left
aligned to bit 15 in the transmit shift register. If the ALC bit is cleared, received words
are left aligned to bit 23 in the receive shift register. Transmitted words must be left
aligned to bit 23 in the transmit shift register. The ALC bit is cleared by either a
hardware RESET signal or a software RESET instruction.
Note:
If the ALC bit is set, only 8-, 12-, or 16-bit words should be used. The use of
24- or 32-bit words leads to unpredictable results.
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ESSI Programming Model
7.4.1.7
CRA Word-length Control (WL[2:0]) Bits 21Ð19
The WL[2:0] bits are used to select the length of the data words being transferred via the
ESSI. Word lengths of 8-, 12-, 16-, 24-, or 32- bits can be selected, as in Table 7-2. The
ESSI data path programming model in Figure 7-16 on page 7-31 and Figure 7-17 on
page 7-32 has additional information about selecting different length data words. The
ESSI data registers are 24 bits long. The ESSI transmits 32-bit words either by duplicating
the last bit eight times when WL[2:0] = 100, or by duplicating the first bit eight times
when WL[2:0] = 101. The WL[2:0] bits are cleared by a hardware RESET signal or by a
software RESET instruction.
Table 7-2 ESSI Word Length Selection
WL2
WL1
WL0
Number of Bits/Word
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
8
12
16
24
32
(valid data in the first 24 bits)
1
0
1
32
(valid data in the last 24 bits)
1
1
1
1
0
1
Reserved
Reserved
7.4.1.8
CRA Select SC1 (SSC1) Bit 22
The SSC1 bit controls the functionality of the SC1 signal. This bit is only valid when the
ESSI is configured in synchronous mode (i.e., if the CRB synchronous/asynchronous bit
(SYN) is set), and transmitter 2 is disabled (i.e., if transmit enable (TE2) = 0). If SSC1 is set
and SC1 is configured as an output (SCD1 = 1), then the SC1 signal acts as the driver
enabled signal of transmitter 0. This enables an external buffer for the transmitter 0
output.
If SSC1 is cleared, SC1 acts as the serial I/O flag.
7.4.1.9
CRA Reserved Bit 23
This bit is reserved. It is read as 0 and should be written with 0.
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ESSI Programming Model
7.4.2
ESSI Control Register B (CRB)
The CRB is one of two 24-bit, read/write control registers used to direct the operation of
the ESSI; see Figure 7-3 on page 7-9. CRB controls the ESSI multifunction signals,
SC[2:0], which can be used as clock inputs or outputs, frame synchronization signals,
transmit data signals, or serial I/O flag signals.
The serial output flag control bits and the direction control bits for the serial control
signals are in the ESSI CRB. Interrupt enable bits for the receiver and the transmitter are
also in the CRB. The bit setting of the CRB also determines how many transmitters are
enabled (0, 1, 2, or 3 transmitters can be enabled). The CRB settings also determine the
ESSI operating mode.
Either a hardware RESET signal or a software RESET instruction clears all the bits in the
CRB.
The relationship between the ESSI signals SC[2:0], SCK, and the CRB bits is summarized
in Table 7-4 on page 7-24. The ESSI CRB bits are described in the following paragraphs.
7.4.2.1
CRB Serial Output Flags (OF0, OF1) Bits 0, 1
The ESSI has two serial output flag bits, OF1 and OF0. The normal sequence for setting
output flags when transmitting data (by transmitter 0 through the STD signal only)
consists of these steps:
1. Wait for TDE (TX0 empty) to be set.
2. Write the flags.
3. Write the transmit data to the TX register.
Bits OF0 and OF1 are double-buffered so that the flag states appear on the signals when
the TX data is transferred to the transmit shift register. The flag bits values are
synchronized with the data transfer.
Note:
The timing of the optional serial output signals SC[2:0] is controlled by the
frame timing and is not affected by the settings of TE2, TE1, TE0, or the receive
enable (RE) bit of the CRB.
7.4.2.1.1
CRB Serial Output Flag 0 (OF0) Bit 0
When the ESSI is in synchronous mode and transmitter 1 is disabled (TE1 = 0), the SC0
signal is configured as ESSI flag 0. If the serial control direction bit (SCD0) is set, the SC0
signal is an output. Data present in bit OF0 is written to SC0 at the beginning of the
frame in normal mode or at the beginning of the next time slot in network mode.
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Bit OF0 is cleared by a hardware RESET signal or by a software RESET instruction.
7.4.2.1.2
CRB Serial Output Flag 1 (OF1) Bit 1
When the ESSI is in synchronous mode and transmitter 2 is disabled (TE2 = 0), the SC1
signal is configured as ESSI flag 1. If the serial control direction bit (SCD1) is set, the SC1
signal is an output. Data present in bit OF1 is written to SC1 at the beginning of the
frame in normal mode or at the beginning of the next time slot in network mode.
Bit OF1 is cleared by a hardware RESET signal or by a software RESET instruction.
7.4.2.2
CRB Serial Control Direction 0 (SCD0) Bit 2
In synchronous mode (SYN = 1) when transmitter 1 is disabled (TE1 = 0), or in
asynchronous mode (SYN = 0), SCD0 controls the direction of the SC0 I/O signal. When
SCD0 is set, SC0 is an output; when SCD0 is cleared, SC0 is an input.
When TE1 is set, the value of SCD0 is ignored, and the SC0 signal is always an output.
Bit SCD0 is cleared by a hardware RESET signal or by a software RESET instruction.
7.4.2.3
CRB Serial Control Direction 1 (SCD1) Bit 3
In synchronous mode (SYN = 1) when transmitter 2 is disabled (TE2 = 0), or in
asynchronous mode (SYN = 0), SCD1 controls the direction of the SC1 I/O signal. When
SCD1 is set, SC1 is an output; when SCD1 is cleared, SC1 is an input.
When TE2 is set, the value of SCD1 is ignored, and the SC1 signal is always an output.
Bit SCD1 is cleared by a hardware RESET signal or by a software RESET instruction.
7.4.2.4
CRB Serial Control Direction 2 (SCD2) Bit 4
SCD2 controls the direction of the SC2 I/O signal. When SCD2 is set, SC2 is an output;
when SCD2 is cleared, SC2 is an input. SCD2 is cleared by a hardware RESET signal or
by a software RESET instruction.
7.4.2.5
CRB Clock Source Direction (SCKD) Bit 5
SCKD selects the source of the clock signal. If SCKD is set and the ESSI is in synchronous
mode, the internal clock is the source of the clock signal used for all the transmit shift
registers and the receive shift register. If SCKD is set and the ESSI is in asynchronous
mode, the internal clock source becomes the bit clock for the transmit shift register and
word length divider. The internal clock is output on the SCK signal.
When SCKD is cleared, the external clock source is selected. The internal clock generator
is disconnected from the SCK signal, and an external clock source can drive this signal.
Either a hardware RESET signal or a software RESET instruction clears SCKD.
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7.4.2.6
CRB Shift Direction (SHFD) Bit 6
The setting of the SHFD bit determines the shift direction of the transmit or receive shift
register. If SHFD is set, data is shifted out with the LSB first. If SHFD is cleared, data is
shifted out MSB first; see Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32.
Received data is shifted in LSB first when SHFD is set or MSB first when SHFD is
cleared.
Either a hardware RESET signal or a software RESET instruction clears SHFD.
7.4.2.7
CRB Frame Sync Length FSL[1:0] Bits 7 and 8
These bits select the length of frame sync to be generated or recognized; see Figure 7-11
on page 7-19, Figure 7-14 on page 7-22, and Figure 7-15 on page 7-23. The values of
FSL[1:0] are documented in Table 7-3.
Table 7-3 FSL1 and FSL0 Encoding
Frame Sync Length
FSL1
FSL0
RX
TX
0
0
1
1
0
1
0
1
word
word
bit
word
bit
bit
bit
word
The word length is defined by WL[2:0].
Either a hardware RESET signal or a software RESET instruction clears FSL[1:0].
7.4.2.8 CRB Frame Sync Relative Timing (FSR) Bit 9
The FSR bit determines the relative timing of the receive and transmit frame sync signal
in reference to the serial data lines, for word length frame sync only. When FSR is
cleared, the word length frame sync occurs together with the first bit of the data word of
the first slot. When FSR is set, the word length frame sync occurs one serial clock cycle
earlier (i.e., simultaneously with the last bit of the previous data word).
Either a hardware RESET signal or a software RESET instruction clears FSR.
7.4.2.9
CRB Frame Sync Polarity (FSP) Bit 10
The FSP bit determines the polarity of the receive and transmit frame sync signals. When
FSP is cleared, the frame sync signal polarity is positive (i.e., the frame start is indicated
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by the frame sync signal going high). When FSP is set, the frame sync signal polarity is
negative (i.e., the frame start is indicated by the frame sync signal going low).
Either a hardware RESET signal or a software RESET instruction clears FRB.
7.4.2.10
CRB Clock Polarity (CKP) Bit 11
The CKP bit controls on which bit clock edge data and frame sync are clocked out and
latched in. If CKP is cleared, the data and the frame sync are clocked out on the rising
edge of the transmit bit clock and latched in on the falling edge of the receive bit clock. If
CKP is set, the data and the frame sync are clocked out on the falling edge of the transmit
bit clock and latched in on the rising edge of the receive bit clock.
Either a hardware RESET signal or a software RESET instruction clears CKP.
7.4.2.11
CRB Synchronous /Asynchronous (SYN) Bit 12
SYN controls whether the receive and transmit functions of the ESSI occur
synchronously or asynchronously with respect to each other; see Figure 7-12
on page 7-20. When SYN is cleared, the ESSI is in asynchronous mode, and separate
clock and frame sync signals are used for the transmit and receive sections. When SYN is
set, the ESSI is in synchronous mode and the transmit and receive sections use common
clock and frame sync signals. Only in synchronous mode can more than one transmitter
be enabled.
Either a hardware RESET signal or a software RESET instruction clears SYN.
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Word Length: FSL1 = 0, FSL0 = 0
Serial Clock
RX, TX Frame SYNC
RX, TX Serial Data
Data
Data
NOTE: Frame sync occurs while data is valid.
One Bit Length: FSL1 = 1, FSL0 = 0
Serial Clock
RX, TX Frame SYNC
RX, TX Serial Data
NOTE: Frame sync occurs for one bit time preceding the data.
Mixed Frame Length: FSL1 = 0, FSL0 = 1
Data
Data
Serial Clock
RX Frame Sync
RXSerial Data
Data
Data
Data
Data
TX Frame SYNC
TX Serial Data
Mixed Frame Length: FSL1 = 1, FSL0 = 1
Serial Clock
RX Frame SYNC
RX Serial Data
TX Frame SYNC
TX Serial Data
Data
Data
Data
Data
AA0681
Figure 7-11 CRB FSL0 and FSL1 Bit Operation (FSR = 0)
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7.4.2.12
CRB ESSI Mode Select (MOD) Bit 13
MOD selects the operational mode of the ESSI; see Figure 7-13 on page 7-21, Figure 7-14
on page 7-22, and Figure 7-15 on page 7-23. When MOD is cleared, normal mode is
selected; when MOD is set, network mode is selected. In normal mode, the frame rate
divider determines the word transfer rate: one word is transferred per frame sync during
the frame sync time slot. In network mode, a word can be transferred every time slot. For
more details, see Section 7.5ÑOperating Modes. Either a hardware RESET signal or a
software RESET instruction clears MOD.
Asynchronous (SYN = 0)
Transmitter
STD
Frame
SYNC
Clock
Clock
External Transmit Clock
Internal Clock
External Transmit Frame SYNC
Internal Frame SYNC
SC
SC2
SC1
ESSI Bit
Clock
External Receive Clock
External Receive Frame SYNC
SC0
Frame
SYNC
SRD
RECEIVER
NOTE: Transmitter and receiver can have different clocks and frame syncs.
SYNCHRONOUS (SYN = 1)
Transmitter
STD
Frame
SYNC
Clock
External Clock
Internal Clock
External Frame SYNC
Internal Frame SYNC
SCK
SC2
ESSI Bit
Clock
Clock
Frame
SYNC
SRD
Receiver
NOTE: Transmitter and receiver can have the same clock frame syncs.
AA0682
Figure 7-12 CRB SYN Bit Operation
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Frame SYNC
(FSL0 = 0, FSL1 = 0)
Frame SYNC
(FSL0 = 0, FSL1 = 1)
Data Out
Flags
Slot 0
Wait
Slot 0
AA0684
Figure 7-14 Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame)
7.4.2.13 Enabling, Disabling ESSI Data Transmission
The ESSI has three transmit enable bits (TE[2:0]), one for each data transmitter. The
process of transmitting data from TX1 and TX2 is the same. TX0 can also operate in
asynchronous mode. The normal transmit enable sequence is to write data to one or
more transmit data registers (or the time slot register (TSR)) before setting the TE bit. The
normal transmit disable sequence is to clear the TE, transmit interrupt enable (TIE), and
transmit exception interrupt enable (TEIE) bits after the transmit data empty (TDE) bit is
set. In network mode, clearing the appropriate TE bit and setting it again disables the
corresponding transmitter (0, 1, or 2) after transmission of the current data word. The
transmitter remains disabled until the beginning of the next frame. During that time
period, the corresponding SC (or STD in the case of TX0) signal remains in the
high-impedance state.
7.4.2.14
CRB ESSI Transmit 2 Enable (TE2) Bit 14
The TE2 bit enables the transfer of data from TX2 to transmit shift register 2. TE2 is
functional only when the ESSI is in synchronous mode and is ignored when the ESSI is
in asynchronous mode.
When TE2 is set and a frame sync is detected, transmitter 2 is enabled for that frame.
When TE2 is cleared, transmitter 2 is disabled after completing transmission of data
currently in the ESSI transmit shift register. Any data present in TX2 is not transmitted. If
TE2 is cleared, data can be written to TX2; the TDE bit is cleared, but data is not
transferred to transmit shift register 2.
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Keeping the TE2 bit cleared until the start of the next frame causes the SC1 signal to act
as serial I/O flag from the start of the frame, in both normal and network mode. The
on-demand mode transmit enable sequence can be the same as normal mode, or the TE2
bit can be left enabled.
The TE2 bit is cleared by either a hardware RESET signal or a software RESET
instruction.
Note:
The setting of the TE2 bit does not affect the generation of frame sync or
output flags.
Frame SYNC
(FSL0 = 0, FSL1 = 0)
Frame SYNC
(FSL0 = 0, FSL1 = 1)
Data
Flags
SLOT 0
SLOT 1
SLOT 0
SLOT 1
AA1593
Figure 7-15 Network Mode, External Frame Sync (8 Bit, 2 Words in Frame)
7.4.2.15
CRB ESSI Transmit 1 Enable (TE1) Bit 15
The TE1 bit enables the transfer of data from TX1 to transmit shift register 1. TE1 is
functional only when the ESSI is in synchronous mode and is ignored when the ESSI is
in asynchronous mode.
When TE1 is set and a frame sync is detected, the transmitter 1 is enabled for that frame.
When TE1 is cleared, transmitter 1 is disabled after completing transmission of data
currently in the ESSI transmit shift register. Any data present in TX1 is not transmitted. If
TE1 is cleared, data can be written to TX1; the TDE bit is cleared, but data is not
transferred to transmit shift register 1.
Keeping the TE1 bit cleared until the start of the next frame causes the SC0 signal to act
as serial I/O flag from the start of the frame, in both normal and network mode. The
transmit enable sequence for on-demand mode can be the same as for normal mode, or
the TE1 bit can be left enabled.
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The TE1 bit is cleared by either a hardware RESET signal or a software RESET
instruction.
Note:
The setting of the TE1 bit does not affect the generation of frame sync or
output flags.
7.4.2.16
CRB ESSI Transmit 0 Enable (TE0) Bit 16
The TE0 bit enables the transfer of data from TX0 to transmit shift register 0. TE0 is
functional when the ESSI is in either synchronous or asynchronous mode.
When TE0 is set and a frame sync is detected, the transmitter 0 is enabled for that frame.
When TE0 is cleared, transmitter 0 is disabled after completing transmission of data
currently in the ESSI transmit shift register. The STD output is tri-stated, and any data
present in TX0 is not transmitted (i.e., data can be written to TX0 with TE0 cleared; the
TDE bit is cleared, but data is not transferred to the transmit shift register 0).
The TE0 bit is cleared by either a hardware RESET signal or a software RESET
instruction.
The transmit enable sequence for on-demand mode can be the same as for normal mode,
or TE0 can be left enabled.
Note:
Transmitter 0 is the only transmitter that can operate in asynchronous mode
(SYN = 0). TE0 does not affect the generation of frame sync or output flags.
Table 7-4 summarizes the preceding sections; it shows possible settings of control bits
and their associated signals.
Table 7-4 Mode and Signal Definition Table
Control Bits
SYN TE0 TE1 TE2
ESSI Signals
RE
SC0
SC1
SC2
SCK
STD
SRD
0
0
0
0
1
0
0
1
1
0
X
X
X
X
0
X
X
X
X
0
0
1
0
1
0
U
RXC
U
U
FSR
U
U
U
U
U
U
U
U
RD
U
FST
FST
U
TXC
TXC
U
TD0
TD0
U
RXC
U
FSR
U
RD
U
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Table 7-4 Mode and Signal Definition Table (Continued)
Control Bits
SYN TE0 TE1 TE2
ESSI Signals
RE
SC0
SC1
SC2
SCK
STD
SRD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F0/U F1/T0D/U
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
U
U
RD
U
F0/U
F0/U
TD2
TD2
U
RD
U
TD1 F1/T0D/U
TD1 F1/T0D/U
U
U
RD
U
TD1
TD1
TD2
TD2
U
U
RD
U
F0/U F1/T0D/U
F0/U F1/T0D/U
TD0
TD0
TD0
TD0
TD0
TD0
TD0
TD0
RD
U
F0/U
F0/U
TD2
TD2
RD
U
TD1 F1/T0D/U
TD1 F1/T0D/U
RD
U
TD1
TD1
TD2
TD2
RD
Note: TXC
Note: RXC
Note: XC
Note: FST
Note: FSR
Note: FS
Note: TD0
Note: TD1
Note: TD2
Note: T0D
Note: RD
Note: F0
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
Transmitter Clock
Receiver Clock
Transmitter/Receiver Clock (Synchronous Operation)
Transmitter Frame Sync
Receiver Frame Sync
Transmitter/Receiver Frame Sync (Synchronous Operation)
Transmit Data signal 0
Transmit Data signal 1
Transmit Data signal 2
Transmitter 0 drive enable if SSC1 = 1 & SCD1 = 1
Receive Data
Flag 0
Note: F1
Flag 1 if SSC1 = 0
Unused (can be used as GPIO signal)
Indeterminate
Note:
Note:
U
X
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7.4.2.17
CRB ESSI Receive Enable (RE) Bit 17
When the RE bit is set, the receive portion of the ESSI is enabled. When this bit is cleared,
the receiver is disabled by inhibiting data transfer into RX. If data is being received while
this bit is cleared, the remainder of the word is shifted in and transferred to the ESSI
receive data register.
RE must be set in both the normal and on-demand modes for the ESSI to receive data. In
network mode, clearing RE and setting it again disables the receiver after reception of
the current data word. The receiver remains disabled until the beginning of the next data
frame.
RE is cleared by either a hardware RESET signal or a software RESET instruction.
Note:
The setting of the RE bit does not affect the generation of a frame sync.
7.4.2.18
CRB ESSI Transmit Interrupt Enable (TIE) Bit 18
Setting the TIE bit enables a DSP transmit interrupt, which is generated when both the
TIE and the TDE bits in the ESSI status register are set. When TIE is cleared, the transmit
interrupt is disabled. The use of the transmit interrupt is described in Section 7.5.3.
Writing data to the data registers of the enabled transmitters or to the TSR clears TDE
and also clears the interrupt. Transmit interrupts with exception conditions have higher
priority than normal transmit data interrupts. If the transmitter underrun error (TUE) bit
is set, signaling that an exception has occurred, and the TEIE bit is set, the ESSI requests
an SSI transmit data with exception interrupt from the interrupt controller.
TIE is cleared by either a hardware RESET signal or a software RESET instruction.
7.4.2.19
CRB ESSI Receive Interrupt Enable (RIE) Bit 19
Setting the RIE enables a DSP receive data interrupt, which is generated when both the
RIE and receive data register full (RDF) bit in the SSISR are set. When RIE is cleared, this
interrupt is disabled. The use of the receive interrupt is described in Section 7.5.3.
Reading the receive data register clears RDF and the pending interrupt. Receive
interrupts with exception have higher priority than normal receive data interrupts. If the
receiver overrun error (ROE) bit is set, signaling that an exception has occurred, and the
REIE bit is set, the ESSI requests an SSI receive data with exception interrupt from the
interrupt controller.
RIE is cleared by either a hardware RESET signal or a software RESET instruction.
7.4.2.20
Transmit Last Slot Interrupt Enable (TLIE) Bit 20
Setting the TLIE bit enables an interrupt at the beginning of the last slot of a frame when
the ESSI is in network mode. When TLIE is set, the DSP is interrupted at the start of the
last slot in a frame regardless of the transmit mask register setting. When TLIE is cleared,
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the transmit last slot interrupt is disabled. The use of the transmit last slot interrupt is
described in Section 7.5.3ÑESSI Exceptions.
TLIE is cleared by either a hardware RESET signal or a software RESET instruction. TLIE
is disabled when the ESSI is in on-demand mode (DC = $0).
7.4.2.21
Receive Last Slot Interrupt Enable (RLIE) Bit 21
Setting the RLIE bit enables an interrupt after the last slot of a frame ends when the ESSI
is in network mode. When RLIE is set, the DSP is interrupted after the last slot in a frame
ends regardless of the receive mask register setting. When RLIE is cleared, the receive
last slot interrupt is disabled. The use of the receive last slot interrupt is described in
Section 7.5.3ÑESSI Exceptions.
RLIE is cleared by either a hardware RESET signal or a software RESET instruction.
RLIE is disabled when the ESSI is in on-demand mode (DC = $0).
7.4.2.22
Transmit Exception Interrupt Enable (TEIE) Bit 22
When the TEIE bit is set, the DSP is interrupted when both TDE and TUE in the ESSI
Status Register are set. When TEIE is cleared, this interrupt is disabled. The use of the
transmit interrupt is described in Section 7.5.3ÑESSI Exceptions. Reading the status
register, followed by writing to all the data registers of the enabled transmitters, clears
both TUE and the pending interrupt.
TEIE is cleared by either a hardware RESET signal or a software RESET instruction.
7.4.2.23
Receive Exception Interrupt Enable (REIE) Bit 23
When the REIE bit is set, the DSP is interrupted when both RDF and ROE in the ESSI
status register are set. When REIE is cleared, this interrupt is disabled. The use of the
receive interrupt is described in Section 7.5.3ÑESSI Exceptions. Reading the status
register followed by reading the receive data register clears both ROE and the pending
interrupt.
REIE is cleared by either a hardware RESET signal or a software RESET instruction.
7.4.3
ESSI Status Register (SSISR)
The SSISR (in Figure 7-4 on page 7-9) is a 24-bit, read-only status register used by the
DSP to read the status and serial input flags of the ESSI. The SSISR bits are documented
in the following paragraphs.
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7.4.3.1
SSISR Serial Input Flag 0 (IF0) Bit 0
The IF0 bit is enabled only when SC0 is an input flag and synchronous mode is selected
(i.e., when the SYN bit is set, and the TE1 and SCD0 bits are cleared).
The ESSI latches data present on the SC0 signal during reception of the first received bit
after the frame sync is detected. The IF0 bit is updated with this data when the data in
the receive shift register is transferred into the receive data register.
If it is not enabled, the IF0 bit is cleared.
A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears the IF0 bit.
7.4.3.2
SSISR Serial Input Flag 1 (IF1) Bit 1
The IF1 bit is enabled only when SC1 is an input flag and synchronous mode is selected,
the SYN bit is set, and the TE2 and SCD1 bits are cleared.
The ESSI latches data present on the SC1 signal during reception of the first received bit
after the frame sync is detected. The IF1 bit is updated with this data when the data in
the receive shift register is transferred into the receive data register.
If it is not enabled, the IF1 bit is cleared.
A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears the IF1 bit.
7.4.3.3
SSISR Transmit Frame Sync Flag (TFS) Bit 2
When set, TFS indicates that a transmit frame sync occurred in the current time slot. TFS
is set at the start of the first time slot in the frame and cleared during all other time slots.
If the transmitter is enabled, data written to a transmit data register during the time slot
when TFS is set is transmitted (in network mode) during the second time slot in the
frame. TFS is useful in network mode to identify the start of a frame. TFS is valid only if
at least one transmitter is enabled (TE0, TE1 or TE2 are set).
A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears TFS.
Note:
In normal mode, TFS is always read as 1 when transmitting data because there
is only one time slot per frame, the Ôframe syncÕ time slot.
7.4.3.4
SSISR Receive Frame Sync Flag (RFS) Bit 3
When set, the RFS bit indicates that a receive frame sync occurred during the reception
of a word in the serial receive data register. This means that the data word is from the
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ESSI Programming Model
first time slot in the frame. When the RFS bit is cleared and a word is received, it
indicates (only in Network mode) that the frame sync did not occur during reception of
that word. RFS is valid only if the receiver is enabled (i.e., the RE bit is set).
A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears RFS.
Note:
In normal mode, RFS is always read as 1 when reading data because there is
only one time slot per frame, the frame sync time slot.
7.4.3.5
SSISR Transmitter Underrun Error Flag (TUE) Bit 4
The TUE bit is set when at least one of the enabled serial transmit shift registers is empty
(no new data to be transmitted) and a transmit time slot occurs. When a transmit
underrun error occurs, the previous data (which is still present in the TX registers that
were not written) is retransmitted. In normal mode, there is only one transmit time slot
per frame. In network mode, there can be up to thirty-two transmit time slots per frame.
If the TEIE bit is set, a DSP transmit underrun error interrupt request is issued when the
TUE bit is set.
A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears TUE. TUE can also be cleared by first reading the SSISR with the TUE
bit set, then writing to all the enabled transmit data registers or to the TSR.
7.4.3.6
SSISR Receiver Overrun Error Flag (ROE) Bit 5
The ROE bit is set when the serial receive shift register is filled and ready to transfer to
the receive data register (RX), but RX is already full (i.e., the RDF bit is set). If the REIE
bit is set, a DSP receiver overrun error interrupt request is issued when the ROE bit is set.
A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears ROE. ROE can also be cleared by reading the SSISR with the ROE bit
set and then reading the RX.
7.4.3.7
ESSI Transmit Data Register Empty (TDE) Bit 6
The TDE bit is set when the contents of the transmit data register of every enabled
transmitter are transferred to the transmit shift register. It is also set for a TSR disabled
time slot period in network mode (as if data were being transmitted after the TSR was
written). When set, the TDE bit indicates that data should be written to all the TX
registers of the enabled transmitters or to the TSR. The TDE bit is cleared when the
DSP56309 writes to all the transmit data registers of the enabled transmitters or when the
DSP writes to the TSR to disable transmission of the next time slot. If the TIE bit is set, a
DSP transmit data interrupt request is issued when TDE is set. A hardware RESET
signal, software RESET instruction, ESSI individual reset, or STOP instruction clears the
TDE bit.
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ESSI Programming Model
7.4.3.8
ESSI Receive Data Register Full (RDF) Bit 7
The RDF bit is set when the contents of the receive shift register are transferred to the
receive data register. The RDF bit is cleared when the DSP reads the receive data
register. If RIE is set, a DSP receive data interrupt request is issued when RDF is set. A
hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears the RDF bit.
The ESSI data path programming models are shown in Figure 7-16 on page 7-31 and
Figure 7-17 on page 7-32.
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ESSI Programming Model
23
8 7
0
16 15
ESSI Receive Data Register
(Read Only)
Receive High Byte
Receive High Byte
Receive Middle Byte
Receive Middle Byte
Receive Low Byte
Receive Low Byte
7
0
7
0 7
8 7
0
0
23
16
15
Serial
Receive
Shift
Register
7
0
7
0
7
0
24 Bit
16 Bit
SRD
12 Bit
8 Bit
WL1, WL0
MSB
LSB
Least Significant
Zero Fill
8-bit Data
0
0
0
MSB
LSB
12-bit Data
16-bit Data
LSB
MSB
MSB
LSB
24-bit Data
NOTES:
(a) Receive Registers
Data is received MSB first if SHFD = 0.
24-bit fractional format (ALC = 0).
32-bit mode is not shown.
23
16 15
8 7
0
ESSI Transmit Data
Register
(Write Only)
Transmit High Byte
Transmit Middle Byte
Transmit Middle Byte
Transmit Low Byte
7
0
7
0 7
0 7
0
0
23
16 15
ESSI Transmit
Shift Register
Transmit High Byte
7
Transmit Low Byte
STD
0
7
0
7
0
LSB
MSB
Least Significant
Zero Fill
8-bit Data
0
0
0
LSB
MSB
MSB
MSB
12-bit Data
16-bit Data
LSB
LSB
24-bit Data
NOTES:
(b) Transmit Registers
Data is transmitted MSB first if
SHFD = 0.
4-bit fractional format (ALC = 0).
32-bit mode is not shown.
AA0686
Figure 7-16 ESSI Data Path Programming Model (SHFD = 0)
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ESSI Programming Model
23
8 7
0
16 15
ESSI Receive Data Register
(Read Only)
Receive High Byte
Receive Middle Byte
Receive Middle Byte
Receive Low Byte
7
0
7
0 7
0 7
0
0
23
16 15
ESSI Receive
Shift Register
Receive High Byte
Receive Low Byte
SRD
7
0
7
0 7
0
MSB
MSB
LSB
Least Significant
Zero Fill
8-bit Data
0
0
0
LSB
12-bit Data
16-bit Data
LSB
MSB
MSB
LSB
NOTES:
24-bit Data
(a) Receive Registers
Data is received MSB first if SHFD = 0.
24-bit fractional format (ALC = 0).
32-bit mode is not shown.
23
16 15
8 7
0
ESSI Transmit Data
Register
(Write Only)
Transmit High Byte
Transmit Middle Byte
Transmit Middle Byte
Transmit Low Byte
7
0
7
0 7
0 7
0
0
23
16 15
ESSI Transmit Shift
Register
Transmit High Byte
Transmit Low Byte
7
0
7
0 7
0
24 Bit
16 Bit
12 Bit
8 Bit
STD
MSB
MSB
MSB
MSB
LSB
8-bit Data
12-bit Data
16-bit Data
0
0
0
WL1, WL0
Least Significant
Zero Fill
LSB
LSB
LSB
NOTES:
24-bit Data
(b) Transmit Registers
Data is received MSB first if SHFD = 0.
4-bit fractional format (ALC = 0).
32-bit mode is not shown.
AA0687
Figure 7-17 ESSI Data Path Programming Model (SHFD = 1)
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ESSI Programming Model
7.4.4
ESSI Receive Shift Register
The 24-bit receive shift register (in Figure 7-16 on page 7-31 and Figure 7-17 on
page 7-32) receives the incoming data from the serial receive data signal. Data is shifted
in by the selected (internal/external) bit clock when the associated frame sync I/O is
asserted. It is assumed that data is received MSB first if SHFD is cleared and LSB first if
SHFD is set. Data is transferred to the ESSI receive data register after 8, 12, 16, 24, or 32
serial clock cycles are counted, depending on the word-length control bits in the CRA.
7.4.5
ESSI Receive Data Register (RX)
The receive data register (RX) is a 24-bit, read-only register that accepts data from the
receive shift register as it becomes full; see Figure 7-16 on page 7-31 and Figure 7-17 on
page 7-32. The data read is aligned according to the value of the ALC bit. When the ALC
bit is cleared, the MSB is bit 23 and the least significant byte is unused. When the ALC bit
is set, the MSB is bit 15 and the most significant byte is unused. Unused bits are read as
0s. If the associated interrupt is enabled, the DSP is interrupted whenever the RX register
becomes full.
7.4.6
ESSI Transmit Shift Registers
The three 24-bit transmit shift registers contain the data being transmitted; see
Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32. Data is shifted out to the serial
transmit data signals by the selected (internal/external) bit clock when the associated
frame sync I/O is asserted. The word-length control bits in the CRA determine the
number of bits that must be shifted out before the shift registers are considered empty
and can be written to again. Depending on the setting of the CRA, the number of bits to
be shifted out can be 8, 12, 16, 24, or 32 bits.
The data transmitted is aligned according to the value of the ALC bit. When the ALC bit
is cleared, the MSB is bit 23 and the least significant byte is unused. When ALC is set, the
MSB is bit 15 and the most significant byte is unused. Unused bits are read as 0s. Data is
shifted out of these registers MSB first if the SHFD bit is cleared and LSB first if the
SHFD bit is set.
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ESSI Programming Model
7.4.7
ESSI Transmit Data Registers (TX0-2)
TX20, TX10, and TX00 are transmit data registers for ESSI0. TX21, TX11, and TX01 are
transmit data registers for ESSI1. TX20 and TX21 are known as TX2. TX10 and TX11 are
known as TX1. TX00 and TX01 are known as TX0.
TX2, TX1, and TX0 are 24-bit, write-only registers. Data to be transmitted is written into
these registers and automatically transferred to the transmit shift registers; see
Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32. The data transmitted (8, 12, 16, or
24 bits) is aligned according to the value of the ALC bit. When the ALC bit is cleared, the
MSB is Bit 23. When ALC is set, the MSB is Bit 15. If the transmit data register empty
interrupt has been enabled, the DSP is interrupted whenever a transmit data register
becomes empty.
Note:
When data is written to a peripheral device, there is a two cycle pipeline delay
until any status bits affected by this operation are updated. If you read any of
those status bits within the next two cycles, the bit does not reflect its current
status. See the DSP56300 Family Manual, Appendix B, Polling a Peripheral
Device for Write for further details.
7.4.8
ESSI Time Slot Register (TSR)
TSR is effectively a write-only null data register that is used to prevent data transmission
in the current transmit time slot. For the purposes of timing, TSR is a write-only register
that behaves like an alternative transmit data register, except that, rather than
transmitting data, the transmit data signals of all the enabled transmitters are in the
high-impedance state for the current time slot.
7.4.9
Transmit Slot Mask Registers (TSMA, TSMB)
The transmit slot mask Registers are two 16-bit, read/write registers. When the TSMA or
TSMB is read to the internal data bus, the register contents occupy the two low-order
bytes of the data bus, and the high-order byte is zero-filled. In network mode, these
registers are used by the transmitter(s) to determine what action to take in the current
transmission slot. Depending on the setting of the bits, the transmitter(s) either tri-state
the transmitter(s) data signal(s) or transmit a data word and generate a transmitter
empty condition.
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TSMA and TSMB (in Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32) can be seen
as a single 32-bit register, TSM. Bit n in TSM (TSn) is an enable/disable control bit for
transmission in slot number N. When TSn is cleared, all the transmit data signals of the
enabled transmitters are tri-stated during transmit time slot number N. The data is still
transferred from the enabled transmit data register(s) to the transmit shift register.
However, the TDE and the TUE flags are not set. This means that during a disabled slot,
no transmitter empty interrupt is generated. The DSP is interrupted only for enabled
slots. Data written to the transmit data register when servicing the transmitter empty
interrupt request is transmitted in the next enabled transmit time slot.
When TSn is set, the transmit sequence proceeds normally. Data is transferred from the
TX register to the shift register during slot number N and the TDE flag is set.
Using the TSM slot mask does not conflict with using the TSR. Even if a slot is enabled in
the TSM, you can write to the TSR to tri-state the signals of the enabled transmitters
during the next transmission slot. Setting the bits in the TSM affects the next frame
transmission. The frame currently being transmitted is not affected by the new TSM
setting. If the TSM is read, it shows the current setting.
After a hardware RESET signal or software RESET instruction, the TSM register is reset
to $FFFFFFFF; this setting enables all thirty-two slots for data transmission.
7.4.10
Receive Slot Mask Registers (RSMA, RSMB)
The receive slot mask registers are two 16-bit, read/write registers. In network mode,
these registers are used by the receiver(s) to determine what action to take in the current
time slot. Depending on the setting of the bits, the receiver(s) either tri-state the
receiver(s) data signal(s) or receive a data word and generate a receiver full condition.
RSMA and RSMB (in Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32) can be seen
as one 32-bit register, RSM. Bit n in RSM (RSn) is an enable/disable control bit for time
slot number N. When RSn is cleared, all the data signals of the enabled receivers are
tri-stated during time slot number N. Data is transferred from the receive data register(s)
to the receive shift register(s) and the RDF and ROE flags are not set. During a disabled
slot, no receiver full interrupt is generated. The DSP is interrupted only for enabled slots.
When RSn is set, the receive sequence proceeds normally. Data is received during slot
number N, and the RDF flag is set.
Setting the bits in the RSM affects the next frame transmission. The frame currently
being transmitted is not affected by the new RSM setting. If the RSM is read, it shows the
current setting.
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Operating Modes
When the RSMA or RSMB register are read by the internal data bus, the register contents
occupy the two low-order bytes of the data bus, and the high-order byte is zero-filled.
After a hardware RESET signal or a software RESET instruction, the RSM register is reset
to $FFFFFFFF; this setting enables all thirty-two time slots for data transmission.
7.5
OPERATING MODES
The ESSI operating modes are selected by the ESSI control registers (CRA and CRB). The
operating modes are described in the following paragraphs.
7.5.1
ESSI After Reset
A hardware RESET signal or software RESET instruction clears the port control register
and the port direction control register. This situation configures all the ESSI signals as
GPIO. The ESSI is in the reset state while all ESSI signals are programmed as GPIO; the
ESSI is active only if at least one of the ESSI I/O signals is programmed as an ESSI signal.
7.5.2
ESSI Initialization
To initialize the ESSI, do the following:
1. Send a reset: a hardware RESET signal, software RESET instruction, ESSI
individual reset, or STOP instruction.
2. Program the ESSI control and time slot registers.
3. Write data to all the enabled transmitters.
4. Configure at least one signal as an ESSI signal.
5. If an external frame sync is used, from the moment the ESSI is activated, at least
five serial clocks are needed before the first external frame sync is supplied.
Otherwise, improper operation can result.
Clearing the PC[5:0] bits in the GPIO PCR during program execution causes the ESSI to
stop serial activity and enter the individual reset state. All status bits of the interface are
set to their reset state. The contents of CRA and CRB are not affected. The ESSI
individual reset allows a program to reset each interface separately from the other
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Operating Modes
internal peripherals. During ESSI individual reset, internal DMA accesses to the data
registers of the ESSI are not valid and data read is undefined.
To insure proper operation of the ESSI, use an ESSI individual reset when changing the
ESSI control registers (except for bits TEIE, REIE, TLIE, RLIE, TIE, RIE, TE2, TE1, TE0,
and RE).
Here is an example of initializing the ESSI.
1. Put the ESSI in its individual reset state by clearing the PCR bits.
2. Configure the control registers (CRA, CRB) to set the operating mode. Disable the
transmitters and receiver by clearing the TE[2:0] and RE bits. Set the interrupt
enable bits for the operating mode chosen.
3. Enable the ESSI by setting the PCR bits to activate the input/output signals to be
used.
4. Write initial data to the transmitters that are used during operation. This step is
needed even if DMA is used to service the transmitters.
5. Enable the transmitters and receiver to be used.
Now the ESSI can be serviced by polling, interrupts, or DMA.
Once the ESSI has been enabled (Step 3), operation starts as follows:
¥ For internally generated clock and frame sync, these signals start activity
immediately after the ESSI is enabled.
¥ Data is received by the ESSI after the occurrence of a frame sync signal (either
internally or externally generated) only when the receive enable (RE) bit is set.
¥ Data is transmitted after the occurrence of a frame sync signal (either internally or
externally generated) only when the transmitter enable (TE[2:0]) bit is set.
7.5.3
ESSI Exceptions
The ESSI can generate six different exceptions. They are discussed in the following
paragraphs (ordered from the highest to the lowest exception priority):
1. ESSI receive data with exception status:
Occurs when the receive exception interrupt is enabled, the receive data register
is full, and a receiver overrun error has occurred. This exception sets the ROE bit.
The ROE bit is cleared by first reading the SSISR and then reading RX.
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Operating Modes
2. ESSI receive data:
Occurs when the receive interrupt is enabled, the receive data register is full, and
no receive error conditions exist. Reading RX clears the pending interrupt. This
error-free interrupt can use a fast interrupt service routine for minimum
overhead.
3. ESSI receive last slot interrupt:
Occurs when the ESSI is in network mode and the last slot of the frame has ended.
This interrupt is generated regardless of the receive mask register setting. The
receive last slot interrupt can be used to signal that the receive mask slot register
can be reset, the DMA channels can be reconfigured, and data memory pointers
can be reassigned. Using the receive last slot interrupt guarantees that the
previous frame was serviced with the previous setting and the new frame is
serviced with the new setting without synchronization problems.
Note:
The maximum time it takes to service a receive last slot interrupt should not
exceed N Ð 1 ESSI bits service time (where N is the number of bits the ESSI can
transmit per time slot).
4. ESSI transmit data with exception status:
Occurs when the transmit exception interrupt is enabled, at least one transmit
data register of the enabled transmitters is empty, and a transmitter underrun
error has occurred. This exception sets the TUE bit. The TUE bit is cleared by first
reading the SSISR and then writing to all the transmit data registers of the enabled
transmitters or by writing to the TSR to clear the pending interrupt.
5. ESSI transmit last slot interrupt:
Occurs when the ESSI is in network mode at the start of the last slot of the frame.
This exception occurs regardless of the transmit mask register setting. The
transmit last slot interrupt can be used to signal that the transmit mask slot
register can be reset, the DMA channels can be reconfigured, and data memory
pointers can be reassigned. Using the transmit last slot interrupt guarantees that
the previous frame was serviced with the previous setting, and the new frame is
serviced with the new setting without synchronization problems.
Note:
The maximum transmit last slot interrupt service time should not exceed
N Ð 1 ESSI bits service time (where N is the number of bits in a slot).
6. ESSI transmit data:
Occurs when the transmit interrupt is enabled, at least one of the enabled transmit
data registers is empty, and no transmitter error conditions exist. Writing to all
the enabled TX registers or to the TSR clears this interrupt. This error-free
interrupt can use a fast interrupt service routine for minimum overhead (if no
more than two transmitters are used).
To configure an ESSI exception, perform the following steps:
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Operating Modes
1. Configure interrupt service routine (ISR)
a. Load vector base address register.
VBA (b23:8)
b. Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined,
I_VEC must be defined for the assembler before the interrupt equate file is
included.
c. Load the exception vector table entry: two-word fast interrupt or
jump/branch to subroutine (long interrupt).
p:I_SI0TD
2. Configure interrupt trigger/preload transmit data
a. Enable and prioritize overall peripheral interrupt functionality.
IPRP (S0L1:0)
b. Enable peripheral and associated signals.
c. Write data to all enabled transmit registers.
PCRC (PC5:0)
TX00
d. Enable peripheral interrupt-generating function. CRB (TE0)
e. Enable specific peripheral interrupt.
f. Unmask interrupts at global level.
CRB0 (TIE)
SR (I1:0)
Notes:
1. The example material to the right of the steps above shows register settings
for configuring an ESSI0 transmit interrupt using transmitter 0.
2. The order of the steps is optional except that the interrupt trigger
configuration must not be completed until the ISR configuration has been
completed. Since 2d can cause an immediate transmit without generating
an interrupt, perform the transmit data preload in 2c before 2d to insure
valid data is sent in the first transmission.
3. After the first transmit, subsequent transmit values are typically loaded
into TXnn by the ISR (one value per register per interrupt). Therefore, if N
items are to be sent from a particular TXnn, the ISR will need to load the
transmit register (N Ð 1) times.
4. Steps d and e can be performed using a single instruction.
5. If an interrupt trigger event occurs at a time when not all interrupt trigger
configuration steps have been performed, the event is ignored forever (the
event is not queued in this case).
6. If interrupts derived from the core or other peripherals need to be enabled
at the same time as ESSI interrupts, step f should be done last.
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Operating Modes
7.5.4
Operating Modes: Normal, Network, and On-Demand
The ESSI has three basic operating modes and several data/operation formats. These
modes can be programmed using the ESSI control registers. The data/operation formats
available to the ESSI are selected by setting or clearing control bits in the CRA and CRB.
These control bits are WL[2:1], MOD, SYN, FSL[1:0], FSR, FSP, CKP, and SHFD.
7.5.4.1
Normal/Network/On-Demand Mode Selection
To select normal mode (or network mode), clear (or set) the MOD bit in the CRB. In
normal mode, the ESSI sends or receives one data word per frame (per enabled receiver
or transmitter). In network mode, two to thirty-two time slots per frame can be selected.
During each frame, zero to thirty-two data words can be received or transmitted (from
each enabled receiver or transmitter). In either case, the transfers are periodic.
Normal mode is typically used to transfer data to or from a single device. Network mode
is typically used in TDM networks of codecs or DSPs with multiple words per frame.
Network mode has a sub-mode called on-demand mode. Setting the MOD bit in the CRB
for network mode, and setting the frame rate divider to 0 (DC = $00000) selects the
on-demand mode. This sub-mode does not generate a periodic frame sync. A frame sync
pulse is generated only when data is available to transmit. The frame sync signal
indicates the first time slot in the frame. The on-demand mode requires that the transmit
frame sync be internal (output) and the receive frame sync be external (input). For
simplex operation, synchronous mode could be used; however, for full-duplex
operation, asynchronous mode must be used. Data transmission that is data driven is
enabled by writing data into each TX. Although the ESSI is double-buffered, only one
word can be written to each TX, even if the transmit shift register is empty. The receive
and transmit interrupts function normally, using TDE and RDF; however, transmit
underruns are impossible for Ôon- demandÕ transmission and are disabled. This mode is
useful for interfacing to codecs requiring a continuous clock.
7.5.4.2
Synchronous/Asynchronous Operating Modes
The transmit and receive sections of the ESSI interface can be synchronous or
asynchronous. The transmitter and receiver use common clock and synchronization
signals in synchronous mode; they use separate clock and sync signals in asynchronous
mode. The SYN bit in CRB selects synchronous or asynchronous operation. When the
SYN bit is cleared, the ESSI TX and RX clocks and frame sync sources are independent. If
the SYN bit is set, the ESSI TX and RX clocks and frame sync are driven by the same
source (either external or internal). Since the ESSI is designed to operate either
synchronously or asynchronously, separate receive and transmit interrupts are
provided.
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Operating Modes
Transmitter 1 and transmitter 2 operate only in synchronous mode. Data clock and
frame sync signals can be generated internally by the DSP or can be obtained from
external sources. If clocks are internally generated, the ESSI clock generator derives bit
clock and frame sync signals from the DSP internal system clock. The ESSI clock
generator consists of a selectable fixed prescaler with a programmable prescaler for bit
rate clock generation and a programmable frame-rate divider with a word-length
divider for frame-rate sync-signal generation.
7.5.4.3
Frame Sync Selection
The transmitter and receiver can operate independently. The transmitter can have either
a bit-long or word-long frame-sync signal format, and the receiver can have the same or
another format. The selection is made by programming FSL[1:0], FSR, and FSP bits in the
CRB.
7.5.4.3.1
Frame Sync Signal Format
FSL1 controls the frame-sync signal format.
¥ If the FSL1 bit is cleared, the RX frame sync is asserted during the entire data
transfer period. This frame sync length is compatible with Motorola codecs, serial
peripherals that conform to the Motorola SPI, serial A/D and D/A converters,
shift registers, and telecommunication pulse code modulation (PCM) serial I/O.
¥ If the FSL1 bit is set, the RX frame sync pulses active for one bit clock immediately
before the data transfer period. This frame sync length is compatible with Intel
and National components, codecs, and telecommunication PCM serial I/O.
7.5.4.3.2
Frame Sync Length for Multiple Devices
The ability to mix frame sync lengths is useful in configuring systems in which data is
received from one type of device (e.g., codec) and transmitted to a different type of
device. FSL0 controls whether RX and TX have the same frame sync length.
¥ If the FSL0 bit is cleared, both RX and TX have the same frame sync length.
¥ If the FSL0 bit is set, RX and TX have different frame sync lengths.
FSL0 is ignored when the SYN bit is set.
7.5.4.3.3
Word-Length Frame Sync and Data-Word Timing
The FSR bit controls the relative timing of the word-length frame sync relative to the
data word timing.
¥ When the FSR bit is cleared, the word length frame sync is generated (or
expected) with the first bit of the data word.
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Operating Modes
¥ When the FSR bit is set, the word length frame sync is generated (or expected)
with the last bit of the previous word.
FSR is ignored when a bit length frame sync is selected.
7.5.4.3.4
Frame Sync Polarity
The FSP bit controls the polarity of the frame sync.
¥ When the FSP bit is cleared, the polarity of the frame sync is positive (i.e., the
frame sync signal is asserted high). The ESSI synchronizes on the leading edge of
the frame sync signal.
¥ When the FSP bit is set, the polarity of the frame sync is negative (i.e., the frame
sync is asserted low). The ESSI synchronizes on the trailing edge of the frame sync
signal.
The ESSI receiver looks for a receive frame sync edge (leading edge if FSP is cleared,
trailing edge if FSP is set) only when the previous frame is completed. If the frame sync
is asserted before the frame is completed (or before the last bit of the frame is received in
the case of a bit frame sync or a word length frame sync with FSR set), the current frame
sync is not recognized, and the receiver is internally disabled until the next frame sync.
Frames do not have to be adjacent, that is, a new frame sync does not have to follow
immediately the previous frame. Gaps of arbitrary periods can occur between frames.
All the enabled transmitters are tri-stated during these gaps.
7.5.4.4
Byte Format (LSB/MSB) for the Transmitter
Some devices, such as codecs, require a MSB-first data format. Other devices, such as
those that use the AES-EBU digital audio format, require the LSB first. To be compatible
with all formats, the shift registers in the ESSI are bidirectional. The MSB/LSB selection
is made by programming the SHFD bit in the CRB.
¥ If the SHFD bit is cleared, data is shifted into the receive shift register MSB first
and shifted out of the transmit shift register MSB first.
¥ If the SHFD bit is set, data is shifted into the receive shift register LSB first and
shifted out of the transmit shift register LSB first.
7.5.5
Flags
Two ESSI signals (SC[1:0]) are available for use as serial I/O flags. Their operation is
controlled by the SYN, SCD[1:0], SSC1, and TE[2:1] bits in the CRB/CRA.The control bits
OF[1:0] and status bits IF[1:0] are double-buffered to/from SC[1:0]. Double-buffering the
flags keeps the flags in sync with TX and RX.
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Enhanced Synchronous Serial Interface (ESSI)
GPIO Signals and Registers
The SC[1:0] flags are available in synchronous mode only. Each flag can be separately
programmed.
Flag SC0 is enabled when transmitter 1 is disabled (TE1 = 0). The flagÕs direction is
selected by the SCD0 bit. When SCD0 is set, SC0 is configured as output. When SCD0 is
cleared, SC0 is configured as input.
Similarly, the SC1 flag is enabled when transmitter 2 is disabled (TE2 = 0) and the SC1
signal is not configured as transmitter drive enable (Bit SSC1 = 0). SC1Õs direction is
selected by the SCD1 bit. When SCD1 is set, SC1 is an output flag. When SCD1 is cleared,
SC1 is an input flag.
When programmed as input flags, the value of the SC[1:0] bits are latched at the same
time as the first bit of the receive data word is sampled. Once the input has been latched,
the signal on the input flag signal (SC0 and SC1) can change without affecting the input
flag. The value of SC[1:0] does not change until the first bit of the next data word is
received. When the received data word is latched by RX, the latched values of SC[1:0] are
latched by the respective SSISR IF[1:0] bits and can be read by software.
When programed as output flags, the value of the SC[1:0] bits is taken from the value of
the OF[1:0] bits. The value of the OF[1:0] bits is latched when the contents of TX are
transferred to the transmit shift register. The value on SC[1:0] is stable from the time the
first bit of the transmit data word is transmitted until the first bit of the next transmit
data word is transmitted. The OF[1:0] values can be set directly by software. This allows
the DSP56309 to control data transmission by indirectly controlling the value of the
SC[1:0] flags.
7.6
GPIO SIGNALS AND REGISTERS
The GPIO functionality of an ESSI port (C, D) is controlled by three registers: port
control register (PCRC, PCRD), port direction register (PRRC, PRRD) and port data
register (PDRC, PDRD).
7.6.1
Port Control Register (PCR)
The read/write, 24-bit PCR controls the functionality of the ESSI GPIO signals. Each of
PC[5:0] bits controls the functionality of the corresponding port signal. When a PC[i] bit
is set, the corresponding port signal is configured as a ESSI signal. When a PC[i] bit is
cleared, the corresponding port signal is configured as a GPIO signal. Either a hardware
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Enhanced Synchronous Serial Interface (ESSI)
GPIO Signals and Registers
RESET signal or a software RESET instruction clears all PCR bits. Figure 7-18 shows the
PCR bits.
7
6
5
4
3
2
1
0
PC5
PC4
PC3
PC2
PC1
PC0
0 = GPIO, 1 = ESSI
STDn
13
SRDn SCKn SCKn2 SCKn1 SCKn0
PCRC: ESSI0, PCRD: ESSI1
12
11
10
9
8
15
23
14
22
21
20
19
18
17
16
Reserved Bit, Read As Zero, Should Be Written With Zero For Future Compatibility
AA0688
Figure 7-18 Port Control Register (PCR) (PCRC X:$FFFFBF)
(PCRD X:$FFFFAF)
7.6.2
Port Direction Register (PRR)
The read/write, 24-bit PRR controls the data direction of the ESSI GPIO signals. When
PRR[i] is set, the corresponding signal is an output signal. When PRR[i] is cleared, the
corresponding signal is an input signal. Figure 7-19 shows the PRR bits.
7
6
5
4
3
2
1
0
0 = Input, 1 = Output
PDC5 PDC4 PDC3 PDC2 PDC1 PDC0
STDn
13
SRDn SCKn SCKn2 SCKn1 SCKn0
PRRC: ESSI0, PRRD: ESSI1
12
20
11
19
10
18
9
8
15
23
14
22
21
17
16
Reserved Bit, Read As Zero, Should Be Written With Zero For Future Compatibility
AA0689
Figure 7-19 Port Direction Register (PRR)(PRRC X:$FFFFBE)
(PRRD X:$FFFFAE)
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Enhanced Synchronous Serial Interface (ESSI)
GPIO Signals and Registers
Note:
Either a hardware RESET signal or a software RESET instruction clears all
PRR bits.
Table 7-5 shows the port signal configurations.
Table 7-5 Port Control Register and Port Direction Register Bits
PC[i]
PDC[i]
Port Signal[i] Function
1
0
0
X
0
ESSI
GPIO input
GPIO output
1
Note: X: The signal setting is irrelevant to port
signal [i] function.
7.6.3
Port Data Register (PDR)
The read/write, 24-bit PDR is used to read or write data to and from the ESSI GPIO
signals. The PD[5:0] bits are used to read or write data from and to the corresponding
port signals if they are configured as GPIO signals. If a port signal [i] is configured as a
GPIO input, then the corresponding PD[i] bit reflects the value present on this signal. If a
port signal [i] is configured as a GPIO output, then the value written into the
corresponding PD[i] bit is reflected on the this signal. Figure 7-20 shows the PDR bits.
7
6
5
4
3
2
1
0
PD5
STDn
PD4
PD3
PD2
PD1
PD0
SRDn SCKn SCKn2 SCKn1 SCKn0
PDRD: ESSI0, PDRD: ESSI1
13
21
12
20
11
19
10
18
9
8
15
23
14
22
17
16
Reserved Bit, Read As Zero, Should Be Written With Zero For Future Compatibility
AA0690
Figure 7-20 Port Data Register (PDR) (PDRC X:$FFFFBD)
(PDRD X:$FFFFAD)
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GPIO Signals and Registers
Note:
Either a hardware RESET signal or a software RESET instruction clears all
PDR bits.
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SECTION 8
SERIAL COMMUNICATION INTERFACE
(SCI)
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Serial Communication Interface (SCI)
8.1
8.2
8.3
8.4
8.5
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
SCI I/O SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
SCI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . 8-4
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
GPIO SIGNALS AND REGISTERS. . . . . . . . . . . . . . . . . . . 8-27
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Serial Communication Interface (SCI)
Introduction
8.1
INTRODUCTION
The DSP56309 serial communication interface (SCI) provides a full-duplex port for serial
communication to other DSPs, microprocessors, or peripherals such as modems. The SCI
interfaces without additional logic to peripherals that use TTL-level signals. With a small
amount of additional logic, the SCI can connect to peripheral interfaces that have
non-TTL level signals, such as the RS232C, RS422, etc.
This interface uses three dedicated signals: transmit data (TXD), receive data (RXD), and
SCI serial clock (SCLK). It supports industry-standard asynchronous bit rates and
protocols, as well as high-speed synchronous data transmission. The asynchronous
protocols supported by the SCI include a multidrop mode for master/slave operation
with wakeup on idle line and wakeup on address bit capability. This mode allows the
DSP56309 to share a single serial line efficiently with other peripherals.
The SCI consists of separate transmit and receive sections that can operate
asynchronously with respect to each other. A programmable baud-rate generator
provides the transmit and receive clocks. An enable vector and an interrupt vector have
been included so that the baud-rate generator can function as a general purpose timer
when it is not being used by the SCI, or when the interrupt timing is the same as that
used by the SCI.
8.2
SCI I/O SIGNALS
Each of the three SCI signals (RXD, TXD, and SCLK) can be configured as either a GPIO
signal or as a specific SCI signal. Each signal is independent of the others. For example, if
only the TXD signal is needed, the RXD and SCLK signals can be programmed for GPIO.
However, at least one of the three signals must be selected as an SCI signal to release the
SCI from reset.
SCI interrupts can be enabled by programming the SCI control registers before any of
the SCI signals are programmed as SCI functions. In this case, only one transmit
interrupt can be generated because the transmit data register is empty. The timer and
timer interrupt operate regardless of how the SCI pins are configuredÑeither as SCI or
GPIO.
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Serial Communication Interface (SCI)
SCI Programming Model
8.2.1
Receive Data (RXD)
This input signal receives byte-oriented serial data and transfers the data to the SCI
receive shift register. Asynchronous input data is sampled on the positive edge of the
receive clock (1 ´ SCLK) if SCKP is cleared. RXD can be configured as a GPIO signal
(PE0) when the SCI RXD function is not being used.
8.2.2
Transmit Data (TXD)
This output signal transmits serial data from the SCI transmit shift register. Data
changes on the negative edge of the asynchronous transmit clock (SCLK) if SCKP is
cleared. This output is stable on the positive edge of the transmit clock. TXD can be
programmed as a GPIO signal (PE1) when the SCI TXD function is not being used.
8.2.3
SCI Serial Clock (SCLK)
This bidirectional signal provides an input or output clock from which the transmit
and/or receive baud rate is derived in asynchronous mode and from which data is
transferred in synchronous mode. SCLK can be programmed as a GPIO signal (PE2)
when the SCI SCLK function is not being used. This signal can be programmed as PE2
when data is being transmitted on TXD, since the clock does not need to be transmitted
in asynchronous mode. Because SCLK is independent of SCI data I/O, there is no
connection between programming the PE2 signal as SCLK and data coming out the TXD
signal.
8.3
SCI PROGRAMMING MODEL
The SCI programming model can be viewed as three types of registers:
¥ Control
Ð SCI control register (SCR) in Figure 8-1
Ð SCI clock control register (SCCR) in Figure 8-3
¥ Status
Ð SCI status register (SSR) in Figure 8-2
¥ Data transfer
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Serial Communication Interface (SCI)
SCI Programming Model
Ð SCI Receive Data Registers (SRX) in Figure 8-7 on page 8-19
Ð SCI Transmit Data Registers (STX) in Figure 8-7
Ð SCI Transmit Data Address Register (STXA) in Figure 8-7
The SCI also supports the GPIO functions documented in Section 8ÑGPIO Signals and
Registers on page 8-27. The following paragraphs describe each bit in the programming
model. Beginning on page 8-6, Figure 8-4 shows the formats of data words.
7
6
5
4
3
2
1
0
WOMS
RWU
WAKE
SBK
SSFTD
WDS2
WDS1
WDS0
15
14
13
12
11
10
9
8
SCKP
STIR
TMIE
TIE
RIE
ILIE
TE
RE
23
22
21
20
19
18
17
16
REIE
AA0854
Figure 8-1 SCI Control Register (SCR)
7
6
5
4
3
2
1
0
R8
FE
PE
OR
IDLE
RDRF
TDRE
TRNE
15
23
14
22
13
21
12
20
11
19
10
18
9
8
17
16
AA0855
Figure 8-2 SCI Status Register (SSR)
7
6
5
4
3
2
1
0
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
15
14
13
12
11
10
9
8
TCM
RCM
SCP
COD
CD11
CD10
CD9
CD8
23
22
21
20
19
18
17
16
Reserved bit - read as 0 should be written with 0 for future compatibility
AA0856
Figure 8-3 SCI Clock Control Register (SCCR)
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Serial Communication Interface (SCI)
SCI Programming Model
SSFTD = 0
Mode 0
0
0
0
8-bit Synchronous Data (Shift Register Mode)
WDS2 WDS1 WDS0
TX
D0
D1
D2
D3
D4
D5
D6
D7
(SSFTD = 0)
One Byte From Shift Register
Mode 2
0
1
0
10-bit Asynchronous (1 Start, 8 Data, 1 Stop)
WDS2 WDS1 WDS0
D7 or
Data
Type
TX
Start
Bit
Stop
Bit
D0
D1
D2
D3
D4
D5
D6
(SSFTD = 0)
Mode 4
1
0
0
11-bit Asynchronous (1 Start, 8 Data, 1 Even Parity, 1 Stop)
WDS2 WDS1 WDS0
D7 or
Data
Type
TX
Start
Bit
Even
Parity
Stop
Bit
D0
D1
D2
D3
D4
D5
D6
(SSFTD = 0)
Mode 5
1
0
1
11-bit Asynchronous (1 Start, 8 Data, 1 Odd Parity, 1 Stop)
WDS2 WDS1 WDS0
D7 or
Data
Type
TX
Start
Bit
Odd
Parity
Stop
Bit
D0
D1
D2
D3
D4
D5
D6
(SSFTD = 0)
Mode 6
1
1
0
11-bit Asynchronous Multidrop (1 Start, 8 Data, 1 Data Type, 1 Stop)
WDS2 WDS1 WDS0
TX
Start
Bit
Stop
Bit
Data
Type
D0
D1
D2
D3
D4
D5
D6
D7
(SSFTD = 0)
Data Type: 1 = Address Byte
0 = Data Byte
Note: 1. Modes 1, 3, and 7 are reserved.
2. D0 = LSB; D7 = MSB
3. Data is transmitted and received LSB first if SSFTD = 0, or MSB first if SSFTD = 1
AA0691
Figure 8-4 SCI Data Word Formats
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SCI Programming Model
SSFTD = 1
Mode 0
0
0
0
8-bit Synchronous Data (Shift Register Mode)
WDS2 WDS1 WDS0
TX
D7
D6
D5
D4
D3
D2
D1
D0
(SSFTD = 1)
One Byte From Shift Register
Mode 2
0
1
0
10-bit Asynchronous (1 Start, 8 Data, 1 Stop)
WDS2 WDS1 WDS0
D0 or
TX
Start
Bit
Stop
Data
D7
D6
D5
D4
D3
D2
D1
(SSFTD = 1)
Bit
Type
Mode 4
1
0
0
11-bit Asynchronous (1 Start, 8 Data, 1 Even Parity, 1 Stop)
WDS2 WDS1 WDS0
D0 or
Data
Type
TX
Start
Bit
Even
Parity
Stop
Bit
D7
D6
D5
D4
D3
D2
D1
(SSFTD = 1)
Mode 5
11-bit Asynchronous (1 Start, 8 Data, 1 Odd Parity, 1 Stop)
1
0
1
WDS2 WDS1 WDS0
D0 or
Data
Type
TX
Start
Bit
Odd
Parity
Stop
Bit
D7
D6
D5
D4
D3
D2
D1
(SSFTD = 1)
Mode 6
11-bit Asynchronous Multidrop (1 Start, 8 Data, 1 Data Type, 1 Stop)
1
1
0
WDS2 WDS1 WDS0
Data
Type
TX
Start
Bit
Stop
Bit
D7
D6
D5
D4
D3
D2
D1
D0
(SSFTD = 1)
Data Type: 1 = Address Byte
0 = Data Byte
Note: 1. Modes 1, 3, and 7 are reserved.
2. D0 = LSB; D7 = MSB
3. Data is transmitted and received LSB first if SSFTD = 0, or MSB first if SSFTD = 1
AA0691 (cont.)
Figure 8-4 SCI Data Word Formats (Continued)
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Serial Communication Interface (SCI)
SCI Programming Model
8.3.1
SCI Control Register (SCR)
The SCR is a 24-bit, read/write register that controls the serial interface operation.
Seventeen of the twenty-four bits are currently defined. Each bit is described in the
following paragraphs.
8.3.1.1
SCR Word Select (WDS[0:2]) Bits 0Ð2
The word select WDS[0:2] bits select the format of transmitted and received data. Format
modes are listed in Table 8-1 below and shown in Figure 8-4 on page 8-6.
Table 8-1 Word Formats
WDS2 WDS1 WDS0 Mode
Word Formats
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
1
2
3
4
8-bit synchronous data (shift register mode)
Reserved
10-bit asynchronous (1 start, 8 data, 1 stop)
Reserved
11-bit asynchronous
(1 start, 8 data, 1 even parity, 1 stop)
1
1
1
0
1
1
1
0
1
5
6
7
11-bit asynchronous
(1 start, 8 data, 1 odd parity, 1 stop)
11-bit multidrop asynchronous
(1 start, 8 data, 1 data type, 1 stop)
Reserved
Asynchronous modes are compatible with most UART-type serial devices and support
standard RS232C communication links. Multidrop asynchronous mode is compatible
with the MC68681 DUART, the M68HC11 SCI interface, and the Intel 8051 serial
interface. Synchronous data mode is essentially a high-speed shift register used for I/O
expansion and stream-mode channel interfaces. A gated transmit and receive clock
compatible with the Intel 8051 serial interface mode 0 makes it possible for you to
synchronize data.
When odd parity is selected, the transmitter counts the number of 1s in the data word. If
the total is not an odd number, the parity bit is set, thus producing an odd number. If the
receiver counts an even number of 1s, an error in transmission has occurred. When even
parity is selected, an even number must result from the calculation performed at both
ends of the line, or an error in transmission has occurred.
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Serial Communication Interface (SCI)
SCI Programming Model
The word select bits are cleared by either a hardware RESET signal or a software RESET
instruction.
8.3.1.2
SCR SCI Shift Direction (SSFTD) Bit 3
The SSFTD bit determines the order in which the SCI data shift registers shift data in or
out: MSB first when set, LSB first when cleared. The parity and data type bits do not
change their position in the frame; they remain adjacent to the stop bit. SSFTD is cleared
by either a hardware RESET signal or a software RESET instruction.
8.3.1.3
SCR Send Break (SBK) Bit 4
A break is an all-zero word frameÑa start bit 0, characters of all 0s (including any
parity), and a stop bit 0 (i.e., ten or eleven 0s, depending on the mode selected). If SBK is
set and then cleared, the transmitter completes transmission of the current frame, sends
ten or eleven 0s (depending on WDS mode), and reverts to idle or sending data. If SBK
remains set, the transmitter continually sends whole frames of 0s (ten or eleven bits with
no stop bit). At the completion of the break code, the transmitter sends at least one high
(set) bit before transmitting any data to guarantee recognition of a valid start bit. Break
can be used to signal an unusual condition, message, etc. by forcing a frame error, which
is caused by a missing stop bit. Either a hardware RESET signal or a software RESET
instruction clears SBK.
8.3.1.4
SCR Wakeup Mode Select (WAKE) Bit 5
When WAKE is cleared, the wakeup on idle line mode is selected. In the wakeup on idle
line mode, the SCI receiver is reenabled by an idle string of at least ten or eleven
(depending on WDS mode) consecutive 1s. The transmitterÕs software must provide this
idle string between consecutive messages. The idle string cannot occur within a valid
message because each word frame contains a start bit that is 0.
When WAKE is set, the wakeup on address bit mode is selected. In the wakeup on
address bit mode, the SCI receiver is reenabled when the last (eighth or ninth) data bit
received in a character (frame) is 1. The ninth data bit is the address bit (R8) in the 11-bit
multidrop mode; the eighth data bit is the address bit in the 10-bit asynchronous and
11-bit asynchronous with parity modes. Thus, the received character is an address that
has to be processed by all sleeping processorsÑthat is, each processor has to compare
the received character with its own address and decide whether to receive or ignore all
following characters. Either a hardware RESET signal or a software RESET instruction
clears WAKE.
8.3.1.5
SCR Receiver Wakeup Enable (RWU) Bit 6
When RWU is set and the SCI is in an asynchronous mode, the wakeup function is
enabledÑthat is, the SCI is asleep, and can be awakened by the event defined by the
WAKE bit. In the sleep state, all interrupts and all receive flags except IDLE are disabled.
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SCI Programming Model
When the receiver wakes up, RWU is cleared by the wakeup hardware. The
programmer can also clear the RWU bit to wake up the receiver.
RWU can be used by the programmer to ignore messages that are for other devices on a
multidrop serial network. Wakeup on idle line (WAKE is cleared) or wakeup on address
bit (WAKE is set) must be chosen.
1. When WAKE is cleared and RWU is set, the receiver does not respond to data on
the data line until an idle line is detected.
2. When WAKE is set and RWU is set, the receiver does not respond to data on the
data line until a data frame with the address bit set is detected.
When the receiver wakes up, the RWU bit is cleared, and the first frame of data is
received. If interrupts are enabled, the CPU is interrupted and the interrupt routine
reads the message header to determine if the message is intended for this DSP.
1. If the message is for this DSP, the message is received, and RWU is set to wait for
the next message.
2. If the message is not for this DSP, the DSP immediately sets RWU. Setting RWU
causes the DSP to ignore the remainder of the message and wait for the next
message.
Either a hardware RESET signal or a software RESET instruction clears RWU. RWU is
ignored in synchronous mode.
8.3.1.6
SCR Wired-OR Mode Select (WOMS) Bit 7
When the WOMS bit is set, the SCI TXD driver is programmed to function as an
open-drain output and can be wired together with other TXD signals in an appropriate
bus configuration, such as a master-slave multidrop configuration. An external pullup
resistor is required on the bus. When the WOMS is cleared, the TXD signal uses an active
internal pullup. Either a hardware RESET signal or a software RESET instruction clears
WOMS.
8.3.1.7
SCR Receiver Enable (RE) Bit 8
When RE is set, the receiver is enabled. When RE is cleared, the receiver is disabled, and
data transfer from the receive shift register to the receive data register (SRX) is inhibited.
If RE is cleared while a character is being received, the reception of the character is
completed before the receiver is disabled. RE does not inhibit RDRF or receive
interrupts. Either a hardware RESET signal or a software RESET instruction clears RE.
8.3.1.8
SCR Transmitter Enable (TE) Bit 9
When TE is set, the transmitter is enabled. When TE is cleared, the transmitter completes
transmission of data in the SCI Transmit Data Shift Register, then the serial output is
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forced high (i.e., idle). Data present in the SCI transmit data register (STX) is not
transmitted. STX can be written and TDRE cleared, but the data is not transferred into
the shift register. TE does not inhibit TDRE or transmit interrupts. Either a hardware
RESET signal or a software RESET instruction clears TE.
Setting TE causes the transmitter to send a preamble of ten or eleven consecutive 1s
(depending on WDS). This procedure gives the programmer a convenient way to insure
that the line goes idle before starting a new message. To force this separation of
messages by the minimum idle line time, the following sequence is recommended:
1. Write the last byte of the first message to STX.
2. Wait for TDRE to go high, indicating the last byte has been transferred to the
transmit shift register.
3. Clear TE and set TE. This queues an idle line preamble to follow immediately the
transmission of the last character of the message (including the stop bit).
4. Write the first byte of the second message to STX.
In this sequence, if the first byte of the second message is not transferred to STX prior to
the finish of the preamble transmission, the transmit data line marks idle until STX is
finally written.
8.3.1.9
SCR Idle Line Interrupt Enable (ILIE) Bit 10
When ILIE is set, the SCI interrupt occurs when IDLE (SCI status register bit 3) is set.
When ILIE is cleared, the IDLE interrupt is disabled. Either a hardware RESET signal or
a software RESET instruction clears ILIE.
An internal flag, the shift register idle interrupt (SRIINT) flag, is the interrupt request to
the interrupt controller. SRIINT is not directly accessible to the user.
When a valid start bit has been received, an idle interrupt is generated if both IDLE and
ILIE are set. The idle interrupt acknowledge from the interrupt controller clears this
interrupt request. The idle interrupt is not asserted again until at least one character has
been received. The results are as follows:
1. The IDLE bit shows the real status of the receive line at all times.
2. An idle interrupt is generated once for each idle state, no matter how long the idle
state lasts.
8.3.1.10
SCR SCI Receive Interrupt Enable (RIE) Bit 11
The RIE bit is set to enable the SCI Receive Data interrupt. If RIE is cleared, the Receive
Data interrupt is disabled, and then the RDRF bit in the SCI Status Register must be
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SCI Programming Model
polled to determine if the receive data register is full. If both RIE and RDRF are set, the
SCI requests an SCI receive data interrupt from the interrupt controller.
Receive interrupts with exception have higher priority than normal receive data
interrupts. Therefore, if an exception occurs (i.e., if PE, FE, or OR are set) and REIE is set,
the SCI requests an SCI receive data with exception interrupt from the interrupt
controller. Either a hardware RESET signal or a software RESET instruction clears RIE.
8.3.1.11
SCR SCI Transmit Interrupt Enable (TIE) Bit 12
The TIE bit is set to enable the SCI transmit data interrupt. If TIE is cleared, transmit data
interrupts are disabled, and the transmit data register empty (TDRE) bit in the SCI status
register must be polled to determine if the transmit data register is empty. If both TIE
and TDRE are set, the SCI requests an SCI transmit data interrupt from the interrupt
controller. Either a hardware RESET signal or a software RESET instruction clears TIE.
8.3.1.12
SCR Timer Interrupt Enable (TMIE) Bit 13
The TMIE bit is set to enable the SCI timer interrupt. If TMIE is set, timer interrupt
requests are sent to the interrupt controller at the rate set by the SCI clock register. The
timer interrupt is automatically cleared by the timer interrupt acknowledge from the
interrupt controller. This feature allows DSP programmers to use the SCI baud rate
generator as a simple periodic interrupt generator if the SCI is not in use, if external
clocks are used for the SCI, or if periodic interrupts are needed at the SCI baud rate. The
SCI internal clock is divided by 16 (to match the 1 ´ SCI baud rate) for timer interrupt
generation. This timer does not require that any SCI signals be configured for SCI use to
operate. Either a hardware RESET signal or a software RESET instruction clears TMIE.
8.3.1.13
SCR Timer Interrupt Rate (STIR) Bit 14
The STIR bit controls a divide-by-32 in the SCI Timer interrupt generator. When STIR is
cleared, the divide-by-32 is inserted in the chain. When STIR is set, the divide-by-32 is
bypassed, thereby increasing timer resolution by a factor of 32. Either a hardware RESET
signal or a software RESET instruction clears this bit. To insure proper operation of the
timer, STIR must not be changed during timer operation (i.e., if TMIE = 1).
8.3.1.14
SCR SCI Clock Polarity (SCKP) Bit 15
The SCKP bit controls the clock polarity sourced or received on the clock signal (SCLK),
eliminating the need for an external inverter. When SCKP is cleared, the clock polarity is
positive. When SCKP is set, the clock polarity is negative. In synchronous mode, positive
polarity means that the clock is normally positive and transitions negative during valid
data. Negative polarity means that the clock is normally negative and transitions
positive during valid data. In asynchronous mode, positive polarity means that the
rising edge of the clock occurs in the center of the period that data is valid. Negative
polarity means that the falling edge of the clock occurs during the center of the period
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SCI Programming Model
that data is valid. Either a hardware RESET signal or a software RESET instruction clears
SCKP.
8.3.1.15
Receive with Exception Interrupt Enable (REIE) Bit 16
The REIE bit is set to enable the SCI receive data with exception interrupt. If REIE is
cleared, the receive data with exception interrupt is disabled. If both REIE and RDRF are
set, and PE, FE, and OR are not all cleared, the SCI requests an SCI receive data with
exception interrupt from the interrupt controller. Either a hardware RESET signal or a
software RESET instruction clears REIE.
8.3.2
SCI Status Register (SSR)
The SSR is a 24-bit, read-only register used by the DSP to determine the status of the SCI.
The status bits are described in the following paragraphs.
8.3.2.1
SSR Transmitter Empty (TRNE) Bit 0
The TRNE flag bit is set when both the transmit shift register and transmit data register
(STX) are empty to indicate that there is no data in the transmitter. When TRNE is set,
data written to one of the three STX locations or to the transmit data address register
(STXA) is transferred to the transmit shift register and is the first data transmitted. TRNE
is cleared when TDRE is cleared by writing data into the STX or the STXA, or when an
idle, preamble, or break is transmitted. This bit, when set, indicates that the transmitter
is empty; therefore, the data written to STX or STXA is transmitted next. That is, there is
no word in the transmit shift register presently being transmitted. This procedure is
useful when initiating the transfer of a message (i.e., a string of characters). TRNE is set
by a hardware RESET signal, software RESET instruction, SCI individual reset, or STOP
instruction.
8.3.2.2
SSR Transmit Data Register Empty (TDRE) Bit 1
The TDRE flag bit is set when the SCI transmit data register is empty. When TDRE is set,
new data can be written to one of the SCI transmit data registers (STX) or the transmit
data address register (STXA). TDRE is cleared when the SCI transmit data register is
written. TDRE is set by the hardware RESET signal, software RESET instruction, SCI
individual reset, or STOP instruction.
In synchronous mode, when using the internal SCI clock, there is a delay of up to 5.5
serial clock cycles between the time that STX is written until TDRE is set, indicating the
data has been transferred from the STX to the transmit shift register. There is a 2 to
4 serial clock cycle delay between writing STX and loading the transmit shift register; in
addition, TDRE is set in the middle of transmitting the second bit. When using an
external serial transmit clock, if the clock stops, the SCI transmitter stops. TDRE is not set
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SCI Programming Model
until the middle of the second bit transmitted after the external clock starts. Gating the
external clock off after the first bit has been transmitted delays TDRE indefinitely.
In asynchronous mode, the TDRE flag is not set immediately after a word is transferred
from the STX or STXA to the transmit shift register nor when the word first begins to be
shifted out. TDRE is set two cycles of the 16 ´ clock after the start bitÑ that is, two
16 ´ clock cycles into the transmission time of the first data bit.
8.3.2.3
SSR Receive Data Register Full (RDRF) Bit 2
The RDRF bit is set when a valid character is transferred to the SCI Receive Data Register
from the SCI receive shift register (regardless of the error bits condition). RDRF is
cleared when the SCI receive data register is read or by a hardware RESET signal,
software RESET instruction, SCI individual reset, or STOP instruction.
8.3.2.4
SSR Idle Line Flag (IDLE) Bit 3
IDLE is set when 10 (or 11) consecutive 1s are received. IDLE is cleared by a start-bit
detection. The IDLE status bit represents the status of the receive line. The transition of
IDLE from 0 to 1 can cause an IDLE interrupt (ILIE). IDLE is cleared by a hardware
RESET signal, software RESET instruction, SCI individual reset, or STOP instruction.
8.3.2.5
SSR Overrun Error Flag (OR) Bit 4
The OR flag bit is set when a byte is ready to be transferred from the receive shift register
to the receive data register (SRX) that is already full (RDRF = 1). The receive shift register
data is not transferred to the SRX. The OR flag indicates that character(s) in the received
data stream may have been lost. The only valid data is located in the SRX. OR is cleared
when the SCI Status Register is read, followed by a read of SRX. The OR bit clears the FE
and PE bitsÑthat is, an overrun error has higher priority than FE or PE. OR is cleared by
a hardware RESET signal, software RESET instruction, SCI individual reset, or STOP
instruction.
8.3.2.6
SSR Parity Error (PE) Bit 5
In the 11-bit asynchronous modes, the PE bit is set when an incorrect parity bit has been
detected in the received character. It is set simultaneously with RDRF for the byte which
contains the parity errorÑthat is, when the received word is transferred to the SRX. If PE
is set, further data transfer into the SRX is not inhibited. PE is cleared when the SCI
status register is read, followed by a read of SRX. PE is also cleared by a hardware
RESET signal, software RESET instruction, SCI individual reset, or STOP instruction. In
10-bit asynchronous mode, 11-bit multidrop mode, and 8-bit synchronous mode, the PE
bit is always cleared since there is no parity bit in these modes. If the byte received
causes both parity and overrun errors, the SCI receiver recognizes only the overrun
error.
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SCI Programming Model
8.3.2.7
SSR Framing Error Flag (FE) Bit 6
The FE bit is set in asynchronous modes when no stop bit is detected in the data string
received. FE and RDRE are set simultaneously when the received word is transferred to
the SRX. However, the FE flag inhibits further transfer of data into the SRX until it is
cleared. FE is cleared when the SCI status register is read followed by reading the SRX. A
hardware RESET signal, software RESET instruction, SCI individual reset, or STOP
instruction also clears FE. In 8-bit synchronous mode, FE is always cleared. If the byte
received causes both framing and overrun errors, the SCI receiver recognizes only the
overrun error.
8.3.2.8
SSR Received Bit 8 (R8) Address Bit 7
In 11-bit asynchronous multidrop mode, the R8 bit is used to indicate whether the
received byte is an address or data. R8 is set for addresses and is cleared for data. R8 is
not affected by reading the SRX or SCI status register. A hardware RESET signal,
software RESET instruction, SCI individual reset, or STOP instruction also clears R8.
8.3.3
SCI Clock Control Register (SCCR)
The SCCR is a 24-bit, read/write register that controls the selection of the clock modes
and baud rates for the transmit and receive sections of the SCI interface. The control bits
are described in the following paragraphs. The SCCR is cleared by a hardware RESET
signal. The basic features of the clock generator (as in Figure 8-5 on page 8-16 and
Figure 8-6 on page 8-18) are these:
¥ The SCI logic always uses a 16 ´ internal clock in asynchronous modes and
always uses a 2 ´ internal clock in synchronous mode. The maximum internal
clock available to the SCI peripheral block is the oscillator frequency divided by 4.
¥ The 16 ´ clock is necessary for asynchronous modes to synchronize the SCI to the
incoming data, as in Figure 8-5.
¥ For asynchronous modes, the user must provide a 16 ´ clock to use an external
baud rate generator (i.e., SCLK input).
¥ For asynchronous modes, the user can select either 1 ´ or 16 ´ for the output clock
when using internal TX and RX clocks (TCM = 0 and RCM = 0).
¥ When SCKP is cleared, the transmitted data on the TXD signal changes on the
negative edge of the 1 ´ serial clock and is stable on the positive edge. When
SCKP is set, the data changes on the positive edge and is stable on the negative
edge.
¥ The received data on the RXD signal is sampled on the positive edge (if SCKP = 0)
or on the negative edge (if SCKP = 1) of the 1 ´ serial clock.
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SCI Programming Model
¥ For asynchronous mode, the output clock is continuous.
¥ For synchronous mode, a 1 ´ clock is used for the output or input baud rate. The
maximum 1 ´ clock is the crystal frequency divided by 8.
¥ For synchronous mode, the clock is gated.
¥ For synchronous mode, the transmitter and receiver are synchronous with each
other.
Select 8-or 9-bit Words
0
1
2
3
4
5
6
7
8
Idle Line
RX, TX Data
(SSFTD = 0)
Start
Stop
Start
x1 Clock
x16 Clock
(SCKP = 0)
AA0692
Figure 8-5 16 x Serial Clock
8.3.3.1
SCCR Clock Divider (CD[11:0]) Bits 11Ð0
The CD[11:0] bits specify the divide ratio of the prescale divider in the SCI clock
generator. A divide ratio from 1 to 4096 (CD[11:0] = $000 to $FFF) can be selected. Either
a hardware RESET signal or a software RESET instruction clears CD11ÐCD0.
8.3.3.2
SCCR Clock Out Divider (COD) Bit 12
The clock output divider is controlled by COD and SCI mode. If SCI mode is
synchronous, the output divider is fixed at divide by 2.
If SCI mode is asynchronous, then one of the following conditions occurs:
¥ If COD is cleared and SCLK is an output (i.e., TCM and RCM are both cleared),
the SCI clock is divided by 16 before being output to the SCLK signal. Thus, the
SCLK output is a 1 ´ clock.
¥ If COD is set and SCLK is an output, the SCI clock is fed directly out to the SCLK
signal. Thus, the SCLK output is a 16 ´ baud clock.
Either a hardware RESET signal or a software RESET instruction clears COD.
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SCI Programming Model
8.3.3.3
SCCR SCI Clock Prescaler (SCP) Bit 13
The SCP bit selects a divide by 1 (SCP is cleared) or divide by 8 (SCP is set) prescaler for
the clock divider. The output of the prescaler is further divided by 2 to form the SCI
clock. Either a hardware RESET signal or a software RESET instruction clears SCP.
8.3.3.4
SCCR Receive Clock Mode Source (RCM) Bit 14
RCM selects whether an internal or external clock is used for the receiver. If RCM is
cleared, the internal clock is used. If RCM is set, the external clock (from the SCLK
signal) is used. Either a hardware RESET signal or a software RESET instruction clears
RCM.
Table 8-2 TCM and RCM Bit Configuration
SCLK
Signal
TCM RCM TX Clock
RX Clock
Mode
0
0
1
1
0
1
0
1
Internal
Internal
External
External
Internal
External
Internal
External
Output
Input
Input
Input
Synchronous/Asynchronous
Asynchronous Only
Asynchronous Only
Synchronous/Asynchronous
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SCI Programming Model
F
core
Divide
By 2
Divide
By 2
Prescaler:
Divide by
1 or 8
12-bit Counter
CD11ÐCD0
SCP
Internal Clock
Divide
By 16
SCI Core Logic
Uses Divide by 16 for
Asynchronous
Uses Divide by 2 for
Synchronous
Timer
Interrupt
(STMINT)
If Asynchronous
Divide by 1 or 16
If Synchronous
Divide By 2
COD
F
core
BPS =
where:
SCKP = 0
SCKP = 1
+
Ð
64 ´ ((7 ´ SCP + 1) ´ CD + 1)
SCKP
SCP = 0 or 1
CD = $000 to $FFF
TO SCLK
AA0693
Figure 8-6 SCI Baud Rate Generator
SCCR Transmit Clock Source Bit (TCM) Bit 15
8.3.3.5
TCM selects whether an internal or external clock is used for the transmitter. If TCM is
cleared, the internal clock is used. If TCM is set, the external clock (from the SCLK
signal) is used. Either a hardware RESET signal or a software RESET instruction clears
TCM.
8.3.4
SCI Data Registers
The SCI data registers are divided into two groups: receive and transmit (as in
Figure 8-7). There are two receive registersÑa receive data register (SRX) and a
serial-to-parallel receive shift register. There are also two transmit registersÑa transmit
data register (called either STX or STXA) and a parallel-to-serial transmit shift register.
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SCI Programming Model
23
16 15
8
7
0
SRX
RXD
SCI Receive Data Register High (Read Only)
SRX
SCI Receive Data Register Middle (Read Only)
SCI Receive Data Register Low (Read Only)
SRX
SCI Receive Data Shift Register
Note: 1. SRX is the same register decoded at three different addresses.
(a) Receive Data Register
23
16 15
8
7
0
STX
SCI Transmit Data Register High (Write Only)
SCI Transmit Data Register Middle (Write Only)
SCI Transmit Data Register Low (Write Only)
STX
STX
SCI Transmit Data Shift Register
16 15
TXD
23
8
7
0
SCI Transmit Data Address Register (Write Only)
STXA
Note: 1. Bytes are masked on the fly.
2. STX is the same register decoded at four different addresses.
(b) Transmit Data Register
AA0694
Figure 8-7 SCI Programming Model Data Registers
8.3.4.1
SCI Receive Registers (SRX)
Data bits received on the RXD signal are shifted into the SCI receive shift register. When
a complete word has been received, the data portion of the word is transferred to the
byte-wide SRX. This process converts the serial data to parallel data and provides
double-buffering. Double-buffering provides flexibility to the programmer and
increased throughput since the programmer can save (and process) the previous word
while the current word is being received.
The SRX can be read at three locations as SRXL, SRXM, and SRXH. When SRXL is read,
the contents of the SRX are placed in the lower byte of the data bus and the remaining
bits on the data bus are read as 0s. Similarly, when SRXM is read, the contents of SRX are
placed in the middle byte of the bus, and when SRXH is read, the contents of SRX are
placed in the high byte with the remaining bits read as 0s. Mapping SRX as described
allows three bytes to be efficiently packed into one 24-bit word by ORing three data
bytes read from the three addresses.
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SCI Programming Model
The length and format of the serial word are defined by the WDS0, WDS1, and WDS2
control bits in the SCR. The clock source is defined by the receive clock mode (RCM)
select bit in the SCR.
In synchronous mode, the start bit, the eight data bits, the address/data indicator bit
and/or the parity bit, and the stop bit are received in that order. Data bits are sent LSB
first if SSFTD is cleared, and MSB first if SSFTD is set. In synchronous mode, the
synchronization is provided by gating the clock.
In either synchronous or asynchronous mode, when a complete word has been clocked
in, the contents of the shift register can be transferred to the SRX and the flags; RDRF, FE,
PE, and OR are changed appropriately. Because the operation of the receive shift register
is transparent to the DSP, the contents of this register are not directly accessible to the
programmer.
8.3.4.2
SCI Transmit Registers
The transmit data register is a one byte-wide register mapped into four addresses as
STXL, STXM, STXH, and STXA. In asynchronous mode, when data is to be transmitted,
STXL, STXM, and STXH are used. When STXL is written, the low byte on the data bus is
transferred to the STX. When STXM is written, the middle byte is transferred to the STX.
When STXH is written, the high byte is transferred to the STX. This structure makes it
easy for the programmer to unpack the bytes in a 24-bit word for transmission. TDXA
should be written in the 11-bit asynchronous multidrop mode when the data is an
address and it is desired that the ninth bit (the address bit) be set. When STXA is written,
the data from the low byte on the data bus is stored in it. The address data bit is cleared
in the 11-bit asynchronous multidrop mode when any of STXL, STXM or STXH is
written. When either STX (STXL, STXM, or STXH) or STXA is written, TDRE is cleared.
The transfer from either STX or STXA to the transmit shift register occurs automatically,
but not immediately, when the last bit from the previous word has been shifted out; that
is, the transmit shift register is empty. Like the receiver, the transmitter is
double-buffered. However, a 2 to 4 serial clock cycle delay occurs between when the
data is transferred from either STX or STXA to the transmit shift register and when the
first bit appears on the TXD signal. (A serial clock cycle is the time required to transmit
one data bit). The transmit shift register is not directly addressable, and a dedicated flag
for this register does not exist. Because of this fact and the 2 to 4 cycle delay, two bytes
cannot be written consecutively to STX or STXA without polling, as the second byte
might overwrite the first byte. The TDRE flag should always be polled prior to writing
STX or STXA to prevent overruns unless transmit interrupts have been enabled. Either
STX or STXA is usually written as part of the interrupt service routine. An interrupt is
generated only if TDRE is set. The transmit shift register is indirectly visible via the
TRNE bit in the SSR.
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Serial Communication Interface (SCI)
Operating Modes
In synchronous mode, data is synchronized with the transmit clock, which can have
either an internal or external source, as defined by the TCM bit in the SCCR. The length
and format of the serial word is defined by the WDS0, WDS1, and WDS2 control bits in
the SCR. In asynchronous modes, the start bit, the eight data bits (with the LSB first if
SSFTD = 0 and the MSB first if SSFTD = 1), the address/data indicator bit or parity bit,
and the stop bit are transmitted in that order.
The data to be transmitted can be written to any one of the three STX addresses. If SCKP
is set and SSHTD is set, the SCI synchronous mode is equivalent to the SSI operation in
the 8-bit data on-demand mode.
Note:
When writing data to a peripheral device, there is a two cycle pipeline delay
until any status bits affected by this operation are updated. If you read any of
those status bits within the next two cycles, the bit does not reflect its current
status. See the DSP56300 Family Manual, Appendix B, Polling a Peripheral
Device for Write for further details.
8.4
OPERATING MODES
The operating modes for the DSP56309 SCI are these:
¥ 8-bit synchronous (shift register mode)
¥ 10-bit asynchronous (1 start, 8 data, 1 stop)
¥ 11-bit asynchronous (1 start, 8 data, 1 even parity, 1 stop)
¥ 11-bit asynchronous (1 start, 8 data, 1 odd parity, 1 stop)
¥ 11-bit multidrop asynchronous (1 start, 8 data, 1 data type, 1 stop)
This mode is used for master/slave operation with wakeup on idle line and
wakeup on address bit capability. It allows the DSP56309 to share a single serial
line efficiently with other peripherals.
These modes are selected using the WD[0:2] bits in the SCR.
The synchronous data mode is essentially a high-speed shift register used for I/O
expansion and stream-mode channel interfaces. Data synchronization is accomplished
Ò
by the use of a gated transmit and receive clock that is compatible with the Intel 8051
serial interface mode 0.
Asynchronous modes are compatible with most UART-type serial devices. Standard
RS232C communication links are supported by these modes.
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Serial Communication Interface (SCI)
Operating Modes
The multidrop asynchronous modes are compatible with the MC68681 DUART, the
M68HC11 SCI interface, and the Intel 8051 serial interface.
8.4.1
SCI After Reset
There are four different methods of resetting the SCI.
1. Hardware RESET signal
2. Software RESET instruction:
Both hardware and software resets clear the port control register bits, which
configure all I/O as GPIO input. The SCI remains in the reset state as long as all
SCI signals are programmed as GPIO (PC2, PC1, and PC0 all are cleared); the SCI
becomes active only when at least one of the SCI I/O signals is not programmed
as GPIO.
3. Individual reset:
During program execution, the PC2, PC1, and PC0 bits can be cleared (individual
reset), which causes the SCI to stop serial activity and enter the reset state. All SCI
status bits are set to their reset state. However, the contents of the SCR are not
affected, allowing the DSP program to reset the SCI separately from the other
internal peripherals. During individual reset, internal DMA accesses to the data
registers of the SCI are not valid and the data read is unknown.
4. Stop processing state reset:
Executing the STOP instruction halts operation of the SCI until the DSP is
restarted, causing the SSR to be reset. No other SCI registers are affected by the
STOP instruction.
Table 8-3 on page 8-23 illustrates how each type of reset affects each register in the SCI.
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Serial Communication Interface (SCI)
Operating Modes
Table 8-3 SCI Registers after Reset
Reset Type
Register
Bit
Bit Mnemonic
Bit Number
HW
SW
IR
ST
Reset
Reset
Reset
Reset
REIE
SCKP
STIR
TMIE
TIE
16
15
14
13
12
11
10
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
0
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
0
RIE
ILIE
TE
SCR
RE
8
WOMS
RWU
WAKE
SBK
7
6
5
4
SSFTD
WDS[2:0]
R8
3
2Ð0
7
FE
6
0
0
PE
5
0
0
SSR
OR
4
0
0
IDLE
RDRF
TDRE
3
0
0
2
0
0
1
1
1
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Serial Communication Interface (SCI)
Operating Modes
Table 8-3 SCI Registers after Reset (Continued)
Reset Type
Register
Bit Mnemonic
Bit Number
Bit
HW
Reset
SW
Reset
IR
Reset
ST
Reset
TRNE
TCM
0
1
0
1
0
1
1
15
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ð
RCM
14
0
0
SCCR
SCP
13
0
0
COD
12
0
0
CD[11:0]
SRX [23:0]
STX[23:0]
SRS[8:0]
STS[8:0]
11Ð0
0
0
SRX
STX
23Ð16, 15Ð8, 7Ð0
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
23Ð0
8Ð0
SRSH
STSH
8Ð0
Note: SRSHÑSCI Receive Shift Register, STSH Ñ SCI Transmit Shift Register
HWÑHardware reset is caused by asserting the external RESET signal.
SWÑSoftware reset is caused by executing the RESET instruction.
IRÑIndividual reset is caused by clearing PCRE (bits 0Ð2) (configured for GPIO).
STÑStop reset is caused by executing the STOP instruction.
1ÑThe bit is set during this reset.
0ÑThe bit is cleared during this reset.
Ñ Ñ The bit is not changed during this reset
8.4.2
SCI Initialization
The correct way to initialize the SCI is as follows:
1. Send a hardware RESET signal or software RESET instruction.
2. Program SCI control registers.
3. Configure at least one SCI signal as other than GPIO.
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Serial Communication Interface (SCI)
Operating Modes
If interrupts are to be used, the signals must be selected, and interrupts must be enabled
and unmasked before the SCI can operate. The order does not matter; any one of these
three requirements for interrupts can be used to enable the SCI.
Synchronous applications usually require exact frequencies, which require that the
crystal frequency be chosen carefully. An alternative to selecting the system clock to
accommodate the SCI requirements is to provide an external clock to the SCI.
8.4.3
SCI Initialization Example
One way to initialize the SCI is described here as an example.
1. The SCI should be in its individual reset state (PCR = $0).
2. Configure the control registers (SCR, SCCR) according to the operating mode, but
do not enable either transmitter (TE = 0) or receiver (RE = 0).
It is possible to set the interrupt enable bits that would be in use during the
operation (no interrupt occurs).
3. Enable the SCI by setting the PCR bits according to which signals will be in use
during operation.
4. If transmit interrupt is not used, write data to the transmitter.
If transmitter interrupt enable is set, an interrupt is issued and the interrupt
handler should write data into the transmitter.
SCI transmit request is serviced by DMA channel if it is programmed to service
the SCI transmitter.
5. Enable transmitters (TE = 1) and receiver (RE = 1), according to usage.
Operation starts as follows:
¥ For an internally generated clock, the SCLK signal starts operation immediately
after the SCI is enabled (Step 3 above) for asynchronous modes. In synchronous
mode, the SCLK signal is active only while transmitting (gated clock).
¥ Data is received only when the receiver is enabled (RE = 1) and after the
occurrence of the SCI receive sequence on the RXD signal, as defined by the
operating mode (i.e., idle line sequence).
¥ Data is transmitted only after the transmitter is enabled (TE = 1), and after
transmitting the initialization sequence depending on the operating mode.
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Serial Communication Interface (SCI)
Operating Modes
8.4.4
Preamble, Break, and Data Transmission Priority
Two or three transmission commands can be set simultaneously:
1. A preamble (TE is set.)
2. A break (SBK is set or is cleared.)
3. There is data for transmission (TDRE is cleared.)
After the current character transmission, if two or more of these commands are set, the
transmitter executes them in the following order:
1. Preamble
2. Break
3. Data
8.4.5
SCI Exceptions
The SCI can cause five different exceptions in the DSP. These exceptions are as follows
(ordered from the highest to the lowest priority):
1. SCI receive data with exception status is caused by receive data register full with
a receiver error (parity, framing, or overrun error). Clearing the pending interrupt
is done by reading the SCI status register, followed by a read of SRX. A long
interrupt service routine should be used to handle the error condition. This
interrupt is enabled by SCR bit 16 (REIE).
2. SCI receive data is caused by receive data register full. Reading SRX clears the
pending interrupt. This error-free interrupt can use a fast interrupt service routine
for minimum overhead. This interrupt is enabled by SCR bit 11 (RIE).
3. SCI transmit data is caused by transmit data register empty. Writing STX clears
the pending interrupt. This error-free interrupt can use a fast interrupt service
routine for minimum overhead. This interrupt is enabled by SCR bit 12 (TIE).
4. SCI idle line is caused by the receive line entering the idle state (10 or 11 bits of
1s). This interrupt is latched and then automatically reset when the interrupt is
accepted. This interrupt is enabled by SCR bit 10 (ILIE).
5. SCI timer is caused by the baud rate counter reaching zero. This interrupt is
automatically reset when the interrupt is accepted. This interrupt is enabled by
SCR bit 13 (TMIE).
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Serial Communication Interface (SCI)
GPIO Signals and Registers
8.5
GPIO SIGNALS AND REGISTERS
The GPIO functionality of port SCI is controlled by three registers: Port E control register
(PCRE), Port E direction register (PRRE) and Port E data register (PDRE).
8.5.1
Port E Control Register (PCRE)
The read/write, 24-bit PCRE controls the functionality of SCI GPIO signals. Each of the
PC[2:0] bits controls the functionality of the corresponding port signal. When a PC[i] bit
is set, the corresponding port signal is configured as a SCI signal. When a PC[i] bit is
cleared, the corresponding port signal is configured as a GPIO signal. Bits in the Port E
control register appear in Figure 8-8.
7
6
5
4
3
2
1
0
PC2 PC1 PC0
Port Control Bits: 1 = SCI
0 = GPIO
13
21
12
20
11
19
10
18
9
8
15
23
14
22
17
16
Reserved Bit, Read as 0, Should be Written with 0 for Future Compatibility
AA0695
Figure 8-8 Port E Control Register (PCRE)
Note:
A hardware RESET signal or a software RESET instruction clears all PCR bits.
8.5.2
Port E Direction Register (PRRE)
The read/write, 24-bit PRRE controls the direction of SCI GPIO signals. When port
signal[i] is configured as GPIO, PDC[i] controls the port signal direction. When PDC[i] is
set, the GPIO port signal[i] is configured as output. When PDC[i] is cleared, the GPIO
port signal[i] is configured as input. Bits in the Port E direction register appear in
Figure 8-9.
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Serial Communication Interface (SCI)
GPIO Signals and Registers
7
6
5
4
3
2
1
0
PDC2 PDC1 PDC0
Direction Control Bits: 1 = Output
0 = Input
13
21
12
20
11
19
10
18
9
8
15
23
14
22
17
16
Reserved Bit, Read as 0, Should be Written with 0 for Future Compatibility
AA0696
Figure 8-9 Port E Direction Register (PRRE)
Note:
A hardware RESET signal or a software RESET instruction clears all PRR bits.
Table 8-4 shows the port signal configurations.
Table 8-4 Port Control Register and Port Direction Register Bits
PC[i]
PDC[i]
Port Signal[i] Function
1
0
0
1 or 0
SCI
0
1
GPIO input
GPIO output
8.5.3
Port E Data Register (PDRE)
The read/write, 24-bit PDRE is used to read or write data to or from SCI GPIO signals.
Bits PD[2:0] are used to read or write data from or to the corresponding port signals if
they are configured as GPIO. If a port signal[i] is configured as a GPIO input, then the
corresponding PD[i] bit reflects the value of this signal. If a port signal[i] is configured as
a GPIO output, then the value of the corresponding PD[i] bit is reflected on this signal.
Bits of the Port E data register appear in Figure 8-10.
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Serial Communication Interface (SCI)
GPIO Signals and Registers
7
6
5
4
3
2
1
0
PD2 PD1 PD0
13
21
12
20
11
19
10
18
9
8
15
23
14
22
17
16
Reserved Bit, Read as 0, Should be Written with 0 for Future Compatibility
AA0697
Figure 8-10 Port E Data Register (PDRE)
Note:
A hardware RESET signal or a software RESET instruction clears all PDRE
bits.
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Serial Communication Interface (SCI)
GPIO Signals and Registers
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SECTION 9
TRIPLE TIMER MODULE
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Triple Timer Module
9.1
9.2
9.3
9.4
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
TRIPLE TIMER MODULE ARCHITECTURE . . . . . . . . . . . . 9-3
TRIPLE TIMER MODULE PROGRAMMING MODEL. . . . . . 9-5
TIMER OPERATIONAL MODES. . . . . . . . . . . . . . . . . . . . . 9-16
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Triple Timer Module
Introduction
9.1
INTRODUCTION
This section describes the internal triple timer module in the DSP56309. Each timer has a
single signal that can be used as a GPIO signal or as a timer signal. These three timers
can be used to generate timed pulses or as pulse width modulators. They can also be
used as an event counter, to capture an event, or to measure the width or period of a
signal.
9.2
TRIPLE TIMER MODULE ARCHITECTURE
The timer module is composed of a common 21-bit prescaler and three independent and
identical general purpose 24-bit timer/event counters, each having its own register set.
Each timer can use internal or external clocking and can interrupt the DSP56309 after a
specified number of events (clocks) or can signal an external device after counting
internal events. Each timer can also be used to trigger DMA transfers after a specified
number of events (clocks) has occurred. Each timer connects to the external world
through one bidirectional signal, designated TIO0ÐTIO2 for Timers 0Ð2, respectively.
When the TIO signal is configured as input, the timer functions as an external event
counter or measures external pulse width/signal period. When the TIO signal is used as
output, the timer functions as a timer, a watchdog timer, or a pulse width modulator.
When the TIO signal is not used by the timer, it can be used as a GPIO signal (also called
TIO0ÐTIO2).
9.2.1
Triple Timer Module Block Diagram
Figure 9-1 shows a block diagram of the triple timer module. This module includes a
24-bit timer prescaler load register (TPLR), a 24-bit timer prescaler count register
(TPCR), a 21-bit prescaler clock counter, and three timers. Each of the three timers can
use the prescaler clock as its clock source.
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Triple Timer Module
Triple Timer Module Architecture
GDB
24
24
24
TPLR
TPCR
24
Timer Prescaler
Count Register
Timer Prescaler
Load Register
Timer 0
Timer 1
Timer 2
21-bit Counter
AA0673
CLK/2 TIO0 TIO1 TIO2
Figure 9-1 Triple Timer Module Block Diagram
9.2.2
Timer Block Diagram
The timer block diagram (in Figure 9-2) shows the structure of a timer module. The
timer programmerÕs model (in Figure 9-3 on page 9-6) shows the structure of the timer
registers. The three timers are identical in structure and function. A generic timer is
discussed in this section.
The timer includes a 24-bit counter, a 24-bit read/write timer control and status register
(TCSR), a 24-bit read-only timer count register (TCR), a 24-bit write-only timer load
register (TLR), a 24-bit read/write timer compare register (TCPR), and logic for clock
selection and interrupt/DMA trigger generation.
The timer mode is controlled by the TC[3:0] bits of the timer control/status register
(TCSR). For a listing of the timer modes, see Section 9ÑTimer Operational Modes. For
a description of their operation, see Section 9.4.1ÑTiming Modes.
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Triple Timer Module
Triple Timer Module Programming Model
The DSP56309 views each timer as a memory-mapped peripheral with four registers
occupying four 24-bit words in the X data memory space. Either standard polled or
interrupt programming techniques can be used to service the timers. The timer
programming model is shown in Figure 9-3 on page 9-6.
GDB
24
24
TCSR
24
24
TCR
24
TCPR
TLR
Control/Status
Register
Load
Register
Count
Register
Compare
Register
9
24
24
24
2
24
Timer Control
Logic
Counter
=
Timer interrupt/
DMA request
TIO
CLK/2 prescaler CLK
AA0676
Figure 9-2 Timer Module Block Diagram
9.3
TRIPLE TIMER MODULE PROGRAMMING MODEL
The programming model for the triple timer module appears in Figure 9-3 on page 9-6.
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Triple Timer Module
Triple Timer Module Programming Model
23
0
0
Timer Prescaler Load
Register (TPLR)
TPLR = $FFFF83
23
Timer Prescaler Count
Register (TPCR)
TPLR = $FFFF82
7
6
5
4
3
2
1
0
TC1 TC0
TC3 TC2
TCIE TOIE TE
Timer Control/Status
Register (TCSR)
TCSR0 = $FFFF8F
TCSR1 = $FFFF8B
TCSR2 = $FFFF87
15
14
22
13
12
DI
11
10
18
9
8
PCE
DO
DIR
TRM
INV
23
21
20
19
17
16
TCF TOF
23
0
Timer Load
Register (TLR)
TLR0 = $FFFF8E
TLR1 = $FFFF8A
TLR2 = $FFFF86
23
23
0
0
Timer Compare
Register (TCPR)
TCPR0 = $FFFF8D
TCPR1 = $FFFF89
TCPR2 = $FFFF85
Timer Count
Register (TCR)
TCR0 = $FFFF8C
TCR1 = $FFFF88
TCR2 = $FFFF84
- reserved, read as 0, should be written with 0 for future compatibility
Figure 9-3 Timer Module ProgrammerÕs Model
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Triple Timer Module Programming Model
9.3.1
Prescaler Counter
The prescaler counter is a 21-bit counter that is decremented on the rising edge of the
prescaler input clock. The counter is enabled when at least one of the three timers is
enabled (i.e., one or more of the timer enable (TE) bits are set) and is using the prescaler
output as its source (i.e., one or more of the PCE bits are set).
9.3.2
Timer Prescaler Load Register (TPLR)
The TPLR is a 24-bit, read/write register that controls the prescaler divide factor (i. e.,
the number that the prescaler counter loads and begins counting from) and the source
for the prescaler input clock. The control bits are shown below in Figure 9-4.
23
22
21
20
19
18
17
16
15
14
13
12
PS1
PS0
PL20
PL19
PL18
PL17
PL16
PL15
PL14
PL13
PL12
11
10
9
8
7
6
5
4
3
2
1
0
PL11
PL10
PL9
PL8
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
Ñ reserved, read as 0, should be written with 0 for future compatibility
Figure 9-4 Timer Prescaler Load Register (TPLR)
9.3.2.1
TPLR Prescaler Preload Value (PL[20:0]) Bits 20-0
These 21 bits contain the prescaler preload value. This value is loaded into the prescaler
counter when the counter value reaches 0, or the counter switches state from disabled to
enabled.
If PL[20:0] = N, then the prescaler counts N + 1 source clock cycles before generating a
prescaler clock pulse. Therefore, the prescaler divide factor = (preload value) + 1.
The PL[20:0] bits are cleared by a hardware RESET signal or a software RESET
instruction.
9.3.2.2
TPLR Prescaler Source (PS[1:0]) Bits 22-21
The two PS bits control the source of the prescaler clock. Table 9-1 summarizes PS bit
functionality. The prescalerÕs use of a TIO signal is not affected by the TCSR settings of
the timer corresponding to the TIO signal being used.
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Triple Timer Module Programming Model
If the prescaler source clock is external, the prescaler counter is incremented by signal
transitions on the TIO signal. The external clock is internally synchronized to the internal
clock. The external clock frequency must be lower than the DSP56309 internal operating
frequency divided by 4 (CLK/4).
The PS[1:0] bits are cleared by a hardware RESET signal or a software RESET instruction.
Note:
To insure proper operation, change the PS[1:0] bits only when the prescaler
counter is disabled. Disable the prescaler counter by clearing the TE bit in the
TCSR of each of three timers.
Table 9-1 Prescaler Source Selection
PS1
PS0
Prescaler Clock Source
0
0
1
1
0
1
0
1
Internal CLK/2
TIO0
TIO1
TIO2
9.3.2.3
TPLR Reserved Bit 23
This reserved bit is read as 0 and should be written with 0 for future compatibility.
9.3.3
Timer Prescaler Count Register (TPCR)
The TPCR is a 24-bit, read-only register that reflects the current value in the prescaler
counter. The register bits are shown in Figure 9-5.
23
22
21
20
19
18
17
16
15
14
13
12
PC20 PC19 PC18 PC17 PC16 PC15 PC14 PC13 PC12
11
10
9
8
7
6
5
4
3
2
1
0
PC11 PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Ñ reserved, read as 0, should be written with 0 for future compatibility
Figure 9-5 Timer Prescaler Count Register (TPCR)
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Triple Timer Module Programming Model
9.3.3.1
TPCR Prescaler Counter Value (PC[20:0]) Bits 20-0
These 21 bits contain the current value of the prescaler counter.
9.3.3.2
TPCR Reserved Bits 23-21
These reserved bits are read as 0 and should be written with 0 for future compatibility.
9.3.4
Timer Control/Status Register (TCSR)
The TCSR is a 24-bit, read/write register controlling the timer and reflecting its status.
The register bits are shown in Figure 9-6. The control and status bits are documented in
Table 9-2 on page 9-10.
23
22
21
20
19
18
17
16
15
14
13
12
TCF
TOF
PCE
DO
DI
11
10
9
8
7
6
5
4
3
2
1
0
DIR
TRM
INV
TC3
TC2
TC1
TC0
TCIE TOIE
TE
Ñ reserved, read as 0, should be written with 0 for future compatibility
Figure 9-6 Timer Control/Status Register
9.3.4.1
Timer Enable (TE) Bit 0
The TE bit is used to enable or disable the timer. Setting TE enables the timer and clears
the timer counter. The counter starts counting according to the mode selected by the
timer control (TC[3:0]) bit values.
Clearing the TE bit disables the timer. The TE bit is cleared by a hardware RESET signal
or a software RESET instruction.
Note:
When all three timers are disabled and the signals are not in GPIO mode, all
three TIO signals are tri-stated. To prevent undesired spikes on the TIO
signals when switching from tri-state into active state, these signals should be
tied to the high or low signal state by the use of pull-up or pull-down resistors.
9.3.4.2
Timer Overflow Interrupt Enable (TOIE) Bit 1
The TOIE bit is used to enable the timer overflow interrupts. Setting TOIE enables
overflow interrupt generation. The timer counter can hold a maximum value of
$FFFFFF. When the counter value is at the maximum value and a new event causes the
counter to be incremented to $000000, the timer generates an overflow interrupt.
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Triple Timer Module
Triple Timer Module Programming Model
Clearing the TOIE bit disables overflow interrupt generation. The TOIE bit is cleared by
a hardware RESET signal or a software RESET instruction.
9.3.4.3
Timer Compare Interrupt Enable (TCIE) Bit 2
The TCIE bit is used to enable or disable the timer compare interrupts. Setting TCIE
enables the compare interrupts. In the timer, pulse width modulation (PWM), or
watchdog modes, a compare interrupt is generated after the counter value matches the
value of the TCPR. The counter starts counting up from the number loaded from the
TLR and if the TCPR value is N, an interrupt occurs after (N Ð M + 1) events, where M is
the value of TLR.
Clearing the TCIE bit disables the compare interrupts. The TCIE bit is cleared by a
hardware RESET signal or a software RESET instruction.
9.3.4.4
Timer Control (TC[3:0]) Bits 4-7
The four TC bits control the source of the timer clock, the behavior of the TIO signal, and
timer mode. Table 9-2 summarizes the TC bit functionality. There is a detailed
description of the timer operating modes in Section 9.4ÑTimer Operational Modes.
The TC bits are cleared by a hardware RESET signal or a software RESET instruction.
Note:
If the clock is external, the counter is incremented by the transitions on the
TIO signal. The external clock is internally synchronized to the internal clock,
and its frequency should be lower than the internal operating frequency
divided by 4 (CLK/4).
Note:
To insure proper operation, the TC[3:0] bits should be changed only when the
timer is disabled (i.e., when the TE bit in the TCSR has been cleared).
Table 9-2 Timer Control Bits
Bit Settings
TC3 TC2 TC1 TC0
Mode Characteristics
Mode Function
Mode
Number
TIO
Clock
1
0
0
0
0
0
Timer and GPIO
Internal
GPIO
0
0
0
0
0
0
0
1
1
1
0
1
1
2
3
Timer Pulse
Timer Toggle
Event Counter
Output Internal
Output Internal
Input
External
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Table 9-2 Timer Control Bits (Continued)
Bit Settings
Mode Characteristics
Mode Function
Mode
Number
TC3 TC2 TC1 TC0
TIO
Clock
0
0
1
1
0
0
0
1
4
5
Input Width
Measurement
Input
Internal
Input Period
Measurement
Input
Internal
0
0
1
1
1
1
0
1
6
7
Capture Event
Input
Internal
Pulse Width Modulation Output Internal
(PWM)
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
Reserved
Watchdog Pulse
Watchdog Toggle
Reserved
Ñ
Ñ
9
Output Internal
Output Internal
10
11
12
13
14
15
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Reserved
Reserved
Reserved
Reserved
Note 1: The GPIO function is enabled only if all of the TC[3:0] bits are 0.
9.3.4.5
Inverter (INV) Bit 8
The Inverter (INV) bit affects the polarity definition of the incoming signal on the TIO
signal when TIO is programmed as input. It also affects the polarity of the output pulse
generated on the TIO signal when TIO is programmed as output.
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The inverter bit operation is described below in Table 9-3.
Table 9-3 Inverter (INV) Bit Operation
TIO Programmed as Input
TIO Programmed as Output
Mode
0
INV = 0
INV = 1
INV = 0
INV = 1
GPIO signal on
the TIO signal
read directly
GPIO signal on
the TIO signal
inverted
Bit written to
GPIO put on TIO
signal directly
Bit written to GPIO
inverted and put
on TIO signal
1
2
3
Counter is
incremented on
the rising edge of the falling edge
the signal from
the TIO signal
Counter is
incremented on
Ñ
Ñ
of the signal from
the TIO signal
Counter is
incremented on
the rising edge of the falling edge
the signal from
the TIO signal
Counter is
incremented on
TCRx output put
on TIO signal
directly
TCRx output
inverted and put
on TIO signal
of the signal from
the TIO signal
Counter is
incremented on
Counter is
incremented on
Ñ
Ñ
the rising edge of the falling edge
the signal from
the TIO signal
of the signal from
the TIO signal
4
5
Width of the high Width of the low
Ñ
Ñ
Ñ
Ñ
input pulse is
measured
input pulse is
measured
Period is
measured
Period is
measured
between the
rising edges of
the input signal
between the
falling edges of
the input signal
6
Event is captured Event is captured
on the rising edge on the falling
of the signal from edge of the signal
Ñ
Ñ
the TIO signal
from the TIO
signal
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Table 9-3 Inverter (INV) Bit Operation (Continued)
TIO Programmed as Input
TIO Programmed as Output
Mode
7
INV = 0
INV = 1
INV = 0
INV = 1
Ñ
Ñ
Pulse generated
by the timer has
positive polarity
Pulse generated by
the timer has
negative polarity
9
Ñ
Ñ
Ñ
Ñ
Pulse generated
by the timer has
positive polarity
Pulse generated by
the timer has
negative polarity
10
Pulse generated
by the timer has
positive polarity.
Pulse generated by
the timer has
negative polarity
The INV bit is cleared by a hardware RESET signal or a software RESET instruction.
The INV bit affects both the timer and GPIO modes. To insure correct operation, this bit
should be changed only when one or both of the following conditions is true:
¥ The timer has been disabled by clearing the TE bit in the TCSR.
¥ The timer is in GPIO mode.
The INV bit does not affect the polarity of the prescaler source when the TIO is used as
input to the prescaler.
9.3.4.6
Timer Reload Mode (TRM) Bit 9
The TRM bit controls the counter preload operation.
In timer (0Ð3) and watchdog (9Ð10) modes, the counter is preloaded with the TLR value
after the TE bit is set and the first internal or external clock signal is received. If the TRM
bit is set, the counter is reloaded each time after it reaches the value contained by the
TCR. In PWM mode (7), the counter is reloaded each time counter overflow occurs. In
measurement (4Ð5) modes, if the TRM and the TE bits are set, the counter is preloaded
with the TLR value on each appropriate edge of the input signal.
If the TRM bit is cleared, the counter operates as a free running counter and is
incremented on each incoming event. The TRM bit is cleared by a hardware RESET
signal or a software RESET instruction.
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9.3.4.7
Direction (DIR) Bit 11
The DIR bit determines the behavior of the TIO signal when it is used as a GPIO signal.
When the DIR bit is set, the TIO signal is an output; when the DIR bit is cleared, the TIO
signal is an input. The TIO signal can be used as a GPIO signal only when all of the
TC[3:0] bits are cleared. If any of the TC[3:0] bits are set, then the GPIO function is
disabled and the DIR bit has no effect.
The DIR bit is cleared by a hardware RESET signal or a software RESET instruction.
9.3.4.8
Data Input (DI) Bit 12
The DI bit reflects the value of the TIO signal. If the INV bit is set, the value of the TIO
signal is inverted before it is written to the DI bit. If the INV bit is cleared, the value of
the TIO signal is written directly to the DI bit.
DI is cleared by a hardware RESET signal or a software RESET instruction.
9.3.4.9
Data Output (DO) Bit 13
The DO bit is the source of the TIO value when it is a data output signal. The TIO signal
is data output when GPIO mode is enabled and DIR is set. A value written to the DO bit
is written to the TIO signal. If the INV bit is set, the value of the DO bit is inverted when
written to the TIO signal. When the INV bit is cleared, the value of the DO bit is written
directly to the TIO signal. When GPIO mode is disabled, writing the DO bit has no effect.
The DO bit is cleared by a hardware RESET signal or a software RESET instruction.
9.3.4.10
Prescaler Clock Enable (PCE) Bit 15
The PCE bit is used to select the prescaler clock as the timer source clock. When the PCE
bit is cleared, the timer uses either an internal (CLK/2) signal or an external (TIO) signal
as its source clock. When the PCE bit is set, the prescaler output is used as the timer
source clock for the counter regardless of the timer operating mode. To insure proper
operation, the PCE bit should be changed only when the timer is disabled (when the TE
bit is cleared). Which source clock is used for the prescaler is determined by the PS[1:0]
bits of the TPLR. A timer can be clocked by a prescaler clock that is derived from the TIO
of another timer.
9.3.4.11
Timer Overflow Flag (TOF) Bit 20
The TOF bit is set to indicate that counter overflow has occurred. This bit is cleared by
writing a 1 to the TOF bit. Writing a 0 to the TOF bit has no effect. The bit is also cleared
when the timer overflow interrupt is serviced.
The TOF bit is cleared by a hardware RESET signal, a software RESET instruction, the
STOP instruction, or by clearing the TE bit to disable the timer.
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9.3.4.12
Timer Compare Flag (TCF) Bit 21
The TCF bit is set to indicate that the event count is complete. In the timer, PWM, and
watchdog modes, the TCF bit is set when (N Ð M + 1) events have been counted. (N is the
value in the compare register and M is the TLR value.) In measurement modes, the TCF
bit is set when the measurement is completed.
Writing a 1 into the TCF bit clears this bit. Writing a 0 into the TCF bit has no effect. The
bit is also cleared when the timer compare interrupt is serviced.
The TCF bit is cleared by a hardware RESET signal, a software RESET instruction, the
STOP instruction, or by clearing the TE bit to disable the timer.
Note:
The TOF and TCF bits are cleared by writing a 1 to the specific bit. In order to
insure that only the desired bit is cleared, do not use the BSET command. The
proper way to clear these bits is to write (using a MOVEP instruction) a 1 to
the flag to be cleared and a 0 to the other flag.
9.3.4.13
TCSR Reserved Bits 3, 10, 14, 16-19, 22, 23
These reserved bits are read as 0 and should be written with 0 for future compatibility.
9.3.5
Timer Load Register (TLR)
The TLR is a 24-bit, write-only register. In all modes, the counter is preloaded with the
TLR value after the TE bit in the TCSR is set and a first event occurs.
¥ In timer modes, if the timer reload mode (TRM) bit in the TCSR is set, the counter
is reloaded each time after it has reached the value contained by the timer
compare register (TCPR) and the new event occurs.
¥ In measurement modes, if the TRM bit in the TCSR is set and the TE bit in the
TCSR is set, the counter is reloaded with the value in the TLR on each appropriate
edge of the input signal.
¥ In PWM modes, if the TRM bit in the TCSR is set, the counter is reloaded each
time after it has overflowed and the new event occurs.
¥ In watchdog modes, if the TRM bit in the TCSR is set, the counter is reloaded each
time after it has reached the value contained by the TCPR and the new event
occurs. In this mode, the counter is also reloaded whenever the TLR is written
with a new value while the TE bit in the TCSR is set.
¥ In all modes, if the TRM bit in the TCSR is cleared (TRM = 0), the counter operates
as a free-running counter.
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9.3.6
Timer Compare Register (TCPR)
The TCPR is a 24-bit, read/write register that contains the value to be compared to the
counter value. These two values are compared every timer clock after the TE bit in the
TCSR is set. When the values match, the timer compare flag (TCF) bit is set and an
interrupt is generated if interrupts are enabled (if the timer compare interrupt enable
(TCIE) bit in the TCSR is set). The TCPR is ignored in measurement modes.
9.3.7
Timer Count Register (TCR)
The Timer Count Register (TCR) is a 24-bit, read-only register. In timer and watchdog
modes, the counterÕs contents can be read at any time by reading the TCR register. In
Measurement modes, the TCR is loaded with the current value of the counter on the
appropriate edge of the input signal, and its value can be read to determine the width,
period, or delay of the leading edge of the input signal. When the timer is in
measurement modes, the TIO signal is used for the input signal.
9.4
TIMER OPERATIONAL MODES
Each timer has these operational modes to meet a variety of system requirements:
¥ Timer
Ð GPIO, mode 0: Internal timer interrupt generated by the internal clock
Ð Pulse, mode 1: External timer pulse generated by the internal clock
Ð Toggle, mode 2: Output timing signal toggled by the internal clock
Ð Event counter, mode 3: Internal timer interrupt generated by an external clock
¥ Measurement
Ð Input width, mode 4: Input pulse width measurement
Ð Input pulse, mode 5: Input signal period measurement
Ð Capture, mode 6: Capture external signal
¥ PWM, mode 7: Pulse width modulation
¥ Watchdog
Ð Pulse, mode 9: Output pulse, internal clock
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Ð Toggle, mode 10: Output toggle, internal clock
These modes are described in detail below. Timer modes are selected by setting the
TC[3:0] bits in the TCSR. Table 9-2 on page 9-10 shows how the different timer modes
are selected by setting the bits in the TCSR. The table also shows the TIO signal direction
and the clock source for each timer mode. That table summarizes these modes, and the
following paragraphs describe these modes in detail.
Note:
To insure proper operation, the TC[3:0] bits should be changed only when the
timer is disabled (i.e., when the TE bit in the TCSR is cleared).
9.4.1
Timing Modes
The following timing modes are provided:
¥ Timer GPIO
¥ Timer pulse
¥ Timer toggle
¥ Event counter
9.4.1.1
Timer GPIO (Mode 0)
Bit Settings
TC3 TC2 TC1 TC0
Mode Characteristics
TIO
Clock
#
Function
Name
0
0
0
0
GPIO
Internal
0
Timer
GPIO
In this mode, the timer generates an internal interrupt when a counter value is reached
(if the timer compare interrupt is enabled).
Set the TE bit to clear the counter and enable the timer. Load the value the timer is to
count into the TCPR. The counter is loaded with the TLR value when the first timer clock
signal is received. The timer clock can be taken from either the DSP56309 clock divided
by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal
increments the counter.
When the counter equals the TCPR value, the TCF bit in TCSR is set, and a compare
interrupt is generated if the TCIE bit is set. If the TRM bit in the TCSR is set, the counter
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is reloaded with the TLR value at the next timer clock and the count is resumed. If the
TRM bit is cleared, the counter continues to be incremented on each timer clock signal.
This process is repeated until the timer is disabled (i.e., TE is cleared).
If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is
generated.
The counter contents can be read at any time by reading the TCR.
9.4.1.2
Timer Pulse (Mode 1)
Bit Settings
TC3 TC2 TC1 TC0
Mode Characteristics
TIO
Clock
#
Function
Name
0
0
0
1
Output Internal
1
Timer
Pulse
In this mode, the timer generates an external pulse on its TIO signal when the timer
count reaches a pre-set value.
Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TCPR. The counter is loaded with the TLR value when the first
timer clock signal is received. The TIO signal is loaded with the value of the INV bit. The
timer clock signal can be taken from either the DSP56309 clock divided by two (CLK/2)
or from the prescaler clock output. Each subsequent clock signal increments the counter.
When the counter matches the TCPR value, the TCF bit in TCSR is set and a compare
interrupt is generated if the TCIE bit is set. The polarity of the TIO signal is inverted for
one timer clock period.
If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and
the count is resumed. If the TRM bit is cleared, the counter continues to be incremented
on each timer clock.
This process is repeated until the TE bit is cleared (disabling the timer). The counter
contents can be read at any time by reading TCR.
The value of the TLR sets the delay between starting the timer and the generation of the
output pulse. To generate successive output pulses with a delay of X clocks between
signals, the TLR value should be set to X/2 and the TRM bit should be set.
This process is repeated until the timer is disabled (i.e., TE is cleared).
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If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is
generated.
The counter contents can be read at any time by reading the TCR.
9.4.1.3
Timer Toggle (Mode 2)
Bit Settings
TC3 TC2 TC1 TC0
Mode Characteristics
TIO
Clock
#
Function
Name
0
0
1
0
Output Internal
0
Timer
Toggle
In this mode, the timer periodically toggles the polarity of the TIO signal.
Set the TE bit in the TCR to clear the counter and enable the timer. The value to which
the timer is to count is loaded into the TPCR. The counter is loaded with the TLR value
when the first timer clock signal is received. The TIO signal is loaded with the value of
the INV bit. The timer clock signal can be taken from either the DSP56309 clock divided
by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal
increments the counter.
When the counter value matches the value in the TCPR, the polarity of the TIO output
signal is inverted. The TCF bit in the TCSR is set and a compare interrupt is generated if
the TCIE bit is set.
If the TRM bit is set, the counter is loaded with the value of the TLR when the next timer
clock is received, and the count is resumed. If the TRM bit is cleared, the counter
continues to be incremented on each timer clock.
This process is repeated until the TE bit is cleared, disabling the timer. The counter
contents can be read at any time by reading the TCR.
The TLR value in the TCPR sets the delay between starting the timer and toggling the
TIO signal. To generate output signals with a delay of X clock cycles between toggles,
the TLR value should be set to X/2, and the TRM bit should be set.
This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter
overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated.
The counter contents can be read at any time by reading the TCR.
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9.4.1.4
Timer Event Counter (Mode 3)
Bit Settings
TC3 TC2 TC1 TC0
Mode Characteristics
TIO
Clock
#
Function
Name
0
0
1
1
Input
External
3
Timer
Event Counter
In this mode, the timer counts external events and issues an interrupt when a preset
number of events is counted.
Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TPCR. The counter is loaded with the TLR value when the first
timer clock signal is received. The timer clock signal can be taken from either the TIO
input signal or the prescaler clock output. Each subsequent clock signal increments the
counter. If an external clock is used, it must be internally synchronized to the internal
clock, and its frequency must be less than the DSP56309 internal operating frequency
divided by 4.
The value of the INV bit in the TCSR determines whether low-to-high (0 to 1) transitions
or high-to-low (1 to 0) transitions increment the counter. If the INV bit is set, high-to-low
transitions increment the counter. If the INV bit is cleared, low-to-high transitions
increment the counter.
When the counter matches the value contained in the TCPR, the TCF bit in the TCSR is
set, and a compare interrupt is generated if the TCIE bit is set. If the TRM bit is set, the
counter is loaded with the value of the TLR when the next timer clock is received, and
the count is resumed. If the TRM bit is cleared, the counter continues to be incremented
on each timer clock.
This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter
overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated.
The counter contents can be read at any time by reading the TCR.
9.4.2
Signal Measurement Modes
The following Signal Measurement modes are provided:
¥ Measurement input width
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¥ Measurement input period
¥ Measurement capture
9.4.2.1
Measurement Accuracy
The external signal is synchronized with the internal clock used to increment the
counter. This synchronization process can cause the number of clocks measured for the
selected signal value to vary from the actual signal value by plus or minus one counter
clock cycle.
9.4.2.2
Measurement Input Width (Mode 4)
Bit Settings
TC3 TC2 TC1 TC0
Mode Characteristics
Name Function
Input Width Measurement Input Internal
Mode
TIO
Clock
0
1
0
0
4
In this mode, the timer counts the number of clocks that occur between opposite edges of
an input signal.
Set the TE bit to clear the counter and enable the timer. Load the timerÕs count value into
the TLR. After the first appropriate transition (as determined by the INV bit) occurs on
the TIO input signal, the counter is loaded with the TLR value on the first timer clock
signal received either from the DSP56309 clock divided by two (CLK/2) or from the
prescaler clock input. Each subsequent clock signal increments the counter.
If the INV bit is set, the timer starts on the first high-to-low (1 to 0) signal transition on
the TIO signal. If the INV bit is cleared, the timer starts on the first low-to-high
(0 to 1) transition on the TIO signal.
When the first transition opposite in polarity to the INV bit setting occurs on the TIO
signal, the counter stops. The TCF bit in the TCSR is set and a compare interrupt is
generated if the TCIE bit is set. The value of the counter (which measures the width of
the TIO pulse) is loaded into the TCR. The TCR can be read to determine the external
signal pulse width.
If the TRM bit is set, the counter is loaded with the TLR value on the first timer clock
received following the next valid transition occurring on the TIO input signal and the
count is resumed. If the TRM bit is cleared, the counter continues to be incremented on
each timer clock.
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This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter
overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The
counter contents can be read at any time by reading the TCR.
9.4.2.3
Measurement Input Period (Mode 5)
Bit Settings
TC3 TC2 TC1 TC0 Mode
Mode Characteristics
Name
Function
TIO
Clock
0
1
0
1
5
Input Period
Measurement
Input Internal
In this mode, the timer counts the period between the reception of signal edges of the
same polarity across the TIO signal.
Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TLR. The value of the INV bit determines whether the period is
measured between consecutive low-to-high (0 to 1) transitions of TIO or between
consecutive high-to-low (1 to 0) transitions of TIO. If INV is set, high-to-low signal
transitions are selected. If INV is cleared, low-to-high signal transitions are selected.
After the first appropriate transition occurs on the TIO input signal, the counter is
loaded with the TLR value on the first timer clock signal received from either the
DSP56309 clock divided by two (CLK/2) or the prescaler clock output. Each subsequent
clock signal increments the counter.
On the next signal transition of the same polarity that occurs on TIO, the TCF bit in the
TCSR is set and a compare interrupt is generated if the TCIE bit is set. The contents of the
counter are loaded into the TCR. The TCR then contains the value of the time that
elapsed between the two signal transitions on the TIO signal.
After the second signal transition, if the TRM bit is set, the TE bit is set to clear the
counter and enable the timer. The counter is loaded with the TLR value on the first timer
clock signal. Each subsequent clock signal increments the counter.
After the second signal transition, if the TRM bit is set, the TE bit is set to clear if the TRM
bit is cleared, the counter continues to be incremented on each timer clock. This process
is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the
TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents
can be read at any time by reading the TCR.
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9.4.2.4
Measurement Capture (Mode 6)
Bit Settings
TC3 TC2 TC1 TC0 Mode
Mode Characteristics
Function
Name
Capture
TIO
Clock
0
1
1
0
6
Measurement
Input
Internal
In this mode, the timer counts the number of clocks that elapse between starting the
timer and receiving an external signal.
Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TLR. When the first timer clock signal is received, the counter is
loaded with the TLR value. The timer clock signal can be taken from either the DSP56309
clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock
signal increments the counter.
At the first appropriate transition of the external clock detected on the TIO signal, the
TCF bit in the TCSR is set and, if the TCIE bit is set, a compare interrupt is generated, the
counter halts, and the contents of the counter are loaded into the TCR. The value of the
TCR represents the delay between the setting of the TE bit and the detection of the first
clock edge signal on the TIO signal.
The value of the INV bit determines whether a high-to-low (1 to 0) or low-to-high (0 to 1)
transition of the external clock signals the end of the timing period. If the INV bit is set, a
high-to-low transition signals the end of the timing period. If INV is cleared, a
low-to-high transition signals the end of the timing period.
If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is
generated. The counter contents can be read at any time by reading the TCR.
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Triple Timer Module
Timer Operational Modes
9.4.3
Pulse Width Modulation (PWM, Mode 7)
Bit Settings
TC3 TC2 TC1 TC0 Mode
Mode Characteristics
Name
Function
TIO
Clock
0
1
1
1
7
Pulse Width
Modulation
PWM
Output Internal
In this mode, the timer generates periodic pulses of a preset width.
Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TPCR. When first timer clock is received from either the
DSP56309 internal clock divided by two (CLK/2) or the prescaler clock output, the
counter is loaded with the TLR value. Each subsequent timer clock increments the
counter.
When the counter equals the value in the TCPR, the TIO output signal is toggled and the
TCF bit in the TCSR is set. The contents of the counter are placed into the TCR. If the
TCIE bit is set, a compare interrupt is generated. The counter continues to be
incremented on each timer clock.
If counter overflow has occurred, the TIO output signal is toggled, the TOF bit in TCSR
is set, and an overflow interrupt is generated if the TOIE bit is set. If the TRM bit is set,
the counter is loaded with the TLR value on the next timer clock and the count is
resumed. If the TRM bit is cleared, the counter continues to be incremented on each
timer clock.
This process is repeated until the timer is disabled by clearing the TE bit.
TIO signal polarity is determined by the value of the INV bit. When the counter is
started by setting the TE bit, the TIO signal assumes the value of the INV bit. On each
subsequent toggling of the TIO signal, the polarity of the TIO signal is reversed. For
example, if the INV bit is set, the TIO signal generates the following signal: 1010. If the
INV bit is cleared, the TIO signal generates the following signal: 0101.
The counter contents can be read at any time by reading the TCR.
The value of the TLR determines the output period ($FFFFFF - TLR + 1). The timer
counter increments the initial TLR value and toggles the TIO signal when the counter
value exceeds $FFFFFF.
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Triple Timer Module
Timer Operational Modes
The duty cycle of the TIO signal is determined by the value in the TCPR. When the value
in the TLR is incremented to a value equal to the value in the TCPR, the TIO signal is
toggled. The duty cycle is equal to ($FFFFFF Ð TCPR) divided by ($FFFFFF - TLR + 1).
For a 50% duty cycle, the value of TCPR is equal to ($FFFFFF + TLR + 1) / 2.
Note:
The value in TCPR must be greater than the value in TLR.
9.4.4
Watchdog Modes
The following watchdog timer modes are provided:
¥ Watchdog pulse
¥ Watchdog toggle
9.4.4.1
Watchdog Pulse (Mode 9)
Bit Settings
TC3 TC2 TC1 TC0 Mode
Mode Characteristics
Name
Function
TIO
Clock
1
0
0
1
9
Pulse
Watchdog
Output Internal
In this mode, the timer generates an external signal at a preset rate. The signal period is
equal to the period of one timer clock.
Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TCPR. The counter is loaded with the TLR value on the first
timer clock received from either the DSP56309 internal clock divided by two (CLK/2) or
the prescaler clock output. Each subsequent timer clock increments the counter.
When the counter matches the value of the TCPR, the TCF bit in the TCSR is set and a
compare interrupt is generated if the TCIE bit is also set.
If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and
the count is resumed. If the TRM bit is cleared, the counter continues to be incremented
on each subsequent timer clock.
This process is repeated until the timer is disabled (i.e., TE is cleared).
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Triple Timer Module
Timer Operational Modes
If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is
generated. At the same time, a pulse is output on the TIO signal with a pulse width equal
to the timer clock period. The pulse polarity is determined by the value of the INV bit. If
the INV bit is set, the pulse polarity is high (logical 1). If the INV bit is cleared, the pulse
polarity is low (logical 0).
The counter contents can be read at any time by reading the TCR. The counter is
reloaded whenever the TLR is written with a new value while the TE bit is set.
Note:
In this mode, internal logic preserves the TIO value and direction for an
additional 2.5 internal clock cycles after a DSP56309 hardware RESET signal is
asserted. This insures that a valid RESET signal is generated when the TIO
signal is used to reset the DSP56309.
9.4.4.2
Watchdog Toggle (Mode 10)
Bit Settings
TC3 TC2 TC1 TC0 Mode
10
Mode Characteristics
NAME
Toggle
Function
TIO
Clock
1
0
1
0
Watchdog
Output Internal
In this mode, the timer toggles an external signal after preset period.
Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TPCR. The counter is loaded with the TLR value on the first
timer clock received from either the DSP56309 internal clock divided by two (CLK/2) or
the prescaler clock output. Each subsequent timer clock increments the counter. The TIO
signal is set to the value of the INV bit.
When the counter equals the value in the TCPR, the TCF bit in the TCSR is set, and a
compare interrupt is generated if the TCIE bit is also set. If the TRM bit is set, the counter
is loaded with the TLR value on the next timer clock and the count is resumed. If the
TRM bit is cleared, the counter continues to be incremented on each subsequent timer
clock.
When counter overflow has occurred, the polarity of the TIO output signal is inverted,
the TOF bit in the TCSR is set, and an overflow interrupt is generated if the TOIE bit is
also set. The TIO polarity is determined by the INV bit.
The counter is reloaded whenever the TLR is written with a new value while the TE bit is
set. This process is repeated until the timer is disabled by clearing the TE bit. The counter
contents can be read at any time by reading the TCR register.
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Timer Operational Modes
Note:
In this mode, internal logic preserves the TIO value and direction for an
additional 2.5 internal clock cycles after a DSP56309 hardware RESET signal is
asserted. This insures that a valid reset signal is generated when the TIO signal
is used to reset the DSP56309.
9.4.5
Reserved Modes
Modes 8, 11, 12, 13, 14, and 15 are reserved.
9.4.6
Special Cases
The following special cases apply during wait and stop state.
9.4.6.1 Timer Behavior during Wait
Timer clocks are active during the execution of the WAIT instruction and timer activity
is undisturbed. If a timer interrupt is generated, the DSP56309 leaves the wait state and
services the interrupt.
9.4.6.2
Timer Behavior during Stop
During the execution of the STOP instruction, the timer clocks are disabled, timer
activity is stopped, and the TIO signals are disconnected. Any external changes that
happen to the TIO signals are ignored when the DSP56309 is in the stop state. To insure
correct operation, the timers should be disabled before the DSP56309 is placed into the
stop state.
9.4.7
DMA Trigger
Each timer can also be used to trigger DMA transfers. For this to occur, a DMA channel
must be programmed to be triggered by a timer event. The timer issues a DMA trigger
on every event in all modes of operation. The DMA channel does not have the capability
to save multiple DMA triggers generated by the timer. To insure that all DMA triggers
are serviced, the user must provide for the preceding DMA trigger to be serviced before
the next trigger is received by the DMA channel.
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SECTION 10
ON-CHIP EMULATION MODULE
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On-Chip Emulation Module
10.1
10.2
10.4
10.5
10.6
10.7
10.8
10.9
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
ONCE MODULE SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
ONCE CONTROLLER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
ONCE MEMORY BREAKPOINT LOGIC. . . . . . . . . . . . . . . 10-9
ONCE TRACE LOGIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
METHODS OF ENTERING DEBUG MODE . . . . . . . . . . . 10-16
PIPELINE INFORMATION AND OGDB REGISTER. . . . . 10-18
DEBUGGING RESOURCES. . . . . . . . . . . . . . . . . . . . . . . 10-20
10.10 SERIAL PROTOCOL DESCRIPTION . . . . . . . . . . . . . . . . 10-22
10.11 TARGET SITE DEBUG SYSTEM REQUIREMENTS . . . . 10-23
10.12 ONCE MODULE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . 10-23
10.13 JTAG PORT/ONCE MODULE INTERACTION . . . . . . . . . 10-29
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On-Chip Emulation Module
Introduction
10.1 INTRODUCTION
The DSP56300 core On-Chip Emulation (OnCEª) module provides a means of
interacting with the DSP56300 core and its peripherals nonintrusively so that a user can
examine registers, memory, or on-chip peripherals, thus facilitating hardware and
software development on the DSP56300 core processor. To achieve this, special circuits
and dedicated signals on the DSP56300 core are defined to avoid sacrificing any
user-accessible on-chip resource. The OnCE module resources can be accessed only after
executing the JTAG instruction ENABLE_ONCE. These resources are accessible even
when the chip is operating in normal mode. See Section 11ÑJTAG Port for a description
of the JTAG functionality and its relation to the OnCE module. Figure 10-1 shows the
block diagram of the OnCE module.
PDB PIL GDB
Pipeline
Trace Logic
Information
TCK
Control Bus
TDI
OnCE
Controller
XAB
TDO
YAB
PAB
TRST
DE
Breakpoint
Logic
Tags
Buffer
Trace
Buffer
AA0702
Figure 10-1 OnCE Module Block Diagram
10.2 OnCE MODULE SIGNALS
The OnCE module controller functionality is accessed through the JTAG port. There are
no dedicated OnCE module signals for the clock, data in, or data out. The JTAG signals
TCK, TDI, and TDO are used to shift in and out data and instructions. See
Section 11.2ÑJTAG Signals on page 11-4 for the description of the JTAG signals. To
facilitate emulation-specific functions, one additional signal, called DE, is provided on
the DSP56309.
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Debug Event (DE)
10.3 DEBUG EVENT (DE)
The bidirectional open drain debug event signal (DE) provides a fast means of entering
debug mode from an external command controller (when input), and a fast means of
acknowledging the entering of debug mode to an external command controller (when
output). The assertion of this signal by a command controller causes the DSP56300 core
to finish the current instruction being executed, save the instruction pipeline
information, enter debug mode, and wait for commands to be entered from the TDI line.
If the DE signal is used to enter debug mode, then it must be deasserted after the OnCE
port responds with an acknowledge and before sending the first OnCE command. The
assertion of this signal by the DSP56300 core indicates that the DSP has entered debug
mode and is waiting for commands to be entered from the TDI line. The DE signal also
facilitates multiple processor connections, as shown in Figure 10-2.
DE
TDI
TDO
TDI
TDO
TDI
TDO
TDO
TDI
TMS
TCK
TRST
AA0703
Figure 10-2 OnCE Module Multiprocessor Configuration
In this way, the user can stop all the devices in the system when one of the devices enters
debug mode. The user can also stop all the devices synchronously by asserting the DE
line.
10.4 OnCE CONTROLLER
The OnCE controller contains the following blocks: OnCE Command Register (OCR),
OnCE Decoder, and the status/control register. Figure 10-3 illustrates a block diagram
of the OnCE controller.
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OnCE Controller
TDI
TCK
OnCE Command Register
ISBKPT
Update
ISTRACE
ISDR
OnCE Decoder
ISDEBUG
ISSWDBG
Status and Control
Register
TDO
Register Read Register Write
Mode Select
AA0704
Figure 10-3 OnCE Controller Block Diagram
10.4.1
OnCE Command Register (OCR)
The OCR is an 8-bit shift register that receives its serial data from the TDI signal. It holds
the 8-bit commands to be used as input for the OnCE decoder. The OCR is shown in
Figure 10-4.
OCR
OnCE Command
Register
7
6
5
4
3
2
1
0
R/W GO EX RS4 RS3 RS2 RS1 RS0
Reset = $00
Write Only
AA0106
Figure 10-4 OnCE Command Register
Register Select (RS4ÐRS0) Bits 0Ð4
10.4.1.1
The register select bits define which register is source/destination for the read/write
operation. See Table 10-4 for the OnCE register select encoding.
10.4.1.2
Exit Command (EX) Bit 5
If the EX bit is set, leave debug mode and resume normal operation. The EXIT command
is executed only if the GO command is issued, and the operation is write to OPDBR or
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OnCE Controller
read/write to ÒNo Register SelectedÓ. Otherwise the EX bit is ignored. Table 10-1 shows
the definition of the EX bit.
Table 10-1 EX Bit Definition
EX
Action
0
1
Remain in Debug mode
Leave Debug mode
10.4.1.3
GO Command (GO) Bit 6
If the GO bit is set, execute the instruction that resides in the PIL register. To execute the
instruction, the core leaves debug mode. The core returns to debug mode immediately
after executing the instruction if the EX bit is cleared. The core goes on to normal
operation if the EX bit is set. The GO command is executed only if the operation is write
to OPDBR or read/write to ÒNo Register SelectedÓ. Otherwise the GO bit is ignored.
Table 10-2 shows the definition of the GO bit.
Table 10-2 GO Bit Definition
GO
Action
0
1
InactiveÑno action taken
Execute instruction in PIL
10.4.1.4
Read/Write Command (R/W) Bit 7
The R/W bit, as shown in Table 10-3, specifies the direction of data transfer. Table 10-4
shows how to encode OnCE register selections.
Table 10-3 R/W Bit Definition
R/W
Action
0
Write the data associated with the command into the register specified by
RS4ÐRS0.
1
Read the data contained in the register specified by RS4ÐRS0.
Table 10-4 OnCE Register Select Encoding
RS[4:0]
Register Selected
00000
OnCE Status and Control Register (OSCR)
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Table 10-4 OnCE Register Select Encoding (Continued)
RS[4:0]
Register Selected
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
101xx
11xx0
11x0x
110xx
11111
Memory Breakpoint Counter (OMBC)
Breakpoint Control Register (OBCR)
Reserved Address
Reserved Address
Memory Limit Register 0 (OMLR0)
Memory Limit Register 1 (OMLR1)
Reserved Address
Reserved Address
GDB Register (OGDBR)
PDB Register (OPDBR)
PIL Register (OPILR)
PDB GO-TO Register (for GO TO command)
Trace Counter (OTC)
Reserved Address
PAB Register for Fetch (OPABFR)
PAB Register for Decode (OPABDR)
PAB Register for Execute (OPABEX)
Trace Buffer and Increment Pointer
Reserved Address
Reserved Address
Reserved Address
Reserved Address
Reserved Address
No Register Selected
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10.4.2
OnCE Decoder (ODEC)
The ODEC supervises the entire OnCE module activity. It receives as input the 8-bit
command from the OCR, a signal from JTAG Controller (indicating that 8 or 24 bits have
been received and update of the selected data register must be performed), and a signal
indicating that the core was halted. The ODEC generates all the strobes required for
reading and writing the selected OnCE registers.
10.4.3
OnCE Status and Control Register (OSCR)
The OSCR is a 24-bit register used to enable trace mode and to indicate the cause of
entering debug mode. The control bits are read/write while the status bits are read-only.
The OSCR bits are cleared by a hardware RESET signal. The OSCR is shown in
Figure 10-5.
23
9
8
7
6
5
4
3
2
1
0
OnCE Status and
Control Register
Read/Write
OS1 OS0
TO MBO SWO IME TME
AA0705
Indicates reserved bits, written as 0 for future compatibility
Figure 10-5 OnCE Status and Control Register (OSCR)
10.4.3.1
Trace Mode Enable (TME) Bit 0
The TME control bit, when set, enables trace mode.
10.4.3.2 Interrupt Mode Enable (IME) Bit 1
The IME control bit, when set, causes the chip to execute a vectored interrupt to the
address VBA:$06 instead of entering debug mode.
10.4.3.3
Software Debug Occurrence (SWO) Bit 2
The SWO bit is a read-only status bit that is set when debug mode is entered because of
the execution of the DEBUG or DEBUGcc instruction with condition true. This bit is
cleared when leaving debug mode.
10.4.3.4
Memory Breakpoint Occurrence (MBO) Bit 3
The MBO bit is a read-only status bit that is set when debug mode is entered because a
memory breakpoint has been encountered. This bit is cleared when leaving debug mode.
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10.4.3.5
Trace Occurrence (TO) Bit 4
The TO bit is a read-only status bit that is set when debug mode is entered when the
trace counter is zero while trace mode is enabled. This bit is cleared when leaving debug
mode.
10.4.3.6
Reserved OCSR Bit 5
Bit 5 is reserved for future use. It is read as 0 and should be written with 0 for future
compatibility.
10.4.3.7
Core Status (OS0, OS1) Bits 6-7
The OS0, OS1 bits are read-only status bits that provide core status information. By
examining the status bits, the user can determine whether the chip has entered debug
mode. Examining SWO, MBO, and TO identifies the cause of entering debug mode. The
user can also examine these bits and determine the cause why the chip has not entered
debug mode after debug event (DE) assertion or as a result of the execution of the JTAG
debug request instruction (core waiting for the bus, STOP or WAIT instruction, etc.).
These bits are also reflected in the JTAG instruction shift register, which allows the
polling of the core status information at the JTAG level. This is useful when the
DSP56300 core executes the STOP instruction (and therefore there are no clocks) to allow
the reading of OSCR. See Table 10-5 for the definition of the OS0ÐOS1 bits.
Table 10-5 Core Status Bits Description
OS1
OS0
Description
0
0
1
1
0
1
0
1
DSP56300 core is executing instructions
DSP56300 core is in wait or stop
DSP56300 core is waiting for bus
DSP56300 core is in debug mode
10.4.3.8
Reserved Bits 8-23
Bits 8Ð23 are reserved for future use. They are read as 0 and should be written with 0 for
future compatibility.
10.5 OnCE MEMORY BREAKPOINT LOGIC
Memory breakpoints can be set on program memory or data memory locations. In
addition, the breakpoint does not have to be in a specific memory address, but within an
approximate address range where the program may be executing. This significantly
increases the programmerÕs ability to monitor what the program is doing in real time.
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OnCE Memory Breakpoint Logic
The breakpoint logic, described in Figure 10-6, contains a latch for the addresses, which
are registers that store the upper and lower address limit, address comparators, and a
breakpoint counter.
TCK
TDO TDI
PAB
XAB
YAB
Memory Address Latch
Memory Bus Select
TDI TCK TDO
N,V
N,V
DEC
Address Comparator 0
Memory Limit Register 0
Address Comparator 1
Memory Limit Register 1
Breakpoint Counter
Count = 0
Breakpoint Control
Memory
Breakpoint
Selection
Breakpoint
Occurred
ISBKPT
AA0706
Figure 10-6 OnCE Memory Breakpoint Logic 0
Address comparators are useful in determining where a program may be getting lost or
when data is being written where it should not be written. They are also useful in halting
a program at a specific point to examine/change registers or memory. Using address
comparators to set breakpoints enables the user to set breakpoints in RAM or ROM and
while in any operating mode. Memory accesses are monitored according to the contents
of the OBCR as specified in Section 10.5.6ÑOnCE Breakpoint Control Register
(OBCR).
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OnCE Memory Breakpoint Logic
10.5.1
OnCE Memory Address Latch (OMAL)
The OMAL is a 16-bit register that latches the PAB, XAB or YAB on every instruction
cycle according to the MBS1ÐMBS0 bits in OBCR.
10.5.2
OnCE Memory Limit Register 0 (OMLR0)
The OMLR0 is a 16-bit register that stores the memory breakpoint limit. OMLR0 can be
read or written through the JTAG port. Before enabling breakpoints, OMLR0 must be
loaded by the external command controller.
10.5.3
OnCE Memory Address Comparator 0 (OMAC0)
The OMAC0 compares the current memory address (stored in OMAL0) with the
OMLR0 contents.
10.5.4
OnCE Memory Limit Register 1 (OMLR1)
The OMLR1 is a 16-bit register that stores the memory breakpoint limit. OMLR1 can be
read or written through the JTAG port. Before enabling breakpoints, OMLR1 must be
loaded by the external command controller.
10.5.5
OnCE Memory Address Comparator 1 (OMAC1)
The OMAC1 compares the current memory address (stored in OMAL0) with the
OMLR1 contents.
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OnCE Memory Breakpoint Logic
10.5.6
OnCE Breakpoint Control Register (OBCR)
The OBCR is a 16-bit register used to define the memory breakpoint events. OBCR can
be read or written through the JTAG port. All the bits of the OBCR are cleared by a
hardware RESET signal. The OBCR appears in Figure 10-7.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OnCE Breakpoint
Control Register
Reset = $0010
Read/Write
*
*
*
*
BT1 BT0 CC CC RW RW CC CC RW RW MB MB
11
10
11
10
01
00
01
00
S1
S0
AA0707
* Indicates reserved bits, written as 0 for future compatibility
Figure 10-7 OnCE Breakpoint Control Register (OBCR)
10.5.6.1
Memory Breakpoint Select (MBS0ÐMBS1)
Bits 0Ð1
The MBS0ÐMBS1 bits enable memory breakpoints 0 and 1, allowing them to occur when
a memory access is performed on P, X, or Y space. See Table 10-6 for the definition of the
MBS0ÐMBS1 bits.
Table 10-6 Memory Breakpoint 0 and 1 Select Table
MBS1 MBS0
Description
0
0
1
1
0
1
0
1
Reserved
Breakpoint on P access
Breakpoint on X access
Breakpoint on Y access
10.5.6.2
Breakpoint 0 Read/Write Select (RW00ÐRW01)
Bits 2Ð3
The RW00ÐRW01 bits define the memory breakpoint 0 to occur when a memory address
access is performed for read, write, or both. See Table 10-7 for the definition of the
RW00ÐRW01 bits.
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OnCE Memory Breakpoint Logic
Table 10-7 Breakpoint 0 Read/Write Select Table
RW01
RW00
Description
0
0
1
1
0
1
0
1
Breakpoint disabled
Breakpoint on write access
Breakpoint on read access
Breakpoint on read or write access
10.5.6.3
Breakpoint 0 Condition Code Select (CC00ÐCC01)
Bits 4Ð5
The CC00ÐCC01 bits define the condition of the comparison between the current
memory address (OMAL0) and the memory limit register 0 (OMLR0). See Table 10-8 for
the definition of the CC00ÐCC01 bits.
Table 10-8 Breakpoint 0 Condition Select Table
CC01
CC00
Description
0
0
1
1
0
1
0
1
Breakpoint on not equal
Breakpoint on equal
Breakpoint on less than
Breakpoint on greater than
10.5.6.4
Breakpoint 1 Read/Write Select (RW10ÐRW11)
Bits 6Ð7
The RW10ÐRW11 bits control define memory breakpoint 1 to occur when a memory
address access is performed for read, write, or both. See Table 10-9 for the definition of
the RW10ÐRW11 bits.
Table 10-9 Breakpoint 1 Read/Write Select Table
RW11
RW10
Description
0
0
1
1
0
1
0
1
Breakpoint disabled
Breakpoint on write access
Breakpoint on read access
Breakpoint read or write access
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OnCE Memory Breakpoint Logic
10.5.6.5
Breakpoint 1 Condition Code Select (CC10ÐCC11)
Bits 8Ð9
The CC10ÐCC11 bits define the condition of the comparison between the current
memory address (OMAL0) and the OnCE Memory Limit Register 1 (OMLR1). See
Table 10-10 for the definition of the CC10ÐCC11 bits.
Table 10-10 Breakpoint 1 Condition Select Table
CC11
CC10
Description
0
0
1
1
0
1
0
1
Breakpoint on not equal
Breakpoint on equal
Breakpoint on less than
Breakpoint on greater than
10.5.6.6
Breakpoint 0 and 1 Event Select (BT0ÐBT1)
Bits 10Ð11
The BT0ÐBT1 bits define the sequence between breakpoint 0 and 1. If the condition
defined by BT0ÐBT1 is met, then the OnCE Breakpoint Counter (OMBC) is decremented.
See Table 10-11 for the definition of the BT0ÐBT1 bits.
Table 10-11 Breakpoint 0 and 1 Event Select Table
BT1
BT0
Description
0
0
1
1
0
1
0
1
Breakpoint 0 and Breakpoint 1
Breakpoint 0 or Breakpoint 1
Breakpoint 1 after Breakpoint 0
Breakpoint 0 after Breakpoint 1
10.5.6.7
OnCE Memory Breakpoint Counter (OMBC)
The OMBC is a 16-bit counter that is loaded with a value equal to the number of times
minus one that a memory access event should occur before a memory breakpoint is
declared. The memory access event is specified by the OBCR and by the memory limit
registers. On each occurrence of the memory access event, the breakpoint counter is
decremented. When the counter reaches 0 and a new occurrence takes place, the chip
enters debug mode. The OMBC can be read or written through the JTAG port. Every
time that the limit register is changed or a different breakpoint event is selected in the
OBCR, the breakpoint counter must be written afterwards. This insures that the OnCE
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OnCE Trace Logic
breakpoint logic is reset and that no previous events can affect the new breakpoint event
selected. The breakpoint counter is cleared by a hardware RESET signal.
10.5.6.8
Reserved Bits 12-15
Bits 12Ð15 are reserved for future use. They are read as 0 and should be written with 0 for
future compatibility.
10.6 OnCE TRACE LOGIC
Using the OnCE trace logic, execution of instructions in single or multiple steps is
possible. The OnCE trace logic causes the chip to enter debug mode after the execution
of one or more instructions and wait for OnCE commands from the debug serial port.
The OnCE trace logic block diagram is shown in Figure 10-8.
End of Instruction
TDI
DEC
TDO
Trace Counter
TCK
Count = 0
ISTRACE
AA0708
Figure 10-8 OnCE Trace Logic Block Diagram
Trace mode has a counter associated with it so that more than one instruction can be
executed before returning back to debug mode. The objective of the counter is to allow
the user to take multiple instruction steps real time before entering debug mode. This
feature helps the software developer debug sections of code that do not have a normal
flow or are getting hung up in infinite loops. The OTC also enables the user to count the
number of instructions executed in a code segment.
To enable trace mode, the counter is loaded with a value, the program counter is set to
the start location of the instruction(s) to be executed real time, the TME bit is set in the
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Methods of Entering Debug Mode
OSCR, and the DSP56300 core exits debug mode by executing the appropriate command
issued by the external command controller.
Upon exiting debug mode, the counter is decremented after each execution of an
instruction. Interrupts are serviceable then. Moreover, all executed instructions,
including fast interrupt services and the execution of each repeated instruction, cause
the OTC to be decremented. Upon decrementing to 0, the DSP56300 core reenters debug
mode, the trace occurrence bit (TO) in the OSCR register is set, the core status bits
OS[1:0] are set to 11, and the DE signal is asserted to indicate that the DSP56300 core has
entered debug mode and is requesting service.
The OnCE Trace Counter (OTC) is a 16-bit counter that can be read or written through
the JTAG port. If N instructions are to be executed before entering debug mode, the OTC
should be loaded with N Ð 1. The OTC is cleared by a hardware RESET signal.
10.7 METHODS OF ENTERING DEBUG MODE
Entering debug mode is acknowledged by the chip by setting the core status bits OS1
and OS0 and asserting the DE line. This informs the external command controller that
the chip has entered debug mode and is waiting for commands. The DSP56300 core can
disable the OnCE module if the ROM Security option is implemented. If the ROM
security is implemented, the OnCE module remains inactive until a write operation to
the OGDBR is executed by the DSP56300 core.
10.7.1
External Debug Request During RESET Assertion
Holding the DE line asserted during the assertion of RESET causes the chip to enter
debug mode. After receiving the acknowledge, the external command controller must
negate the DE line before sending the first command.
Note:
In this case, the chip does not execute any instruction before entering debug
mode.
10.7.2
External Debug Request During Normal Activity
Holding the DE line asserted during normal chip activity causes the chip to finish the
execution of the current instruction and then enter Debug mode. After receiving the
acknowledge, the external command controller must negate the DE line before sending
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Methods of Entering Debug Mode
the first command. This process is the same for any newly fetched instruction, including
instructions fetched by the interrupt processing or instructions that will be aborted by
the interrupt processing.
Note:
In this case the chip completes the execution of the current instruction and
stops after the newly fetched instruction enters the instruction latch.
10.7.3
Executing the JTAG DEBUG_REQUEST Instruction
Executing the JTAG instruction DEBUG_REQUEST asserts an internal debug request
signal. Consequently, the chip finishes the execution of the current instruction and stops
after the newly fetched instruction enters the instruction latch. After entering debug
mode, the core status bits OS1 and OS0 are set and the DE line is asserted, thus
acknowledging the external command controller that debug mode has been entered.
10.7.4
External Debug Request During Stop
Executing the JTAG instruction DEBUG_REQUEST (or asserting DE) while the chip is in
the stop state (i. e., has executed a STOP instruction) causes the chip to exit the stop state
and enter debug mode. After receiving the acknowledge, the external command
controller must negate DE before sending the first command.
Note:
In this case, the chip completes the execution of the STOP instruction and halts
after the next instruction enters the instruction latch.
10.7.5
External Debug Request During Wait
Executing the JTAG instruction DEBUG_REQUEST (or asserting DE) while the chip is in
the wait state (i. e., has executed a WAIT instruction) causes the chip to exit the wait state
and enter debug mode. After receiving the acknowledge, the external command
controller must negate DE before sending the first command.
Note:
In this case, the chip completes the execution of the WAIT instruction and
halts after the next instruction enters the instruction latch.
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Pipeline Information and OGDB Register
10.7.6
Software Request During Normal Activity
Upon executing the DSP56300 core instruction DEBUG (or DEBUGcc when the specified
condition is true), the chip enters debug mode after the instruction following the DEBUG
instruction has entered the instruction latch.
10.7.7
Enabling Trace Mode
When Trace mode is enabled and the OTC is greater than zero, the OTC is decremented
after each instruction execution. Execution of an instruction when the value in the OTC
is 0 causes the chip to enter debug mode after completing the execution of the
instruction. Only instructions actually executed cause the OTC to decrement. An aborted
instruction does not decrement the OTC and does not cause the chip to enter debug
mode.
10.7.8
Enabling Memory Breakpoints
When the memory breakpoint mechanism is enabled with a breakpoint counter value of
0, the chip enters debug mode after completing the execution of the instruction that
caused the memory breakpoint to occur. In case of breakpoints on executed program
memory fetches, the breakpoint is acknowledged immediately after the execution of the
fetched instruction. In case of breakpoints on accesses to X, Y or program memory spaces
by MOVE instructions, the breakpoint is acknowledged after the completion of the
instruction following the instruction that accessed the specified address.
10.8 PIPELINE INFORMATION AND OGDB REGISTER
To restore the pipeline and to resume normal chip activity upon returning from debug
mode, a number of on-chip registers store the chip pipeline status. Figure 10-9 shows the
block diagram of the pipeline information registers, with the exception of the PAB
registers, which appear in Figure 10-10 on page 10-22.
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Pipeline Information and OGDB Register
GDB Register (OGDBR)
GDB
PDB Register (OPDBR)
PIL Register (OPILR)
TDI
PDB
TDO
TCK
PIL
AA0709
Figure 10-9 OnCE Pipeline Information and GDB Registers
10.8.1
OnCE PDB Register (OPDBR)
The OPDBR is a 24-bit latch that stores the value of the program data bus generated by
the last program memory access of the core before debug mode is entered. The OPDBR
register can be read or written through the JTAG port. This register is affected by the
operations performed during debug mode and must be restored by the external
command controller when returning to normal mode.
10.8.2
OnCE PIL Register (OPILR)
The OPILR is a 24-bit latch that stores the value of the instruction latch before debug
mode is entered. OPILR can only be read through the JTAG port.
Note:
Since the instruction latch is affected by the operations performed during
debug mode, it must be restored by the external command controller when
returning to normal mode. Since there is no direct write access to the
instruction latch, the task of restoring is accomplished by writing to OPDBR
with no-GO and no-EX. In this case the data written on PDB is transferred into
the instruction latch.
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Debugging Resources
10.8.3
OnCE GDB Register (OGDBR)
The OGDBR is a 16-bit latch that can only be read through the JTAG port. The OGDBR is
not actually required for restoring the pipeline status but is required as a means of
passing information between the chip and the external command controller. The
OGDBR is mapped on the X internal I/O space at address $FFFC. Whenever the external
command controller needs the contents of a register or memory location, it forces the
chip to execute an instruction that brings that information to the OGDBR. Then the
contents of the OGDBR are delivered serially to the external command controller by the
command READ GDB REGISTER.
10.9 DEBUGGING RESOURCES
To ease debugging activity and keep track of program flow, the DSP56300 core provides
a number of on-chip dedicated resources. There are three read-only PAB registers that
give pipeline information when debug mode is entered, and a trace buffer that stores the
address of the last instruction that was executed, as well as the addresses of the last 12
change-of-flow instructions.
10.9.1
OnCE PAB Register for Fetch (OPABFR)
The OPABFR is a 16-bit register that stores the address of the last instruction whose fetch
was started before debug mode was entered. The OPABFR can only be read through the
JTAG port. This register is not affected by the operations performed during debug mode.
10.9.2
PAB Register for Decode (OPABDR)
The OPABDR is a 16-bit register that stores the address of the instruction currently on
the PDB. This is the instruction whose fetch was completed before the chip has entered
debug mode. The OPABDR can only be read through the JTAG port. This register is not
affected by the operations performed during debug mode.
10.9.3
OnCE PAB Register for Execute (OPABEX)
The OPABEX is a 16-bit register that stores the address of the instruction currently in the
instruction latch. This is the instruction that would have been decoded and executed if
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Debugging Resources
the chip would not have entered debug mode. The OPABEX register can only be read
through the JTAG port. This register is not affected by the operations performed during
debug mode.
10.9.4
Trace Buffer
The trace buffer stores the addresses of the last 12 change-of-flow instructions that were
executed, as well as the address of the last executed instruction. The trace buffer is
implemented as a circular buffer containing 12 17-bit registers and one 4-bit counter. All
the registers have the same address, but any read access to the trace buffer address
causes the counter to increment, thus pointing to the next trace buffer register. The
registers are serially available to the external command controller through their common
trace buffer address. Figure 10-10 on page 10-22 shows the block diagram of the trace
buffer. The trace buffer is not affected by the operations performed during debug mode
except for the trace buffer pointer increment when reading the trace buffer. When
entering debug mode, the trace buffer counter is pointing to the trace buffer register
containing the address of the last executed instructions. The first trace buffer read
obtains the oldest address and the following trace buffer reads get the other addresses
from the oldest to the newest, in order of execution.
Notes:
1. To insure trace buffer coherence, a complete set of 12 reads of the Trace
buffer must be performed. This is necessary due to the fact that each read
increments the trace buffer pointer, thus pointing to the next location.
After 12 reads, the pointer indicates the same location as before starting the
read procedure.
2. On any change of flow instruction, the trace buffer stores both the address
of the change of flow instruction, as well as the address of the target of the
change of flow instruction. In the case of conditional change of flows, the
address of the change of flow instruction is always stored (regardless of the
fact that the change of flow is true or false), but if the conditional change of
flow is false (i.e., not taken) the address of the target is not stored. In order
to facilitate the program trace reconstruction, every trace buffer location
has an additional Ôinvalid bitÕ (bit 24). If a conditional change of flow
instruction has a Ôcondition falseÕ, the invalid bit is set, thus marking this
instruction as not taken. Therefore, it is imperative to read 17 bits of data
when reading the 12 trace buffer registers. Since data is read LSB first, the
invalid bit is the first bit to be read.
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Serial Protocol Description
PAB
Fetch Address (OPABFR)
Decode Address (OPABDR)
Execute Address (OPABEX)
Trace Buffer Register 0
Trace Buffer Register 1
Trace Buffer Register 2
Circular
Buffer
Pointer
Trace Buffer Register 11
Trace Buffer Shift Register
TCK
TDO
TDI
AA0710
Figure 10-10 OnCE Trace Buffer
10.10 SERIAL PROTOCOL DESCRIPTION
To permit an efficient means of communication between the external command
controller and the DSP56300 core chip, the following protocol is adopted. Before starting
any debugging activity, the external command controller has to wait for an acknowledge
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Target Site Debug System Requirements
on the DE line indicating that the chip has entered debug mode. Optionally the external
command controller can poll the OS1 and OS0 bits in the JTAG instruction shift register.
The external command controller communicates with the chip by sending 8-bit
commands that can be accompanied by 24 bits of data. Both commands and data are sent
or received LSB first. After sending a command, the external command controller should
wait for the DSP56300 core chip to acknowledge execution of the command. The external
command controller can send a new command only after the chip has acknowledged
execution of the previous command.
The OnCE commands are classified as follows:
¥ Read commands (when the chip delivers the required data)
¥ Write commands (when the chip receives data and writes the data in one of the
OnCE registers)
¥ Commands that do not have data transfers associated with them
The commands are 8 bits long. The command formats are shown in Figure 10-4
on page 10-5.
10.11 TARGET SITE DEBUG SYSTEM REQUIREMENTS
A typical debug environment consists of a target system where the DSP56300 core-based
device resides in the user defined hardware. The JTAG port interfaces to the external
command controller over a 8-wire link consisting of the five JTAG port wires, one OnCE
module wire, a ground, and a reset wire. The reset wire is optional and is only used to
reset the DSP56300 core-based device and its associated circuitry.
The external command controller acts as the medium between the DSP56300 core target
system and a host computer. The external command controller circuit acts as a JTAG
port driver and host computer command interpreter. The controller issues commands
based on the host computer inputs from a user interface program that communicates
with the user.
10.12 OnCE MODULE EXAMPLES
Following are some examples of debugging procedures. All these examples assume that
the DSP is the only device in the JTAG chain. If there is more than one device in the chain
(additional DSPs or other devices), the other devices can be forced to execute the JTAG
BYPASS instruction such as their effect in the serial stream will be one bit per additional
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device. The events such as select-DR, select-IR, update-DR, and shift-DR refer to
bringing the JTAG TAP in the corresponding state. For a detailed description of the
JTAG protocol, see Section 11ÑJTAG Port.
10.12.1 Checking Whether the Chip Has Entered Debug Mode
There are two methods to verify that the chip has entered debug mode:
¥ Every time the chip enters debug mode, a pulse is generated on the DE signal. A
pulse is also generated every time the chip acknowledges the execution of an
instruction while in debug mode. An external command controller can connect
the DE line to an interrupt signal in order to sense the acknowledge.
¥ An external command controller can poll the JTAG instruction shift register for
the status bits OS[1:0]. When the chip is in Debug mode, these bits are set to the
value 11.
Note:
In the following paragraphs, the ACK notation denotes the operation
performed by the command controller to check whether debug mode has been
entered (either by sensing DE or by polling JTAG instruction shift register).
10.12.2 Polling the JTAG Instruction Shift Register
In order to poll the core status bits in the JTAG instruction shift register the following
sequence must be performed:
1. Select shift-IR. Passing through capture-IR loads the core status bits into the
instruction shift register.
2. Shift in ENABLE_ONCE. While shifting-in the new instruction, the captured
status information is shifted-out. Pass through update-IR.
3. Return to Run-Test/Idle.
The external command controller can analyze the information shifted out and detect
whether the chip has entered debug mode.
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10.12.3 Saving Pipeline Information
The debugging activity is accomplished by means of DSP56300 core instructions
supplied from the external command controller. Therefore, the current state of the
DSP56300 core pipeline must be saved prior to starting the debug activity and the state
must be restored prior to returning to normal mode. Here is the description of the save
procedure (it assumes that ENABLE_ONCE has been executed and Debug mode has
been entered and verified, as described in Section 10.12.1ÑChecking Whether the Chip
Has Entered Debug Mode):
1. Select shift-DR. Shift in the ÒRead PDBÓ. Pass through update-DR.
2. Select shift-DR. Shift out the 24 bit OPDB register. Pass through update-DR.
3. Select shift-DR. Shift in the ÒRead PILÓ. Pass through update-DR.
4. Select shift-DR. Shift out the 24 bit OPILR register. Pass through update-DR.
Note that there is no need to verify acknowledge between steps 1 and 2, as well as 3 and
4, because completion is guaranteed by design.
10.12.4 Reading the Trace Buffer
An optional step during debugging activity is reading the information associated with
the trace buffer in order to enable an external program to reconstruct the full trace of the
executed program. In the following description of the read trace buffer procedure, it is
assumed that all actions described in Saving Pipeline Information have been executed.
1. Select shift-DR. Shift in the ÒRead PABFRÓ. Pass through update-DR.
2. Select shift-DR. Shift out the 16 bit OPABFR register. Pass through update-DR.
3. Select shift-DR. Shift in the ÒRead PABDRÓ. Pass through update-DR.
4. Select shift-DR. Shift out the 16 bit OPABDR register. Pass through update-DR.
5. Select shift-DR. Shift in the ÒRead PABEXÓ. Pass through update-DR.
6. Select shift-DR. Shift out the 16 bit OPABEX register. Pass through update-DR.
7. Select shift-DR. Shift in the ÒRead FIFOÓ. Pass through update-DR.
8. Select shift-DR. Shift out the 17 bit FIFO register. Pass through update-DR.
9. Repeat steps 7 and 8 for the entire FIFO (12 times).
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Note:
The user must read the entire FIFO, since each read increments the FIFO
pointer, thus pointing to the next FIFO location. At the end of this procedure,
the FIFO pointer points back to the beginning of the FIFO.
The information that has been read by the external command controller now contains
the address of the newly fetched instruction, the address of the instruction currently on
the PDB, the address of the instruction currently on the instruction latch, as well as the
addresses of the last 12 instructions that have been executed and are change of flow. A
user program can now reconstruct the flow of a full trace based on this information and
on the original source code of the currently running program.
10.12.5 Displaying a Specified Register
To display a specified register, the DSP56300 must be in debug mode and all actions
described in Section 10.12.3ÑSaving Pipeline Information have been executed. The
sequence of actions is as follows:
1. Select shift-DR. Shift in the ÒWrite PDB with GO no-EXÓ. Pass through
update-DR.
2. Select shift-DR. Shift in the 24-bit opcode: ÒMOVE reg, X:OGDBÓ. Pass through
update-DR to actually write OPDBR and thus begin executing the MOVE
instruction.
3. Wait for DSP to reenter debug mode (wait for DE or poll core status).
4. Select shift-DR and shift in ÒREAD GDB REGISTERÓ. Pass through update-DR.
This step selects OGDBR as the data register for the read.
5. Select shift-DR. Shift out the OGDBR contents. Pass through update-DR. Wait for
next command.
10.12.6 Displaying X Memory Area Starting at Address $xxxx
The DSP56309 must be in debug mode and all actions described in
Section 10.12.3ÑSaving Pipeline Information must have been executed. Since R0 is
used as pointer for the memory, R0 is saved first. The sequence of actions is as follows:
1. Select shift-DR. Shift in the ÒWrite PDB with GO no-EXÓ. Pass through
update-DR.
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2. Select shift-DR. Shift in the 24-bit opcode: ÒMOVE R0, X:OGDBÓ. Pass through
update-DR to actually write OPDBR and thus begin executing the MOVE
instruction.
3. Wait for DSP to reenter debug mode (wait for DE or poll core status).
4. Select shift-DR and shift in ÒREAD GDB REGISTERÓ. Pass through update-DR.
(This selects OGDBR as the data register for read.)
5. Select shift-DR. Shift out the OGDBR contents. Pass through update-DR. R0 is
now saved.
6. Select shift-DR. Shift in the ÒWrite PDB with no-GO no-EXÓ. Pass through
update-DR.
7. Select shift-DR. Shift in the 24 bit opcode: ÒMOVE #$xxxx,R0Ó. Pass through
update-DR to actually write OPDBR.
8. Select shift-DR. Shift in the ÒWrite PDB with GO no-EXÓ. Pass through
update-DR.
9. Select shift-DR. Shift in the second word of the 24 bit opcode: ÒMOVE #$xxxx,R0Ó
(the $xxxx field). Pass through update-DR to actually write OPDBR and execute
the instruction. R0 is loaded with the base address of the memory block to be
read.
10. Wait for DSP to reenter debug mode. (Wait for DE or poll core status.)
11. Select shift-DR. Shift in the ÒWrite PDB with GO no-EXÓ. Pass through
update-DR.
12. Select shift-DR. Shift in the 24-bit opcode: ÒMOVE X:(R0)+, X:OGDBÓ. Pass
through update-DR to actually write OPDBR and thus begin executing the MOVE
instruction.
13. Wait for DSP to reenter debug mode. (Wait for DE or poll core status.)
14. Select shift-DR and shift in ÒREAD GDB REGISTERÓ. Pass through update-DR.
(This selects OGDBR as the data register for read.)
15. Select shift-DR. Shift out the OGDBR contents. Pass through update-DR. The
memory contents of address $xxxx have been read.
16. Select shift-DR. Shift in the ÒNO SELECT with GO no-EXÓ. Pass through
update-DR. This reexecutes the same ÒMOVE X:(R0)+, X:OGDBÓ instruction.
17. Repeat from step 14 to complete the reading of the entire block. When finished,
restore the original value of R0.
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10.12.7 Returning from Debug to Normal Mode (Same Program)
In this case, you have finished examining the current state of the machine, changed some
of the registers, and wish to return and continue execution of the same program from the
point where it stopped. Therefore, you must restore the pipeline of the machine and
enable normal instruction execution. The sequence of actions to do so is listed below:
1. Select shift-DR. Shift in the ÒWrite PDB with no-GO no-EXÓ. Pass through
update-DR.
2. Select shift-DR. Shift in the 24 bits of saved PIL (instruction latch value). Pass
through update-DR to actually write the instruction latch.
3. Select shift-DR. Shift in the ÒWrite PDB with GO and EXÓ. Pass through
update-DR.
4. Select shift-DR. Shift in the 24 bits of saved PDB. Pass through update-DR to
actually write the PDB. At the same time the internally saved value of the PAB is
driven back from the PABFR register onto the PAB, the ODEC releases the chip
from debug mode, and the normal flow of execution is continued.
10.12.8 Returning from Debug to Normal Mode (New Program)
In this case, you have finished examining the current state of the machine, changed some
of the registers, and wish to start the execution of a new program (the GOTO command).
Therefore, you must force a Òchange-of-flowÓ to the starting address of the new program
($xxxx). The sequence of actions to do so is listed below:
1. Select shift-DR. Shift in the ÒWrite PDB with no-GO no-EXÓ. Pass through
update-DR.
1. Select shift-DR. Shift in the 24-bit Ò$0AF080Ó which is the opcode of the JUMP
instruction. Pass through update-DR to actually write the instruction latch.
2. Select shift-DR. Shift in the ÒWrite PDB-GO-TO with GO and EXÓ. Pass through
update-DR.
3. Select shift-DR. Shift in the 16 bit of Ò$xxxxÓ. Pass through update-DR to actually
write the PDB. At this time the ODEC releases the chip from debug mode and the
execution is started from the address $xxxx.
Note:
If the device enters debug mode during a DO LOOP, REP instruction, or other
special cases such as interrupt processing, STOP, WAIT, or conditional
branching, you must first reset the DSP56300 and then proceed with the
execution of the new program.
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JTAG PORT/onCE MODULE INTERACTION
10.13 JTAG PORT/OnCE MODULE INTERACTION
This subsection lists the details of the JTAG port/OnCE module interaction and TMS
sequencing required in order to achieve the communication described in
Section 10.12ÑOnCE Module Examples.
The external command controller can force the DSP56300 into debug mode by executing
the JTAG instruction DEBUG_REQUEST. In order to check that the DSP56300 has
entered debug mode, the external command controller must poll the status by reading
the OS[1:0] bits in the JTAG instruction shift register. The TMS sequencing appears in
Table 10-12.
The sequence to enable the OnCE module appears in Table 10-13.
After executing the JTAG instructions DEBUG_REQUEST and ENABLE_ONCE and
after the core status was polled to verify that the chip is in debug mode, the pipeline
saving procedure must take place. The TMS sequencing for this procedure is depicted in
Table 10-12.
Table 10-12 TMS Sequencing for DEBUG_REQUEST
Step TMS
JTAG Port
OnCE Module
Note
a
b
c
0
1
1
0
0
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Capture-IR
Idle
Idle
Idle
Idle
Idle
Ñ
Ñ
Ñ
d
e
The status is sampled in the shifter.
Shift-IR
The four bits of the JTAG
DEBUG_REQUEST (0111) are
shifted in while status is
shifted out.
..................................................................
e
f
0
1
1
1
1
0
Shift-IR
Exit1-IR
Idle
Idle
Idle
Idle
Idle
Idle
Ñ
g
h
i
Update-IR
The debug request is generated.
Ñ
Select-DR-Scan
Select-IR-Scan
Capture-IR
j
The status is sampled in the shifter.
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JTAG PORT/onCE MODULE INTERACTION
Table 10-12 TMS Sequencing for DEBUG_REQUEST (Continued)
Step TMS
JTAG Port
OnCE Module
Note
k
0
Shift-IR
Idle
The four bits of the JTAG
DEBUG_REQUEST (0111) are
shifted in while status is
shifted out.
..................................................................
k
l
0
1
1
0
Shift-IR
Exit1-IR
Idle
Idle
Idle
Idle
m
n
Update-IR
Run-Test/Idle
................................................
Run-Test/Idle
This step is repeated, enabling an
external command controller to
poll the status.
n
0
Idle
In Òstep nÓ the external command controller verifies that the OS[1:0] bits have the value
11, indicating that the chip has entered debug mode. If the chip has not yet entered
debug mode, the external command controller goes to Òstep bÓ, Òstep cÓ etc. until debug
mode is acknowledged.
Table 10-13 TMS Sequencing for ENABLE_ONCE
Step TMS
JTAG Port
OnCE Module
Note
a
b
c
d
e
f
1
0
1
1
0
0
0
0
0
1
1
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Capture-IR
Shift-IR
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Ñ
Ñ
Ñ
Ñ
The core status bits are captured.
The four bits of the JTAG
ENABLE_ONCE instruction
(0110) are shifted into the JTAG
instruction register while status is
shifted out.
g
h
i
Shift-IR
Shift-IR
Shift-IR
j
Exit1-IR
Ñ
k
Update-IR
The OnCE module is enabled.
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JTAG PORT/onCE MODULE INTERACTION
Table 10-13 TMS Sequencing for ENABLE_ONCE (Continued)
Step TMS
JTAG Port
OnCE Module
Note
l
0
Run-Test/Idle
Idle
This step can be repeated,
enabling an external command
controller to poll the status.
................................................
Run-Test/Idle
l
0
Idle
Table 10-14 TMS Sequencing for Reading Pipeline Registers
Step TMS
JTAG Port
OnCE Module
Note
a
b
c
0
1
0
0
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Idle
Idle
Idle
Idle
Ñ
Ñ
Ñ
d
The eight bits of the OnCE
command ÒRead PILÓ
(10001011) are shifted in.
..................................................................
d
e
f
0
Shift-DR
Exit1-DR
Idle
1
1
Idle
Ñ
Update-DR
Execute ÒRead PILÓ
The PIL value is loaded in
the shifter.
g
h
i
1
0
0
Select-DR-Scan
Capture-DR
Shift-DR
Idle
Idle
Idle
Ñ
Ñ
The 24 bits of the PIL are
shifted out (24 steps).
..................................................................
i
j
0
Shift-DR
Exit1-DR
Idle
1
1
1
0
Idle
Idle
Idle
Idle
Ñ
Ñ
Ñ
Ñ
k
l
Update-DR
Select-DR-Scan
Capture-DR
m
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JTAG PORT/onCE MODULE INTERACTION
Table 10-14 TMS Sequencing for Reading Pipeline Registers (Continued)
Step TMS
JTAG Port
OnCE Module
Note
n
0
Shift-DR
Idle
The eight bits of the OnCE
command ÒRead PDBÓ
(10001010) are shifted in.
..................................................................
n
o
p
0
Shift-DR
Exit1-DR
Idle
1
1
Idle
Ñ
Update-DR
Execute ÒRead PDBÓ
PDB value is loaded in
shifter.
q
r
1
0
0
Select-DR-Scan
Capture-DR
Shift-DR
Idle
Idle
Idle
Ñ
Ñ
s
The 24 bits of the PDB are
shifted out (24 steps).
..................................................................
s
t
0
Shift-DR
Exit1-DR
Idle
1
1
0
Idle
Idle
Idle
Ñ
Ñ
u
v
Update-DR
Run-Test/Idle
................................................
Run-Test/Idle
This step can be repeated,
enabling an external
command controller to
analyze the information.
v
0
Idle
During Òstep vÓ the external command controller stores the pipeline information.
Afterwards, it can proceed with the debug activities as requested by the user.
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SECTION 11
JTAG PORT
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11.1
11.2
11.3
11.4
11.5
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
JTAG SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
TAP CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
DSP56300 RESTRICTIONS . . . . . . . . . . . . . . . . . . . . . . . 11-12
DSP56309 BOUNDARY SCAN REGISTER . . . . . . . . . . . 11-13
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Introduction
11.1 INTRODUCTION
The DSP56300 core provides a dedicated user-accessible test access port (TAP) that is
fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture. Problems associated with testing high density circuit boards have led to
development of this proposed standard under the sponsorship of the Test Technology
Committee of IEEE and the JTAG. The DSP56300 core implementation supports
circuit-board test strategies based on this standard.
The test logic includes a TAP that consists of five dedicated signals, a 16-state controller,
and three test data registers. A Boundary Scan Register (BSR) links all device signals into
a single shift register. The test logic, implemented utilizing static logic design, is
independent of the device system logic. The DSP56300 core implementation provides the
following capabilities:
¥ Performs boundary scan operations to test circuit-board electrical continuity
(EXTEST)
¥ Bypasses the DSP56300 core for a given circuit-board test by effectively reducing
the BSR to a single cell (BYPASS)
¥ Samples the DSP56300 core-based device system signals during operation and
transparently shifts out the result in the BSR
¥ Preloads values to output signals prior to invoking the EXTEST instruction
(SAMPLE/PRELOAD)
¥ Disables the output drive to signals during circuit-board testing (HI-Z)
¥ Provides a means of accessing the OnCE controller and circuits to control a target
system (ENABLE_ONCE)
¥ Provides a means of entering debug Mode (DEBUG_REQUEST)
¥ Queries identification information (manufacturer, part number and version) from
a DSP56300 core-based device (IDCODE)
¥ Forces test data onto the outputs of a DSP56300 core-based device while replacing
its boundary scan register in the serial data path with a single bit register
(CLAMP)
This section, which includes aspects of the JTAG implementation that are specific to the
DSP56300 core, is intended to be used with the supporting IEEE 1149.1 document. The
discussion includes those items required by the standard to be defined and, in certain
cases, provides additional information specific to the DSP56300 core implementation.
For internal details and applications of the standard, refer to the IEEE 1149.1 document.
Figure 11-1 shows a block diagram of the TAP port.
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JTAG Signals
Boundary Scan Register
TDI
Bypass
ID Register
OnCE Logic
Decoder
3
2
1
0
TDO
4-Bit Instruction Register
TMS
TAP
Ctrl
TCK
AA0113
TRST
Figure 11-1 TAP Block Diagram
11.2 JTAG SIGNALS
As described in the IEEE 1149.1 document, the JTAG port requires a minimum of four
signals to support TDI, TDO, TCK, and TMS signals. The DSP56300 family also provides
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JTAG Signals
the optional TRST signal. On the DSP56309, the debug event (DE) signal is provided for
use by the OnCE module; it is documented in Section 10ÑOn-Chip Emulation Module.
The signal functions are described in the following paragraphs.
11.2.1
Test Clock (TCK)
The TCK signal is used to synchronize the test logic.
11.2.2
Test Mode Select (TMS)
The TMS signal is used to sequence the test controllerÕs state machine. The TMS is
sampled on the rising edge of TCK, and it has an internal pull-up resistor.
11.2.3
Test Data Input (TDI)
Serial test instruction and data are received through the Test Data Input (TDI) signal.
TDI is sampled on the rising edge of TCK, and it has an internal pull-up resistor.
11.2.4
Test Data Output (TDO)
The TDO signal is the serial output for test instructions and data. TDO is tri-stateable
and is actively driven in the Shift-IR and Shift-DR controller states. TDO changes on the
falling edge of TCK.
11.2.5
Test Reset (TRST)
The TRST signal is used to asynchronously initialize the test controller. The TRST signal
has an internal pullup resistor.
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11.3 TAP CONTROLLER
The TAP controller is responsible for interpreting the sequence of logical values on the
TMS signal. It is a synchronous state machine that controls the operation of the JTAG
logic. The state machine is shown in Figure 11-2. The TAP controller responds to
changes at the TMS and TCK signals. Transitions from one state to another occur on the
rising edge of TCK. The value shown adjacent to each state transition represents the
value of the TMS signal sampled on the rising edge of TCK signal. For a description of
the TAP controller states, refer to the IEEE 1149.1 document.
Test-Logic-Reset
1
0
0
1
1
1
Select-IR-Scan
Run-Test/Idle
Select-DR-Scan
0
0
Capture-IR
0
1
1
Capture-DR
0
Shift-DR
1
Shift-IR
1
0
0
1
1
Exit1-DR
Exit1-IR
0
0
Pause-DR
1
Pause-IR
0
0
1
0
0
Exit2-DR
Exit2-IR
1
1
Update-IR
Update-DR
0
1
1
0
AA0114
Figure 11-2 TAP Controller State Machine
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11.3.1
Boundary Scan Register (BSR)
The BSR in the DSP56309 JTAG implementation contains bits for all device signal and
clock signals and associated control signals. All DSP56309 bidirectional signals have a
single register bit in the BSR for signal data; each such signal is controlled by an
associated control bit in the BSR. The DSP56309 BSR bit definitions are described in
Table 11-2 on page 11-13.
11.3.2
Instruction Register
The DSP56309 JTAG implementation includes the three mandatory public instructions
(EXTEST, SAMPLE/PRELOAD, and BYPASS), and also supports the optional CLAMP
instruction defined by IEEE 1149.1. The HI-Z public instruction provides the capability
for disabling all device output drivers. The ENABLE_ONCE public instruction enables
the JTAG port to communicate with the OnCE circuitry. The DEBUG_REQUEST public
instruction enables the JTAG port to force the DSP56300 core into debug mode. The
DSP56300 core includes a 4-bit instruction register without parity consisting of a shift
register with four parallel outputs. Data is transferred from the shift register to the
parallel outputs during the Update-IR controller state. Figure 11-3 shows the JTAG
instruction register.
JTAG Instruction
B3
B2
B1
B0
Register (IR)
AA0746
Figure 11-3 JTAG Instruction Register
The four bits are used to decode the eight unique instructions shown in Table 11-1. All
other encodings are reserved for future enhancements and are decoded as BYPASS.
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TAP Controller
Table 11-1 JTAG Instructions
Code
Instruction
B3
B2
B1
B0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
0
0
1
1
0
0
1
1
x
0
1
1
0
1
0
1
0
1
0
1
x
x
0
1
EXTEST
SAMPLE/PRELOAD
IDCODE
CLAMP
HI-Z
RESERVED
ENABLE_ONCE
DEBUG_REQUEST
RESERVED
RESERVED
RESERVED
BYPASS
The parallel output of the instruction register is reset to 0010 in the Test-Logic-Reset
controller state, which is equivalent to the IDCODE instruction.
During the Capture-IR controller state, the parallel inputs to the instruction shift register
are loaded with 01 in the LSBs as required by the standard. The two MSBs are loaded
with the values of the core status bits OS1 and OS0 from the OnCE controller. See
Section 10ÑOn-Chip Emulation Module for a description of the status bits.
11.3.2.1
EXTEST (B[3:0] = 0000)
The external test (EXTEST) instruction selects the BSR. EXTEST also asserts internal reset
for the DSP56300 core system logic to force a predictable internal state while performing
external boundary scan operations.
By using the TAP, the BSR is capable of the following:
¥ Scanning user-defined values into the output buffers
¥ Capturing values presented to input signals
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¥ Controlling the direction of bidirectional signals
¥ Controlling the output drive of tri-stateable output signals
For more details on the function and use of the EXTEST instruction, please refer to the
IEEE 1149.1 document.
11.3.2.2
SAMPLE/PRELOAD (B[3:0] = 0001)
The SAMPLE/PRELOAD instruction provides two separate functions. First, it provides
a means to obtain a snapshot of system data and control signals. The snapshot occurs on
the rising edge of TCK in the Capture-DR controller state. The data can be observed by
shifting it transparently through the BSR.
Note:
Because there is no internal synchronization between the JTAG clock (TCK)
and the system clock (CLK), the user must provide some form of external
synchronization to achieve meaningful results.
The second function of the SAMPLE/PRELOAD instruction is to initialize the BSR
output cells prior to selection of EXTEST. This initialization insures that known data
appears on the outputs when entering the EXTEST instruction.
11.3.2.3
IDCODE (B[3:0] = 0010)
The IDCODE instruction selects the ID register. This instruction is provided as a public
instruction to allow the manufacturer, part number, and version of a component to be
determined through the TAP. Figure 11-4 shows the ID register configuration.
31
28 27
22 21
17 16
12 11
1 0
1
Version
Manufacturer
Identity
Customer Part Number
Information
0 0 1 0
Design
Center
Number
Chip
Core
Derivative
Number
Number
0 0 0 0 0
0 0 0 1 1 0
0 0 0 1 0
0 0 0 0 0 0 0 1 1 1 0 1
AA0718
Figure 11-4 JTAG ID Register
One application of the ID register is to distinguish the manufacturer(s) of components on
a board when multiple sourcing is used. As more components emerge which conform to
the IEEE 1149.1 standard, it is desirable to allow for a system diagnostic controller unit to
blindly interrogate a board design in order to determine the type of each component in
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TAP Controller
each location. This information is also available for factory process monitoring and for
failure mode analysis of assembled boards.
MotorolaÕs manufacturer identity is 00000001110. The customer part number consists of
two parts: Motorola design center number (bits 27:22) and a sequence number (bits
21:12). The sequence number is divided into two parts: core number (bits 21:17) and chip
derivative number (bits 16:12). Motorola Semiconductor Israel (MSIL) design center
number is 000110 and DSP56300 core number is 00001.
Once the IDCODE instruction is decoded, it selects the ID register, which is a 32-bit data
register. Since the Bypass register loads a logical 0 at the start of a scan cycle, whereas the
ID register loads a logical 1 into its LSB, examination of the first bit of data shifted out of
a component during a test data scan sequence immediately following exit from
Test-Logic-Reset controller state shows whether such a register is included in the design.
When the IDCODE instruction is selected, the operation of the test logic has no effect on
the operation of the on-chip system logic as required by the IEEE 1149.1 standard.
11.3.2.4
CLAMP (B[3:0] = 0011)
The CLAMP instruction is not included in the IEEE 1149.1 standard. It is provided as a
public instruction that selects the 1-bit bypass register as the serial path between TDI and
TDO while allowing signals driven from the component signals to be determined from
the BSR. During testing of ICs on PCB, it may be necessary to place static guarding
values on signals that control operation of logic not involved in the test. The EXTEST
instruction could be used for this purpose, but because it selects the BSR, the required
guarding signals would be loaded as part of the complete serial data stream shifted in,
both at the start of the test and each time a new test pattern is entered. Since the CLAMP
instruction allows guarding values to be applied using the BSR of the appropriate ICs
while selecting their bypass registers, it allows much faster testing than does the EXTEST
instruction. Data in the boundary scan cell remains unchanged until a new instruction is
shifted in or the JTAG state machine is set to its reset state. The CLAMP instruction also
asserts internal reset for the DSP56300 core system logic to force a predictable internal
state while performing external boundary scan operations.
11.3.2.5
HI-Z (B[3:0] = 0100)
The HI-Z instruction is not included in the IEEE 1149.1 standard. It is provided as a
manufacturerÕs optional public instruction to prevent having to backdrive the output
signals during circuit-board testing. When HI-Z is invoked, all output drivers, including
the two-state drivers, are turned off (i.e., high impedance). The instruction selects the
bypass register. The HI-Z instruction also asserts internal reset for the DSP56300 core
system logic to force a predictable internal state while performing external boundary
scan operations.
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11.3.2.6
ENABLE_ONCE(B[3:0] = 0110)
The ENABLE_ONCE instruction is not included in the IEEE 1149.1 standard. It is
provided as a public instruction to allow you to perform system debug functions. When
the ENABLE_ONCE instruction is decoded the TDI and TDO signals are connected
directly to the OnCE registers. The particular OnCE register connected between TDI and
TDO at a given time is selected by the OnCE controller depending on the OnCE
instruction being currently executed. All communication with the OnCE controller is
done through the Select-DR-Scan path of the JTAG TAP controller. See
Section 10ÑOn-Chip Emulation Module for more information.
11.3.2.7
DEBUG_REQUEST(B[3:0] = 0111)
The DEBUG_REQUEST instruction is not included in the IEEE 1149.1 standard. It is
provided as a public instruction to allow you to generate a debug request signal to the
DSP56300 core. When the DEBUG_REQUEST instruction is decoded, the TDI and TDO
signals are connected to the instruction registers. Due to the fact that in the Capture-IR
state of the TAP the OnCE status bits are captured in the Instruction shift register, the
external JTAG controller must continue to shift-in the DEBUG_REQUEST instruction
while polling the status bits that are shifted-out until debug mode is entered
(acknowledged by the combination 11 on OS1ÐOS0). After the acknowledgment of
debug mode is received, the external JTAG controller must issue the ENABLE_ONCE
instruction to allow the user to perform system debug functions.
11.3.2.8
BYPASS (B[3:0] = 1111)
The BYPASS instruction selects the single-bit bypass register, as shown in Figure 11-5.
This choice creates a shift-register path from TDI to the bypass register, and finally to
TDO, circumventing the BSR. This instruction is used to enhance test efficiency when a
component other than the DSP56300 core-based device becomes the device under test.
When the bypass register is selected by the current instruction, the shift-register stage is
set to a logical 0 on the rising edge of TCK in the Capture-DR controller state. Therefore,
the first bit shifted out after selecting the bypass register is always a logical 0.
Shift DR
G1
1
0
D
C
Mux
To TDO
1
From TDI
AA0115
CLOCKDR
Figure 11-5 Bypass Register
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DSP56300 Restrictions
11.4 DSP56300 RESTRICTIONS
The control afforded by the output enable signals using the BSR and the EXTEST
instruction requires a compatible circuit-board test environment to avoid
device-destructive configurations. You must avoid situations in which the DSP56300
core output drivers are enabled into actively driven networks. In addition, the EXTEST
instruction can be performed only after power-up or a regular hardware RESET signal
while EXTAL was provided. Then during the execution of EXTEST, EXTAL can remain
inactive.
There are two constraints related to the JTAG interface. First, the TCK input does not
include an internal pullup resistor and should not be left unconnected. The second
constraint is to insure that the JTAG test logic is kept transparent to the system logic by
forcing the TAP into the Test-Logic-Reset controller state, using either of two methods.
During power-up, TRST must be externally asserted to force the TAP controller into this
state. After power-up is concluded, TMS must be sampled as a logical 1 for five
consecutive TCK rising edges. If TMS either remains unconnected or is connected to
V
, then the TAP controller cannot leave the Test-Logic-Reset state, regardless of the
CC
state of TCK.
The DSP56300 core features a low-power stop mode, which is invoked using the STOP
instruction. The interaction of the JTAG interface with low-power Stop mode is as
follows:
1. The TAP controller must be in the Test-Logic-Reset state to either enter or remain
in the low-power stop mode. Leaving the TAP controller Test-Logic-Reset state
negates the ability to achieve low-power, but does not otherwise affect device
functionality.
2. The TCK input is not blocked in low-power stop mode. To consume minimal
power, the TCK input should be externally connected to V or GND.
CC
3. The TMS and TDI signals include on-chip pullup resistors. In low-power stop
mode, these two signals should remain either unconnected or connected to V to
CC
achieve minimal power consumption.
Since during stop mode all DSP56309 core clocks are disabled, the JTAG interface
provides the means of polling the device status (sampled in the Capture-IR state).
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DSP56309 Boundary Scan Register
11.5 DSP56309 BOUNDARY SCAN REGISTER
Table 11-2 provides a listing of the contents of the BSR for the DSP56309.
Table 11-2 DSP56309 BSR Bit Definitions
Bit #
Cell Type
Signal Name
Signal Type
BSR Cell Type
0
BC_1
BC_1
BC_1
BC_1
BC_6
BC_6
BC_6
BC_6
BC_6
BC_6
BC_6
BC_6
BC_6
BC_1
BC_6
BC_6
BC_6
BC_6
BC_6
BC_6
BC_6
BC_6
MODA
MODB
MODC
MODD
D23
Input
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Control
Data
Data
Data
Data
Data
Data
Data
Data
1
Input
2
Input
3
Input
4
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Ñ
5
D22
6
D21
7
D20
8
D19
9
D18
10
11
12
13
14
15
16
17
18
19
20
21
D17
D16
D15
D[23:12]
D14
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
D13
D12
D11
D10
D9
D8
D7
MOTOROLA
DSP56309UM/D
11-13
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JTAG Port
DSP56309 Boundary Scan Register
Table 11-2 DSP56309 BSR Bit Definitions (Continued)
Bit #
Cell Type
Signal Name
Signal Type
BSR Cell Type
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
BC_6
BC_6
BC_6
BC_6
BC_1
BC_6
BC_6
BC_6
BC_2
BC_2
BC_2
BC_2
BC_2
BC_2
BC_2
BC_2
BC_2
BC_2
BC_2
BC_2
BC_2
BC_2
BC_2
BC_2
D6
D5
Input/Output
Input/Output
Input/Output
Input/Output
Ñ
Data
Data
Data
Data
Control
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
D4
D3
D[11:0]
D2
Input/Output
Input/Output
Input/Output
Output 2
D1
D0
A15
A14
A13
A12
A11
A10
A9
Output 2
Output 2
Output 2
Output 2
Output 2
Output 2
A8
Output 2
A7
Output 2
A6
Output 2
A5
Output 2
A4
Output 2
A3
Output 2
A2
Output 2
A1
Output 2
A0
Output 2
11-14
DSP56309UM/D
MOTOROLA
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JTAG Port
DSP56309 Boundary Scan Register
Table 11-2 DSP56309 BSR Bit Definitions (Continued)
Bit #
Cell Type
Signal Name
Signal Type
BSR Cell Type
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
BC_2
BC_2
BC_2
BC_2
BC_2
BC_1
BC_1
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
MCS
RD
Output
Data
Data
Output
WR
Output
Data
AT
Output
Data
CLKOUT
EXTAL
RESET
HAD0
HAD0
HAD1
HAD1
HAD2
HAD2
HAD3
HAD3
HAD4
HAD4
HAD5
HAD5
HAD6
HAD6
HAD7
HAD7
HAS/A0
Output
Data
Input
Data
Input
Data
Ñ
Control
Data
Input/Output
Ñ
Control
Data
Input/Output
Ñ
Control
Data
Input/Output
Ñ
Control
Data
Input/Output
Ñ
Control
Data
Input/Output
Ñ
Control
Data
Input/Output
Ñ
Input/Output
Ñ
Control
Data
Control
Data
Input/Output
Ñ
Control
MOTOROLA
DSP56309UM/D
11-15
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JTAG Port
DSP56309 Boundary Scan Register
Table 11-2 DSP56309 BSR Bit Definitions (Continued)
Bit #
Cell Type
Signal Name
Signal Type
BSR Cell Type
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
HAS/A0
HA8/A1
HA8/A1
HA9/A2
HA9/A2
HCS/A10
HCS/A10
TIO0
Input/Output
Data
Control
Data
Ñ
Input/Output
Ñ
Control
Data
Input/Output
Ñ
Control
Data
Input/Output
Ñ
Control
Data
TIO0
Input/Output
TIO1
Ñ
Control
Data
TIO1
Input/Output
TIO2
Ñ-
Control
Data
TIO2
Input/Output
HREQ/TRQ
HREQ/TRQ
HACK/RRQ
HACK/RRQ
HRW/RD
HRW/RD
HDS/WR
HDS/WR
SCK0
Ñ
Control
Data
Input/Output
Ñ
Control
Data
Input/Output
Ñ
Control
Data
Input/Output
Ñ
Input/Output
Ñ
Control
Data
Control
Data
SCK0
Input/Output
Ñ
SCK1
Control
11-16
DSP56309UM/D
MOTOROLA
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JTAG Port
DSP56309 Boundary Scan Register
Table 11-2 DSP56309 BSR Bit Definitions (Continued)
Bit #
Cell Type
Signal Name
Signal Type
BSR Cell Type
94
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
SCK1
GPIO2
GPIO2
GPIO1
GPIO1
GPIO0
GPIO0
SC00
SC00
SC10
SC10
STD0
STD0
SRD0
SRD0
PINIT
PINIT
DE
Input/Output
Data
Control
Data
95
Ñ
96
Input/Output
97
Ñ
Control
Data
98
Input/Output
99
Ñ
Control
Data
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
Input/Output
Ñ
Control
Data
Input/Output
Ñ
Control
Data
Input/Output
Ñ
Control
Data
Input/Output
Ñ
Control
Data
Input/Output
Ñ
Control
Data
Input/Output
Ñ
Control
Data
DE
Input/Output
SC01
SC01
SC02
SC02
STD1
Ñ
Input/Output
Ñ
Control
Data
Control
Data
Input/Output
Ñ
Control
MOTOROLA
DSP56309UM/D
11-17
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JTAG Port
DSP56309 Boundary Scan Register
Table 11-2 DSP56309 BSR Bit Definitions (Continued)
Bit #
Cell Type
Signal Name
Signal Type
BSR Cell Type
118
119
120
121
122
123
BC_6
BC_1
BC_6
BC_1
BC_6
BC_1
STD1
SRD1
SRD1
SC11
SC11
SC12
Input/Output
Data
Control
Data
Ñ
Input/Output
Ñ
Control
Data
Input/Output
Ñ
Control
11-18
DSP56309UM/D
MOTOROLA
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APPENDIX A
BOOTSTRAP PROGRAMS
; BOOTSTRAP CODE FOR DSP56309 - (C) Copyright 1998 Motorola Inc.
DSP56302 - (C) Copyright 1995 Motorola Inc.
; Revised March, 1998.
June, 29 1995.
;
; Bootstrap through the Host Interface, External EPROM or SCI.
;
; This is the Bootstrap program contained in the DSP56309 192-word Boot
DSP56302 192-word Boot
; ROM. This program can load any program RAM segment from an external
; EPROM, from the Host Interface or from the SCI serial interface.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; If MD:MC:MB:MA=1000, then the Boot ROM is bypassed and the DSP56309 will
DSP56302 will
; start fetching instructions beginning with the address $8000 assuming
that
; an external memory of SRAM type is used. The accesses will be performed
; using 31 wait states with no address attributes selected (default area).
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Bootstrap Programs
; BOOTSTRAP CODE FOR DSP56309 - (C) Copyright 1997 Motorola Inc.
; Revised March, 18 1997.
;
; Bootstrap through the Host Interface, External EPROM or SCI.
;
; This is the Bootstrap program contained in the DSP56309 192-word Boot
; ROM. This program can load any program RAM segment from an external
; EPROM, from the Host Interface or from the SCI serial interface.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=x000, then the Boot ROM is bypassed and the DSP56309
; will start fetching instructions beginning with address $C00000 (MD=0)
; or $008000 (MD=1) assuming that an external memory of SRAM type is
; used. The accesses will be performed using 31 wait states with no
; address attributes selected (default area).
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Operation modes MD:MC:MB:MA=0001-0111 are reserved.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=1001, then it loads a program RAM segment from consecutive
; byte-wide P memory locations, starting at P:$D00000 (bits 7-0).
; The memory is selected by the Address Attribute AA1 and is accessed with
; 31 wait states.
; The EPROM bootstrap code expects to read 3 bytes
; specifying the number of program words, 3 bytes specifying the address
; to start loading the program words and then 3 bytes for each program
; word to be loaded. The number of words, the starting address and the
; program words are read least significant byte first followed by the
; mid and then by the most significant byte.
; The program words will be condensed into 24-bit words and stored in
; contiguous PRAM memory locations starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=1010, then it loads the program RAM from the SCI interface.
; The number of program words to be loaded and the starting address must
; be specified. The SCI bootstrap code expects to receive 3 bytes
; specifying the number of program words, 3 bytes specifying the address
; to start loading the program words and then 3 bytes for each program
; word to be loaded. The number of words, the starting address and the
; program words are received least significant byte first followed by the
; mid and then by the most significant byte. After receiving the
; program words, program execution starts in the same address where
; loading started. The SCI is programmed to work in asynchronous mode
; with 8 data bits, 1 stop bit and no parity. The clock source is
; external and the clock frequency must be 16x the baud rate.
; After each byte is received, it is echoed back through the SCI
A-2
DSP56309UM/D
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Bootstrap Programs
; transmitter.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Operation mode MD:MC:MB:MA=1011 is reserved.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=1100, then it loads the program RAM from the Host
; Interface programmed to operate in the ISA mode.
; The HOST ISA bootstrap code expects to read a 24-bit word
; specifying the number of program words, a 24-bit word specifying the address
; to start loading the program words and then a 24-bit word for each program
; word to be loaded. The program words will be stored in
; contiguous PRAM memory locations starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by
; setting the Host Flag 0 (HF0). This will start execution of the loaded
; program from the specified starting address.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=1101, then it loads the program RAM from the Host
; Interface programmed to operate in the HC11 non multiplexed mode.
;
; The HOST HC11 bootstrap code expects to read a 24-bit word
; specifying the number of program words, a 24-bit word specifying the address
; to start loading the program words and then a 24-bit word for each program
; word to be loaded. The program words will be stored in
; contiguous PRAM memory locations starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by
; setting the Host Flag 0 (HF0). This will start execution of the loaded
; program from the specified starting address.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=1110, then it loads the program RAM from the Host
; Interface programmed to operate in the 8051 multiplexed bus mode,
; in double-strob pin configuration.
; The HOST 8051 bootstrap code expects accesses that are byte wide.
; The HOST 8051 bootstrap code expects to read 3 bytes forming a 24-bit word
; specifying the number of program words, 3 bytes forming a 24-bit word
; specifying the address to start loading the program words and then 3 bytes
; forming 24-bit words for each program word to be loaded.
; The program words will be stored in contiguous PRAM memory locations
; starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by setting the
; Host Flag 0 (HF0). This will start execution of the loaded program from
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Bootstrap Programs
; the specified starting address.
;
; The base address of the HI08 in multiplexed mode is 0x80 and is not
; modified by the bootstrap code. All the address lines are enabled
; and should be connected accordingly.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=1111, then it loads the program RAM from the Host
; Interface programmed to operate in the MC68302 (IMP) bus mode,
; in single-strob pin configuration.
; The HOST MC68302 bootstrap code expects accesses that are byte wide.
; The HOST MC68302 bootstrap code expects to read 3 bytes forming a 24-bit word
; specifying the number of program words, 3 bytes forming a 24-bit word
; specifying the address to start loading the program words and then 3 bytes
; forming 24-bit words for each program word to be loaded.
; The program words will be stored in contiguous PRAM memory locations
; starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by setting the
; Host Flag 0 (HF0). This will start execution of the loaded program from
; the specified starting address.
;
;;;;;;;;;;;;;;;;;;;; MEMORY EQUATES ;;;;;;;;;;;;;;;;;;;;;;;;
page
132,55,0,0,0
opt
mex
EQUALDATA
equ
1
;; 1 if xram and yram are of equal
;; size and addresses, 0 otherwise.
if
start_dram
length_dram
else
(EQUALDATA)
equ
equ
0
;; 24k X and Y RAM
$1c00 ;; same addresses
start_xram
length_xram
start_yram
length_yram
endif
equ
equ
equ
equ
0
;; 7k XRAM
;; 7k YRAM
$1c00
0
$1c00
start_pram
length_pram
equ
equ
0
;; 20k PRAM
$5000
;;
;;;;;;;;;;;;;;;;;;;; GENERAL EQUATES ;;;;;;;;;;;;;;;;;;;;;;;;
;;
BOOT
equ
$D00000
; this is the location in P memory
; on the external memory bus
; where the external byte-wide
; EPROM would be located
A-4
DSP56309UM/D
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Bootstrap Programs
AARV
;;
equ
$D00409
; AAR1 selects the EPROM as CE~
; mapped as P from $D00000 to
; $DFFFFF, active low
;;;;;;;;;;;;;;;;;;;; DSP I/O REGISTERS ;;;;;;;;;;;;;;;;;;;;;;;;
;;
M_PDRC EQU
M_PRRC EQU
M_SSR EQU
M_STXL EQU
M_SRXL EQU
M_SCCR EQU
M_SCR EQU
M_PCRE EQU
M_AAR1 EQU
M_HPCR EQU
M_HSR EQU
M_HRX EQU
$FFFFBD
$FFFFBE
$FFFF93
$FFFF95
$FFFF98
$FFFF9B
$FFFF9C
$FFFF9F
$FFFFF8
$FFFFC4
$FFFFC3
$FFFFC6
$0
;; Port C GPIO Data Register
;; Port C Direction Register
; SCI Status Register
; SCI Transmit Data Register (low)
; SCI Receive Data Register (low)
; SCI Clock Control Register
; SCI Control Register
; Port E Control register
; Address Attribute Register 1
; Host Polarity Control Register
; Host Status Rgister
; Host Recceive Register
; Host Receive Data Full
; Host Flag 0
HRDF
HF0
EQU
EQU
EQU
EQU
$3
$6
$3
HEN
; Host Enable
;; SCK0 is bit #3 as GPIO
SCK0
ORG PL:$ff0000,PL:$ff0000
; bootstrap code starts at $ff0000
START
clr a
; clear a
jclr #3,omr,OMR0XXX
jclr #2,omr,EPRSCILD
jclr #1,omr,OMR1IS0
; If MD:MC:MB:MA=0xxx, go to OMR0XXX
; If MD:MC:MB:MA=10xx, load from EPROM/SCI
; IF MD:MC:MB:MA=110x, look for ISA/HC11
jclr #0,omr,I8051HOSTLD ; If MD:MC:MB:MA=1110, load from 8051 Host
; If MD:MC:MB:MA=1111, load from MC68302 Host
;========================================================================
; This is the routine which loads a program through the HI08 host port
; The program is downloaded from the host MCU with the following rules:
; 1) 3 bytes - Define the program length.
; 2) 3 bytes - Define the address to which to start loading the program to.
; 3) 3n bytes (while n is any integer number)
; The program words will be stroed in contiguous PRAM memory locations starting
; at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The host MCU may terminate the loading process by setting the HF1=0 and HF0=1.
; When the downloading is terminated, the program will start execution of the
; loaded program from the specified starting address.
; The HI08 boot ROM program enables the following busses to download programs
; through the HI08 port:
;
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Bootstrap Programs
;
;
;
;
;
;
;
;
1 - ISA
- Dual strobes non-multiplexed bus with negative strobe
pulses duale positive request
- Single strobe non-multiplexed bus with positive strobe
pulse single negative request.
- Dual strobes multiplexed bus with negative strobe pulses
dual negative request.
- Single strobe non-multiplexed bus with negative strobe
pulse single negative request.
2 - HC11
4 - i8051
5 - MC68302
;========================================================================
MC68302HOSTLD
movep #%0000000000111000,x:M_HPCR
; Configure the following conditions:
; HAP = 0 Negative host acknowledge
; HRP = 0 Negative host request
; HCSP = 0 Negatice chip select input
; HD/HS = 0 Single strobe bus (R/W~ and DS)
; HMUX = 0 Non multiplexed bus
; HASP = 0 (address strobe polarity has no
;
meaning in non-multiplexed bus)
; HDSP = 0 Negative data stobes polarity
; HROD = 0 Host request is active when enabled
; spare = 0 This bit should be set to 0 for
;
future compatability
; HEN = 0 When the HPCR register is modified
HEN should be cleared
;
; HAEN = 1 Host acknowledge is enabled
; HREN = 1 Host requests are enabled
; HCSEN = 1 Host chip select input enabled
; HA9EN = 0 (address 9 enable bit has no
;
meaning in non-multiplexed bus)
; HA8EN = 0 (address 8 enable bit has no
meaning in non-multiplexed bus)
; HGEN = 0 Host GPIO pins are disabled
;
bra
<HI08CONT
OMR1IS0
jset #0,omr,HC11HOSTLD ; If MD:MC:MB:MA=1101, go load from HC11 Host
; If MD:MC:MB:MA=1100, go load from ISA HOST
ISAHOSTLD
movep #%0101000000011000,x:M_HPCR
; Configure the following conditions:
; HAP = 0 Negative host acknowledge
; HRP = 1 Positive host request
; HCSP = 0 Negatice chip select input
; HD/HS = 1 Dual strobes bus (RD and WR)
; HMUX = 0 Non multiplexed bus
; HASP = 0 (address strobe polarity has no
;
meaning in non-multiplexed bus)
; HDSP = 0 Negative data stobes polarity
; HROD = 0 Host request is active when enabled
; spare = 0 This bit should be set to 0 for
;
future compatability
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Bootstrap Programs
; HEN = 0 When the HPCR register is modified
HEN should be cleared
;
; HAEN = 0 Host acknowledge is disabled
; HREN = 1 Host requests are enabled
; HCSEN = 1 Host chip select input enabled
; HA9EN = 0 (address 9 enable bit has no
;
meaning in non-multiplexed bus)
; HA8EN = 0 (address 8 enable bit has no
meaning non-multiplexed bus)
; HGEN = 0 Host GPIO pins are disabled
;
bra
HC11HOSTLD
movep #%0000001000011000,x:M_HPCR
; Configure the following conditions:
<HI08CONT
; HAP = 0 Negative host acknowledge
; HRP = 0 Negative host request
; HCSP = 0 Negatice chip select input
; HD/HS = 0 Single strobe bus (R/W~ and DS)
; HMUX = 0 Non multiplexed bus
; HASP = 0 (address strobe polarity has no
;
meaning in non-multiplexed bus)
; HDSP = 1 Negative data stobes polarity
; HROD = 0 Host request is active when enabled
; spare = 0 This bit should be set to 0 for
;
future compatability
; HEN = 0 When the HPCR register is modified
HEN should be cleared
;
; HAEN = 0 Host acknowledge is disabled
; HREN = 1 Host requests are enabled
; HCSEN = 1 Host chip select input enabled
; HA9EN = 0 (address 9 enable bit has no
;
meaning in non-multiplexed bus)
; HA8EN = 0 (address 8 enable bit has no
meaning in non-multiplexed bus)
; HGEN = 0 Host GPIO pins are disabled
;
bra
<HI08CONT
I8051HOSTLD
movep #%0001110000011110,x:M_HPCR
; Configure the following conditions:
; HAP = 0 Negative host acknowledge
; HRP = 0 Negatice host request
; HCSP = 0 Negatice chip select input
; HD/HS = 1 Dual strobes bus (RD and WR)
; HMUX = 1 Multiplexed bus
; HASP = 1 Positive address strobe polarity
; HDSP = 0 Negative data stobes polarity
; HROD = 0 Host request is active when enabled
; spare = 0 This bit should be set to 0 for
;
future compatability
; HEN = 0 When the HPCR register is modified
HEN should be cleared
;
; HAEN = 0 Host acknowledge is disabled
; HREN = 1 Host requests are enabled
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Bootstrap Programs
; HCSEN = 1 Host chip select input enabled
; HA9EN = 1 Enable address 9 input
; HA8EN = 1 Enable address 8 input
; HGEN = 0 Host GPIO pins are disabled
HI08CONT
bset
#HEN,x:M_HPCR
#HRDF,x:M_HSR,*
; Enable the HI08 to operate as host
; interface (set HEN=1)
; wait for the program length to be
; written
jclr
movep x:M_HRX,a0
jclr
#HRDF,x:M_HSR,*
; wait for the program starting address
; to be written
movep x:M_HRX,r0
move
do
r0,r1
a0,HI08LOOP
; set a loop with the downloaded length
HI08LL
jset
jclr
#HRDF,x:M_HSR,HI08NW
#HF0,x:M_HSR,HI08LL
; If new word was loaded then jump to
; read that word
; If HF0=0 then continue with the
; downloading
enddo
bra
; Must terminate the do loop
<HI08LOOP
HI08NW
movep x:M_HRX,p:(r0)+
nop
; Move the new word into its destination
; location in the program RAM
; pipeline delay
HI08LOOP
bra
<FINISH
;========================================================================
EPRSCILD
jclr #1,omr,EPROMLD
jset #0,omr,SCILD
; If MD:MC:MB:MA=1001, go load from EPROM
; If MD:MC:MB:MA=1011, reserved, default to SCI
;
;========================================================================
; This is the routine that loads from the SCI.
; MD:MC:MB:MA=1010 - external SCI clock
SCILD
movep #$0302,X:M_SCR
; Configure SCI Control Reg
movep #$C000,X:M_SCCR ; Configure SCI Clock Control Reg
movep #7,X:M_PCRE
do #6,_LOOP6
; Configure SCLK, TXD and RXD
; get 3 bytes for number of
; program words and 3 bytes
; for the starting address
; Wait for RDRF to go high
; Put 8 bits in A2
jclr #2,X:M_SSR,*
movep X:M_SRXL,A2
jclr #1,X:M_SSR,*
movep A2,X:M_STXL
asr #8,a,a
; Wait for TDRE to go high
; echo the received byte
_LOOP6
move a1,r0
; starting address for load
A-8
DSP56309UM/D
MOTOROLA
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Bootstrap Programs
move a1,r1
; save starting address
; Receive program words
do a0,_LOOP7
do #3,_LOOP8
jclr #2,X:M_SSR,*
movep X:M_SRXL,A2
jclr #1,X:M_SSR,*
movep a2,X:M_STXL
asr #8,a,a
; Wait for RDRF to go high
; Put 8 bits in A2
; Wait for TDRE to go high
; echo the received byte
_LOOP8
_LOOP7
movem a1,p:(r0)+
nop
; Store 24-bit result in P mem.
; pipeline delay
bra <FINISH
; Boot from SCI done
;========================================================================
; This is the routine that loads from external EPROM.
; MD:MC:MB:MA=1001
EPROMLD
move #BOOT,r2
; r2 = address of external EPROM
movep #AARV,X:M_AAR1
; aar1 configured for SRAM types of access
do #6,_LOOP9
movem p:(r2)+,a2
asr #8,a,a
; read number of words and starting address
; Get the 8 LSB from ext. P mem.
; Shift 8 bit data into A1
;
_LOOP9
move a1,r0
move a1,r1
; starting address for load
; save it in r1
; a0 holds the number of words
do a0,_LOOP10
do #3,_LOOP11
movem p:(r2)+,a2
asr #8,a,a
; read program words
; Each instruction has 3 bytes
; Get the 8 LSB from ext. P mem.
; Shift 8 bit data into A1
; Go get another byte.
_LOOP11
_LOOP10
movem a1,p:(r0)+
nop
; Store 24-bit result in P mem.
; pipeline delay
; and go get another 24-bit word.
; Boot from EPROM done
;========================================================================
FINISH
; This is the exit handler that returns execution to normal
; expanded mode and jumps to the RESET vector.
andi #$0,ccr
jmp (r1)
; Clear CCR as if RESET to 0.
; Then go to starting Prog addr.
;========================================================================
; The following modes are reserved, some of which are used for internal testing
MOTOROLA
DSP56309UM/D
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A-9
Freescale Semiconductor, Inc.
Bootstrap Programs
; Can be implemented in future.
;
OMR0XXX
jclr #2,omr,EPRSCILD
jclr #1,omr,OMR1IS0
; If MD:MC:MB:MA=00xx, default to EPROM/SCI
; IF MD:MC:MB:MA=010x, default to ISA/HC11
jclr #0,omr,I8051HOSTLD ; If MD:MC:MB:MA=0110, default to 8051 Host
; If MD:MC:MB:MA=0111, execute burnin test
;========================================================================
; This mode is reserved for internal testing purposes
; MD:MC:MB:MA=0111
;;---------------------------------------------------------
;;
;; burnin mode
;;
;; Intended to be used for burn-in test. Wake up from reset
;; with PINIT set for execution in maximum frequency.
;; All RAM locations are validated, arithmetic/logic operations
;; are validated (add, eor) and exercised (mac).
;; While all tests pass, the SCK0 pin will continue to toggle.
;; When the test fails the DSP enters DEBUG and stops execution.
;;
;;---------------------------------------------------------
;; get PATTERN pointer
clr b #PATTERNS,r6
;; b is the error accumulator
move
#<(NUM_PATTERNS-1),m6 ;; program runs forever in
;; cyclic form
;; configure SCK0 as gpio output. PRRC register is cleared at reset.
movep b,x:M_PDRC
;; clear GPIO data register
bset
#SCK0,x:M_PRRC
;; Define SCK0 as output GPIO pin
;; SCK0 toggles means test pass
do #9,burn1
;;----------------------------
;; test RAM
;; each pass checks 1 pattern
;;----------------------------
move
move
move
p:(r6)+,x1
p:(r6)+,x0
p:(r6)+,y0
;; pattern for x memory
;; pattern for y memory
;; pattern for p memory
;; write pattern to all memory locations
if
(EQUALDATA)
;; x/y ram symmetrical
;; write x and y memory
clr a #start_dram,r0
;; start of x/y ram
;; length of x/y ram
move
rep
#>length_dram,n0
n0
mac x0,x1,a x,l:(r0)+
;; exercise mac, write x/y ram
A-10
DSP56309UM/D
MOTOROLA
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Bootstrap Programs
else
;; x/y ram not symmetrical
;; write x memory
clr a #start_xram,r0
;; start of xram
;; length of xram
move
rep
#>length_xram,n0
n0
mac x0,y0,a x1,x:(r0)+
;; exercise mac, write xram
;; write y memory
clr a #start_yram,r1
;; start of yram
;; length of yram
move
rep
#>length_yram,n1
n1
mac x1,y0,a x0,y:(r1)+
;; exercise mac, write yram
endif
;; write p memory
clr a #start_pram,r2
;; start of pram
;; length of pram
move
rep
#>length_pram,n2
n2
move
y0,p:(r2)+
;; write pram
;; check memory contents
(EQUALDATA)
if
;; x/y ram symmetrical
;; check dram
clr a #start_dram,r0
;; restore pointer, clear a
;; a0=a2=0
do
n0,_loopd
x:(r0),a1
x1,a
move
eor
add
move
eor
add
a,b
;; accumulate error in b
;; a0=a2=0
y:(r0)+,a1
x0,a
a,b
;; accumulate error in b
;; x/y ram not symmetrical
_loopd
else
;; check xram
clr a #start_xram,r0
;; restore pointer, clear a
;; a0=a2=0
do
n0,_loopx
x:(r0)+,a1
x1,a
move
eor
add
a,b
;; accumulate error in b
_loopx
;; check yram
clr a #start_yram,r1
;; restore pointer, clear a
;; a0=a2=0
do
n1,_loopy
y:(r1)+,a1
x0,a
move
eor
add
a,b
;; accumulate error in b
MOTOROLA
DSP56309UM/D
A-11
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Freescale Semiconductor, Inc.
Bootstrap Programs
_loopy
endif
;; check pram
clr a #start_pram,r2
;; restore pointer, clear a
;; a0=a2=0
do
n2,_loopp
p:(r2)+,a1
y0,a
move
eor
add
a,b
;; accumulate error in b
_loopp
;;---------------------------------------------------
;; toggle pin if no errors, stop execution otherwise.
;;---------------------------------------------------
beq
label1
bclr
enddo
bra
#SCK0,x:M_PDRC
;; clear sck0 if error,
;; terminate the loop normally
;; and stop execution
<burn1
label1
burn1
;; if no error
;; toggle pin and keep on looping
bchg
wait
#SCK0,x:M_PDRC
;; enter wait after test completion
;; align for correct modulo addressing
ORG PL:,PL:
dsm
ORG
PATTERNS
4
PL:PATTERNS,PL:PATTERNS ;; Each value is written to all memories
dc
dc
dc
dc
$555555
$AAAAAA
$333333
$F0F0F0
NUM_PATTERNS
equ
end
*-PATTERNS
A-12
DSP56309UM/D
MOTOROLA
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APPENDIX B
EQUATES
;*****************************************************************************
;
;
;
;
;
EQUATES for DSP56309 I/O registers and ports
56302 I/O registers and ports
Last update: March 1998
June 1 1995
;*****************************************************************************
page
opt
132,55,0,0,0
mex
ioequ ident 1,0
;------------------------------------------------------------------------
MOTOROLA
DSP56309UM/D
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B-1
Freescale Semiconductor, Inc.
Equates
B.1
B.2
B.3
I/O EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
HOST INTERFACE (HI08) EQUATES . . . . . . . . . . . . . . . . . B-3
SCI EQUATES
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
ESSI EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
EXCEPTION PROCESSING EQUATES. . . . . . . . . . . . . . . . B-7
TIMER MODULE EQUATES. . . . . . . . . . . . . . . . . . . . . . . . . B-9
DIRECT MEMORY ACCESS (DMA) EQUATES. . . . . . . . . B-10
PHASE-LOCKED LOOP (PLL) EQUATES . . . . . . . . . . . . . B-12
BUS INTERFACE UNIT (BIU) EQUATES. . . . . . . . . . . . . . B-13
INTERRUPT EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15
B.4
B.5
B.6
B.7
B.8
B.9
B.10
B-2
DSP56309UM/D
MOTOROLA
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Equates
B.1
I/O EQUATES
;------------------------------------------------------------------------
;
;I/O Port Programming
;
;------------------------------------------------------------------------
;
Register Addresses
M_HDR
EQU
$FFFFC9
$FFFFC8
$FFFFBF
$FFFFBE
$FFFFBD
$FFFFAF
$FFFFAE
$FFFFAD
$FFFF9F
$FFFF9E
$FFFF9D
$FFFFFC
; Host port GPIO data Register
; Host port GPIO direction Register
; Port C Control Register
; Port C Direction Register
; Port C GPIO Data Register
; Port D Control register
; Port D Direction Data Register
; Port D GPIO Data Register
; Port E Control register
; Port E Direction Register
; Port E Data Register
M_HDDR EQU
M_PCRC EQU
M_PRRC EQU
M_PDRC EQU
M_PCRD EQU
M_PRRD EQU
M_PDRD EQU
M_PCRE EQU
M_PRRE EQU
M_PDRE EQU
M_OGDB EQU
; OnCE GDB Register
B.2
HOST INTERFACE (HI08) EQUATES
;------------------------------------------------------------------------
Host Interface (HI08) Equates
;------------------------------------------------------------------------
;
Register Addresses
M_HCR
M_HSR
M_HPCR EQU
M_HBAR EQU
M_HRX
M_HTX
EQU
EQU
$FFFFC2
$FFFFC3
$FFFFC4
$FFFFC5
$FFFFC6
$FFFFC7
; Host Control Register
; Host Status Register
; Host Polarity Control Register
; Host Base Address Register
; Host Receive Register
EQU
EQU
; Host Transmit Register
;
HCR bits definition
M_HRIE EQU
M_HTIE EQU
M_HCIE EQU
$0
$1
$2
$3
$4
; Host Receive interrupts Enable
; Host Transmit Interrupt Enable
; Host Command Interrupt Enable
; Host Flag 2
M_HF2
M_HF3
EQU
EQU
; Host Flag 3
;
HSR bits definition
M_HRDF EQU
M_HTDE EQU
$0
$1
$2
; Host Receive Data Full
; Host Receive Data Empty
; Host Command Pending
M_HCP
EQU
MOTOROLA
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B-3
Freescale Semiconductor, Inc.
Equates
M_HF0
M_HF1
EQU
EQU
$3
$4
; Host Flag 0
; Host Flag 1
;
HPCR bits definition
M_HGEN EQU
M_HA8EN EQU
M_HA9EN EQU
M_HCSEN EQU
M_HREN EQU
M_HAEN EQU
$0
$1
$2
$3
$4
$5
$6
$8
$9
$A
$B
$C
$D
$E
$F
; Host Port GPIO Enable
; Host Address 8 Enable
; Host Address 9 Enable
; Host Chip Select Enable
; Host Request Enable
; Host Acknowledge Enable
; Host Enable
M_HEN
M_HOD
EQU
EQU
; Host Request Open Drain mode
; Host Data Strobe Polarity
; Host Address Strobe Polarity
; Host Multiplexed bus select
; Host Double/Single Strobe select
; Host Chip Select Polarity
; Host Request Polarity
M_HDSP EQU
M_HASP EQU
M_HMUX EQU
M_HD_HS EQU
M_HCSP EQU
M_HRP
M_HAP
EQU
EQU
; Host Acknowledge Polarity
B.3
SCI EQUATES
;------------------------------------------------------------------------
;Serial Communications Interface (SCI) Equates
;------------------------------------------------------------------------
;
Register Addresses
M_STXH EQU
M_STXM EQU
M_STXL EQU
M_SRXH EQU
M_SRXM EQU
M_SRXL EQU
M_STXA EQU
$FFFF97
$FFFF96
$FFFF95
$FFFF9A
$FFFF99
$FFFF98
$FFFF94
$FFFF9C
$FFFF93
$FFFF9B
; SCI Transmit Data Register (high)
; SCI Transmit Data Register (middle)
; SCI Transmit Data Register (low)
; SCI Receive Data Register (high)
; SCI Receive Data Register (middle)
; SCI Receive Data Register (low)
; SCI Transmit Address Register
; SCI Control Register
M_SCR
M_SSR
EQU
EQU
; SCI Status Register
; SCI Clock Control Register
M_SCCR EQU
;
SCI Control Register Bit Flags
M_WDS
EQU
$7
0
1
2
3
; Word Select Mask (WDS0-WDS3)
; Word Select 0
; Word Select 1
; Word Select 2
; SCI Shift Direction
; Send Break
M_WDS0 EQU
M_WDS1 EQU
M_WDS2 EQU
M_SSFTD EQU
M_SBK
EQU
4
M_WAKE EQU
5
; Wakeup Mode Select
B-4
DSP56309UM/D
MOTOROLA
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Equates
M_RWU
EQU
6
7
8
9
10
11
12
13
14
15
16
; Receiver Wakeup Enable
; Wired-OR Mode Select
; SCI Receiver Enable
; SCI Transmitter Enable
; Idle Line Interrupt Enable
; SCI Receive Interrupt Enable
; SCI Transmit Interrupt Enable
; Timer Interrupt Enable
; Timer Interrupt Rate
M_WOMS EQU
M_SCRE EQU
M_SCTE EQU
M_ILIE EQU
M_SCRIE EQU
M_SCTIE EQU
M_TMIE EQU
M_TIR
M_SCKP EQU
M_REIE EQU
EQU
; SCI Clock Polarity
; SCI Error Interrupt Enable (REIE)
;
SCI Status Register Bit Flags
M_TRNE EQU
M_TDRE EQU
M_RDRF EQU
M_IDLE EQU
0
1
2
3
4
5
6
7
; Transmitter Empty
; Transmit Data Register Empty
; Receive Data Register Full
; Idle Line Flag
; Overrun Error Flag
; Parity Error
M_OR
M_PE
M_FE
M_R8
EQU
EQU
EQU
EQU
; Framing Error Flag
; Received Bit 8 (R8) Address
;
SCI Clock Control Register
M_CD
EQU
EQU
EQU
EQU
EQU
$FFF
12
13
14
15
; Clock Divider Mask (CD0-CD11)
; Clock Out Divider
; Clock Prescaler
; Receive Clock Mode Source Bit
; Transmit Clock Source Bit
M_COD
M_SCP
M_RCM
M_TCM
B.4
ESSI EQUATES
;------------------------------------------------------------------------
;Enhanced Synchronous Serial Interface (ESSI) Equates
;------------------------------------------------------------------------
;
Register Addresses Of SSI0
M_TX00 EQU
M_TX01 EQU
M_TX02 EQU
M_TSR0 EQU
$FFFFBC
$FFFFBB
$FFFFBA
$FFFFB9
$FFFFB8
$FFFFB7
$FFFFB6
$FFFFB5
$FFFFB4
$FFFFB3
; SSI0 Transmit Data Register 0
; SSIO Transmit Data Register 1
; SSIO Transmit Data Register 2
; SSI0 Time Slot Register
; SSI0 Receive Data Register
; SSI0 Status Register
; SSI0 Control Register B
; SSI0 Control Register A
; SSI0 Transmit Slot Mask Register A
; SSI0 Transmit Slot Mask Register B
M_RX0
EQU
M_SSISR0 EQU
M_CRB0 EQU
M_CRA0 EQU
M_TSMA0 EQU
M_TSMB0 EQU
MOTOROLA
DSP56309UM/D
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B-5
Freescale Semiconductor, Inc.
Equates
M_RSMA0 EQU
M_RSMB0 EQU
$FFFFB2
$FFFFB1
; SSI0 Receive Slot Mask Register A
; SSI0 Receive Slot Mask Register B
;
Register Addresses Of SSI1
M_TX10 EQU
M_TX11 EQU
M_TX12 EQU
M_TSR1 EQU
$FFFFAC
$FFFFAB
$FFFFAA
$FFFFA9
$FFFFA8
$FFFFA7
$FFFFA6
$FFFFA5
$FFFFA4
$FFFFA3
$FFFFA2
$FFFFA1
; SSI1 Transmit Data Register 0
; SSI1 Transmit Data Register 1
; SSI1 Transmit Data Register 2
; SSI1 Time Slot Register
; SSI1 Receive Data Register
; SSI1 Status Register
; SSI1 Control Register B
; SSI1 Control Register A
; SSI1 Transmit Slot Mask Register A
; SSI1 Transmit Slot Mask Register B
; SSI1 Receive Slot Mask Register A
; SSI1 Receive Slot Mask Register B
M_RX1
EQU
M_SSISR1 EQU
M_CRB1 EQU
M_CRA1 EQU
M_TSMA1 EQU
M_TSMB1 EQU
M_RSMA1 EQU
M_RSMB1 EQU
;
SSI Control Register A Bit Flags
M_PM
M_PSR
M_DC
M_ALC
M_WL
EQU
EQU
EQU
EQU
EQU
$FF
11
$1F000
18
$380000
22
; Prescale Modulus Select Mask (PM0-PM7)
; Prescaler Range
; Frame Rate Divider Control Mask (DC0-DC7)
; Alignment Control (ALC)
; Word Length Control Mask (WL0-WL7)
; Select SC1 as TR #0 drive enable (SSC1)
M_SSC1 EQU
;
SSI Control Register B Bit Flags
M_OF
EQU
EQU
EQU
EQU
$3
0
1
$1C
2
3
4
5
6
; Serial Output Flag Mask
; Serial Output Flag 0
; Serial Output Flag 1
; Serial Control Direction Mask
; Serial Control 0 Direction
; Serial Control 1 Direction
; Serial Control 2 Direction
; Clock Source Direction
; Shift Direction
M_OF0
M_OF1
M_SCD
M_SCD0 EQU
M_SCD1 EQU
M_SCD2 EQU
M_SCKD EQU
M_SHFD EQU
M_FSL
M_FSL0 EQU
M_FSL1 EQU
EQU
$180
7
8
; Frame Sync Length Mask (FSL0-FSL1)
; Frame Sync Length 0
; Frame Sync Length 1
M_FSR
M_FSP
M_CKP
M_SYN
M_MOD
M_SSTE EQU
M_SSTE2 EQU
M_SSTE1 EQU
M_SSTE0 EQU
M_SSRE EQU
M_SSTIE EQU
M_SSRIE EQU
EQU
EQU
EQU
EQU
EQU
9
; Frame Sync Relative Timing
; Frame Sync Polarity
; Clock Polarity
; Sync/Async Control
; SSI Mode Select
; SSI Transmit enable Mask
; SSI Transmit #2 Enable
; SSI Transmit #1 Enable
; SSI Transmit #0 Enable
; SSI Receive Enable
10
11
12
13
$1C000
14
15
16
17
18
19
; SSI Transmit Interrupt Enable
; SSI Receive Interrupt Enable
B-6
DSP56309UM/D
MOTOROLA
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Equates
M_STLIE EQU
M_SRLIE EQU
M_STEIE EQU
M_SREIE EQU
20
21
22
23
; SSI Transmit Last Slot Interrupt Enable
; SSI Receive Last Slot Interrupt Enable
; SSI Transmit Error Interrupt Enable
; SSI Receive Error Interrupt Enable
;
SSI Status Register Bit Flags
M_IF
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$3
0
1
2
3
4
5
6
7
; Serial Input Flag Mask
; Serial Input Flag 0
; Serial Input Flag 1
; Transmit Frame Sync Flag
; Receive Frame Sync Flag
; Transmitter Underrun Error FLag
; Receiver Overrun Error Flag
; Transmit Data Register Empty
; Receive Data Register Full
M_IF0
M_IF1
M_TFS
M_RFS
M_TUE
M_ROE
M_TDE
M_RDF
;
SSI Transmit Slot Mask Register A
$FFFF ; SSI Transmit Slot Bits Mask A (TS0-TS15)
SSI Transmit Slot Mask Register B
M_SSTSB EQU $FFFF ; SSI Transmit Slot Bits Mask B (TS16-TS31)
SSI Receive Slot Mask Register A
M_SSRSA EQU $FFFF ; SSI Receive Slot Bits Mask A (RS0-RS15)
SSI Receive Slot Mask Register B
M_SSRSB EQU $FFFF ; SSI Receive Slot Bits Mask B (RS16-RS31)
M_SSTSA EQU
;
;
;
B.5
EXCEPTION PROCESSING EQUATES
;------------------------------------------------------------------------
Exception Processing Equates
;------------------------------------------------------------------------
;
Register Addresses
M_IPRC EQU
M_IPRP EQU
$FFFFFF
$FFFFFE
; Interrupt Priority Register Core
; Interrupt Priority Register Peripheral
;
Interrupt Priority Register Core (IPRC)
M_IAL
EQU
$7
0
1
; IRQA Mode Mask
M_IAL0 EQU
M_IAL1 EQU
M_IAL2 EQU
; IRQA Mode Interrupt Priority Level (low)
; IRQA Mode Interrupt Priority Level (high)
; IRQA Mode Trigger Mode
2
M_IBL
EQU
$38
; IRQB Mode Mask
MOTOROLA
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Equates
M_IBL0 EQU
M_IBL1 EQU
M_IBL2 EQU
3
4
5
; IRQB Mode Interrupt Priority Level (low)
; IRQB Mode Interrupt Priority Level (high)
; IRQB Mode Trigger Mode
M_ICL
EQU
$1C0
6
7
; IRQC Mode Mask
M_ICL0 EQU
M_ICL1 EQU
M_ICL2 EQU
; IRQC Mode Interrupt Priority Level (low)
; IRQC Mode Interrupt Priority Level (high)
; IRQC Mode Trigger Mode
8
M_IDL
M_IDL0 EQU
;(low)
EQU
$E00
9
; IRQD Mode Mask
; IRQD Mode Interrupt Priority Level
M_IDL1 EQU
;(high)
10
; IRQD Mode Interrupt Priority Level
M_IDL2 EQU
11
; IRQD Mode Trigger Mode
M_D0L
M_D0L0 EQU
M_D0L1 EQU
M_D1L
M_D1L0 EQU
M_D1L1 EQU
M_D2L
M_D2L0 EQU
M_D2L1 EQU
M_D3L
M_D3L0 EQU
M_D3L1 EQU
M_D4L
M_D4L0 EQU
M_D4L1 EQU
M_D5L
M_D5L0 EQU
M_D5L1 EQU
EQU
$3000
12
13
$C000
14
15
$30000
16
17
$C0000
18
19
$300000
20
21
$C00000
22
23
; DMA0 Interrupt priority Level Mask
; DMA0 Interrupt Priority Level (low)
; DMA0 Interrupt Priority Level (high)
; DMA1 Interrupt Priority Level Mask
; DMA1 Interrupt Priority Level (low)
; DMA1 Interrupt Priority Level (high)
; DMA2 Interrupt priority Level Mask
; DMA2 Interrupt Priority Level (low)
; DMA2 Interrupt Priority Level (high)
; DMA3 Interrupt Priority Level Mask
; DMA3 Interrupt Priority Level (low)
; DMA3 Interrupt Priority Level (high)
; DMA4 Interrupt priority Level Mask
; DMA4 Interrupt Priority Level (low)
; DMA4 Interrupt Priority Level (high)
; DMA5 Interrupt priority Level Mask
; DMA5 Interrupt Priority Level (low)
; DMA5 Interrupt Priority Level (high)
EQU
EQU
EQU
EQU
EQU
;
Interrupt Priority Register Peripheral (IPRP)
M_HPL
M_HPL0 EQU
M_HPL1 EQU
M_S0L
M_S0L0 EQU
M_S0L1 EQU
M_S1L
M_S1L0 EQU
M_S1L1 EQU
M_SCL
M_SCL0 EQU
M_SCL1 EQU
EQU
$3
0
1
$C
2
3
$30
4
5
$C0
6
7
; Host Interrupt Priority Level Mask
; Host Interrupt Priority Level (low)
; Host Interrupt Priority Level (high)
; SSI0 Interrupt Priority Level Mask
; SSI0 Interrupt Priority Level (low)
; SSI0 Interrupt Priority Level (high)
; SSI1 Interrupt Priority Level Mask
; SSI1 Interrupt Priority Level (low)
; SSI1 Interrupt Priority Level (high)
; SCI Interrupt Priority Level Mask
; SCI Interrupt Priority Level (low)
; SCI Interrupt Priority Level (high)
; TIMER Interrupt Priority Level Mask
; TIMER Interrupt Priority Level (low)
; TIMER Interrupt Priority Level (high)
EQU
EQU
EQU
M_T0L
M_T0L0 EQU
M_T0L1 EQU
EQU
$300
8
9
B-8
DSP56309UM/D
MOTOROLA
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Equates
B.6
TIMER MODULE EQUATES
;---------------------------------------------------------------
;Timer Module Equates
;---------------------------------------------------------------
;
Register Addresses Of TIMER0
M_TCSR0 EQU
M_TLR0 EQU
M_TCPR0 EQU
M_TCR0 EQU
$FFFF8F
$FFFF8E
$FFFF8D
$FFFF8C
; TIMER0 Control/Status Register
; TIMER0 Load Register
; TIMER0 Compare Register
; TIMER0 Count Register
;
Register Addresses Of TIMER1
M_TCSR1 EQU
M_TLR1 EQU
M_TCPR1 EQU
M_TCR1 EQU
$FFFF8B
$FFFF8A
$FFFF89
$FFFF88
; TIMER1 Control/Status Register
; TIMER1 Load Register
; TIMER1 Compare Register
; TIMER1 Count Register
;
Register Addresses Of TIMER2
M_TCSR2 EQU
M_TLR2 EQU
M_TCPR2 EQU
M_TCR2 EQU
M_TPLR EQU
M_TPCR EQU
$FFFF87
$FFFF86
$FFFF85
$FFFF84
$FFFF83
$FFFF82
; TIMER2 Control/Status Register
; TIMER2 Load Register
; TIMER2 Compare Register
; TIMER2 Count Register
; TIMER Prescaler Load Register
; TIMER Prescaler Count Register
;
Timer Control/Status Register Bit Flags
M_TE
EQU
0
; Timer Enable
M_TOIE EQU
M_TCIE EQU
1
2
$F0
8
9
11
12
13
15
20
21
; Timer Overflow Interrupt Enable
; Timer Compare Interrupt Enable
; Timer Control Mask TC(3:0)
; Inverter Bit
; Timer Restart Mode
; Direction Bit
; Data Input
; Data Output
; Prescaled Clock Enable
; Timer Overflow Flag
; Timer Compare Flag
M_TC
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
M_INV
M_TRM
M_DIR
M_DI
M_DO
M_PCE
M_TOF
M_TCF
;
Timer Prescaler Register Bit Flags
M_PS
M_PS0
M_PS1
EQU
EQU
EQU
$600000
21
22
; Prescaler Source Mask
;
Timer Control Bits
MOTOROLA
DSP56309UM/D
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B-9
Freescale Semiconductor, Inc.
Equates
M_TC0
M_TC1
M_TC2
M_TC3
EQU
EQU
EQU
EQU
4
5
6
7
; Timer Control 0
; Timer Control 1
; Timer Control 2
; Timer Control 3
B.7
DIRECT MEMORY ACCESS (DMA) EQUATES
;------------------------------------------------------------------------
;Direct Memory Access (DMA) Equates
;------------------------------------------------------------------------
;
Register Addresses Of DMA
M_DSTR EQU
M_DOR0 EQU
M_DOR1 EQU
M_DOR2 EQU
M_DOR3 EQU
$FFFFF4
$FFFFF3
$FFFFF2
$FFFFF1
$FFFFF0
; DMA Status Register
; DMA Offset Register 0
; DMA Offset Register 1
; DMA Offset Register 2
; DMA Offset Register 3
;
Register Addresses Of DMA0
M_DSR0 EQU
M_DDR0 EQU
M_DCO0 EQU
M_DCR0 EQU
$FFFFEF
$FFFFEE
$FFFFED
$FFFFEC
; DMA0 Source Address Register
; DMA0 Destination Address Register
; DMA0 Counter
; DMA0 Control Register
;
Register Addresses Of DMA1
M_DSR1 EQU
M_DDR1 EQU
M_DCO1 EQU
M_DCR1 EQU
$FFFFEB
$FFFFEA
$FFFFE9
$FFFFE8
; DMA1 Source Address Register
; DMA1 Destination Address Register
; DMA1 Counter
; DMA1 Control Register
;
Register Addresses Of DMA2
M_DSR2 EQU
M_DDR2 EQU
M_DCO2 EQU
M_DCR2 EQU
$FFFFE7
$FFFFE6
$FFFFE5
$FFFFE4
; DMA2 Source Address Register
; DMA2 Destination Address Register
; DMA2 Counter
; DMA2 Control Register
;
Register Addresses Of DMA4
M_DSR3 EQU
M_DDR3 EQU
M_DCO3 EQU
M_DCR3 EQU
$FFFFE3
$FFFFE2
$FFFFE1
$FFFFE0
; DMA3 Source Address Register
; DMA3 Destination Address Register
; DMA3 Counter
; DMA3 Control Register
;
Register Addresses Of DMA4
B-10
DSP56309UM/D
MOTOROLA
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Equates
M_DSR4 EQU
M_DDR4 EQU
M_DCO4 EQU
M_DCR4 EQU
$FFFFDF
; DMA4 Source Address Register
; DMA4 Destination Address Register
; DMA4 Counter
$FFFFDE
$FFFFDD
$FFFFDC
; DMA4 Control Register
;
Register Addresses Of DMA5
M_DSR5 EQU
M_DDR5 EQU
M_DCO5 EQU
M_DCR5 EQU
$FFFFDB
$FFFFDA
$FFFFD9
$FFFFD8
; DMA5 Source Address Register
; DMA5 Destination Address Register
; DMA5 Counter
; DMA5 Control Register
;
DMA Control Register
EQU $3
M_DSS
; DMA Source Space Mask
;(DSS0-Dss1)
M_DSS0 EQU
M_DSS1 EQU
0
1
$C
; DMA Source Memory space 0
; DMA Source Memory space 1
; DMA Destination Space Mask
M_DDS
EQU
;(DDS-DDS1)
M_DDS0 EQU
M_DDS1 EQU
2
3
$3f0
; DMA Destination Memory Space 0
; DMA Destination Memory Space 1
; DMA Address Mode Mask
M_DAM
EQU
;(DAM5-DAM0)
M_DAM0 EQU
M_DAM1 EQU
M_DAM2 EQU
M_DAM3 EQU
M_DAM4 EQU
M_DAM5 EQU
4
5
6
7
8
9
; DMA Address Mode 0
; DMA Address Mode 1
; DMA Address Mode 2
; DMA Address Mode 3
; DMA Address Mode 4
; DMA Address Mode 5
M_D3D
M_DRS
M_DCON EQU
M_DPR EQU
M_DPR0 EQU
M_DPR1 EQU
EQU
EQU
10
$F800
16
$60000
17
18
; DMA Three Dimensional Mode
; DMA Request Source Mask (DRS0-DRS4)
; DMA Continuous Mode
; DMA Channel Priority
; DMA Channel Priority Level (low)
; DMA Channel Priority Level (high)
M_DTM
EQU
$380000 ; DMA Transfer Mode Mask
;(DTM2-DTM0)
M_DTM0 EQU
M_DTM1 EQU
M_DTM2 EQU
19
20
21
22
23
; DMA Transfer Mode 0
; DMA Transfer Mode 1
; DMA Transfer Mode 2
; DMA Interrupt Enable bit
; DMA Channel Enable bit
M_DIE
M_DE
EQU
EQU
MOTOROLA
DSP56309UM/D
B-11
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Equates
;
DMA Status Register
M_DTD
EQU
$3F
0
1
2
3
4
5
8
;Channel Transfer Done Status MASK
; DMA Channel Transfer Done Status 0
; DMA Channel Transfer Done Status 1
; DMA Channel Transfer Done Status 2
; DMA Channel Transfer Done Status 3
; DMA Channel Transfer Done Status 4
; DMA Channel Transfer Done Status 5
; DMA Active State
M_DTD0 EQU
M_DTD1 EQU
M_DTD2 EQU
M_DTD3 EQU
M_DTD4 EQU
M_DTD5 EQU
M_DACT EQU
M_DCH
EQU
$E00
; DMA Active Channel Mask
;(DCH0DCH2)
M_DCH0 EQU
M_DCH1 EQU
M_DCH2 EQU
9
10
11
; DMA Active Channel 0
; DMA Active Channel 1
; DMA Active Channel 2
B.8
PHASE-LOCKED LOOP (PLL) EQUATES
;---------------------------------------------------------------
;Phase Locked Loop (PLL) equates
;---------------------------------------------------------------
;
Register Addresses Of PLL
M_PCTL EQU $FFFFFD
PLL Control Register
; PLL Control Register
;
M_MF
M_DF
M_XTLR EQU
M_XTLD EQU
M_PSTP EQU
EQU
EQU
$FFF
$7000
15
16
17
; Multiplication Factor Bit Mask (MF0-MF11)
; Division Factor Bit Mask (DF0-DF2)
; XTAL Range select bit
; XTAL Disable Bit
; STOP Processing State Bit
; PLL Enable Bit
M_PEN
EQU
18
M_PCOD EQU
19
$F00000
; PLL Clock Output Disable Bit
; PreDivider Factor Bit Mask (PD0-PD3)
M_PD
EQU
B-12
DSP56309UM/D
MOTOROLA
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Equates
B.9
BUS INTERFACE UNIT (BIU) EQUATES
;---------------------------------------------------------------
;Bus Interface Unit (BIU) Equates
;---------------------------------------------------------------
;
Register Addresses Of BIU
M_BCR
M_DCR
M_AAR0 EQU
M_AAR1 EQU
M_AAR2 EQU
M_AAR3 EQU
EQU
EQU
$FFFFFB
$FFFFFA
$FFFFF9
$FFFFF8
$FFFFF7
$FFFFF6
$FFFFF5
; Bus Control Register
; DRAM Control Register
; Address Attribute Register 0
; Address Attribute Register 1
; Address Attribute Register 2
; Address Attribute Register 3
; ID Register
M_IDR
EQU
;
Bus Control Register
M_BA0W EQU
M_BA1W EQU
M_BA2W EQU
M_BA3W EQU
M_BDFW EQU
$1F
; Area 0 Wait Control Mask (BA0W0-BA0W4)
; Area 1 Wait Control Mask (BA1W0-BA14)
; Area 2 Wait Control Mask (BA2W0-BA2W2)
; Area 3 Wait Control Mask (BA3W0-BA3W3)
; Default Area Wait Control Mask (BDFW0-BDFW4)
; Bus State
$3E0
$1C00
$E000
$1F0000
21
M_BBS
M_BLH
M_BRH
EQU
EQU
EQU
22
23
; Bus Lock Hold
; Bus Request Hold
;
DRAM Control Register
M_BCW
M_BRW
M_BPS
EQU
EQU
EQU
$3
$C
$300
11
; In Page Wait States Bit Mask (BCW0-BCW1)
; Out Of Page Wait States Bit Mask (BRW0-BRW1)
; DRAM Page Size Bit Mask (BPS0-BPS1)
; Page Logic Enable
M_BPLE EQU
M_BME
M_BRE
EQU
EQU
12
13
; Mastership Enable
; Refresh Enable
M_BSTR EQU
14
$7F8000
23
; Software Triggered Refresh
; Refresh Rate Bits Mask (BRF0-BRF7)
; Refresh prescaler
M_BRF
M_BRP
EQU
EQU
;
Address Attribute Registers
M_BAT
;
EQU
$3
; External Access Type and Pin Definition Bits
Mask BAT(1:0)
M_BAAP EQU
M_BPEN EQU
M_BXEN EQU
M_BYEN EQU
2
3
4
5
6
7
; Address Attribute Pin Polarity
; Program Space Enable
; X Data Space Enable
; Y Data Space Enable
; Address Muxing
M_BAM
EQU
M_BPAC EQU
; Packing Enable
MOTOROLA
DSP56309UM/D
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B-13
Freescale Semiconductor, Inc.
Equates
M_BNC
M_BAC
EQU
EQU
$F00
$FFF000
; Number of Address Bits to Compare Mask
; Address to Compare Bits Mask BAC(11:0)
;
control and status bits in SR
M_CP
M_CA
M_V
M_Z
M_N
M_U
M_E
M_L
M_S
M_I0
M_I1
M_S0
M_S1
M_SC
M_DM
M_LF
M_FV
M_SA
M_CE
M_SM
M_RM
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$c00000
0
1
2
3
4
5
6
7
; mask for CORE-DMA priority bits in SR
; Carry
; Overflow
; Zero
; Negative
; Unnormalized
; Extension
; Limit
; Scaling Bit
; Interrupt Mask Bit 0
; Interrupt Mask Bit 1
; Scaling Mode Bit 0
; Scaling Mode Bit 1
; Sixteen_Bit Compatibility
; Double Precision Multiply
; DO-Loop Flag
8
9
10
11
13
14
15
16
17
19
20
21
22
23
; DO-Forever Flag
; Sixteen-Bit Arithmetic
; Instruction Cache Enable
; Arithmetic Saturation
; Rounding Mode
; bit 0 of priority bits in SR
; bit 1 of priority bits in SR
M_CP0 EQU
M_CP1 EQU
;
control and status bits in OMR
M_CDP EQU
$300
0
1
2
3
; mask for CORE-DMA priority bits in OMR
; Operating Mode A
; Operating Mode B
; Operating Mode C
; Operating Mode D
M_MA
M_MB
M_MC
M_MD
EQU
EQU
EQU
EQU
M_EBD EQU
4
6
7
8
; External Bus Disable bit in OMR
; Stop Delay
; Memory Switch bit in OMR
; bit 0 of priority bits in OMR
; bit 1 of priority bits in OMR
; Burst Enable
M_SD
M_MS
EQU
EQU
M_CDP0 EQU
M_CDP1 EQU
M_BEN EQU
M_TAS EQU
M_BRT EQU
M_ATE EQU
M_XYS EQU
M_EUN EQU
M_EOV EQU
M_WRP EQU
M_SEN EQU
9
10
11
12
15
16
17
18
19
20
; TA Synchronize Select
; Bus Release Timing
; Address Tracing Enable bit in OMR.
; Stack Extension space select bit in OMR.
; Extended stack UNderflow flag in OMR.
; Extended stack OVerflow flag in OMR.
; Extended WRaP flag in OMR.
; Stack Extension Enable bit in OMR.
B-14
DSP56309UM/D
MOTOROLA
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Equates
B.10 INTERRUPT EQUATES
;***************************************************************
EQUATES for DSP56309 interrupts
;
;**************************************************************
;---------------------------------------------------------------
; Non-Maskable interrupts
;---------------------------------------------------------------
I_RESET EQU I_VEC+$00 ; Hardware RESET
I_STACK EQU I_VEC+$02 ; Stack Error
I_ILL
I_DBG
EQU I_VEC+$04 ; Illegal Instruction
EQU I_VEC+$06 ; Debug Request
I_TRAP EQU I_VEC+$08 ; Trap
I_NMI
EQU I_VEC+$0A ; Non Maskable Interrupt
;---------------------------------------------------------------
; Interrupt Request Pins
;---------------------------------------------------------------
I_IRQA EQU I_VEC+$10 ; IRQA
I_IRQB EQU I_VEC+$12 ; IRQB
I_IRQC EQU I_VEC+$14 ; IRQC
I_IRQD EQU I_VEC+$16 ; IRQD
;---------------------------------------------------------------
; DMA Interrupts
;---------------------------------------------------------------
I_DMA0 EQU I_VEC+$18 ; DMA Channel 0
I_DMA1 EQU I_VEC+$1A ; DMA Channel 1
I_DMA2 EQU I_VEC+$1C ; DMA Channel 2
I_DMA3 EQU I_VEC+$1E ; DMA Channel 3
I_DMA4 EQU I_VEC+$20 ; DMA Channel 4
I_DMA5 EQU I_VEC+$22 ; DMA Channel 5
;---------------------------------------------------------------
; Timer Interrupts
;---------------------------------------------------------------
I_TIM0C EQU I_VEC+$24 ; TIMER 0 compare
I_TIM0OF EQU I_VEC+$26 ; TIMER 0 overflow
I_TIM1C EQU I_VEC+$28 ; TIMER 1 compare
I_TIM1OF EQU I_VEC+$2A ; TIMER 1 overflow
I_TIM2C EQU I_VEC+$2C ; TIMER 2 compare
I_TIM2OF EQU I_VEC+$2E ; TIMER 2 overflow
;---------------------------------------------------------------
MOTOROLA
DSP56309UM/D
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B-15
Freescale Semiconductor, Inc.
Equates
; ESSI Interrupts
;---------------------------------------------------------------
I_SI0RD EQU I_VEC+$30 ; ESSI0 Receive Data
I_SI0RDE EQU I_VEC+$32 ; ESSI0 Receive Data With Exception Status
I_SI0RLS EQU I_VEC+$34 ; ESSI0 Receive last slot
I_SI0TD EQU I_VEC+$36 ; ESSI0 Transmit data
I_SI0TDE EQU I_VEC+$38 ; ESSI0 Transmit Data With Exception Status
I_SI0TLS EQU I_VEC+$3A ; ESSI0 Transmit last slot
I_SI1RD EQU I_VEC+$40 ; ESSI1 Receive Data
I_SI1RDE EQU I_VEC+$42 ; ESSI1 Receive Data With Exception Status
I_SI1RLS EQU I_VEC+$44 ; ESSI1 Receive last slot
I_SI1TD EQU I_VEC+$46 ; ESSI1 Transmit data
I_SI1TDE EQU I_VEC+$48 ; ESSI1 Transmit Data With Exception Status
I_SI1TLS EQU I_VEC+$4A ; ESSI1 Transmit last slot
;---------------------------------------------------------------
; SCI Interrupts
;---------------------------------------------------------------
I_SCIRD EQU I_VEC+$50 ; SCI Receive Data
I_SCIRDE EQU I_VEC+$52 ; SCI Receive Data With Exception Status
I_SCITD EQU I_VEC+$54 ; SCI Transmit Data
I_SCIIL EQU I_VEC+$56 ; SCI Idle Line
I_SCITM EQU I_VEC+$58 ; SCI Timer
;---------------------------------------------------------------
; HOST Interrupts
;---------------------------------------------------------------
I_HRDF EQU
I_HTDE EQU
I_VEC+$60 ; Host Receive Data Full
I_VEC+$62 ; Host Transmit Data Empty
I_VEC+$64 ; Default Host Command
I_HC
EQU
;---------------------------------------------------------------
; INTERRUPT ENDING ADDRESS
;---------------------------------------------------------------
I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space
B-16
DSP56309UM/D
MOTOROLA
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APPENDIX C
DSP56309 BSDL LISTING
-- M O T O R O L A S S D T J T A G S O F T W A R E
-- BSDL File Generated: Mon Apr 8 10:13:47 1996
--
-- Revision History:
--
entity DSP56309 is
3 is
generic (PHYSICAL_PIN_MAP : string := "TQFP144");
port ( DE_:inout
bit;
bit;
bit;
bit;
bit;
bit;
SC02:inout
SC01:inout
SC00:inout
STD0:inout
SCK0:inout
MOTOROLA
DSP56309UM/D
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C-1
Freescale Semiconductor, Inc.
DSP56309 BSDL Listing
-- M O T O R O L A S S D T J T A G S O F T W A R E
-- BSDL File Generated: Tue Mar 3 15:14:41 1998
--
-- Revision History:
--
entity DSP56309 is
generic (PHYSICAL_PIN_MAP : string := ÒTQFP144Ó);
port ( DE_N:inout
SC02:inout
SC01:inout
SC00:inout
STD0:inout
SCK0:inout
SRD0:inout
SRD1:inout
SCK1:inout
STD1:inout
SC10:inout
SC11:inout
SC12:inout
TXD:inout
SCLK:inout
RXD:inout
TIO0:inout
TIO1:inout
TIO2:inout
HAD:inout
HREQ:inout
MODD:in
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit_vector(0 to 7);
bit;
bit;
MODC:in
bit;
MODB:in
bit;
MODA:in
bit;
D:inout
A:out
EXTAL:in
bit_vector(0 to 23);
bit_vector(0 to 17);
bit;
XTAL:linkage bit;
RD_N:out
WR_N:out
AA:out
bit;
bit;
bit_vector(0 to 3);
BR_N:buffer
BG_N:in
BB_N:inout
bit;
bit;
bit;
PCAP:linkage bit;
RESET_N:in
PINIT:in
TA_N:in
CAS_N:out
BCLK:out
BCLK_N:out
CLKOUT:buffer
TRST_N:in
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
C-2
DSP56309UM/D
MOTOROLA
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DSP56309 BSDL Listing
TDO:out
TDI:in
TCK:in
TMS:in
bit;
bit;
bit;
bit;
RESERVED:linkage bit_vector(0 to 1);
SGND:linkage bit_vector(0 to 1);
SVCC:linkage bit_vector(0 to 1);
QGND:linkage bit_vector(0 to 3);
QVCC:linkage bit_vector(0 to 3);
HGND:linkage bit;
HVCC:linkage bit;
DGND:linkage bit_vector(0 to 3);
DVCC:linkage bit_vector(0 to 3);
AGND:linkage bit_vector(0 to 3);
AVCC:linkage bit_vector(0 to 3);
JVCC:linkage bit;
JGND1:linkage bit;
JGND:linkage bit;
HACK:inout
HDS:inout
HRW:inout
bit;
bit;
bit;
CVCC:linkage bit_vector(0 to 1);
CGND:linkage bit_vector(0 to 1);
HCS:inout
HA9:inout
HA8:inout
HAS:inout
bit;
bit;
bit;
bit);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of DSP56309 : entity is ÒSTD_1149_1_1993Ó;
attribute PIN_MAP of DSP56309 : entity is PHYSICAL_PIN_MAP;
constant TQFP144 : PIN_MAP_STRING :=
ÒSRD1:
ÒSTD1:
ÒSC02:
ÒSC01:
ÒDE_N:
ÒPINIT:
ÒSRD0:
ÒSVCC:
ÒSGND:
ÒSTD0:
ÒSC10:
ÒSC00:
ÒRXD:
1, Ò &
2, Ò &
3, Ò &
4, Ò &
5, Ò &
6, Ò &
7, Ò &
(8, 25), Ò &
(9, 26), Ò &
10, Ò &
11, Ò &
12, Ò &
13, Ò &
ÒTXD:
14, Ò &
ÒSCLK:
ÒSCK1:
ÒSCK0:
ÒQVCC:
15, Ò &
16, Ò &
17, Ò &
(18, 56, 91, 126), Ò &
MOTOROLA
DSP56309UM/D
C-3
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DSP56309 BSDL Listing
ÒQGND:
(19, 54, 90, 127), Ò &
ÒRESERVED: (49, 20), Ò &
ÒHDS:
21, Ò &
ÒHRW:
22, Ò &
ÒHACK:
ÒHREQ:
ÒTIO2:
ÒTIO1:
ÒTIO0:
ÒHCS:
23, Ò &
24, Ò &
27, Ò &
28, Ò &
29, Ò &
30, Ò &
ÒHA9:
31, Ò &
ÒHA8:
32, Ò &
ÒHAS:
33, Ò &
ÒHAD:
(43, 42, 41, 40, 37, 36, 35, 34), Ò &
ÒHVCC:
ÒHGND:
ÒRESET_N:
ÒJVCC:
ÒPCAP:
ÒJGND:
ÒJGND1:
ÒAA:
38, Ò &
39, Ò &
44, Ò &
45, Ò &
46, Ò &
47, Ò &
48, Ò &
(70, 69, 51, 50), Ò &
ÒCAS_N:
ÒXTAL:
ÒEXTAL:
ÒCVCC:
ÒCGND:
ÒCLKOUT:
ÒBCLK:
ÒBCLK_N:
ÒTA_N:
ÒBR_N:
ÒBB_N:
ÒWR_N:
ÒRD_N:
ÒBG_N:
ÒA:
52, Ò &
53, Ò &
55, Ò &
(57, 65), Ò &
(58, 66), Ò &
59, Ò &
60, Ò &
61, Ò &
62, Ò &
63, Ò &
64, Ò &
67, Ò &
68, Ò &
71, Ò &
(72, 73, 76, 77, 78, 79, 82, 83, 84, 85, 88, 89, 92, 93, 94, 97, 98, 99), Ò &
ÒAVCC:
ÒAGND:
ÒD:
(74, 80, 86, 95), Ò &
(75, 81, 87, 96), Ò &
(100, 101, 102, 105, 106, 107, 108, 109, 110, 113, 114, 115, 116, 117, Ò &
Ò 118, 121, 122, 123, 124, 125, 128, 131, 132, 133), Ò &
ÒDVCC:
ÒDGND:
ÒMODD:
ÒMODC:
ÒMODB:
ÒMODA:
ÒTRST_N:
ÒTDO:
(103, 111, 119, 129), Ò &
(104, 112, 120, 130), Ò &
134, Ò &
135, Ò &
136, Ò &
137, Ò &
138, Ò &
139, Ò &
ÒTDI:
140, Ò &
ÒTCK:
141, Ò &
ÒTMS:
142, Ò &
ÒSC12:
143, Ò &
C-4
DSP56309UM/D
MOTOROLA
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DSP56309 BSDL Listing
ÒSC11:
144 Ò;
attribute TAP_SCAN_IN
attribute TAP_SCAN_OUT of
attribute TAP_SCAN_MODE of
of
TDI : signal is true;
TDO : signal is true;
TMS : signal is true;
attribute TAP_SCAN_RESET of TRST_N : signal is true;
attribute TAP_SCAN_CLOCK of
TCK : signal is (20.0e6, BOTH);
attribute INSTRUCTION_LENGTH of DSP56309 : entity is 4;
attribute INSTRUCTION_OPCODE of DSP56309 : entity is
ÒEXTEST
ÒSAMPLE
ÒIDCODE
ÒCLAMP
ÒHIGHZ
(0000),Ó &
(0001),Ó &
(0010),Ó &
(0101),Ó &
(0100),Ó &
ÒENABLE_ONCE (0110),Ó &
ÒDEBUG_REQUEST(0111),Ó &
ÒBYPASS
(1111)Ó;
attribute INSTRUCTION_CAPTURE of DSP56309 : entity is Ò0001Ó;
attribute IDCODE_REGISTER of DSP56309 : entity is
Ò0010Ó
& -- version
Ò000110Ó
Ò0000000010Ó
& -- manufacturerÕs use
& -- sequence number
Ò00000001110Ó & -- manufacturer identity
Ò1Ó; -- 1149.1 requirement
attribute REGISTER_ACCESS of DSP56309 : entity is
ÒONCE[8] (ENABLE_ONCE,DEBUG_REQUEST)Ó ;
attribute BOUNDARY_LENGTH of DSP56309 : entity is 144;
attribute BOUNDARY_REGISTER of DSP56309 : entity is
-- num
Ò0
cell port func
(BC_1, MODA,
(BC_1, MODB,
(BC_1, MODC,
(BC_1, MODD,
(BC_6, D(23),
(BC_6, D(22),
(BC_6, D(21),
(BC_6, D(20),
(BC_6, D(19),
(BC_6, D(18),
(BC_6, D(17),
(BC_6, D(16),
(BC_6, D(15),
(BC_1, *,
safe [ccell dis rslt]
input,
input,
input,
input,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
control,
bidir,
bidir,
bidir,
X),Ó &
X),Ó &
X),Ó &
X),Ó &
Ò1
Ò2
Ò3
Ò4
Ò5
Ò6
Ò7
Ò8
X,
13, 1, Z),Ó &
X,
X,
X,
X,
X,
X,
X,
X,
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
Ò9
Ò10
Ò11
Ò12
Ò13
Ò14
Ò15
Ò16
1),Ó &
X,
X,
(BC_6, D(14),
(BC_6, D(13),
(BC_6, D(12),
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
X,
MOTOROLA
DSP56309UM/D
C-5
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DSP56309 BSDL Listing
Ò17
Ò18
Ò19
-- num
Ò20
Ò21
Ò22
Ò23
Ò24
Ò25
Ò26
Ò27
Ò28
Ò29
Ò30
Ò31
Ò32
Ò33
Ò34
Ò35
Ò36
Ò37
Ò38
Ò39
-- num
Ò40
Ò41
Ò42
Ò43
Ò44
Ò45
Ò46
Ò47
Ò48
Ò49
Ò50
Ò51
Ò52
Ò53
Ò54
Ò55
Ò56
Ò57
Ò58
Ò59
-- num
Ò60
Ò61
Ò62
Ò63
Ò64
Ò65
Ò66
(BC_6, D(11),
bidir,
bidir,
bidir,
X,
X,
X,
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
(BC_6, D(10),
(BC_6, D(9),
cell port func
(BC_6, D(8),
(BC_6, D(7),
(BC_6, D(6),
(BC_6, D(5),
(BC_6, D(4),
(BC_6, D(3),
(BC_1, *,
(BC_6, D(2),
(BC_6, D(1),
(BC_6, D(0),
(BC_1, A(17),
(BC_1, A(16),
(BC_1, A(15),
(BC_1, *,
(BC_1, A(14),
(BC_1, A(13),
(BC_1, A(12),
(BC_1, A(11),
(BC_1, A(10),
(BC_1, A(9),
cell port func
(BC_1, A(8),
(BC_1, A(7),
(BC_1, A(6),
(BC_1, *,
(BC_1, A(5),
(BC_1, A(4),
(BC_1, A(3),
(BC_1, A(2),
(BC_1, A(1),
(BC_1, A(0),
(BC_1, BG_N,
(BC_1, AA(0),
(BC_1, AA(1),
(BC_1, RD_N,
(BC_1, WR_N,
(BC_1, *,
safe [ccell dis rslt]
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
control,
bidir,
bidir,
X,
X,
X,
X,
X,
X,
1),Ó &
X,
X,
X,
X,
X,
X,
1),Ó &
X,
X,
X,
X,
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
bidir,
output3,
output3,
output3,
control,
output3,
output3,
output3,
output3,
output3,
output3,
33, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
X,
X,
safe [ccell dis rslt]
output3,
output3,
output3,
control,
output3,
output3,
output3,
output3,
output3,
output3,
input,
output3,
output3,
output3,
output3,
control,
control,
control,
bidir,
X,
X,
X,
1),Ó &
X,
X,
X,
X,
X,
X,
X),Ó &
X,
X,
X,
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
55, 1, Z),Ó &
56, 1, Z),Ó &
64, 1, Z),Ó &
64, 1, Z),Ó &
X,
1),Ó &
1),Ó &
1),Ó &
X,
(BC_1, *,
(BC_1, *,
(BC_6, BB_N,
(BC_1, BR_N,
cell port func
(BC_1, TA_N,
(BC_1, BCLK_N,
(BC_1, BCLK,
(BC_1, CLKOUT,
(BC_1, *,
57, 1, Z),Ó &
output2,
X),Ó &
safe [ccell dis rslt]
X),Ó &
input,
output3,
output3,
output2,
control,
control,
control,
X,
X,
X),Ó &
1),Ó &
1),Ó &
1),Ó &
64, 1, Z),Ó &
64, 1, Z),Ó &
(BC_1, *,
(BC_1, *,
C-6
DSP56309UM/D
MOTOROLA
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DSP56309 BSDL Listing
Ò67
Ò68
Ò69
Ò70
Ò71
Ò72
Ò73
Ò74
Ò75
Ò76
Ò77
Ò78
Ò79
-- num
Ò80
Ò81
Ò82
Ò83
Ò84
Ò85
Ò86
Ò87
Ò88
Ò89
Ò90
Ò91
Ò92
Ò93
Ò94
Ò95
Ò96
Ò97
Ò98
Ò99
-- num
(BC_1, *,
control,
input,
output3,
output3,
output3,
1),Ó &
X),Ó &
X,
X,
X,
X),Ó &
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
(BC_1, EXTAL,
(BC_1, CAS_N,
(BC_1, AA(2),
(BC_1, AA(3),
(BC_1, RESET_N, input,
(BC_1, *,
(BC_6, HAD(0),
(BC_1, *,
(BC_6, HAD(1),
(BC_1, *,
(BC_6, HAD(2),
(BC_1, *,
cell port func
(BC_6, HAD(3),
(BC_1, *,
(BC_6, HAD(4),
(BC_1, *,
(BC_6, HAD(5),
(BC_1, *,
(BC_6, HAD(6),
(BC_1, *,
(BC_6, HAD(7),
(BC_1, *,
(BC_6, HAS,
(BC_1, *,
(BC_6, HA8,
(BC_1, *,
(BC_6, HA9,
(BC_1, *,
(BC_6, HCS,
(BC_1, *,
65, 1, Z),Ó &
66, 1, Z),Ó &
67, 1, Z),Ó &
control,
bidir,
control,
bidir,
control,
bidir,
control,
73, 1, Z),Ó &
75, 1, Z),Ó &
77, 1, Z),Ó &
safe [ccell dis rslt]
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
79, 1, Z),Ó &
81, 1, Z),Ó &
83, 1, Z),Ó &
85, 1, Z),Ó &
87, 1, Z),Ó &
89, 1, Z),Ó &
91, 1, Z),Ó &
93, 1, Z),Ó &
95, 1, Z),Ó &
97, 1, Z),Ó &
control,
bidir,
control,
bidir,
1),Ó &
X,
1),Ó &
X,
(BC_6, TIO0,
(BC_1, *,
cell port func
control,
1),Ó &
safe [ccell dis rslt]
Ò100 (BC_6, TIO1,
bidir,
X,
99, 1, Z),Ó &
Ò101 (BC_1, *,
Ò102 (BC_6, TIO2,
Ò103 (BC_1, *,
Ò104 (BC_6, HREQ,
Ò105 (BC_1, *,
Ò106 (BC_6, HACK,
Ò107 (BC_1, *,
Ò108 (BC_6, HRW,
Ò109 (BC_1, *,
Ò110 (BC_6, HDS,
Ò111 (BC_1, *,
Ò112 (BC_6, SCK0,
Ò113 (BC_1, *,
Ò114 (BC_6, SCK1,
Ò115 (BC_1, *,
Ò116 (BC_6, SCLK,
Ò117 (BC_1, *,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
101, 1, Z),Ó &
103, 1, Z),Ó &
105, 1, Z),Ó &
107, 1, Z),Ó &
109, 1, Z),Ó &
111, 1, Z),Ó &
113, 1, Z),Ó &
115, 1, Z),Ó &
control,
1),Ó &
MOTOROLA
DSP56309UM/D
C-7
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DSP56309 BSDL Listing
Ò118 (BC_6, TXD,
Ò119 (BC_1, *,
-- num cell port func
bidir,
control,
X,
1),Ó &
safe [ccell dis rslt]
117, 1, Z),Ó &
Ò120 (BC_6, RXD,
Ò121 (BC_1, *,
Ò122 (BC_6, SC00,
Ò123 (BC_1, *,
Ò124 (BC_6, SC10,
Ò125 (BC_1, *,
Ò126 (BC_6, STD0,
Ò127 (BC_1, *,
Ò128 (BC_6, SRD0,
Ò129 (BC_1, PINIT,
Ò130 (BC_1, *,
Ò131 (BC_6, DE_N,
Ò132 (BC_1, *,
Ò133 (BC_6, SC01,
Ò134 (BC_1, *,
Ò135 (BC_6, SC02,
Ò136 (BC_1, *,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
input,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
X),Ó &
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
119, 1, Z),Ó &
121, 1, Z),Ó &
123, 1, Z),Ó &
125, 1, Z),Ó &
127, 1, Z),Ó &
130, 1, Z),Ó &
132, 1, Z),Ó &
134, 1, Z),Ó &
136, 1, Z),Ó &
138, 1, Z),Ó &
1),Ó &
X,
1),Ó &
X,
Ò137 (BC_6, STD1,
Ò138 (BC_1, *,
Ò139 (BC_6, SRD1,
-- num
cell port func
safe [ccell dis rslt]
1),Ó &
Ò140 (BC_1, *,
Ò141 (BC_6, SC11,
Ò142 (BC_1, *,
Ò143 (BC_6, SC12,
control,
bidir,
control,
bidir,
X,
140, 1, Z),Ó &
1),Ó &
X,
142, 1, Z)Ó;
end DSP56309 TQFP;
---------------------------------------------------------------------
-- M O T O R O L A S S D T J T A G S O F T W A R E
-- BSDL File Generated: Wed May 20 10:37:28 1998
--
-- Revision History:
--
-- 1) Date : Tue Mar 3 15:14:41 1998
--
--
Changes : Created for dsp56309 rev0, PBGA
-- 2) Date : Wed May 20 10:37:28 1998
--
--
--
Changes : Fix in definition of DE_N, it is Pull1 when disabled
Updated by Roman Sajman
entity DSP56309 is
generic (PHYSICAL_PIN_MAP : string := ÒTQFP144Ó);
port ( DE_N: inout bit;
SC02: inout bit;
SC01: inout bit;
SC00: inout bit;
C-8
DSP56309UM/D
MOTOROLA
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DSP56309 BSDL Listing
STD0: inout bit;
SCK0: inout bit;
SRD0: inout bit;
SRD1: inout bit;
SCK1: inout bit;
STD1: inout bit;
SC10: inout bit;
SC11: inout bit;
SC12: inout bit;
TXD: inout bit;
SCLK: inout bit;
RXD: inout bit;
TIO0: inout bit;
TIO1: inout bit;
TIO2: inout bit;
HAD: inout bit_vector(0 to 7);
HREQ: inout bit;
MODD: in
MODC: in
MODB: in
MODA: in
bit;
bit;
bit;
bit;
D: inout bit_vector(0 to 23);
A: out
EXTAL: in
bit_vector(0 to 17);
bit;
XTAL: linkage bit;
RD_N: out
WR_N: out
AA: out
bit;
bit;
bit_vector(0 to 3);
BR_N: buffer bit;
BG_N: in bit;
BB_N: inout bit;
PCAP: linkage bit;
RESET_N: in
PINIT: in
TA_N: in
CAS_N: out
BCLK: out
BCLK_N: out
bit;
bit;
bit;
bit;
bit;
bit;
CLKOUT: buffer bit;
TRST_N: in
TDO: out
TDI: in
TCK: in
TMS: in
bit;
bit;
bit;
bit;
bit;
RESERVED: linkage bit_vector(0 to 1);
SGND: linkage bit_vector(0 to 1);
SVCC: linkage bit_vector(0 to 1);
QGND: linkage bit_vector(0 to 3);
QVCC: linkage bit_vector(0 to 3);
HGND: linkage bit;
HVCC: linkage bit;
DGND: linkage bit_vector(0 to 3);
DVCC: linkage bit_vector(0 to 3);
MOTOROLA
DSP56309UM/D
C-9
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DSP56309 BSDL Listing
AGND: linkage bit_vector(0 to 3);
AVCC: linkage bit_vector(0 to 3);
JVCC: linkage bit;
JGND1: linkage bit;
JGND: linkage bit;
HACK: inout bit;
HDS: inout bit;
HRW: inout bit;
CVCC: linkage bit_vector(0 to 1);
CGND: linkage bit_vector(0 to 1);
HCS: inout bit;
HA9: inout bit;
HA8: inout bit;
HAS: inout bit);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of DSP56309 : entity is ÒSTD_1149_1_1993Ó;
attribute PIN_MAP of DSP56309 : entity is PHYSICAL_PIN_MAP;
constant TQFP144 : PIN_MAP_STRING :=
ÒSRD1:
ÒSTD1:
ÒSC02:
ÒSC01:
ÒDE_N:
ÒPINIT:
ÒSRD0:
ÒSVCC:
ÒSGND:
ÒSTD0:
ÒSC10:
ÒSC00:
ÒRXD:
1, Ò &
2, Ò &
3, Ò &
4, Ò &
5, Ò &
6, Ò &
7, Ò &
(8, 25), Ò &
(9, 26), Ò &
10, Ò &
11, Ò &
12, Ò &
13, Ò &
ÒTXD:
14, Ò &
ÒSCLK:
ÒSCK1:
ÒSCK0:
ÒQVCC:
ÒQGND:
15, Ò &
16, Ò &
17, Ò &
(18, 56, 91, 126), Ò &
(19, 54, 90, 127), Ò &
ÒRESERVED: (49, 20), Ò &
ÒHDS:
ÒHRW:
ÒHACK:
ÒHREQ:
ÒTIO2:
ÒTIO1:
ÒTIO0:
ÒHCS:
ÒHA9:
ÒHA8:
ÒHAS:
21, Ò &
22, Ò &
23, Ò &
24, Ò &
27, Ò &
28, Ò &
29, Ò &
30, Ò &
31, Ò &
32, Ò &
33, Ò &
C-10
DSP56309UM/D
MOTOROLA
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DSP56309 BSDL Listing
ÒHAD:
(43, 42, 41, 40, 37, 36, 35, 34), Ò &
ÒHVCC:
ÒHGND:
ÒRESET_N:
ÒJVCC:
ÒPCAP:
ÒJGND:
ÒJGND1:
ÒAA:
ÒCAS_N:
ÒXTAL:
ÒEXTAL:
ÒCVCC:
ÒCGND:
ÒCLKOUT:
ÒBCLK:
ÒBCLK_N:
ÒTA_N:
ÒBR_N:
ÒBB_N:
ÒWR_N:
ÒRD_N:
ÒBG_N:
ÒA:
38, Ò &
39, Ò &
44, Ò &
45, Ò &
46, Ò &
47, Ò &
48, Ò &
(70, 69, 51, 50), Ò &
52, Ò &
53, Ò &
55, Ò &
(57, 65), Ò &
(58, 66), Ò &
59, Ò &
60, Ò &
61, Ò &
62, Ò &
63, Ò &
64, Ò &
67, Ò &
68, Ò &
71, Ò &
(72, 73, 76, 77, 78, 79, 82, 83, 84, 85, 88, 89, 92, 93, 94, 97, 98,
99), Ò &
ÒAVCC:
ÒAGND:
ÒD:
(74, 80, 86, 95), Ò &
(75, 81, 87, 96), Ò &
(100, 101, 102, 105, 106, 107, 108, 109, 110, 113, 114, 115, 116, 117,
118, 121, Ò &
Ò122, 123, 124, 125, 128, 131, 132, 133), Ò &
ÒDVCC:
ÒDGND:
ÒMODD:
ÒMODC:
ÒMODB:
ÒMODA:
ÒTRST_N:
ÒTDO:
(103, 111, 119, 129), Ò &
(104, 112, 120, 130), Ò &
134, Ò &
135, Ò &
136, Ò &
137, Ò &
138, Ò &
139, Ò &
ÒTDI:
140, Ò &
ÒTCK:
141, Ò &
ÒTMS:
142, Ò &
ÒSC12:
ÒSC11:
143, Ò &
144 Ò;
attribute TAP_SCAN_IN
attribute TAP_SCAN_OUT of
attribute TAP_SCAN_MODE of
of
TDI : signal is true;
TDO : signal is true;
TMS : signal is true;
attribute TAP_SCAN_RESET of TRST_N : signal is true;
attribute TAP_SCAN_CLOCK of
TCK : signal is (20.0e6, BOTH);
attribute INSTRUCTION_LENGTH of DSP56309 : entity is 4;
attribute INSTRUCTION_OPCODE of DSP56309 : entity is
MOTOROLA
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C-11
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DSP56309 BSDL Listing
ÒEXTEST
ÒSAMPLE
ÒIDCODE
ÒCLAMP
(0000),Ó &
(0001),Ó &
(0010),Ó &
(0101),Ó &
(0100),Ó &
(0110),Ó &
(0111),Ó &
(1111)Ó;
ÒHIGHZ
ÒENABLE_ONCE
ÒDEBUG_REQUEST
ÒBYPASS
attribute INSTRUCTION_CAPTURE of DSP56309 : entity is Ò0001Ó;
attribute IDCODE_REGISTER of DSP56309 : entity is
Ò0010Ó
& -- version
Ò000110Ó
Ò0000000010Ó
& -- manufacturerÕs use
& -- sequence number
Ò00000001110Ó & -- manufacturer identity
Ò1Ó; -- 1149.1 requirement
attribute REGISTER_ACCESS of DSP56309 : entity is
ÒONCE[8] (ENABLE_ONCE,DEBUG_REQUEST)Ó ;
attribute BOUNDARY_LENGTH of DSP56309 : entity is 144;
attribute BOUNDARY_REGISTER of DSP56309 : entity is
-- num
Ò0
cell port func
(BC_1, MODA,
(BC_1, MODB,
(BC_1, MODC,
(BC_1, MODD,
(BC_6, D(23),
(BC_6, D(22),
(BC_6, D(21),
(BC_6, D(20),
(BC_6, D(19),
(BC_6, D(18),
(BC_6, D(17),
(BC_6, D(16),
(BC_6, D(15),
(BC_1, *,
safe [ccell dis rslt]
input,
input,
input,
input,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
control,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
X),Ó &
X),Ó &
X),Ó &
X),Ó &
Ò1
Ò2
Ò3
Ò4
Ò5
Ò6
Ò7
Ò8
X,
13, 1, Z),Ó &
X,
X,
X,
X,
X,
X,
X,
X,
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
Ò9
Ò10
Ò11
Ò12
Ò13
Ò14
Ò15
Ò16
Ò17
Ò18
Ò19
-- num
Ò20
Ò21
Ò22
Ò23
Ò24
Ò25
Ò26
Ò27
1),Ó &
X,
X,
X,
X,
(BC_6, D(14),
(BC_6, D(13),
(BC_6, D(12),
(BC_6, D(11),
(BC_6, D(10),
(BC_6, D(9),
cell port func
(BC_6, D(8),
(BC_6, D(7),
(BC_6, D(6),
(BC_6, D(5),
(BC_6, D(4),
(BC_6, D(3),
(BC_1, *,
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
X,
X,
safe [ccell dis rslt]
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
control,
bidir,
X,
26, 1, Z),Ó &
X,
X,
X,
X,
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
X,
1),Ó &
X,
(BC_6, D(2),
26, 1, Z),Ó &
C-12
DSP56309UM/D
MOTOROLA
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DSP56309 BSDL Listing
Ò28
Ò29
Ò30
Ò31
Ò32
Ò33
Ò34
Ò35
Ò36
Ò37
Ò38
Ò39
-- num
Ò40
Ò41
Ò42
Ò43
Ò44
Ò45
Ò46
Ò47
Ò48
Ò49
Ò50
Ò51
Ò52
Ò53
Ò54
Ò55
Ò56
Ò57
Ò58
Ò59
-- num
Ò60
Ò61
Ò62
Ò63
Ò64
Ò65
Ò66
Ò67
Ò68
Ò69
Ò70
Ò71
Ò72
Ò73
Ò74
Ò75
Ò76
Ò77
Ò78
(BC_6, D(1),
(BC_6, D(0),
(BC_1, A(17),
(BC_1, A(16),
(BC_1, A(15),
(BC_1, *,
(BC_1, A(14),
(BC_1, A(13),
(BC_1, A(12),
(BC_1, A(11),
(BC_1, A(10),
(BC_1, A(9),
cell port func
(BC_1, A(8),
(BC_1, A(7),
(BC_1, A(6),
(BC_1, *,
(BC_1, A(5),
(BC_1, A(4),
(BC_1, A(3),
(BC_1, A(2),
(BC_1, A(1),
(BC_1, A(0),
(BC_1, BG_N,
(BC_1, AA(0),
(BC_1, AA(1),
(BC_1, RD_N,
(BC_1, WR_N,
(BC_1, *,
bidir,
bidir,
X,
X,
X,
X,
X,
1),Ó &
X,
X,
X,
26, 1, Z),Ó &
26, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
output3,
output3,
output3,
control,
output3,
output3,
output3,
output3,
output3,
output3,
33, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
X,
X,
X,
safe [ccell dis rslt]
output3,
output3,
output3,
control,
output3,
output3,
output3,
output3,
output3,
output3,
input,
output3,
output3,
output3,
output3,
control,
control,
control,
bidir,
X,
X,
X,
1),Ó &
X,
X,
X,
X,
X,
X,
X),Ó &
X,
X,
X,
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
55, 1, Z),Ó &
56, 1, Z),Ó &
64, 1, Z),Ó &
64, 1, Z),Ó &
X,
1),Ó &
1),Ó &
1),Ó &
X,
(BC_1, *,
(BC_1, *,
(BC_6, BB_N,
(BC_1, BR_N,
cell port func
(BC_1, TA_N,
(BC_1, BCLK_N,
(BC_1, BCLK,
(BC_1, CLKOUT,
(BC_1, *,
(BC_1, *,
(BC_1, *,
(BC_1, *,
(BC_1, EXTAL,
(BC_1, CAS_N,
(BC_1, AA(2),
(BC_1, AA(3),
(BC_1, RESET_N, input,
(BC_1, *,
57, 1, Z),Ó &
output2,
X),Ó &
safe [ccell dis rslt]
X),Ó &
input,
output3,
output3,
output2,
control,
control,
control,
control,
input,
X,
X,
64, 1, Z),Ó &
64, 1, Z),Ó &
X),Ó &
1),Ó &
1),Ó &
1),Ó &
1),Ó &
X),Ó &
X,
output3,
output3,
output3,
65, 1, Z),Ó &
66, 1, Z),Ó &
67, 1, Z),Ó &
X,
X,
X),Ó &
1),Ó &
X,
1),Ó &
X,
control,
bidir,
control,
bidir,
control,
bidir,
(BC_6, HAD(0),
(BC_1, *,
(BC_6, HAD(1),
(BC_1, *,
73, 1, Z),Ó &
75, 1, Z),Ó &
77, 1, Z),Ó &
1),Ó &
X,
(BC_6, HAD(2),
MOTOROLA
DSP56309UM/D
C-13
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DSP56309 BSDL Listing
Ò79
-- num
Ò80
(BC_1, *,
control,
1),Ó &
safe [ccell dis rslt]
cell port func
(BC_6, HAD(3),
(BC_1, *,
(BC_6, HAD(4),
(BC_1, *,
(BC_6, HAD(5),
(BC_1, *,
(BC_6, HAD(6),
(BC_1, *,
(BC_6, HAD(7),
(BC_1, *,
(BC_6, HAS,
(BC_1, *,
(BC_6, HA8,
(BC_1, *,
(BC_6, HA9,
(BC_1, *,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
79, 1, Z),Ó &
Ò81
Ò82
Ò83
Ò84
Ò85
Ò86
Ò87
Ò88
Ò89
Ò90
Ò91
Ò92
Ò93
Ò94
Ò95
Ò96
81, 1, Z),Ó &
83, 1, Z),Ó &
85, 1, Z),Ó &
87, 1, Z),Ó &
89, 1, Z),Ó &
91, 1, Z),Ó &
93, 1, Z),Ó &
95, 1, Z),Ó &
97, 1, Z),Ó &
control,
bidir,
control,
bidir,
1),Ó &
X,
1),Ó &
X,
(BC_6, HCS,
(BC_1, *,
(BC_6, TIO0,
(BC_1, *,
Ò97
Ò98
Ò99
control,
1),Ó &
-- num
cell port func
safe [ccell dis rslt]
Ò100 (BC_6, TIO1,
bidir,
X,
99, 1, Z),Ó &
Ò101 (BC_1, *,
Ò102 (BC_6, TIO2,
Ò103 (BC_1, *,
Ò104 (BC_6, HREQ,
Ò105 (BC_1, *,
Ò106 (BC_6, HACK,
Ò107 (BC_1, *,
Ò108 (BC_6, HRW,
Ò109 (BC_1, *,
Ò110 (BC_6, HDS,
Ò111 (BC_1, *,
Ò112 (BC_6, SCK0,
Ò113 (BC_1, *,
Ò114 (BC_6, SCK1,
Ò115 (BC_1, *,
Ò116 (BC_6, SCLK,
Ò117 (BC_1, *,
Ò118 (BC_6, TXD,
Ò119 (BC_1, *,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
101, 1, Z),Ó &
103, 1, Z),Ó &
105, 1, Z),Ó &
107, 1, Z),Ó &
109, 1, Z),Ó &
111, 1, Z),Ó &
113, 1, Z),Ó &
115, 1, Z),Ó &
117, 1, Z),Ó &
control,
bidir,
control,
1),Ó &
X,
1),Ó &
-- num
cell port func
safe [ccell dis rslt]
Ò120 (BC_6, RXD,
Ò121 (BC_1, *,
Ò122 (BC_6, SC00,
Ò123 (BC_1, *,
Ò124 (BC_6, SC10,
Ò125 (BC_1, *,
Ò126 (BC_6, STD0,
Ò127 (BC_1, *,
Ò128 (BC_6, SRD0,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
119, 1, Z),Ó &
121, 1, Z),Ó &
123, 1, Z),Ó &
125, 1, Z),Ó &
127, 1, Z),Ó &
control,
bidir,
1),Ó &
X,
C-14
DSP56309UM/D
MOTOROLA
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DSP56309 BSDL Listing
Ò129 (BC_1, PINIT,
Ò130 (BC_1, *,
Ò131 (BC_6, DE_N,
Ò132 (BC_1, *,
Ò133 (BC_6, SC01,
Ò134 (BC_1, *,
Ò135 (BC_6, SC02,
Ò136 (BC_1, *,
input,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
X),Ó &
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
130, 1, Pull1),Ó &
132, 1, Z),Ó &
134, 1, Z),Ó &
136, 1, Z),Ó &
138, 1, Z),Ó &
Ò137 (BC_6, STD1,
Ò138 (BC_1, *,
Ò139 (BC_6, SRD1,
1),Ó &
X,
-- num
cell port func
safe [ccell dis rslt]
1),Ó &
Ò140 (BC_1, *,
Ò141 (BC_6, SC11,
Ò142 (BC_1, *,
Ò143 (BC_6, SC12,
control,
bidir,
control,
bidir,
X,
140, 1, Z),Ó &
1),Ó &
X,
142, 1, Z)Ó;
end DSP56309;
---------------------------------------------------------------------
-- M O T O R O L A S S D T J T A G S O F T W A R E
-- BSDL File Generated: Wed May 20 09:48:32 1998
--
-- Revision History:
--
entity DSP56309 is
generic (PHYSICAL_PIN_MAP : string := ÒPBGA196Ó);
port ( DE_N: inout bit;
SC02: inout bit;
SC01: inout bit;
SC00: inout bit;
STD0: inout bit;
SCK0: inout bit;
SRD0: inout bit;
SRD1: inout bit;
SCK1: inout bit;
STD1: inout bit;
SC10: inout bit;
SC11: inout bit;
SC12: inout bit;
TXD: inout bit;
SCLK: inout bit;
RXD: inout bit;
TIO0: inout bit;
TIO1: inout bit;
TIO2: inout bit;
HAD: inout bit_vector(0 to 7);
HREQ: inout bit;
MODD: in
MODC: in
MODB: in
bit;
bit;
bit;
MOTOROLA
DSP56309UM/D
C-15
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DSP56309 BSDL Listing
MODA: in
bit;
D: inout bit_vector(0 to 23);
A: out
EXTAL: in
bit_vector(0 to 17);
bit;
XTAL: linkage bit;
RD_N: out
WR_N: out
AA: out
bit;
bit;
bit_vector(0 to 3);
BR_N: buffer bit;
BG_N: in bit;
BB_N: inout bit;
PCAP: linkage bit;
RESET_N: in
PINIT: in
TA_N: in
CAS_N: out
BCLK: out
BCLK_N: out
bit;
bit;
bit;
bit;
bit;
bit;
CLKOUT: buffer bit;
TRST_N: in
TDO: out
TDI: in
TCK: in
TMS: in
bit;
bit;
bit;
bit;
bit;
RESERVED: linkage bit_vector(0 to 4);
SVCC: linkage bit_vector(0 to 1);
HVCC: linkage bit;
DVCC: linkage bit_vector(0 to 3);
AVCC: linkage bit_vector(0 to 2);
HACK: inout bit;
HDS: inout bit;
HRW: inout bit;
CVCC: linkage bit_vector(0 to 1);
HCS: inout bit;
HA9: inout bit;
HA8: inout bit;
HAS: inout bit;
GND: linkage bit_vector(0 to 63);
QVCCL: linkage bit_vector(0 to 3);
QVCCH: linkage bit_vector(0 to 2);
PVCC: linkage bit;
PGND: linkage bit;
PGND1: linkage bit);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of DSP56309 : entity is ÒSTD_1149_1_1993Ó;
attribute PIN_MAP of DSP56309 : entity is PHYSICAL_PIN_MAP;
constant PBGA196 : PIN_MAP_STRING :=
ÒRESERVED: (A1, A14, B14, P1, P14), Ò &
ÒSC11:
A2, Ò &
C-16
DSP56309UM/D
MOTOROLA
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DSP56309 BSDL Listing
ÒTMS:
ÒTDO:
A3, Ò &
A4, Ò &
ÒMODB:
ÒD:
A5, Ò &
(E14, D12, D13, C13, C14, B13, C12, A13, B12, A12, B11, A11, C10, B10,
A10, B9, Ò &
ÒA9, B8, C8, A8, B7, B6, C6, A6), Ò &
ÒDVCC:
ÒSRD1:
ÒSC12:
ÒTDI:
(A7, C9, C11, D14), Ò &
B1, Ò &
B2, Ò &
B3, Ò &
ÒTRST_N:
ÒMODD:
ÒSC02:
ÒSTD1:
ÒTCK:
B4, Ò &
B5, Ò &
C1, Ò &
C2, Ò &
C3, Ò &
ÒMODA:
ÒMODC:
ÒQVCCL:
ÒPINIT:
ÒSC01:
ÒDE_N:
ÒGND:
C4, Ò &
C5, Ò &
(C7, G13, H2, N9), Ò &
D1, Ò &
D2, Ò &
D3, Ò &
(E8, E9, E10, E11, F4, F5, F11, G4, G5, G6, G7, G8, G9, G10, G11, H4,
H5, H6, Ò &
K8, K9, Ò &
D11, E4, Ò &
ÒH7, H8, H9, H10, H11, J4, J5, J6, J7, J8, J9, J10, J11, K4, K5, K6, K7,
ÒK10, K11, L4, L5, L6, L7, L8, L9, L10, L11, D4, D5, D6, D7, D8, D9, D10,
ÒE5, E6, E7, F6, F7, F8, F9, F10), Ò &
ÒSTD0:
ÒSVCC:
ÒSRD0:
ÒA:
E1, Ò &
(E2, K1), Ò &
E3, Ò &
(N14, M13, M14, L13, L14, K13, K14, J13, J12, J14, H13, H14, G14, G12,
F13, F14, Ò &
ÒE13, E12), Ò &
F1, Ò &
ÒRXD:
ÒSC10:
ÒSC00:
ÒQVCCH:
ÒSCK1:
ÒSCLK:
ÒTXD:
F2, Ò &
F3, Ò &
(F12, H1, M7), Ò &
G1, Ò &
G2, Ò &
G3, Ò &
ÒSCK0:
ÒAVCC:
ÒHACK:
ÒHRW:
H3, Ò &
(H12, K12, L12), Ò &
J1, Ò &
J2, Ò &
ÒHDS:
J3, Ò &
ÒHREQ:
ÒTIO2:
ÒHCS:
K2, Ò &
K3, Ò &
L1, Ò &
ÒTIO1:
ÒTIO0:
ÒHA8:
L2, Ò &
L3, Ò &
M1, Ò &
ÒHA9:
M2, Ò &
MOTOROLA
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C-17
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DSP56309 BSDL Listing
ÒHAS:
M3, Ò &
ÒHVCC:
ÒHAD:
M4, Ò &
(M5, P4, N4, P3, N3, P2, N1, N2), Ò &
ÒPVCC:
ÒEXTAL:
ÒCLKOUT:
ÒBCLK_N:
ÒWR_N:
ÒRD_N:
ÒRESET_N:
ÒPGND:
ÒAA:
ÒCAS_N:
ÒBCLK:
ÒBR_N:
ÒCVCC:
ÒPCAP:
ÒPGND1:
ÒXTAL:
ÒTA_N:
ÒBB_N:
ÒBG_N:
M6, Ò &
M8, Ò &
M9, Ò &
M10, Ò &
M11, Ò &
M12, Ò &
N5, Ò &
N6, Ò &
(N13, P12, P7, N7), Ò &
N8, Ò &
N10, Ò &
N11, Ò &
(N12, P9), Ò &
P5, Ò &
P6, Ò &
P8, Ò &
P10, Ò &
P11, Ò &
P13 Ò;
attribute TAP_SCAN_IN
attribute TAP_SCAN_OUT of
attribute TAP_SCAN_MODE of
of
TDI : signal is true;
TDO : signal is true;
TMS : signal is true;
attribute TAP_SCAN_RESET of TRST_N : signal is true;
attribute TAP_SCAN_CLOCK of
TCK : signal is (20.0e6, BOTH);
attribute INSTRUCTION_LENGTH of DSP56309 : entity is 4;
attribute INSTRUCTION_OPCODE of DSP56309 : entity is
ÒEXTEST
ÒSAMPLE
ÒIDCODE
ÒCLAMP
(0000),Ó &
(0001),Ó &
(0010),Ó &
(0101),Ó &
(0100),Ó &
(0110),Ó &
(0111),Ó &
(1111)Ó;
ÒHIGHZ
ÒENABLE_ONCE
ÒDEBUG_REQUEST
ÒBYPASS
attribute INSTRUCTION_CAPTURE of DSP56309 : entity is Ò0001Ó;
attribute IDCODE_REGISTER of DSP56309 : entity is
Ò0010Ó
& -- version
Ò000110Ó
Ò0000000010Ó
& -- manufacturerÕs use
& -- sequence number
Ò00000001110Ó & -- manufacturer identity
Ò1Ó; -- 1149.1 requirement
attribute REGISTER_ACCESS of DSP56309 : entity is
ÒONCE[8] (ENABLE_ONCE,DEBUG_REQUEST)Ó ;
attribute BOUNDARY_LENGTH of DSP56309 : entity is 144;
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attribute BOUNDARY_REGISTER of DSP56309 : entity is
-- num
Ò0
cell port func
(BC_1, MODA,
(BC_1, MODB,
(BC_1, MODC,
(BC_1, MODD,
(BC_6, D(23),
(BC_6, D(22),
(BC_6, D(21),
(BC_6, D(20),
(BC_6, D(19),
(BC_6, D(18),
(BC_6, D(17),
(BC_6, D(16),
(BC_6, D(15),
(BC_1, *,
safe [ccell dis rslt]
input,
input,
input,
input,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
control,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
X),Ó &
X),Ó &
X),Ó &
X),Ó &
Ò1
Ò2
Ò3
Ò4
Ò5
Ò6
Ò7
Ò8
X,
X,
13, 1, Z),Ó &
13, 1, Z),Ó &
X,
X,
X,
X,
X,
X,
X,
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
Ò9
Ò10
Ò11
Ò12
Ò13
Ò14
Ò15
Ò16
Ò17
Ò18
Ò19
-- num
Ò20
Ò21
Ò22
Ò23
Ò24
Ò25
Ò26
Ò27
Ò28
Ò29
Ò30
Ò31
Ò32
Ò33
Ò34
Ò35
Ò36
Ò37
Ò38
Ò39
-- num
Ò40
Ò41
Ò42
Ò43
Ò44
Ò45
Ò46
Ò47
1),Ó &
X,
X,
X,
X,
(BC_6, D(14),
(BC_6, D(13),
(BC_6, D(12),
(BC_6, D(11),
(BC_6, D(10),
(BC_6, D(9),
cell port func
(BC_6, D(8),
(BC_6, D(7),
(BC_6, D(6),
(BC_6, D(5),
(BC_6, D(4),
(BC_6, D(3),
(BC_1, *,
13, 1, Z),Ó &
13, 1, Z),Ó &
13, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
X,
X,
safe [ccell dis rslt]
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
control,
bidir,
X,
26, 1, Z),Ó &
X,
X,
X,
X,
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
X,
1),Ó &
X,
X,
X,
X,
(BC_6, D(2),
(BC_6, D(1),
(BC_6, D(0),
(BC_1, A(17),
(BC_1, A(16),
(BC_1, A(15),
(BC_1, *,
(BC_1, A(14),
(BC_1, A(13),
(BC_1, A(12),
(BC_1, A(11),
(BC_1, A(10),
(BC_1, A(9),
cell port func
(BC_1, A(8),
(BC_1, A(7),
(BC_1, A(6),
(BC_1, *,
26, 1, Z),Ó &
26, 1, Z),Ó &
26, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
bidir,
bidir,
output3,
output3,
output3,
control,
output3,
output3,
output3,
output3,
output3,
output3,
X,
X,
1),Ó &
X,
X,
X,
X,
33, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
33, 1, Z),Ó &
X,
X,
safe [ccell dis rslt]
output3,
output3,
output3,
control,
output3,
output3,
output3,
output3,
X,
43, 1, Z),Ó &
X,
X,
43, 1, Z),Ó &
43, 1, Z),Ó &
1),Ó &
X,
X,
X,
X,
(BC_1, A(5),
(BC_1, A(4),
(BC_1, A(3),
(BC_1, A(2),
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
43, 1, Z),Ó &
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Ò48
Ò49
Ò50
Ò51
Ò52
Ò53
Ò54
Ò55
Ò56
Ò57
Ò58
Ò59
-- num
Ò60
Ò61
Ò62
Ò63
Ò64
Ò65
Ò66
Ò67
Ò68
Ò69
Ò70
Ò71
Ò72
Ò73
Ò74
Ò75
Ò76
Ò77
Ò78
Ò79
-- num
Ò80
Ò81
Ò82
Ò83
Ò84
Ò85
Ò86
Ò87
Ò88
Ò89
Ò90
Ò91
Ò92
Ò93
Ò94
Ò95
Ò96
Ò97
Ò98
(BC_1, A(1),
output3,
output3,
input,
X,
X,
X),Ó &
X,
X,
X,
X,
1),Ó &
1),Ó &
1),Ó &
X,
43, 1, Z),Ó &
43, 1, Z),Ó &
(BC_1, A(0),
(BC_1, BG_N,
(BC_1, AA(0),
(BC_1, AA(1),
(BC_1, RD_N,
(BC_1, WR_N,
(BC_1, *,
output3,
output3,
output3,
output3,
control,
control,
control,
bidir,
55, 1, Z),Ó &
56, 1, Z),Ó &
64, 1, Z),Ó &
64, 1, Z),Ó &
(BC_1, *,
(BC_1, *,
(BC_6, BB_N,
(BC_1, BR_N,
cell port func
(BC_1, TA_N,
(BC_1, BCLK_N,
(BC_1, BCLK,
(BC_1, CLKOUT,
(BC_1, *,
(BC_1, *,
(BC_1, *,
(BC_1, *,
(BC_1, EXTAL,
(BC_1, CAS_N,
(BC_1, AA(2),
(BC_1, AA(3),
(BC_1, RESET_N, input,
(BC_1, *,
(BC_6, HAD(0),
(BC_1, *,
(BC_6, HAD(1),
(BC_1, *,
(BC_6, HAD(2),
(BC_1, *,
cell port func
(BC_6, HAD(3),
(BC_1, *,
(BC_6, HAD(4),
(BC_1, *,
(BC_6, HAD(5),
(BC_1, *,
(BC_6, HAD(6),
(BC_1, *,
(BC_6, HAD(7),
(BC_1, *,
(BC_6, HAS,
(BC_1, *,
(BC_6, HA8,
(BC_1, *,
(BC_6, HA9,
(BC_1, *,
(BC_6, HCS,
(BC_1, *,
57, 1, Z),Ó &
output2,
X),Ó &
safe [ccell dis rslt]
X),Ó &
input,
output3,
output3,
output2,
control,
control,
control,
control,
input,
X,
X,
64, 1, Z),Ó &
64, 1, Z),Ó &
X),Ó &
1),Ó &
1),Ó &
1),Ó &
1),Ó &
X),Ó &
X,
output3,
output3,
output3,
65, 1, Z),Ó &
66, 1, Z),Ó &
67, 1, Z),Ó &
X,
X,
X),Ó &
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
control,
bidir,
control,
bidir,
control,
bidir,
control,
73, 1, Z),Ó &
75, 1, Z),Ó &
77, 1, Z),Ó &
safe [ccell dis rslt]
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
79, 1, Z),Ó &
81, 1, Z),Ó &
83, 1, Z),Ó &
85, 1, Z),Ó &
87, 1, Z),Ó &
89, 1, Z),Ó &
91, 1, Z),Ó &
93, 1, Z),Ó &
95, 1, Z),Ó &
97, 1, Z),Ó &
control,
bidir,
control,
bidir,
1),Ó &
X,
1),Ó &
X,
(BC_6, TIO0,
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Ò99
(BC_1, *,
control,
1),Ó &
-- num
cell port func
safe [ccell dis rslt]
Ò100 (BC_6, TIO1,
bidir,
X,
99, 1, Z),Ó &
Ò101 (BC_1, *,
Ò102 (BC_6, TIO2,
Ò103 (BC_1, *,
Ò104 (BC_6, HREQ,
Ò105 (BC_1, *,
Ò106 (BC_6, HACK,
Ò107 (BC_1, *,
Ò108 (BC_6, HRW,
Ò109 (BC_1, *,
Ò110 (BC_6, HDS,
Ò111 (BC_1, *,
Ò112 (BC_6, SCK0,
Ò113 (BC_1, *,
Ò114 (BC_6, SCK1,
Ò115 (BC_1, *,
Ò116 (BC_6, SCLK,
Ò117 (BC_1, *,
Ò118 (BC_6, TXD,
Ò119 (BC_1, *,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
1),Ó &
X,
101, 1, Z),Ó &
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
103, 1, Z),Ó &
105, 1, Z),Ó &
107, 1, Z),Ó &
109, 1, Z),Ó &
111, 1, Z),Ó &
113, 1, Z),Ó &
115, 1, Z),Ó &
117, 1, Z),Ó &
control,
bidir,
control,
1),Ó &
-- num
cell port func
safe [ccell dis rslt]
Ò120 (BC_6, RXD,
Ò121 (BC_1, *,
Ò122 (BC_6, SC00,
Ò123 (BC_1, *,
Ò124 (BC_6, SC10,
Ò125 (BC_1, *,
Ò126 (BC_6, STD0,
Ò127 (BC_1, *,
Ò128 (BC_6, SRD0,
Ò129 (BC_1, PINIT,
Ò130 (BC_1, *,
Ò131 (BC_6, DE_N,
Ò132 (BC_1, *,
Ò133 (BC_6, SC01,
Ò134 (BC_1, *,
Ò135 (BC_6, SC02,
Ò136 (BC_1, *,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
input,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
X),Ó &
1),Ó &
X,
1),Ó &
X,
1),Ó &
X,
119, 1, Z),Ó &
121, 1, Z),Ó &
123, 1, Z),Ó &
125, 1, Z),Ó &
127, 1, Z),Ó &
130, 1, Pull1),Ó &
132, 1, Z),Ó &
134, 1, Z),Ó &
136, 1, Z),Ó &
138, 1, Z),Ó &
1),Ó &
X,
1),Ó &
X,
Ò137 (BC_6, STD1,
Ò138 (BC_1, *,
Ò139 (BC_6, SRD1,
-- num
cell port func
safe [ccell dis rslt]
1),Ó &
Ò140 (BC_1, *,
Ò141 (BC_6, SC11,
Ò142 (BC_1, *,
Ò143 (BC_6, SC12,
control,
bidir,
control,
bidir,
X,
140, 1, Z),Ó &
1),Ó &
X,
142, 1, Z)Ó;
end DSP56309;
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DSP56309 BSDL Listing
C-22
DSP56309UM/D
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APPENDIX D
PROGRAMMING REFERENCE
MOTOROLA
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D-1
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Programming Reference
D.1
D.2
D.3
D.4
D.5
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3
INTERNAL I/O MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . D-4
INTERRUPT ADDRESSES AND SOURCES . . . . . . . . . . . D-11
INTERRUPT PRIORITIES. . . . . . . . . . . . . . . . . . . . . . . . . . D-13
PROGRAMMING REFERENCE:
CENTRAL PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . D-15
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-19
HOST INTERFACE (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . D-20
ENHANCED SYNCHRONOUS SERIAL INTERFACE
(ESSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-26
SERIAL COMMUNICATIONS INTERFACE . . . . . . . . . . . . D-30
TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-33
GENERAL PURPOSE I/O (GPIO). . . . . . . . . . . . . . . . . . . . D-36
D-2
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Programming Reference
PERIPHERAL ADDRESSES
D.1
INTRODUCTION
This section has been compiled as a reference for programmers. It contains a table
showing the addresses of all the DSPÕs memory-mapped peripherals, an exception
priority table, and programming sheets for the major programmable registers on the
DSP. The programming sheets are grouped in the following order: central processor,
Phase-Locked Loop (PLL), Host Interface (HI08), Enhanced Synchronous Serial Interface
(ESSI), Serial Communication Interface (SCI), Timer, and GPIO. Each sheet provides
room to write in the value of each bit and the hexadecimal value for each register. The
programmer can photocopy these sheets and reuse them for each application
development project. For details about the instruction set of the DSP56300 family chips,
see the DSP56300 Family Manual.
D.1.1
Peripheral Addresses
Table D-1 lists the memory addresses of all on-chip peripherals.
D.1.2
Interrupt Addresses
Table D-2 on page -11 lists the interrupt starting addresses and sources.
D.1.3
Interrupt Priorities
Table D-3 on page -13 lists the priorities of specific interrupts within interrupt priority
levels.
D.1.4
Programming Sheets
The remaining figures show the major programmable registers on the DSP56309.
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D-3
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Programming Reference
D.2
INTERNAL I/O MEMORY MAP
Table D-1 Internal I/O Memory Map
16-Bit
Address
24-Bit
Peripheral
Register Name
Address
IPR
$FFFF
$FFFE
$FFFD
$FFFC
$FFFB
$FFFA
$FFF9
$FFF8
$FFF7
$FFF6
$FFF5
$FFF4
$FFF3
$FFF2
$FFF1
$FFF0
$FFEF
$FFEE
$FFED
$FFEC
$FFFFFF
$FFFFFE
$FFFFFD
$FFFFFC
$FFFFFB
$FFFFFA
$FFFFF9
$FFFFF8
$FFFFF7
$FFFFF6
$FFFFF5
$FFFFF4
$FFFFF3
$FFFFF2
$FFFFF1
$FFFFF0
$FFFFEF
$FFFFEE
$FFFFED
$FFFFEC
Interrupt Priority Register Core (IPR-C)
Interrupt Priority Register Peripheral (IPR-P)
PLL Control Register (PCTL)
PLL
OnCE
BIU
OnCE GDB Register (OGDB)
Bus Control Register (BCR)
DRAM Control Register (DCR)
Address Attribute Register 0 (AAR0)
Address Attribute Register 1 (AAR1)
Address Attribute Register 2 (AAR2)
Address Attribute Register 3 (AAR3)
ID Register (IDR)
DMA
DMA Status Register (DSTR)
DMA Offset Register 0 (DOR0)
DMA Offset Register 1 (DOR1)
DMA Offset Register 2 (DOR2)
DMA Offset Register 3 (DOR3)
DMA Source Address Register (DSR0)
DMA Destination Address Register (DDR0)
DMA Counter (DCO0)
DMA0
DMA Control Register (DCR0)
D-4
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Table D-1 Internal I/O Memory Map (Continued)
16-Bit
Address
24-Bit
Address
Peripheral
Register Name
DMA1
$FFEB
$FFEA
$FFE9
$FFE8
$FFE7
$FFE6
$FFE5
$FFE4
$FFE3
$FFE2
$FFE1
$FFE0
$FFDF
$FFDE
$FFDD
$FFDC
$FFDB
$FFDA
$FFD9
$FFD8
$FFFFEB
$FFFFEA
$FFFFE9
$FFFFE8
$FFFFE7
$FFFFE6
$FFFFE5
$FFFFE4
$FFFFE3
$FFFFE2
$FFFFE1
$FFFFE0
$FFFFDF
$FFFFDE
$FFFFDD
$FFFFDC
$FFFFDB
$FFFFDA
$FFFFD9
$FFFFD8
DMA Source Address Register (DSR1)
DMA Destination Address Register (DDR1)
DMA Counter (DCO1)
DMA Control Register (DCR1)
DMA2
DMA3
DMA4
DMA5
DMA Source Address Register (DSR2)
DMA Destination Address Register (DDR2)
DMA Counter (DCO2)
DMA Control Register (DCR2)
DMA Source Address Register (DSR3)
DMA Destination Address Register (DDR3)
DMA Counter (DCO3)
DMA Control Register (DCR3)
DMA Source Address Register (DSR4)
DMA Destination Address Register (DDR4)
DMA Counter (DCO4)
DMA Control Register (DCR4)
DMA Source Address Register (DSR5)
DMA Destination Address Register (DDR5)
DMA Counter (DCO5)
DMA Control Register (DCR5)
MOTOROLA
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Programming Reference
Table D-1 Internal I/O Memory Map (Continued)
16-Bit
Address
24-Bit
Address
Peripheral
Register Name
Ñ
$FFD7
$FFD6
$FFD5
$FFD4
$FFD3
$FFD2
$FFD1
$FFD0
$FFCF
$FFCE
$FFCD
$FFCC
$FFCB
$FFCA
$FFC9
$FFC8
$FFC7
$FFC6
$FFC5
$FFC4
$FFC3
$FFC2
$FFC1
$FFC0
$FFFFD7
$FFFFD6
$FFFFD5
$FFFFD4
$FFFFD3
$FFFFD2
$FFFFD1
$FFFFD0
$FFFFCF
$FFFFCE
$FFFFCD
$FFFFCC
$FFFFCB
$FFFFCA
$FFFFC9
$FFFFC8
$FFFFC7
$FFFFC6
$FFFFC5
$FFFFC4
$FFFFC3
$FFFFC2
$FFFFC1
$FFFFC0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Ñ
PORT B
HI08
Host Port GPIO Data Register (HDR)
Host Port GPIO Direction Register (HDDR)
Host Transmit Register (HTX)
Host Receive Register (HRX)
Host Base Address Register (HBAR)
Host Polarity Control Register (HPCR)
Host Status Register (HSR)
Host Control Register (HCR)
Reserved
Reserved
D-6
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Table D-1 Internal I/O Memory Map (Continued)
16-Bit
Address
24-Bit
Address
Peripheral
Register Name
PORT C
$FFBF
$FFBE
$FFBD
$FFBC
$FFBB
$FFBA
$FFB9
$FFB8
$FFB7
$FFB6
$FFB5
$FFB4
$FFB3
$FFB2
$FFB1
$FFB0
$FFAF
$FFAE
$FFAD
$FFFFBF
$FFFFBE
$FFFFBD
$FFFFBC
$FFFFBB
$FFFFBA
$FFFFB9
$FFFFB8
$FFFFB7
$FFFFB6
$FFFFB5
$FFFFB4
$FFFFB3
$FFFFB2
$FFFFB1
$FFFFB0
$FFFFAF
$FFFFAE
$FFFFAD
Port C Control Register (PCRC)
Port C Direction Register (PRRC)
Port C GPIO Data Register (PDRC)
ESSI 0 Transmit Data Register 0 (TX00)
ESSI 0 Transmit Data Register 1 (TX01)
ESSI 0 Transmit Data Register 2 (TX02)
ESSI 0 Time Slot Register (TSR0)
ESSI 0 Receive Data Register (RX0)
ESSI 0 Status Register (SSISR0)
ESSI 0
ESSI 0 Control Register B (CRB0)
ESSI 0 Control Register A (CRA0)
ESSI 0 Transmit Slot Mask Register A (TSMA0)
ESSI 0 Transmit Slot Mask Register B (TSMB0)
ESSI 0 Receive Slot Mask Register A (RSMA0)
ESSI 0 Receive Slot Mask Register B (RSMB0)
Reserved
Ñ
PORT D
Port D Control Register (PCRD)
Port D Direction Register (PRRD)
Port C GPIO Data Register (PDRD)
MOTOROLA
DSP56309UM/D
D-7
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Table D-1 Internal I/O Memory Map (Continued)
16-Bit
Address
24-Bit
Address
Peripheral
Register Name
ESSI 1
$FFAC
$FFAB
$FFAA
$FFA9
$FFA8
$FFA7
$FFA6
$FFA5
$FFA4
$FFA3
$FFA2
$FFA1
$FFA0
$FF9F
$FF9E
$FF9D
$FFFFAC
$FFFFAB
$FFFFAA
$FFFFA9
$FFFFA8
$FFFFA7
$FFFFA6
$FFFFA5
$FFFFA4
$FFFFA3
$FFFFA2
$FFFFA1
$FFFFA0
$FFFF9F
$FFFF9E
$FFFF9D
ESSI 1 Transmit Data Register 0 (TX10)
ESSI 1 Transmit Data Register 1 (TX11)
ESSI 1 Transmit Data Register 2 (TX12)
ESSI 1 Time Slot Register (TSR1)
ESSI 1 Receive Data Register (RX1)
ESSI 1 Status Register (SSISR1)
ESSI 1 Control Register B (CRB1)
ESSI 1 Control Register A (CRA1)
ESSI 1 Transmit Slot Mask Register A (TSMA1)
ESSI 1 Transmit Slot Mask Register B (TSMB1)
ESSI 1 Receive Slot Mask Register A (RSMA1)
ESSI 1 Receive Slot Mask Register B (RSMB1)
Reserved
Ñ
PORT E
Port E Control Register (PCRE)
Port E Direction Register (PRRE)
Port E GPIO Data Register (PDRE)
D-8
DSP56309UM/D
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Table D-1 Internal I/O Memory Map (Continued)
16-Bit
Address
24-Bit
Address
Peripheral
Register Name
SCI Control Register (SCR)
SCI
$FF9C
$FF9B
$FF9A
$FF99
$FF98
$FF97
$FF96
$FF95
$FF94
$FF93
$FF92
$FF91
$FF90
$FFFF9C
$FFFF9B
$FFFF9A
$FFFF99
$FFFF98
$FFFF97
$FFFF96
$FFFF95
$FFFF94
$FFFF93
$FFFF92
$FFFF91
$FFFF90
SCI Clock Control Register (SCCR)
SCI Receive Data Register - High (SRXH)
SCI Receive Data Register - Middle (SRXM)
SCI Recieve Data Register - Low (SRXL)
SCI Transmit Data Register - High (STXH)
SCI Transmit Data Register - Middle (STXM)
SCI Transmit Data Register - Low (STXL)
SCI Transmit Address Register (STXA)
SCI Status Register (SSR)
Ñ
Reserved
Reserved
Reserved
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D-9
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Table D-1 Internal I/O Memory Map (Continued)
16-Bit
Address
24-Bit
Address
Peripheral
Register Name
TRIPLE
TIMER
$FF8F
$FF8E
$FF8D
$FF8C
$FF8B
$FF8A
$FF89
$FF88
$FF87
$FF86
$FF85
$FF84
$FF83
$FF82
$FF81
$FF80
$FFFF8F
$FFFF8E
$FFFF8D
$FFFF8C
$FFFF8B
$FFFF8A
$FFFF89
$FFFF88
$FFFF87
$FFFF86
$FFFF85
$FFFF84
$FFFF83
$FFFF82
$FFFF81
$FFFF80
Timer 0 Control/Status Register (TCSR0)
Timer 0 Load Register (TLR0)
Timer 0 Compare Register (TCPR0)
Timer 0 Count Register (TCR0)
Timer 1 Control/Status Register (TCSR1)
Timer 1 Load Register (TLR1)
Timer 1 Compare Register (TCPR1)
Timer 1 Count Register (TCR1)
Timer 2 Control/Status Register (TCSR2)
Timer 2 Load Register (TLR2)
Timer 2 Compare Register (TCPR2)
Timer 2 Count Register (TCR2)
Timer Prescaler Load Register (TPLR)
Timer Prescaler Count Register (TPCR)
Reserved
Ñ
Reserved
D-10
DSP56309UM/D
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D.3
INTERRUPT ADDRESSES AND SOURCES
Table D-2 Interrupt Sources
Interrupt
Interrupt
Priority
Starting
Address
Interrupt Source
Level
Range
VBA:$00
VBA:$02
VBA:$04
VBA:$06
VBA:$08
VBA:$0A
VBA:$0C
VBA:$0E
VBA:$10
VBA:$12
VBA:$14
VBA:$16
VBA:$18
VBA:$1A
VBA:$1C
VBA:$1E
VBA:$20
VBA:$22
VBA:$24
VBA:$26
VBA:$28
VBA:$2A
VBA:$2C
VBA:$2E
VBA:$30
VBA:$32
VBA:$34
VBA:$36
3
Hardware RESET
Stack Error
3
3
Illegal Instruction
3
Debug Request Interrupt
Trap
3
3
Non-Maskable Interrupt (NMI)
Reserved
3
3
Reserved
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
IRQA
IRQB
IRQC
IRQD
DMA Channel 0
DMA Channel 1
DMA Channel 2
DMA Channel 3
DMA Channel 4
DMA Channel 5
TIMER 0 Compare
TIMER 0 Overflow
TIMER 1 Compare
TIMER 1 Overflow
TIMER 2 Compare
TIMER 2 Overflow
ESSI0 Receive Data
ESSI0 Receive Data With Exception Status
ESSI0 Receive Last Slot
ESSI0 Transmit Data
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DSP56309UM/D
D-11
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Table D-2 Interrupt Sources (Continued)
Interrupt
Priority
Level
Range
Interrupt
Starting
Address
Interrupt Source
VBA:$38
VBA:$3A
VBA:$3C
VBA:$3E
VBA:$40
VBA:$42
VBA:$44
VBA:$46
VBA:$48
VBA:$4A
VBA:$4C
VBA:$4E
VBA:$50
VBA:$52
VBA:$54
VBA:$56
VBA:$58
VBA:$5A
VBA:$5C
VBA:$5E
VBA:$60
VBA:$62
VBA:$64
VBA:$66
:
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
0Ð2
:
ESSI0 Transmit Data With Exception Status
ESSI0 Transmit Last Slot
Reserved
Reserved
ESSI1 Receive Data
ESSI1 Receive Data With Exception Status
ESSI1 Receive Last Slot
ESSI1 Transmit Data
ESSI1 Transmit Data With Exception Status
ESSI1 Transmit Last Slot
Reserved
Reserved
SCI Receive Data
SCI Receive Data With Exception Status
SCI Transmit Data
SCI Idle Line
SCI Timer
Reserved
Reserved
Reserved
Host Receive Data Full
Host Transmit Data Empty
Host Command (Default)
Reserved
:
VBA:$FE
0Ð2
Reserved
D-12
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D.4
INTERRUPT PRIORITIES
Table D-3 Interrupt Source Priorities within an IPL
Priority
Interrupt Source
Level 3 (Nonmaskable)
Highest
Ñ
Hardware RESET
Stack Error
Ñ
Illegal Instruction
Debug Request Interrupt
Trap
Ñ
Ñ
Lowest
Non-Maskable Interrupt
Levels 0, 1, 2 (Maskable)
Highest
Ñ
IRQA (External Interrupt)
IRQB (External Interrupt)
IRQC (External Interrupt)
IRQD (External Interrupt)
DMA Channel 0 Interrupt
DMA Channel 1 Interrupt
DMA Channel 2 Interrupt
DMA Channel 3 Interrupt
DMA Channel 4 Interrupt
DMA Channel 5 Interrupt
Host Command Interrupt
Host Transmit Data Empty
Host Receive Data Full
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
ESSI0 RX Data with Exception Interrupt
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D-13
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Programming Reference
Table D-3 Interrupt Source Priorities within an IPL (Continued)
Priority
Interrupt Source
ESSI0 RX Data Interrupt
Ñ
Ñ
ESSI0 Receive Last Slot Interrupt
ESSI0 TX Data With Exception Interrupt
ESSI0 Transmit Last Slot Interrupt
ESSI0 TX Data Interrupt
Ñ
Ñ
Ñ
Ñ
ESSI1 RX Data With Exception Interrupt
ESSI1 RX Data Interrupt
Ñ
Ñ
ESSI1 Receive Last Slot Interrupt
ESSI1 TX Data With Exception Interrupt
ESSI1 Transmit Last Slot Interrupt
ESSI1 TX Data Interrupt
Ñ
Ñ
Ñ
Ñ
SCI Receive Data With Exception Interrupt
SCI Receive Data
Ñ
Ñ
SCI Transmit Data
Ñ
SCI Idle Line
Ñ
SCI Timer
Ñ
TIMER0 Overflow Interrupt
TIMER0 Compare Interrupt
TIMER1 Overflow Interrupt
TIMER1 Compare Interrupt
TIMER2 Overflow Interrupt
TIMER2 Compare Interrupt
Ñ
Ñ
Ñ
Ñ
Lowest
D-14
DSP56309UM/D
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Sheet 1 of 5
Carry
Overßow
Zero
Negative
Central Processor
Unnormalized ( U = Acc(47) xnor Acc(46) )
Extension
Limit
FFT Scaling ( S = Acc(46) xor Acc(45) )
Interrupt Mask
I(1:0) Exceptions Masked
00 None
01 IPL 0
10 IPL 0, 1
11 IPL 0, 1, 2
Scaling Mode
S(1:0) Scaling Mode
00 No scaling
01 Scale down
10 Scale up
11 Reserved
Reserved
Sixteen-Bit Compatibilitity
Double Precision Multiply Mode
Loop Flag
DO-Forever Flag
Sixteenth-Bit Arithmetic
Reserved
Instruction Cache Enable
Arithmetic Saturation
Rounding Mode
Core Priority
CP(1:0) Core Priority
00
01
10
11
0 (lowest)
1
2
3 (highest)
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CP1 CP0 RM SM
CE
SA
FV
LF DM
SC
S1
S0
I1
I0
S
L
E
U
N
Z
V
C
*
0
*
0
Extended Mode Register (MR)
Mode Register (MR)
Condition Code Register (CCR)
Status Register (SR)
Read/Write
Reset = $C00300
= Reserved, Program as 0
*
Figure D-1 Status Register (SR)
MOTOROLA
DSP56309UM/D
D-15
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Sheet 2 of 5
Central Processor
Chip Operating Modes
MOD(D:A) Reset Vector Description
Expanded mode
0000
$C00000
$FF0000
$FF0000
Ñ
$FF0000
$FF0000
$FF0000
$FF0000
$008000
X001
X010
X011
X100
X101
X110
X111
1000
Bootstrap from byte wide memory
Bootstrap through SCI
Reserved
Host Bootstrap PCI mode (32-bit wide)
Host Bootstrap 16-bit wide UB mode (ISA)
Host Bootstrap 8-bit wide UB mode (dbl strb)
Host Bootstrap 8-bit wide UB mode (sgl strb)
Expanded mode
External Bus Disable
Stop Delay
Memory Switch Mode
Core-DMA Priority
CDP(1:0)
Core-DMA Priority
00
01
10
11
Core vs DMA Priority
DMA accesses > Core
DMA accesses = Core
DMA accesses < Core
Burst Mode Enable
TA Synchronize Select
Bus Release Timing
Stack Extension Space Select
Extended Stack Underflow Flag
Extended Stack Overflow Flag
Extended Stack Wrap Flag
Stack Extension Enable
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SEN WRP EOV EUN XYS
BRT TAS BE CDP1 CDP0 MS
SD
EBD MD MC MB
MA
* * *
0 0 0
* * *
0 0 0
*
0
System Stack Control
Status Register (SCS)
Extended Chip Operating
Mode Register (COM)
Chip Operating Mode
Register (COM)
Operating Mode Register (OMR)
Read/Write
Reset = $00030X
= Reserved, Program as 0
*
X = Latched from levels on Mode pins
Figure D-2 Operating Mode Register (OMR)
D-16
DSP56309UM/D
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Sheet 3 of 5
Figure D-3 Interrupt Priority RegisterÐCore (IPRÐC)
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D-17
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Sheet 4 of 5
Figure D-4 Interrupt Priority Register Ð Peripherals (IPRÐP)
D-18
DSP56309UM/D
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Sheet 5 of 5
Figure D-5 Phase-Locked Loop Control Register (PCTL)
MOTOROLA
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D-19
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Sheet 1 of 6
HOST
Host Receive Data (usually Read by program)
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Receive High Byte
Receive Middle Byte
Receive Low Byte
Host Receive Data Register (HRX)
X:$FFEC6 Read Only
Reset = empty
Host Transmit Data (usually Loaded by program)
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Transmit High Byte
Transmit Middle Byte
Transmit Low Byte
Host Transmit Data Register (HTX)
X:$FFEC7 Write Only
Reset = empty
Figure D-6 Host Receive and Host Transmit Data Registers
D-20
DSP56309UM/D
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Sheet 2 of 6
HOST
Host Receive Interrupt Enable
0 = Disable 1 = Enable if HRDF = 1
Host Transmit Interrupt Enable
0 = Disable 1 = Enable if HTDE = 1
Host Command Interrupt Enable
0 = Disable 1 = Enable if HCP = 1
Host Flag 2
Host Flag 3
15 7
6
5
4
3
2
1
0
HF3 HF2 HCIE HTIE HRIE
Host Control Register (HCR)
X:$FFFFC2 Read /Write
Reset = $0
* * * *
0 0 0 0
DSP Side
Host Receive Data Full
0 = ¸ Wait 1 = ¸ Read
Host Transmit Data Empty
0 = ¸ Wait 1 = ¸ Write
Host Command Pending
0 = ¸ Wait 1 = ¸ Ready
Host Flags
Read Only
15 7
6
5
4
3
2
1
0
HF1 HF0 HCP HTDE HRDF
Host Staus Register (HSR)
* * * *
0 0 0 0
X:$FFFFC3 Read Only
Reset = $2
= Reserved, Program as 0
*
Figure D-7 Host Control and Host Status Registers
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D-21
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Programmer:
Sheet 3 of 6
HOST
15
8
7
6
5
4
3
2
1
0
BA10
BA9
BA8
BA7
BA6
BA5
BA4
BA3
Host Base Address Register (HBAR)
* *
0
0
X:$FFFFC5
Reset = $80
Host Request Open Drain
Host GPIO Port Enable
0 = GPIO Pins Disable, 1 = GPIO Pin Enable
HDRQ
HROD
HREN/HEW
0
0
1
1
0
1
0
1
1
1
1
1
Host Address Line 8 Enable
0 ® HA8 = GPIO, 1 ® HA8 = HA8
Host Address Line 9 Enable
0 ® HA9 = GPIO, 1 ® HA9 = HA9
Host Data Strobe Polarity
0 = Strobe Active Low, 1 = Strobe Active High
Host Chip Select Enable
0 ® HCS/HAI0 = GPIO,
Host Address Strobe Polarity
0 = Strobe Active Low, 1 = Strobe Active High
1 ® HCS/HA10 = HC8, if HMUX = 0
1 ® HCS/HA10 = HC10, if HMUX = 1
Host Multiplexed Bus
0 = Nonmultiplexed, 1 = Multiplexed
Host Request Enable
0 ® HREQ/HACK = GPIO,
1 ® HREQ = HREQ, if HDRQ = 0
Host Dual Data Strobe
0 = Singles Stroke, 1 = Dual Stoke
Host Chip Select Polarity
0 = HCS Active Low
Host Acknowledge Enable
0 ® HACK = GPIO
If HDRQ & HREN = 1,
HACK = HACK
HTRQ & HRRQ Enable
1 = HCS Active High
Host Request Priority
HDRQ
HRP
Host Enable
0 ® HI08 Disable
Pins = GPIO
0
0
1
1
0
1
0
1
HREQ Active Low
HREQ Active High
HTRQ,HRRQ Active Low
HTRQ,HRRQ Active High
1 ® HI08 Enable
Host Acknowledge Priority
0 = HACK Active Low, 1 = HACK Active High
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
HAP
HRP HCSP HDDS HMUX HASP HDSP HROD
HEN
HAEN HREN HCSEN HA9EN HA8EN HGEN
Host Port Control
Register (HPCR)
*
0
X:$FFFFC4
Read/Write
Reset = $0
= Reserved, Program as 0
*
Figure D-8 Host Base Address and Host Port Control Registers
D-22
DSP56309UM/D
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Sheet 4 of 6
Processor Side
HOST
Receive Request Enable
DMA Off
DMA On
0 = ¸ Interrupts Disabled 1 = Interrupts Enabled
0 = Host ® DSP 1 = DSP ® Host
Transmit Request Enable
DMA Off
DMA On
0 = Õ Interrupts Disabled 1 = Interrupts Enabled
0 = DSP ® Host 1 = Host ® DSP
HDRQ HREQ/HTRQ HACK/HRRQ
0
1
HREQ
HTRQ
HACK
HRRQ
Host Flags
Write Only
Host Little Endian
Initialize (Write Only)
0 = ¸ No Action 1 = ¸ Initialize DMA
7
6
5
4
3
2
1
0
INIT
HLEND HF1
HF0
HDRQ TREQ RREQ
Interrupt Control Register (ICR)
*
0
X:$
Read/Write
Reset = $0
Receive Data Register Full
0 = Wait 1 = Read
Transmit Data Register Empty
0 = Wait 1 = Write
Transmitter Ready
0 = Data in HI 1 = Data Not in HI
Host Flags
Read Only
DMA Status
0 = ¸ DMA Disabled
1 = ¸ DMA Enabled
Host Request
0 = ¸ HREQ Deasserted 1 = ¸ HREQ Asserted
7
6
5
4
3
2
1
0
HREQ DMA
HF3
HF2
TRDY TXDE RXDF
Interrupt Status Register (ISR)
*
0
$2 Read/Write
Reset = $06
= Reserved, Program as 0
*
*
Figure D-9 Interrupt Control and Interrupt Status Registers
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D-23
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Application:
Programmer:
Sheet 5 of 6
HOST
7
6
5
4
3
2
1
0
IV7
IV6
IV5
IV4
IV3
IV2
IV1
IV0
Interrupt Vector Register (IVR)
Reset = $0F
Contains the interrupt vector or number
Host Vector
Contains Host Command Interrupt Address Ö 2
Host Command
Handshakes Executing Host Command Interrupts
7
6
5
4
3
2
1
0
HC7
HC6
HC5
HC4
HC3
HC2
HC1
HC0
Command Vector Register (CVR)
Reset = $2A
Contains the host command interrupt address
Figure D-10 Interrupt Vector and Command Vector Registers
D-24
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Sheet 6 of 6
Processor Side
HOST
Host Receive Data (usually Read by program)
7
0 7
0 7
0 7
0
Receive Low Byte
Receive Middle Byte
Receive High Byte
Not Used
0
0
0
0
0
0
0
0
$7
$6
$5
$4
Receive Byte Registers
$7, $6, $5, $4 Read Only
Reset = $00
Receive Byte Registers
Host Transmit Data (usually loaded by program)
7
0 7
0 7
0 7
0
Transmit Low Byte
Transmit Middle Byte
Transmit High Byte
Not Used
0
0
0
0
0
0
0
0
$7
$6
$5
$4
Transmit Byte Registers
$7, $6, $5, $4 Write Only
Reset = $00
Figure D-11 Host Receive and Host Transmit Data Registers
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D-25
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Sheet 1 of 4
Figure D-12 ESSI Control Register A (CRA)
D-26
DSP56309UM/D
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Sheet 2 of 4
Figure D-13 ESSI Control Register B (CRB)
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D-27
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Programmer:
Sheet 3 of 4
ESSI
Serial Input Flag 0
If SCD0 = 0, SYN = 1, & TE1 = 0
latch SC0 on FS
Serial Input Flag 1
If SCD1 = 0, SYN = 1, & TE2 = 0
latch SC0 on FS
Transmit Frame Sync
0 = ¸ Sync Inactive 1 = ¸ Sync Active
Receive Frame Sync
0 = ¸ Wait 1 = ¸ Frame Sync Occurred
Transmitter Underrun Error Flag
0 = ¸ OK
1 = ¸ Error
Receiver Overrun Error Flag
0 = ¸ OK 1 = ¸ Error
Transmit Data Register Empty
0 = ¸ Wait 1 = ¸ Write
Receive Data Register Full
0 = ¸ Wait
1 = ¸ Read
23
7
6
5
4
3
2
1
0
RDF TDE ROE TUE RFS TFS IF1
IF0
*
0
SSI Status Register (SSISRx)
ESSI0: $FFFFB7 (Read)
ESSI1: $FFFFA7 (Read)
SSI Status Bits
= Reserved, program as 0
*
Figure D-14 ESSI Status Register (SSISR)
D-28
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Programming Reference
Date:
Application:
Programmer:
Sheet 4 of 4
SSI Transmit Slot Mask
0 = IgnoreTime Slot
1 = Active Time Slot
ESSI
23 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ESSI Transmit Slot Mask A
TSMAx
ESSI0: $FFFFB4 Read/Write
ESSI1: $FFFFA4 Read/Write
Reset = $FFFF
TS15 TS14 TS13 TS12 TS11 TS10 TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0
* *
0 0
ESSI Transmit Slot Mask A
= Reserved, Program as 0
*
SSI Transmit Slot Mask
0 = IgnoreTime Slot
1 = ActiveTime Slot
23 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TS31 TS30 TS29 TS28 TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16
ESSI Transmit Slot Mask B
TSMBx
ESSI0: $FFFFB3 Read/Write
ESSI1: $FFFFA3 Read/Write
Reset = $FFFF
* *
0 0
ESSI Transmit Slot Mask B
= Reserved, Program as 0
*
SSI Receive Slot Mask
0 = IgnoreTime Slot
1 = ActiveTime Slot
23 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SSI Receive Slot Mask A
RSMAx
ESSI0: $FFFFB2 Read/Write
ESSI1: $FFFFA2 Read/Write
Reset = $FFFF
RS15 RS14 RS13 RS12 RS11 RS10 RS9 RS8 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0
* *
0 0
ESSI Receive Slot Mask A
= Reserved, Program as 0
*
SSI Receive Slot Mask
0 = Ignore Time Slot
1 = Active Time Slot
23 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SSI Receive Slot Mask B
RSMBx
ESSI0: $FFFFB1 Read/Write
ESSI1: $FFFFA1 Read/Write
Reset = $FFFF
RS31 RS30 RS29 RS28 RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16
* *
0 0
ESSI Receive Slot Mask B
= Reserved, Program as 0
*
Figure D-15 ESSR Transmit and Receive Slot Mask Registers (TSM, RSM)
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Programming Reference
Date:
Application:
Programmer:
Sheet 1 of 3
SCI
Word Select Bits
0 0 0 = 8-bit Synchronous Data (Shift Register Mode)
0 0 1 = Reserved
Transmitter Enable
0 = Transmitter Disable
1 = Transmitter Enable
0 1 0 = 10-bit Asynchronous (1 Start, 8 Data, 1 Stop)
0 1 1 = Reserved
1 0 0 = 11-bit Asynchronous (1 Start, 8 Data, Even Parity, 1 Stop)
1 0 1 = 11-bit Asynchronous (1 Start, 8 Data, Odd Parity, 1 Stop)
1 1 0 = 11-bit Multidrop (1 Start, 8 Data, Data Type, 1 Stop)
1 1 1 = Reserved
Idle Line Interrupt Enable
0 = Idle Line Interrupt Disabled
1 = Idle Line Interrupt Enabled
Receive Interrupt Enable
0 = Receive Interrupt Disabled
1 = Idle Line Interrupt Enabled
Receiver Wakeup Enable
0 = receiver has awakened
1 = Wakeup function enabled
SCI Shift Direction
0 = LSB First
1 = MSB First
Transmit Interrupt Enable
0 = Transmit Interrupts Disabled
1 = Transmit Interrupts Enabled
Wired-Or Mode Select
1 = Multidrop
0 = Point to Point
Send Break
Timer Interrupt Enable
0 = Timer Interrupts Disabled
1 = Timer Interrupts Enabled
0 = Send break, then revert
1 = Continually send breaks
Receiver Enable
0 = Receiver Disabled
1 = Receiver Enabled
Wakeup Mode Select
0 = Idle Line Wakeup
1 = Address Bit Wakeup
SCI Timer Interrupt Rate
0 = Ö 32, 1 = Ö 1
SCI Clock Polarity
0 = Clock Polarity is Positive
1 = Clock Polarity is Negative
SCI Receive Exception Inerrupt
0 = Receive Interrupt Disable
1 = Receive Interrupt Enable
23 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SCI Control
Register (SCR)
Address X:$FFFF9C
Read/Write
REIE SCKP STIR TMIE TIE RIE ILIE TE RE WOMS RWU WAKE SBK SSFTD WDS2 WDS1 WDS0
*
0
= Reserved, Program as 0
*
SCI Control Register (SCR)
Figure D-16 SCI Control Register (SCR)
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Programming Reference
Date:
Application:
Programmer:
Sheet 2 of 3
Overrun Error Flag
0 = No error
Idle Line Flag
0 = Idle not detected
SCI
1 = Overrun detected
1 = Idle State
Parity Error Flag
0 = No error
1 = Incorrect Parity detected
Receive Data Register Full
0 = Receive Data Register Empty
1 = Receive Data Register Full
Framing Error Flag
0 = No error
1 = No Stop Bit detected
Transmitter Data Register Empty
0 = Transmitter Data Register full
1 = Transmitter Data Register empty
Received Bit 8
0 = Data
1 = Address
Transmitter Empty
0 = Transmitter full
1 = Transmitter empty
23
7
6
5
4
3
2
1
0
R8
FE
PE
OR IDLE RDRF TDRE TRNE
SCI Status Register (SSR)
*
0
Address X:$FFFF93
Read Only
Reset = $000003
$0
$3
= Reserved, Program as 0
SCI Status Register (SSR)
*
Clock Divider Bits CD11 Ð CD0)
Clock Divider Bits CD11 Ð CD0)
TCM RCM TX Clock RX Clock SCLK Pin
CD11 Ð CD0
I
Rate
Mode
cyc
$000
$001
$002
¥
I
I
I
/1
0
0
1
1
0
1
0
1
Internal
Internal
Output
Input
Input
Input
Synchronous/Asynchronous
Asynchronous only
Asynchronous only
Synchronous/Asynchronous
cyc
/2
/3
Internal External
External Internal
External External
cyc
cyc
¥
¥
¥
¥
¥
Receiver Clock Mode/Source
Transmitter Clock Mode/Source
0 = Internal clock for Receiver
0 = Internal clock for Transmitter
$FFE
$FFF
I
I
/4095
/4096
cyc
cyc
1 = External clock from SCLK
1 = External clock from SCLK
Clock Out Divider
0 = Divide clock by 16 before feed to SCLK
1 = Feed clock to directly to SCLK
SCI Clock Prescaler
0 = Ö1 1 = Ö 8
23 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TCM RCM SCP COD CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
*
0
= Reserved, Program as 0
*
SCI Clock Control Register (SCCR)
Figure D-17 SCI Status and Clock Control Registers (SSR, SCCR)
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Programming Reference
Date:
Application:
Programmer:
Sheet 3 of 3
SCI
ÒAÓ
ÒBÓ
ÒCÓ
X0
Unpacking
16 15
23
8 7
0
SCI Transmit Data Registers
Address X:$FFFF95 Ð X:$FFFF97
Write
X:$FFFF97
X:$FFFF96
X:$FFFF95
STX
STX
Reset = xxxxxx
STX
TXD
Note: STX is the same register decoded at four different addresses
SCI Transmit SR
SCI Transmit Data Registers
X:$FFFF94
STXA
RXD
23
SCI Receive SR
16 15
8 7
0
SRX
SCI Receive Data Registers
Address X:$FFFF98 Ð X:$FFFF9A
X:$FFFF9A
X:$FFFF99
X:$FFFF98
SRX
ÒBÓ
Read
Reset = xxxxxx
SRX
ÒAÓ
Packing
ÒCÓ
Note: STX is the same register decoded at three different addresses
SCI Receive Data Registers
Figure D-18 SCI Receive and Transmit Data Registers (SRX, TRX)
D-32
DSP56309UM/D
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Programming Reference
Date:
Programmer:
Application:
Sheet 1 of 3
Timers
PS (1:0)
00
Prescaler Clock Source
Internal CLK/2
TIO0
01
10
TIO1
11
TIO2
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PS1 PS0
Prescaler Preload Value (PL [0:20])
*
0
Timer Prescaler Load Register
TPLR:$FFFF83 Read/Write
Reset = $000000
= Reserved, Program as 0
*
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Current Value of Prescaler Counter (PC [0:20])
* * *
0 0 0
Timer Prescaler Count Register
TPCR:$FFFF82 Read Only
Reset = $000000
= Reserved, Program as 0
*
Figure D-19 Timer Prescaler Load/Count Register (TPLR, TPCR)
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Programming Reference
Date:
Application:
Programmer:
Sheet 2 of 3
Inverter Bit 8
0 = 0- to-1 transitions on TIO input increment the counter,
Timers
or high pulse width measured, or high pulse output on TIO
1 = 1-to-0 transitions on TIO input increment the counter,
or low pulse width measured, or low pulse output on TIO
Timer Control Bits 4 Ð 7 (TC0 Ð TC3)
TIO Clock Mode
GPIO Internal Timer
Output Internal Timer Pulse
Output Internal Timer Toggle
Input External Event Counter
Timer Reload Mode Bit 9
TC (3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0 = Timer operates as a free
running counter
1 = Timer is reloaded when
selected condition occurs
Input
Input
Input
Internal Input Width
Internal Input Period
Internal Capture
Direction Bit 11
0 = TIO pin is input
1 = TIO pin is output
Output Internal Pulse Width Modulation
Reserved
Ð
Ð
Data Input Bit 12
0 = Zero read on TIO pin
1 = One read on TIO pin
Output Internal Watchdog Pulse
Output Internal Watchdog Toggle
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Reserved
Reserved
Reserved
Reserved
Reserved
Data Output Bit 13
0 = Zero written to TIO pin
1 = One written to TIO pin
Timer Enable Bit 0
0 = Timer Disabled
1 = Timer Enabled
Prescaled Clock Enable Bit 15
0 = Clock source is CLK/2 or TIO
1 = Clock source is prescaler output
Timer Overflow Interrupt Enable Bit 1
0 = Overflow Interrupts Disabled
1 = Overflow Interrupts Enabled
Timer Compare Flag Bit 21
0 = Ò1Ó has been written to TCSR(TCF),
or timer compare interrupt serviced
Timer Compare Interrupt Enable Bit 2
0 = Compare Interrupts Disabled
1 = Compare Interrupts Enabled
1 = Timer Compare has occurred
Timer Overflow Flag Bit 20
0 = Ò1Ó has been written to TCSR(TOF),
or timer Overflow interrupt serviced
1 = Counter wraparound has occurred
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TCF TOF
PCE
DO
DI
DIR
TRM INV TC3 TC2 TC1 TC0
TCIE TQIE TE
* * * * * * *
*
0
*
0
0 0
0 0 0 0
0
Timer Control/Status Register
TCSR0:$FFFF8F Read/Write
TCSR1:$FFFF8B Read/Write
TCSR2:$FFFF87 Read/Write
Reset = $000000
= Reserved, Program as 0
*
Figure D-20 Timer Control/Status Register (TCSR)
D-34
DSP56309UM/D
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Programming Reference
Date:
Programmer:
Application:
Sheet 3 of 3
Timers
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
Timer Reload Value
Timer Load Register
TLR0:$FFFF8E Write Only
TLR1:$FFFF8A Write Only
TLR2:$FFFF86 Write Only
Reset = $000000
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
Value Compared to Counter Value
Timer Compare Register
TCPR0:$FFFF8D Read/Write
TCPR1:$FFFF89 Read/Write
TCPR2:$FFFF85 Read/Write
Reset = $000000
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
Timer Count Value
Timer Count Register
TCR0:$FFFF8C Read Only
TCR1:$FFFF88 Read Only
TCR2:$FFFF84 Read Only
Reset = $000000
Figure D-21 Timer Load, Compare, Count Registers (TLR, TCPR, TCR)
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Programming Reference
Date:
Application:
Programmer:
Sheet 1 of 4
Port B (HI08)
GPIO
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Host Data
Direction Register
(HDDR)
DR15 DR14 DR13 DR12 DR11 DR10 DR9
DR8
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
X:$FFFFC8
Write
Reset = $0
DRx = 1 ® HIx is Output
DRx = 0 ® HIx is Input
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Host Data
Register
(HDR)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X:$FFFFC9
Write
Reset = Undefined
DRx holds value of corresponding HI08 GPIO pin.
Function depends on HDDR.
Figure D-22 Host Data Direction and Host Data Registers (HDDR, HDR)
D-36
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Programming Reference
Date:
Application:
Programmer:
Sheet 2 of 4
Port C (ESSI0)
GPIO
23
6
5
4
3
2
1
0
Port C Control Register
PC5
PC4
PC3
PC2
PC1
PC0
(PCRC)
X:$FFFFBF
ReadWrite
Reset = $0
* *
0 0
PCn = 1 ® Port Pin configured as ESSI
PCn = 0 ® Port Pin configured as GPIO
23
6
5
4
3
2
1
0
Port C Direction Register
(PRRC)
PDC5 PDC4 PDC3 PDC2 PDC1 PDC0
* *
0 0
X:$FFFFBE
ReadWrite
Reset = $0
PDCn = 1 ® Port Pin is Output
PDCn = 0 ® Port Pin is Input
23
6
5
4
3
2
1
0
Port C GPIO Data Register
(PDRC)
PD5
PD4
PD3
PD2
PD1
PD0
* *
0 0
X:$FFFFBD
ReadWrite
Reset = $0
port pin n is GPIO input, then PDn reflects the
value on port pin n
if port pin n is GPIO output, then value written to
PDn is reflected on port pin n
= Reserved, Program as 0
*
Figure D-23 Port C Registers (PCRC, PRRC, PDRC)
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Programming Reference
Date:
Application:
Programmer:
Sheet 3 of 4
Port D (ESSI1)
GPIO
23
6
5
4
3
2
1
0
Port D Control Register
PC5
PC4
PC3
PC2
PC1
PC0
(PCRD)
X:$FFFFAF
ReadWrite
Reset = $0
* *
0 0
PCn = 1 ® Port Pin configured as ESSI
PCn = 0 ® Port Pin configured as GPIO
23
6
5
4
3
2
1
0
Port D Direction Register
(PRRD)
PDC5 PDC4 PDC3 PDC2 PDC1 PDC0
* *
0 0
X:$FFFFAE
ReadWrite
Reset = $0
PDCn = 1 ® Port Pin is Output
PDCn = 0 ® Port Pin is Input
23
6
5
4
3
2
1
0
Port D GPIO Data Register
(PDRD)
PD5
PD4
PD3
PD2
PD1
PD0
* *
0 0
X:$FFFFAD
ReadWrite
Reset = $0
port pin n is GPIO input, then PDn reflects the
value on port pin n
if port pin n is GPIO output, then value written to
PDn is reflected on port pin n
= Reserved, Program as 0
*
Figure D-24 Port D Registers (PCRD, PRRD, PDRD)
D-38
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Programming Reference
Date:
Application:
Programmer:
Sheet 4 of 4
Port E (SCI)
GPIO
23
6
5
4
3
2
1
0
Port E Control Register
PC2
PC1
PC0
(PCRE)
X:$FFFF9F
ReadWrite
Reset = $0
* * * * *
0 0 0 0 0
PCn = 1 ® Port Pin configured as SCI
PCn = 0 ® Port Pin configured as GPIO
23
6
5
4
3
2
1
0
Port E Direction Register
(PRRE)
PDC2 PDC1 PDC0
* * * * *
0 0 0 0 0
X:$FFFF9E
ReadWrite
Reset = $0
PDCn = 1 ® Port Pin is Output
PDCn = 0 ® Port Pin is Input
23
6
5
4
3
2
1
0
Port E GPIO Data Register
(PDRE)
PD2
PD1
PD0
* * * * *
0 0 0 0 0
X:$FFFF9D
ReadWrite
Reset = $0
port pin n is GPIO input, then PDn reflects the
value on port pin n
if port pin n is GPIO output, then value written to
PDn is reflected on port pin n
= Reserved, Program as 0
*
Figure D-25 Port E Registers (PCRE, PRRE, PDRE)
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Programming Reference
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INDEX
Breakpoint 1 Read/Write Select bits
(RW10ÐRW11) 10-13
BSDL listing
A
A0ÐA17 signals 2-9
AA0ÐAA3 signals 2-10
adder
PBGA C-8
TQFP C-2
BSR register 11-7
BT0ÐBT1 bits 10-14
bus
modulo 1-9
offset 1-9
reverse-carry 1-9
address 2-4
data 2-4
address attribute signals 2-10
address bus 2-3
external address 2-9
external data 2-9
multiplexed 2-4
signals 2-9
Address Generation Unit 1-9
addressing modes 1-10
AGU 1-9
ALC bit 7-13
Alignment Control bit (ALC) 7-13
applications 1-7
non-multiplexed 2-4
bus busy signal (BB) 2-13
bus clock not signal (BCLK) 2-13
bus clock signal (BCLK) 2-13
bus control 2-3
Asynchronous/Synchronous bit (SYN) 7-18
bus grant signal (BG) 2-12
bus parking 2-13
bus request signal (BR) 2-12
buses
internal 1-13
BYPASS instruction 11-11
B
BA3ÐBA10 bits 6-12
barrel shifter 1-8
Base Address bits (BA3ÐBA10) 6-12
BB signal 2-13
BCLK signal 2-13
BCLK signal 2-13
C
CAS signal 2-13
BG signal 2-12
CC00ÐCC01 bits 10-13
CC10ÐCC11 bits 10-14
CD0ÐCD11 bits 8-16
Central Processing Unit (CPU) 1-3
CKP bit 7-18
bootstrap 4-4
bootstrap from byte-wide external memory 4-7
bootstrap program options
invoking 4-5
bootstrap ROM 3-7
CLAMP instruction 11-10
CLKGEN 1-11
CLKOUT signal 2-8
bootstrap through HI08 (68302/68360) 4-9
bootstrap through HI08 (ISA) 4-8
bootstrap through HI08 (Multiplexed) 4-9
bootstrap through HI08 (non-multiplexed) 4-8
bootstrap through SCI 4-7
Boundary Scan Description Language
PBGA C-8
TQFP C-2
Boundary Scan Register (BSR) 11-7
BR signal 2-12
clock 1-7, 2-3
Clock Divider bits (CD0ÐCD11) 8-16
Clock Generator (CLKGEN) 1-11
Clock Out Divider bit (COD) 8-16
clock output signal (CLKOUT) 2-8
Clock Polarity bit (CKP) 7-18
clock signals 2-7
Clock Source Direction bit (SCKD) 7-16
CMOS 1-7
COD bit 8-16
break 8-9
Breakpoint 0 and 1 Event bits (BT0ÐBT1) 10-14
Breakpoint 0 Condition Code Select bits
(CC00ÐCC01) 10-13
Breakpoint 0 Read/Write Select bits
(RW00ÐRW01) 10-12
code
compatible 1-7
column address strobe signal (CAS) 2-13
CRA register 7-11
Breakpoint 1 Condition Code Select bits
(CC10ÐCC11) 10-14
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D
bits 0Ð7ÑPrescale Modulus Select bits
bit 22ÑESSI Transmit Exception Interrupt
(PM0ÐPM7) 7-11
Enable bit (TEIE) 7-27
bit 23ÑESSI Receive Exception Interrupt
Enable bit (REIE) 7-27
bits 8Ð10Ñreserved bits 7-11
bit 11ÑPrescaler Range bit (PSR) 7-11
bits 12Ð16ÑFrame Rate Divider Control bits
(DC4ÐDC0) 7-12
crystal input 2-8
CVR register
bit 17Ñreserved bit 7-13
bits 0Ð6ÑHost Vector bits (HV0ÐHV6) 6-25
bit 18ÑAlignment Control bit (ALC) 7-13
bits 19Ð21ÑWord Length Control bits
(WL0ÐWL1) 7-14
bit 22ÑSelect SC1 as Transmitter 0 Drive
Enable bit (SSC1) 7-14
bit 23Ñreserved bit 7-14
reserved bitsÑbit 17 7-13
reserved bitsÑbit 23 7-14
reserved bitsÑbits 8Ð10 7-11
D
D0ÐD23 2-10
data ALU 1-8
registers 1-8
data bus 2-3
signals 2-10
Data Output bit (DO) 9-14
DC4ÐDC0 bits 7-12
DE signal 2-37, 10-4
Debug Event signal (DE signal) 10-4
Debug mode
in OnCE module 10-16
DEBUG_REQUEST instruction 11-11
executing during Stop state 10-17
executing during Wait state 10-17
executing in OnCE module 10-17
Direct Memory Access (DMA) 1-15
Divide Factor (DF) 1-11
DMA 1-15
triggered by timer 9-27
DO bit 9-14
DO loop 1-10
Double Data Strobe 2-4
Double Host Request bit (HDRQ) 6-23
DRAM 1-13
CRB register
bits 0Ð1ÑSerial Output Flag bits
(OF0ÐOF1) 7-15
bit 2ÑSerial Control 0 Direction bit
(SCD0) 7-16
bit 3ÑSerial Control 1 Direction bit
(SCD1) 7-16
bit 4ÑSerial Control 2 Direction bit
(SCD2) 7-16
bit 5ÑClock Source Direction bit (SCKD) 7-16
bit 6ÑShift Direction bit (SHFD) 7-17
bits 7Ð8ÑFrame Sync Length bits
(FSL1ÐFSL0) 7-17
bit 9ÑFrame Sync Relative Timing bit
(FSR) 7-17
bit 10ÑFrame Sync Polarity bit (FSP) 7-17
bit 11ÑClock Polarity bit (CKP) 7-18
bit 12ÑAsynchronous/Synchronous bit
(SYN) 7-18
bit 13ÑESSI Mode Select bit (MOD) 7-20
bit 14ÑESSI Transmit 2 Enable bit (TE2) 7-22
bit 15ÑESSI Transmit 1 Enable bit (TE1) 7-23
bit 16ÑESSI Transmit 0 Enable bit (TE0) 7-24
bit 17ÑESSI Receive Enable bit (RE) 7-26
bit 18ÑESSI Transmit Interrupt Enable bit
(TIE) 7-26
DS 2-4
DSP56300 core 1-3, 1-6
DSP56300 Family Manual 1-3, 1-7
DSP56303 Functional Signal Groupings 2-3
signal groupings 2-3
DSP56303 Technical Data 1-3
E
bit 19ÑESSI Receive Interrupt Enable bit
(RIE) 7-26
bit 20ÑESSI Transmit Last Slot Interrupt
Enable bit (TLIE) 7-26
bit 21ÑESSI Receive Last Slot Interrupt Enable
bit (RLIE) 7-27
ENABLE_ONCE instruction 11-11
Enhanced Synchronous Serial Interface
(ESSI) 1-16, 2-3, 2-25, 2-28
Enhanced Synchronous Serial Interface 0 2-24
Enhanced Synchronous Serial Interface 1 2-28
equates
BIU B-13
I-2
DSP56309UM/D
MOTOROLA
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F
bus interface unit B-13
ESSI Transmit Data registers (TX2, TX1, TX0) 7-34
direct memory access B-10
DMA B-10
ESSI Transmit Exception Interrupt Enable bit
(TEIE) 7-27
enhanced serial communication interface B-5
ESSI B-5
exception processing B-7
HI08 B-3
host interface B-3
i/o port programming B-3
interrupt B-15
ESSI Transmit Interrupt Enable bit (TIE) 7-26
ESSI Transmit Last Slot Interrupt Enable bit
(TLIE) 7-26
ESSI Transmit Shift Registers 7-33
ESSI Transmit Slot Mask Registers (TSMA,
TSMB) 7-34
ESSI0 2-24
phase locked loop B-12
PLL B-12
ESSI0 (GPIO) 5-3
ESSI1 2-28
SCI B-4
ESSI1 (GPIO) 5-4
serial communication interface B-4
timer module B-9
ESSI 2-4
EX bit 10-5
exception processing equates B-7
Exit Command bit (EX) 10-5
expanded mode 4-6
after reset 7-36
asynchronous operating mode 7-40
frame sync length 7-41
EXTAL 2-7
EXTAL signal 2-7
frame sync polarity 7-42
external address bus 2-9
frame sync selection 7-41
frame sync word length 7-41
GPIO functionality 7-43
external bus control 2-9, 2-11, 2-12
external clock/crystal input 2-7
external data bus 2-9
initialization 7-36
interrupts 7-37
Network mode 7-40
Normal mode 7-40
operating mode 7-36
operating modes 7-40
external interrupt request A signal 2-14
external interrupt request B signal 2-15
external interrupt request C signal 2-15
external interrupt request D signal 2-16
external memory expansion port 2-9
EXTEST instruction 11-8
Port Control Register (PCR) 7-43
Port Data Register (PDR) 7-45
Port Direction Register (PRR) 7-44
programming model 7-8
F
FE bit 8-15
Frame Rate Divider Control bits (DC4ÐDC0) 7-12
Frame Sync Length bits (FSL1ÐFSL0) 7-17
Frame Sync Polarity bit (FSP) 7-17
Frame Sync Relative Timing bit (FSR) 7-17
frame sync selection
synchronous operating mode 7-40
ESSI Control Register A (CRA) 7-11
ESSI Mode Select bit (MOD) 7-20
ESSI Receive Data Register (RX) 7-33
ESSI Receive Enable bit (RE) 7-26
ESSI Receive Exception Interrupt Enable bit
(REIE) 7-27
ESSI Receive Interrupt Enable bit (RIE) 7-26
ESSI Receive Last Slot Interrupt Enable bit
(RLIE) 7-27
ESSI 7-41
Framing Error Flag bit (FE) 8-15
frequency
operation 1-7
FSL1ÐFSL0 bits 7-17
FSP bit 7-17
FSR bit 7-17
functional groups 2-4
ESSI Receive Shift Register 7-33
ESSI Receive Slot Mask Registers (RSMA,
RSMB) 7-35
ESSI Status Register (SSISR) 7-27
ESSI Time Slot Register (TSR) 7-34
ESSI Transmit 0 Enable bit (TE0) 7-24
ESSI Transmit 1 Enable bit (TE1) 7-23
ESSI Transmit 2 Enable bit (TE2) 7-22
G
general purpose input/output (GPIO) 2-34
Global Data Bus 1-13
MOTOROLA
DSP56309UM/D
I-3
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H
GO Command bit (GO) 10-6
GPIO 1-15, 2-4, 2-34
on HI08 6-30
bit 2ÑHost Command Interrupt Enable bit
(HCIE) 6-10
bits 3, 4ÑHost Flag 2 and 3 bits (HF2,
HF3) 6-10
Timers 2-4
GPIO (ESSI0, Port C) 5-3
GPIO (ESSI1, Port D) 5-4
GPIO (HI08, Port B) 5-3
GPIO (SCI, Port E) 5-4
GPIO (Timer) 5-4
GPIO functionality
on ESSI 7-43
reserved bitsÑbits 5Ð15 6-10
HCS signal 2-21
HCSEN bit 6-13
HCSP bit 6-16
HDDR register 6-17
HDDS bit 6-15
HDR register 6-17
ground 2-3, 2-6
address bus 2-6
bus control 2-7
data bus 2-7
HDRQ bit 6-23
HDS signal 2-20
HDSP bit 6-14
HEN bit 6-14
ESSI 2-7
HF0 bit 6-24
host interface 2-7
PLL 2-6
HF0, HF1 bits 6-11
HF1 bit 6-24
quiet 2-6
HF2 bit 6-27
SCI 2-7
HF2, HF3 bits 6-10
timer 2-7
HF3 bit 6-27
HGEN bit 6-13
H
HI08 1-16, 2-3, 2-4, 2-16, 2-18, 2-19, 2-21, 6-3
(GPIO) 5-3
H0ÐH7 signals 2-18
HA0 signal 2-18
HA1 signal 2-19
HA2 signal 2-19
HA8 signal 2-19
HA10 signal 2-21
HA9 signal 2-19
HA8EN bit 6-13
HA9EN bit 6-13
HAD0ÐHAD7 signals 2-18
HAEN bit 6-14
HAP bit 6-16
hardware stack 1-10
HAS/HAS 2-18
HASP bit 6-15
HBAR register 6-12
bits 0Ð7ÑBase Address bits (BA3ÐBA10) 6-12
reserved bitsÑbits 5Ð15 6-12
HCIE bit 6-10
data transfer 6-31
DSP side control registers 6-8
DSP side data registers 6-8
DSP side registers after reset 6-18
DSP to host
data word 6-5
handshaking protocols 6-5
interrupts 6-5
mapping 6-4
transfer modes 6-5
external host programmerÕs model 6-20
GPIO 6-30
HI08 to DSP core interface 6-3
HI08 to host processor interface 6-4
Host Base Address Register (HBAR) 6-12
Host Control Register (HCR) 6-9, 6-10
Host Data Direction Register (HDDR) 6-17
Host Data Register (HDR) 6-17
Host Port Control Register (HPCR) 6-12
Host Receive Data Register (HRX) 6-8
host side
HCP bit 6-11
HCR register 6-9, 6-10
bit 0ÑHost Receive Interrupt Enable bit
(HRIE) 6-10
Interface Control Register (ICR) 6-22
Interface Status Register (ISR) 6-26
Interface Vector Register (IVR) 6-28
bit 1ÑHost Transmit Interrupt Enable bit
(HTIE) 6-10
I-4
DSP56309UM/D
MOTOROLA
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H
Receive Byte Registers (RXH, RXM,
Host Flag 2 bit (HF2) 6-27
RXL) 6-28
Host Flag 3 bit (HF3) 6-27
Transmit Byte Registers (TXH, TXM,
TXL) 6-29
host side registers after reset 6-30
Host Status Register (HSR) 6-11
host to DSP
Host GPIO Port Enable bit (HGEN) 6-13
Host Interface 1-16, 2-3, 2-4, 2-16, 2-18, 2-19, 2-21,
6-3
Host Little Endian bit (HLEND) 6-24
Host Multiplexed Bus bit (HMUX) 6-15
host port
data word 6-3
handshaking protocols 6-4
configuration 2-17
instructions 6-4
usage considerations 2-16
mapping 6-3
transfer modes 6-3
Host Transmit Data Register (HTX) 6-9
polling 6-31
registers 6-7
Host Port Control Register (HPCR) 6-12
host read data signal (HRD/HRD) signal 2-20
host read/write signal (HRW) 2-20
Host Receive Data Full bit (HRDF) 6-11
Host Receive Data Register (HRX) 6-8
Host Receive Interrupt Enable bit (HRIE) 6-10
Host Request
servicing interrupts 6-32
HI-Z instruction 11-10
HLEND bit 6-24
Double 2-4
HMUX bit 6-15
Single 2-4
Host Acknowledge Enable bit (HAEN) 6-14
Host Acknowledge Polarity bit (HAP) 6-16
host acknowledge signal (HACK/HACK 2-23
host address 10 signal (HA10) 2-21
host address 8 signal (HA8) 2-19
host address 9 signal (HA9) 2-19
host address input 0 signal (HA0) 2-18
host address input 1 signal (HA1) 2-19
host address input 2 signal (HA2) 2-19
Host Address Line 8 Enable bit (HA8EN) 6-13
Host Address Line 9 Enable bit (HA9EN) 6-13
host address signal HAD0ÐHAD7) 2-18
Host Address Strobe Polarity bit (HASP) 6-15
host address strobe signal (HAS/HAS) signal 2-18
Host Base Address Register (HBAR) 6-12
Host Chip Select Enable bit (HCSEN) 6-13
Host Chip Select Polarity bit (HCSP) 6-16
host chip select signal (HCS) 2-21
Host Command Interrupt Enable bit (HCIE) 6-10
Host Command Pending bit (HCP) 6-11
Host Control Register (HCR) 6-9, 6-10
Host Data Direction Register (HDDR) 6-17
Host Data Register (HDR) 6-17
host data signal (H0ÐH7) 2-18
Host Data Strobe Polarity bit (HDSP) 6-14
host data strobe signal (HDS/HDS) 2-20
Host Dual Data Strobe bit (HDDS) 6-15
Host Enable bit (HEN) 6-14
Host Request Enable bit (HREN) 6-14
Host Request Open Drain bit (HROD) 6-14
Host Request Polarity bit (HRP) 6-16
host request signal (HREQ/HREQ 2-22
Host Status Register (HSR) 6-11
Host Transmit Data Empty bit (HTDE) 6-11
Host Transmit Data Register (HTX) 6-9
Host Transmit Interrupt Enable bit (HTIE) 6-10
Host Vector bits (HV0ÐHV6) 6-25
host write data signal (HWR/HWR) 2-20
HPCR register 6-12
bit 0ÑHost GPIO Port Enable bit (HGEN) 6-13
bit 1ÑHost Address Line 8 bit (HA8EN) 6-13
bit 2ÑHost Address Line 9 bit (HA9EN) 6-13
bit 3ÑHost Chip Select Enable bit
(HCSEN) 6-13
bit 4ÑHost Request Enable bit (HREN) 6-14
bit 5ÑHost Acknowledge Enable bit
(HAEN) 6-14
bit 6ÑHost Enable bit (HEN) 6-14
bit 7Ñreserved bit 6-14
bit 8ÑHost Request Open Drain bit
(HROD) 6-14
bit 9ÑHost Data Strobe Polarity bit
(HDSP) 6-14
bit 10ÑHost Address Strobe Polarity bit
(HASP) 6-15
bit 11ÑHost Multiplexed Bus bit (HMUX) 6-15
bit 12ÑHost Dual Data Strobe bit (HDDS) 6-15
bit 13ÑHost Chip Select Polarity bit
(HCSP) 6-16
Host Flag 0 and 1 bits (HF0, HF1) 6-11
Host Flag 0 bit (HF0) 6-24
Host Flag 1 bit (HF1) 6-24
Host Flag 2 and 3 bits (HF2, HF3) 6-10
bit 14ÑHost Request Polarity bit (HRP) 6-16
MOTOROLA
DSP56309UM/D
I-5
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I
bit 15ÑHost Acknowledge Polarity bit
location 3-8
(HAP) 6-16
instruction set 1-7
reserved bitÑbit 7 6-14
HR 2-4
HRD/HRD 2-20
HRDF bit 6-11
Interface Control Register (ICR) 6-22
Interface Status Register (ISR) 6-26
Interface Vector Register (IVR) 6-28
internal buses 1-13
HREN bit 6-14
interrupt 1-10
HRIE bit 6-10
ESSI 7-37
HROD bit 6-14
priority levels 4-12
HRP bit 6-16
HRRQ/HRRQ 2-23
HRW 2-20
HRX register 6-8
HSR register 6-11
servicing on HI08 6-32
sources 4-9
interrupt and mode control 2-3, 2-14, 2-15
interrupt control 2-14, 2-15
interrupt equates B-15
Interrupt Mode Enable bit (IME) 10-8
Interrupt Priority Register P (IPRÑP) 4-13
interrupts
bit 0ÑHost Receive Data Full bit (HRDF) 6-11
bit 1ÑHost Transmit Data Empty bit
(HTDE) 6-11
bit 2ÑHost Command Pending bit (HCP) 6-11
bits 3, 4ÑHost Flag 0 and 1 bits (HF0,
HF1) 6-11
DMA equates B-15
ending address B-16
ESSI equates B-16
reserved bitsÑbits 5Ð15 6-11
HTDE bit 6-11
host equates B-16
non-maskable B-15
HTIE bit 6-10
request pins B-15
HTRQ/HTRQ 2-22
HTX register 6-9
SCI equates B-16
timer equates B-15
HV0ÐHV6 bits 6-25
HWR/HWR signal 2-20
INV bit 9-11
Inverter bit (INV) 9-11
IPRÑP 4-13
I
ISR register 6-26
bit 0ÑReceive Data Register Full bit
(RXDF) 6-26
bit 1ÑTransmit Data Register Empty bit
(TXDE) 6-27
ICR register 6-22
bit 0ÑReceive Request Enable bit (RREQ) 6-23
bit 1ÑTransmit Request Enable bit
(TREQ) 6-23
bit 2ÑTransmitter Ready bit (TRDY) 6-27
bit 3ÑHost Flag 2 bit (HF2) 6-27
bit 4ÑHost Flag 3 bit (HF3) 6-27
bit 5Ñreserved bit 6-27
bit 6Ñreserved bit 6-27
reserved bitsÑbits 5,6 6-27
IVR register 6-28
bit 2ÑDouble Host Request bit (HDRQ) 6-23
bit 3ÑHost Flag 0 bit (HF0) 6-24
bit 4ÑHost Flag 1 bit (HF1) 6-24
bit 5ÑHost Little Endian bit (HLEND) 6-24
bit 6Ñreserved bit 6-24
reserved bitÑbit 6 6-24
IDCODE instruction 11-9
IDLE bit 8-14
J
Idle Line Flag bit (IDLE) 8-14
Idle Line Interrupt Enable bit (ILIE) 8-11
IF0 bit 7-28
Joint Test Action Group (JTAG) 11-3
JTAG 1-11, 2-35
JTAG instructions
IF1 bit 7-28
ILIE bit 8-11
IME bit 10-8
instruction cache 3-3
BYPASS instruction 11-11
CLAMP instruction 11-10
DEBUG_REQUEST instruction 11-11
I-6
DSP56309UM/D
MOTOROLA
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K
ENABLE_ONCE instruction 11-11
EXTEST instruction 11-8
HI-Z instruction 11-10
mode select A signal 2-14
mode select B signal 2-15
mode select C signal 2-15
mode select D signal 2-16
modulo adder 1-9
multiplexed bus 2-4
Multiplication Factor bits (MF) 4-18
multiplier-accumulator (MAC) 1-8, 1-9
IDCODE instruction 11-9
SAMPLE/PRELOAD instruction 11-9
JTAG/OnCE Interface signals
Debug Event signal (DE signal) 10-4
K
N
keeper, weak 2-24, 2-25, 2-26, 2-27, 2-28, 2-29,
2-30, 2-31, 2-32, 2-33, 2-34, 2-35
non-maskable interrupt 2-8, 2-9
non-multiplexed bus 2-4
L
O
LA register 1-10
LC register 1-10
OBCR register 10-12
logic 1-7
Loop Address register (LA) 1-10
Loop Counter register (LC) 1-10
bits 0Ð1ÑMemory Breakpoint Select bits
(MBS0ÐMBS1) 10-12
bits 2Ð3ÑBreakpoint 0 Read/Write Select bits
(RW00ÐRW01) 10-12
bits 4Ð5ÑBreakpoint 0 Condition Code Select
bits (CC00ÐCC01) 10-13
bits 6Ð7ÑBreakpoint 1 Read/Write Select bits
(RW10ÐRW11) 10-13
bits 8Ð9ÑBreakpoint 1 Condition Code Select
bits (CC10ÐCC11) 10-14
bits 10Ð11ÑBreakpoint 0 and 1 Event Select
bits (BT0ÐBT1) 10-14
M
MAC 1-9
Manual Conventions 1-5
MBO bit 10-8
MBS0ÐMBS1 bits 10-12
memory
bootstrap ROM 3-7
enabling breakpoints 10-18
external expansion port 1-13
maps 3-9
on-chip 1-12
program RAM 3-6
X data RAM 3-6
reserved bitsÑbits 12Ð15 10-15
OCR register
bits 0Ð4ÑRegister Select bits (RS0ÐRS4) 10-5
bit 5ÑExit Command bit (EX) 10-5
bit 6ÑGO Command bit (GO) 10-6
bit 7ÑRead/Write Command bit (R/W) 10-6
Y data RAM 3-7
ODEC 10-8
Memory Breakpoint Occurrence bit (MBO) 10-8
Memory Breakpoint Select bits
(MBS0ÐMBS1) 10-12
memory configuration 3-7
memory spaces 3-7
RAM 3-8
MF bits 4-18
MIPS 1-7
MOD bit 7-20
MODA/IRQA 2-14
MODB/IRQB 2-15
MODC/IRQC 2-15
MODD/IRQD 2-16
mode control 2-14, 2-15
Mode Select bit (MOD) 7-20
OF0ÐOF1 bits 7-15
offset adder 1-9
OGDBR register 10-20
OMAC0 comparator 10-11
OMAC1 comparator 10-11
OMAL register 10-11
OMBC counter 10-14
OMLR0 register 10-11
OMLR1 register 10-11
OMR register 1-11
OnCE 1-4
commands 10-23
controller 10-4
trace logic 10-15
OnCE Breakpoint Control Register (OBCR) 10-12
MOTOROLA
DSP56309UM/D
I-7
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P
OnCE Command Register (OCR) 10-5
OnCE Decoder (ODEC) 10-8
OnCE GDB Register (OGDBR) 10-20
OnCE Memory Address Comparator 0
(OMAC0) 10-11
OnCE Memory Address Comparator 1
(OMAC1) 10-11
OnCE Memory Address Latch register
(OMAL) 10-11
operating mode 4-3
bootstrap from byte-wide external memory 4-7
bootstrap thorugh HI08 (68302/68360) 4-9
bootstrap through HI08 (ISA) 4-8
bootstrap through HI08 (multiplexed) 4-9
bootstrap through HI08 (non-multiplexed) 4-8
bootstrap through SCI 4-7
ESSI 7-36, 7-40
expanded 4-6
OnCE Memory Breakpoint Counter (OMBC) 10-14
OnCE Memory Limit Register 0 (OMLR0) 10-11
OnCE Memory Limit Register 1 (OMLR1) 10-11
OnCE module 1-12, 10-3
expanded mode 4-6
Operating Mode Register (OMR) 1-11
operating modes 4-3
OPILR register 10-19
OR bit 8-14
checking for Debug mode 10-24
displaying a specified register 10-26
displaying X data memory 10-26
interaction with JTAG port 10-29
polling the JTAG Instruction Shift
register 10-24
OSCR register 10-8
bit 0ÑTrace Mode Enable bit (TME) 10-8
bit 1ÑInterrupt Mode Enable bit (IME) 10-8
bit 2ÑSoftware Debug Occurrence bit
(SWO) 10-8
reading the Trace buffer 10-25
returning to Normal mode 10-28
saving pipeline information 10-25
OnCE PAB Register for Decode Register
(OPABDR) 10-20
OnCE PAB Register for Execute (OPABEX) 10-20
OnCE PAB Register for Fetch Register
(OPABFR) 10-20
OnCE PIL Register (OPILR) 10-19
OnCE Program Data Bus Register (OPDBR) 10-19
OnCE Status and Control Register (OSCR) 10-8
OnCE Trace Counter (OTC) 10-16
OnCE/JTAG 2-4
debug event signal (DE) 2-37
test clock signal (TCK) 2-35
test data input signal (TDI) 2-35
test data output signal (TDO) 2-36
test mode select signal (TMS) 2-36
OnCE/JTAG port 2-3
On-Chip Emulation (OnCE) module 1-12
On-Chip Emulation module 10-3
on-chip memory 1-12
bit 3ÑMemory Breakpoint Occurrence bit
(MBO) 10-8
bit 4ÑTrace Occurrence bit (TO) 10-9
bit 5Ñreserved bit 10-9
reserved bitsÑbits 8Ð23 10-9
OTC counter 10-16
Overrun Error Flag bit (OR) 8-14
P
PAB 1-13
PAG 1-10
Parity Error bit (PE) 8-14
PB0ÐPB7 signals 2-18
PB10 signal 2-19
PB11 signal 2-20
PB12 signal 2-20
PB13 signal 2-21
PB14 signal 2-22
PB15 signal 2-23
PB8 signal 2-18
PB9 signal 2-19
PC register 1-10
PC0 signal 2-24
PC0-PC20 bits 9-9
PC1 signal 2-25
PC2 signal 2-25
PC3 signal 2-26
PC4 signal 2-26
PC5 signal 2-27
program 3-6
X data RAM 3-6
Y data RAM 3-7
OPABDR register 10-20
OPABEX register 10-20
OPABFR register 10-20
OPDBR register 10-19
Operating 4-3
I-8
DSP56309UM/D
MOTOROLA
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P
PCAP signal 2-8
PCRC register 7-43
PCRD register 7-43
PCRE register 8-27
PCTL register
port C 1 signal (PC1) 2-25
port C 2 signal (PC2) 2-25
port C 3 signal (PC3) 2-26
port C 4 signal (PC4) 2-26
port C 5 signal (PC5) 2-27
bits 0Ð11ÑMultiplication Factor bits
(MF0ÐMF11) 4-18
bit 16ÑXTAL Disable bit (XTLD) 4-18
bits 20Ð23ÑPreDivider Factor bits
(PD0ÐPD3) 4-18
Port C Control Register (PCRC) 7-43
Port C Data Register (PDRC) 7-45
Port C Direction Register (PRRC) 7-44
Port D 2-3, 2-4, 2-28, 5-4
port D 0 signal (PD0) 2-28
port D 1 signal (PD1) 2-28
port D 2 signal (PD2) 2-29
port D 3 signal (PD3) 2-30
port D 4 signal (PD4) 2-30
port D 5 signal (PD5) 2-31
Port D Control Register (PCRD) 7-43
Port D Data Register (PDRD) 7-45
Port D Direction Register (PRRD) 7-44
Port E 2-3, 2-32, 5-4
PCU 1-10
PD bits 4-18
PD0 signal 2-28
PD1 signal 2-28
PD2 signal 2-29
PD3 signal 2-30
PD4 signal 2-30
PD5 signal 2-31
PDB 1-13
PDC 1-10
PDRC register 7-45
PDRD register 7-45
PDRE register 8-28
PE bit 8-14
PE0 signal 2-32
PE1 signal 2-32
PE2 signal 2-33
port E 0 signal (PE0) 2-32
port E 1 signal (PE1) 2-32
port E 2 signal (PE2) 2-33
Port E Control Register (PCRE) 8-27
Port E Data Register (PDRE) 8-28
Port E Direction Register (PRRE) 8-27
power 2-3, 2-5
ground 2-6
Peripheral I/O Expansion Bus 1-13
PIC 1-10
low 1-7
management 1-7
PINIT/NMI 2-9
standby modes 1-7
PLL initial 2-8
power input
PL0-PL20 bits 9-7
address bus 2-5
PL21-PL22 bits 9-7
PLL 1-11, 2-3
PLL capacitor signal 2-8
PLL initialize signal 2-9
PLL signals 2-7
bus control 2-5
data bus 2-5
ESSI 2-6
host interface 2-5
PLL 2-5
PM0ÐPM7 bits 7-11
Port A 2-3, 2-9
quiet 2-5
SCI 2-6
timer 2-6
Port B 2-3, 2-4, 2-19, 5-3
port B 10 signal (PB10) 2-19
port B 11 signal (PB11) 2-20
port B 12 signal (PB12) 2-20
port B 13 signal (PB13) 2-21
port B 14 signal (PB14) 2-22
port B 15 signal (PB15) 2-23
port B 8 signal (PB8) 2-18
port B 9 signal (PB9) 2-19
port B signal (PB0ÐPB7) 2-18
Port C 2-3, 2-4, 2-24, 2-25, 2-28, 5-3
port C 0 signal (PC0) 2-24
PreDivider Factor bits (PD) 4-18
Prescale Modulus Select bits (PM0ÐPM7) 7-11
Prescaler Counter 9-7
Prescaler Counter Value bits (PC0-PC20) 9-9
Prescaler Load Value bits (PL0-PL20) 9-7
Prescaler Range bit (PSR) 7-11
Prescaler Source bits (PL21-PL22) 9-7
Program Address Bus (PAB) 1-13
Program Address Generator (PAG) 1-10
Program Control Unit (PCU) 1-10
Program Counter register (PC) 1-10
MOTOROLA
DSP56309UM/D
I-9
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R
Program Data Bus (PDB) 1-13
bits 5Ð15 6-10
Program Decode Controller (PDC) 1-10
Program Interrupt Controller (PIC) 1-10
Program Memory Expansion Bus 1-13
program RAM 3-6
Programming Sheets Ñ See Appendix B
PRRC register 7-44
in HPC register
bit 7 6-14
in HSR register
bits 5Ð15 6-11
in ICR register
bit 6 6-24
PRRD register 7-44
PRRE register 8-27
in ISR register
bit 5 6-27
PSR bit 7-11
bit 6 6-27
in OBCR register
bits 12Ð15 10-15
in OSCR register
bit 5, bits 8Ð23 10-9
in TCSR register
bits 3, 10, 14, 16Ð19, 22, 23 9-15
in TPCR 9-9
R
R/W bit 10-6
R8 bit 8-15
RAS0ÐRAS3 signals 2-10
RCM bit 8-17
RD signal 2-10
RDF bit 7-30
RDRF bit 8-14
RE bit 7-26, 8-10
read enable signal (RD) 2-10
Read/Write Command bit (R/W) 10-6
Receive Byte Registers (RXH, RXM, RXL) 6-28
Receive Clock Mode Source bit (RCM) 8-17
Receive Data Register (RX) 7-33
Receive Data Register Full bit (RDF) 7-30
Receive Data Register Full bit (RDRF) 8-14
Receive Data Register Full bit (RXDF) 6-26
Receive Data signal (RXD) 8-4
Receive Exception Interrupt Enable bit (REIE) 7-27
Receive Frame Sync Flag bit (RFS) 7-28
receive host request signal (HRRQ/HRRQ) 2-23
Receive Interrupt Enable bit (RIE) 7-26, 8-11
Receive Last Slot Interrupt Enable bit (RLIE) 7-27
Receive Request Enable bit (RREQ) 6-23
Receive Shift Register 7-33
in TPLR 9-8
RESET 2-14
reset signal 2-14
reverse-carry adder 1-9
RFS bit 7-28
RIE bit 7-26, 8-11
RLIE bit 7-27
ROE bit 7-29
ROM
bootstrap 3-7
row address strobe signals RAS0ÐRAS3 2-10
RREQ bit 6-23
RS0ÐRS4 bits 10-5
RSMA, RSMB registers 7-35
RW00ÐRW01 bits 10-12
RW10ÐRW11 bits 10-13
RWU bit 8-9
RX register 7-33
RXD 2-32
RXD signal 8-4
Receive Slot Mask Registers (RSMA, RSMB) 7-35
Received Bit 8 Address bit (R8) 8-15
Receiver Enable bit (RE) 8-10
Receiver Overrun Error Flag bit (ROE) 7-29
Receiver Wakeup Enable bit (SBK) 8-9
Register Select bits (RS0ÐRS4) 10-5
REIE bit 7-27, 8-13
RXDF bit 6-26
RXH, RXM, RXL registers 6-28
S
SAMPLE/PRELOAD instruction 11-9
SBK bit 8-9
SC register 1-11
reserved bits
in CRA register 7-11, 7-13, 7-14
in HBAR register
SC0 signal 7-6, 7-8
SC00 signal 2-24
bits 5Ð15 6-12
SC01 signal 2-25
in HCR register
SC02 signal 2-25
I-10
DSP56309UM/D
MOTOROLA
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Freescale Semiconductor, Inc.
S
SC1 signal 7-7
SC10 2-28
SCK signal 7-5
SCK0 2-26
SC11 2-28
SC12 2-29
SCCR register 8-15
SCK1 signal 2-30
SCKD bit 7-16
SCKP bit 8-12
bits 0Ð11ÑClock Divider bits
SCLK signal 2-33, 8-4
SCP bit 8-17
(CD0ÐCD11) 8-16
bit 12ÑClock Out Divider bit (COD) 8-16
bit 13ÑSCI Clock Prescaler bit (SCP) 8-17
bit 14ÑReceive Clock Mode Source bit
(RCM) 8-17
SCR register
bits 0-2ÑWord Select bits (WDS0-WDS2) 8-8
bit 3ÑSCI Shift Direction bit (SSFTD) 8-9
bit 4ÑSend Break bit (SBK) 8-9
bit 5ÑWakeup Mode Select bit (WAKE) 8-9
bit 15ÑTransmit Clock Source bit (TCM) 8-18
SCD0 bit 7-16
SCD1 bit 7-16
SCD2 bit 7-16
bit 6ÑReceiver Wakeup Enable bit (RWU) 8-9
bit 7ÑWired-OR Mode Select bit
(WOMS) 8-10
SCI 1-16, 2-4, 2-32
exceptions 8-26
Idle Line 8-26
bit 8ÑReceiver Enable bit (RE) 8-10
bit 9ÑTransmitter Enable bit (TE) 8-10
bit 10ÑIdle Line Interrupt Enable bit
(ILIE) 8-11
Receive Data 8-26
Receive Data with Exception Status 8-26
Timer 8-26
Transmit Data 8-26
GPIO functionality 8-27
initialization 8-24
example 8-25
bit 11ÑReceive Interrupt Enable bit (RIE) 8-11
bit 12ÑTransmit Interrupt Enable bit
(TIE) 8-12
bit 13ÑTimer Interrupt Enable bit (TMIE) 8-12
bit 14ÑTimer Interrupt Rate bit (STIR) 8-12
bit 15ÑSCI Clock Polarity bit (SCKP) 8-12
bit 16ÑSCI Receive with Exception Interrupt
Enable bit (REIE) 8-13
operating mode
Asynchronous 8-21
Synchronous 8-21
operating modes
Select SC1 as Transmitter 0 Drive Enable bit
(SSC1) 7-14
Asynchronous 8-21
programming model 8-4
reset 8-22
Send Break bit (SBK) 8-9
Serial Clock signal (SCK) 7-5
serial clock signal (SCK0) 2-26
state after reset 8-23
transmission priority
preamble, break, and data 8-26
serial clock signal (SCK1) 2-30
serial clock signal (SCLK) 2-33
Serial Communication Interface (SCI) 2-32
Serial Communications Interface (SCI) 1-16, 2-3,
8-3
SCI (GPIO) 5-4
SCI Clock Control Register (SCCR) 8-15
SCI Clock Polarity bit (SCKP) 8-12
SCI Clock Prescaler bit (SCP) 8-17
SCI exceptions
Receive Data 8-26
SCI pins
Serial Control 0 Direction bit (SCD0) 7-16
serial control 0 signal (SC0) 7-6, 7-8
serial control 0 signal (SC00) 2-24
serial control 0 signal (SC10) 2-28
Serial Control 1 Direction bit (SCD1) 7-16
serial control 1 signal (SC01) 2-25
serial control 1 signal (SC1) 7-7
serial control 1 signal (SC11) 2-28
Serial Control 2 Direction bit (SCD2) 7-16
serial control 2 signal (SC02) 2-25
serial control 2 signal (SC12) 2-29
Serial Input Flag 0 bit (IF0) 7-28
Serial Input Flag 1 bit (IF1) 7-28
Serial Output Flag bits (OF0ÐOF1) 7-15
RXD, TXD, SCLK 8-3
SCI Receive Register (SRX) 8-19
SCI Receive with Exception Interrupt bit
(REIE) 8-13
SCI Serial Clock signal (SCLK) 8-4
SCI Shift Direction bit (SSFTD) 8-9
SCI Status Register (SSR) 8-13
SCI Transmit Register (STX)
STX register 8-20
MOTOROLA
DSP56309UM/D
I-11
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Freescale Semiconductor, Inc.
T
serial protocol
bit 2ÑTransmit Data Register Empty bit
in OnCE module 10-22
(TDRE) 8-13
bit 3ÑIdle Line Flag bit (IDLE) 8-14
bit 4ÑOverrun Error Flag bit (OR) 8-14
bit 5ÑParity Error bit (PE) 8-14
bit 6ÑFraming Error Flag bit (FE) 8-15
bit 7ÑReceived Bit 8 Address bit (R8) 8-15
Stack Counter register (SC) 1-11
Stack Pointer (SP) 1-11
standby
serial receive data signal (RXD) 2-32
Serial Receive Data signal (SRD) 7-4
serial receive data signal (SRD0) 2-26
serial receive data signal (SRD1) 2-30
Serial Transmit Data signal (STD) 7-4
serial transmit data signal (STD0) 2-27
serial transmit data signal (STD1) 2-31
serial transmit data signal (TXD) 2-32
SHFD bit 7-17
mode
Shift Direction bit (SHFD) 7-17
signal groupings 2-3
Stop 1-7
Wait 1-7
signals 2-3
functional grouping 2-4
Single Data Strobe 2-4
Status Register (SR) 1-10
STD signal 7-4
STD0 2-27
Sixteen-bit Compatibility 3-3
Size register (SZ) 1-10
STD1 2-31
STIR bit 8-12
Software Debug Occurrence bit (SWO) 10-8
SP 1-11
stop
standby mode 1-7
SR register 1-10
STX register
SRAM
read as STXL, STXM. STXH, and STXA 8-20
SWO bit 10-8
interfacing 1-13
SRD signal 7-4
SYN bit 7-18
SRD0 2-26
SRD1 2-30
System Stack (SS) 1-11
SZ register 1-10
SRX
T
read as SRXL, SRXM, SRXH 8-19
SRX register 8-19
TA signal 2-11
TAP 1-11
TAP controller 11-6
TC0ÐTC3 bits 9-10
TCIE 9-10
TCK pin 11-5
TCK signal 2-35
TCM bit 8-18
TCR register 9-16
SS 1-11
SSC1 bit 7-14
SSFTD bit 8-9
SSISR register 7-27
bit 0ÑSerial Input Flag 0 bit (IF0) 7-28
bit 1ÑSerial Input Flag 1 bit (IF1) 7-28
bit 2ÑTransmit Frame Sync Flag bit (TFS) 7-28
bit 3ÑReceive Frame Sync Flag bit (RFS) 7-28
bit 4ÑTransmitter Underrun Error Flag bit
(TUE) 7-29
TCSR register 9-9
bit 0ÑTimer Enable bit (TE) 9-9
bits 4Ð7ÑTimer Control bits (TC0ÐTC3) 9-10
bit 8ÑInverter bit (INV) 9-11
bit 13ÑData Output bit (DO) 9-14
reserved bitsÑbits 3, 10, 14, 16Ð19, 22, 23 9-15
TDE bit 7-29
TDI pin 11-5
TDI signal 2-35
TDO signal 2-36
TDRE bit 8-13
bit 5ÑReceiver Overrun Error Flag bit
(ROE) 7-29
bit 6ÑTransmit Data Register Empty bit
(TDE) 7-29
bit 7ÑReceive Data Register Full bit
(RDF) 7-30
SSR register 8-13
bit 1ÑTransmitter Empty bit (TRNE) 8-13
bit 2ÑReceive Data Register Full bit
(RDRF) 8-14
I-12
DSP56309UM/D
MOTOROLA
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Freescale Semiconductor, Inc.
T
TE bit 8-10, 9-9
TE0 bit 7-24
TOIE 9-9
TPCR register 9-8
TE1 bit 7-23
bits 0-20ÑPrescaler Counter Value bits
TE2 bit 7-22
(PC0-PC20) 9-9
TEIE bit 7-27
bit 21-23Ñreserved bits 9-9
Test Access Port (TAP) 1-11, 11-3
Test Clock Input pin (TCK) 11-5
Test Data Input pin (TDI) 11-5
Test Mode Select Input pin (TMS) 11-5
Test Reset Input pin (TRST) 11-5
TFS bit 7-28
reserved bitsÑbits 21-23 9-9
TPLR register 9-7
bits 0-20ÑPrescaler Load Value bits
(PL0-PL20) 9-7
bits 21-22ÑPrescaler Source bits
(PL0-PL20) 9-7
TIE bit 7-26, 8-12
Time Slot Register (TSR) 7-34
timer
bit 23Ñreserved bit 9-8
reserved bitÑbit 23 9-8
Trace buffer 10-21
special cases 9-27
Trace mode
Timer (GPIO) 5-4
enabling 10-18
timer 0 signal (TIO0) 2-34
timer 1 signal (TIO1) 2-34
timer 2 signal (TIO2) 2-35
Timer Control bits (TC0ÐTC3) 9-10
Timer Control/Status Register (TCSR) 9-9
Timer Count Register (TCR) 9-16
Timer Enable bit (TE) 9-9
Timer Interrupt Enable bit (TMIE) 8-12
Timer Interrupt Rate bit (STIR) 8-12
timer mode
in OnCE module 10-15
Trace Mode Enable bit (TME) 10-8
Trace Occurrence bit (TO) 10-9
transfer acknowledge signal 2-11
Transmit 0 Enable bit (TE0) 7-24
Transmit 1 Enable bit (TE1) 7-23
Transmit 2 Enable bit (TE2) 7-22
Transmit Byte Registers (TXH, TXM, TXL) 6-29
Transmit Clock Source bit (TCM) 8-18
Transmit Data Register Empty bit (TDE) 7-29
Transmit Data Register Empty bit (TDRE) 8-13
Transmit Data Register Empty bit (TXDE) 6-27
Transmit Data signal (TXD) 8-4
Transmit Exception Interrupt Enable bit
(TEIE) 7-27
mode 0ÑGPIO 9-17
mode 1Ñtimer pulse 9-18
mode 2Ñtimer toggle 9-19
mode 3Ñtimer event counter 9-20
mode 4Ñmeasurement input width 9-21
mode 5Ñmeasurement input period 9-22
mode 6Ñmeasurement capture 9-23
mode 7Ñpulse width modulation 9-24
mode 8Ñreserved 9-25
mode 9Ñwatchdog pulse 9-25
mode 10Ñmeasurement toggle 9-26
modes 11Ð15Ñreserved 9-27
Timer module 1-17, 2-34
architecture 9-3
Transmit Frame Sync Flag bit (TFS) 7-28
transmit host request signal (HTRQ/HTRQ) 2-22
Transmit Interrupt Enable bit (TIE) 7-26, 8-12
Transmit Last Slot Interrupt Enable bit (TLIE) 7-26
Transmit Request Enable bit (TREQ) 6-23
Transmit Shift Registers 7-33
Transmit Slot Mask Registers (TSMA, TSMB) 7-34
Transmitter Empty bit (TRNE) 8-13
Transmitter Enable bit (TE) 8-10
Transmitter Ready bit (TRDY) 6-27
Transmitter Underrun Error Flag bit (TUE) 7-29
TRDY bit 6-27
programming model 9-5
timer block diagram 9-4
Timer Prescaler Count Register (TPCR) 9-8
Timer Prescaler Load Register (TPLR) 9-7
Timers 2-3, 2-4
TREQ bit 6-23
triple timer module 1-17
TRNE bit 8-13
TLIE bit 7-26
TME bit 10-8
TRST pin 11-5
TMIE bit 8-12
TMS pin 11-5
TSMA, TSMB registers 7-34
TSR register 7-34
TMS signal 2-36
TUE bit 7-29
TO bit 10-9
TX2, TX1, TX0 registers 7-34
MOTOROLA
DSP56309UM/D
I-13
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Freescale Semiconductor, Inc.
V
TXD signal 2-32, 8-4
TXDE bit 6-27
TXH, TXM, TXL registers 6-29
V
VBA register 1-10
Vector Base Address register (VBA) 1-10
W
wait
standby mode 1-7
WAKE bit 8-9
Wakeup Mode Select bit (WAKE) 8-9
WDS0-WDS2 bits 8-8
weak keeper 2-24, 2-25, 2-26, 2-27, 2-28, 2-29, 2-30,
2-31, 2-32, 2-33, 2-34, 2-35
Wired-OR Select bit (WOMS) 8-10
WL0ÐWL1 bits 7-14
WOMS bit 8-10
Word Length Control bits (WL0ÐWL1) 7-14
Word Select bits (WDS0-WDS2) 8-8
WR signal 2-10
write enable signal 2-10
X
X data RAM 3-6
X Memory Address Bus (XAB) 1-13
X Memory Data Bus (XDB) 1-13
X Memory Expansion Bus 1-13
XAB 1-13
XDB 1-13
XTAL 2-8
XTAL Disable bit (XTLD) 4-18
XTLD bit 4-18
Y
Y data RAM 3-7
Y Memory Address Bus (YAB) 1-13
Y Memory Data Bus (YDB) 1-13
Y Memory Expansion Bus 1-13
YAB 1-13
YDB 1-13
I-14
DSP56309UM/D
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
1
2
DSP56309 OVERVIEW
SIGNAL/CONNECTION DESCRIPTIONS
MEMORY CONFIGURATION
CORE CONFIGURATION
GENERAL PURPOSE I/O
HOST INTERFACE (HI08)
ENHANCED SYNCHRONOUS SERIAL INTERFACE
SERIAL COMMUNICATION INTERFACE (SCI)
TIMER MODULE
3
4
5
6
7
8
9
10
11
A
B
C
D
I
ON-CHIP EMULATION MODULE
JTAG PORT
BOOTSTRAP PROGRAM
EQUATES
BSDL LISTING
PROGRAMMING REFERENCE
INDEX
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
DSP56309 OVERVIEW
SIGNAL/CONNECTION DESCRIPTIONS
MEMORY CONFIGURATION
CORE CONFIGURATION
1
2
3
4
GENERAL PURPOSE I/O
HOST INTERFACE (HI08)
ENHANCED SYNCHRONOUS SERIAL INTERFACE
SERIAL COMMUNICATION INTERFACE (SCI)
TIMER MODULE
5
6
7
8
9
ON-CHIP EMULATION MODULE
JTAG PORT
10
11
A
B
C
D
I
BOOTSTRAP PROGRAM
EQUATES
BSDL LISTING
PROGRAMMING REFERENCE
INDEX
For More Information On This Product,
Go to: www.freescale.com
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