MC100E1651FN [MOTOROLA]
DUAL ECL OUTPUT COMPARATOR WITH LATCH; 与LATCH双ECL输出比较器型号: | MC100E1651FN |
厂家: | MOTOROLA |
描述: | DUAL ECL OUTPUT COMPARATOR WITH LATCH |
文件: | 总7页 (文件大小:137K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The MC10E1651 is functionally and pin-for-pin compatible with the
MC1651 in the MECL III family, but is fabricated using Motorola’s
advanced MOSAIC III process. The MC10E1651 incorporates a fixed
level of input hysteresis as well as output compatibility with 10KH logic
devices. In addition, a latch is available allowing a sample and hold
function to be performed. The device is available in both a 16-pin DIP and
a 20-pin surface mount package.
DUAL ECL OUTPUT
COMPARATOR
WITH LATCH
The latch enable (LEN and LEN ) input pins operate from standard
a
b
ECL 10KH logic levels. When the latch enable is at a logic high level the
MC10E1651 acts as a comparator, hence Q will be at a logic high level if
V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When
the latch enable input goes to a low logic level, the outputs are latched in
their present state providing the latch enable setup and hold time
constraints are met.
• Typ. 3.0 dB Bandwidth > 1.0 GHz
• Typ. V to Q Propagation Delay of 775 ps
• Typ. Output Rise/Fall of 350 ps
• Common Mode Range –2.0 V to +3.0 V
• Individual Latch Enables
FN SUFFIX
PLASTIC PACKAGE
CASE 775-02
• Differential Outputs
• 28mV Input Hysteresis
L SUFFIX
CERAMIC PACKAGE
CASE 620-10
LOGIC DIAGRAM
V1a
FUNCTION TABLE
Qa
V2a
LEN
V1, V2
Function
H
H
L
V1 > V2
V1 < V2
X
H
L
LEN
Qa
a
Latched
V1b
V2b
Qb
Qb
LEN
b
V
V
= –5.2 V
= +5.0 V
EE
CC
12/93
Motorola, Inc. 1996
REV 1
MC10E1651
Pinout: 20-Lead PLCC (Top View)
Pinout: 16-Pin Ceramic DIP (Top View)
Qb LEN
b
NC V1b
V2b
14
18
17
16
15
GND Qb Qb LEN
V1b V2b
V
NC
9
b
CC
19
20
1
13
12
11
Qb
GND
NC
V
CC
16
15
14
13
12
11
10
NC
NC
V
GND
Qa
2
3
10
9
EE
1
2
3
4
5
6
7
8
V
CC
GND Qa Qa LEN V2a V1a
V
V
EE
a
CC
4
5
6
7
8
Qa LEN
a
NC
V2a V1a
ABSOLUTE MAXIMUM RATINGS (Beyond which device life may be impaired)
Symbol
VSUP
Characteristic
Min
Typ
Max
12.0
3.7
Unit
Total Supply Voltage
V
|V | + |V
|
EE CC
VPP
Differential Input Voltage
|V1 – V2|
V
DC CHARACTERISTICS (V
= –5.2 V ±5%; V
= +5.0 V ±5%)
EE
CC
0°C
Typ
25°C
85°C
Symbol
Characteristic
Output HIGH Voltage
Output Low Voltage
Input Current (V1, V2)
Min
Max
Min
Typ
Max
Min
Typ
Max
Unit Condition
V
V
II
–1020
–1950
–840
–980
–810
–920
–735
mV
mV
µA
OH
–1630 –1950
–1630 –1950
–1600
OL
65
65
65
I
IH
Input HIGH Current (LEN)
150
150
150
I
I
Positive Supply Current
Negative Supply Current
50
–55
50
–55
50
–55
mA
CC
EE
VCMR
Hys
Common Mode Range
Hysteresis
–2.0
3.0
–2.0
3.0
–2.0
3.0
V
27
27
30
0
mV
V
skew
Hysteresis Skew
–1.0
–1.0
mV
pF
1
C
Input Capacitance
DIP
PLCC
in
3
2
3
2
3
2
1. Hysteresis skew (V
) is provided to indicate the offset of the hysteresis window. For example, at 25°C the nominal hysteresis value is 27mV
skew
value indicates that the hysteresis was skewed from the reference level by 1mV in the negative direction. Hence the hysteresis
and the V
skew
window ranged from 14mV below the reference level to 13mV above the reference level. All hysteresis measurements were determined using
a reference voltage of 0mV.
MOTOROLA
2–2
MC10E1651
AC CHARACTERISTICS (V
EE
= –5.2 V ±5%; V
CC
= +5.0 V ±5%)
0°C
25°C
85°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit Condition
t
t
Propagation Delay to Output
V to Q
LEN to Q
ps
1
PLH
PHL
600
400
750
575
900
750
625
400
775
575
925
750
700
500
850
650
1050
850
t
t
t
t
Setup Time
V
ps
ps
ps
s
450
–50
400
300
450
–50
400
300
550
350
Enable Hold Time
V
h
–250
–250
–100 –250
Minimum Pulse Width
LEN
pw
400
15
Within Device Skew
15
15
ps
ps
2
skew
T
Delay Dispersion
(ECL Levels)
DE
DL
100
60
3, 4
3, 5
T
Delay Dispersion
(TTL Levels)
ps
ps
350
100
6, 7
5, 6
t
r
t
f
Rise/Fall Times
20-80%
225
325
475
225
325
475
250
375
500
1. ThepropagationdelayismeasuredfromthecrosspointoftheinputsignalandthethresholdvaluetothecrosspointoftheQandQoutputsignals.
For propagation delay measurements the threshold level (V ) is centered about an 850mV input logic swing with a slew rate of 0.75 V/NS.
THR
There is an insignificant change in the propagation delay over the input common mode range.
2. t is the propagation delay skew between comparator A and comparator B for a particular part under identical input conditions.
skew
3. Refer to figure 4 and note that the input is at 850mV ECL levels with the input threshold range between the 20% and 80% points. The delay
is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals.
4. The slew rate is 0.25 V/NS for input rising edges.
5. The slew rate is 0.75 V/NS for input rising edges.
6. Refer to Figure 5 and note that the input is at 2.5 V TTL levels with the input threshold range between the 20% and 80% points. The delay is
measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals.
7. The slew rate is 0.3 V/NS for input rising edges.
APPLICATIONS INFORMATION
The timing diagram (Figure 3) is presented to illustrate the
MC10E1651’s compare and latch features. When the signal
on the LEN pin is at a logic high level, the device is operating
in the “compare mode,” and the signal on the input arrives at
internally generated reference level, hence is nominally at
the ECL VBB level.
Finally, V
OD
is the input voltage overdrive and represents
) to which
the voltage level beyond the threshold level (V
THR
theoutputafteranominalpropagationdelay(t
input signal must be asserted for a time, t , prior to the
negative going transition on LEN and held for a time, t , after
,t
).The
PHL PLH
s
the input is driven. As an example, if the threshold level is set
on one of the comparator inputs as 80mV and the input signal
swing on the complementary input is from zero to 100mV, the
positive going overdrive would be 20mV and the negative
going overdrive would be 80mV. The result of differing
overdrive levels is that the devices have shorter propagation
delays with greater overdrive because the threshold level is
crossed sooner than the case of lower overdrive levels.
Typically, semiconductor manufactures refer to the threshold
voltage as the input offset voltage (VOS) since the threshold
voltage is the sum of the externally supplied reference
voltage and inherent device offset voltage.
h
the LEN transition. After time t , the latch is operating in the
h
“latch mode,” thus transitions on the input do not appear at
the output. The device continues to operate in the “latch
mode” until the latch is asserted once again. Moreover, the
LEN pulse must meet the minimum pulse width (t
requirement to effect the correct input-output relationship.
Note that the LEN waveform in Figure 3 shows the LEN
)
pw
signal swinging around a reference labeled VBB ; this
INT
waveform emphasizes the requirement that LEN follow
typical ECL 10KH logic levels because VBB
is the
INT
2–3
MOTOROLA
MC10E1651
VBB
INT
LEN
t
pw
t
t
h
s
V
V
OD
V
IN
V
THR
t
t
PLH(LEN)
PHL
Q
Q
Figure 3. Input/Output Timing Diagram
DELAY DISPERSION
Under a constant set of input conditions comparators have
a specified nominal propagation delay. However, since
propagation delay is a function of input slew rate and input
where T
is the nominal propagation delay. T
NOM
NOM
accounts for nonuniformity introduced by temperature and
voltage variability, whereas the delay dispersion parameter
takes into consideration input slew rate and input voltage
overdrive variability. Thus a modified propagation delay can
be approximated to account for the effects of input conditions
that differ from those under which the parts where tested. For
example, an application may specify an ECL input with a slew
rate of 0.25 V/NS, an overdrive of 17mV and a temperature of
25°C, the delay dispersion parameter would be 100 ps. The
modified propagation delay would be
voltage overdrive the delay dispersion parameters, T
and
DE
T
, are provided to allow the user to adjust for these
DT
variables (where T
and T apply to inputs with standard
DT
DE
ECL and TTL levels, respectively).
Figure 4 and Figure 5 define a range of input conditions
which incorporate varying input slew rates and input voltage
overdrive. For input parameters that adhere to these
constraints the propagation delay can be described as:
T
± T
(or T )
DT
775ps ± 100ps
NOM
DE
–0.9 V
2.5 V
– 1.07 V
2.0 V
SLEW RATE =
0.25 V/NS
SLEW RATE =
0.30 V/NS
INPUT
THRESHOLD
RANGE
INPUT
THRESHOLD
SLEW RATE = 0.75 V/NS
SLEW RATE = 0.75 V/NS
RANGE
– 1.58 V
– 1.75 V
0.5 V
0 V
Figure 4. ECL Dispersion Test Input Conditions
Figure 5. TTL Dispersion Test Input Conditions
MOTOROLA
2–4
MC10E1651
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
M
S
S
S
B
0.007 (0.180)
T
L –M
N
Y BRK
-M-
-N-
D
D
M
S
U
0.007 (0.180)
T
L –M
N
-L-
Z
W
20
1
S
S
S
G1
V
0.010 (0.250)
T
L –M
N
X
VIEW D-D
A
M
M
S
S
S
S
0.007 (0.180)
0.007 (0.180)
T
T
L –M
L –M
N
N
Z
R
M
S
S
H
0.007 (0.180)
T L
–M
N
C
K1
E
K
0.004 (0.100)
SEATING
G
-T-
VIEW S
J
PLANE
M
S
S
F
0.007 (0.180)
T
L –M
N
G1
VIEW S
S
S
S
0.010 (0.250)
T
L –M
N
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE
TOP OF LEAD SHOULDER EXITS PLASTIC BODY
AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED AT
DATUM -T-, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER
SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
INCHES
MILLIMETERS
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
MIN
MAX
0.395
0.395
0.180
0.110
0.019
MIN
9.78
9.78
4.20
2.29
0.33
MAX
10.03
10.03
4.57
2.79
0.48
0.385
0.385
0.165
0.090
0.013
0.050 BSC
1.27 BSC
5. CONTROLLING DIMENSION: INCH.
0.026
0.032
—
—
0.356
0.356
0.048
0.048
0.056
0.020
0.66
0.51
0.64
8.89
8.89
1.07
1.07
1.07
—
0.81
—
—
9.04
9.04
1.21
1.21
1.42
0.50
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
0.020
0.025
0.350
0.350
0.042
0.042
0.042
—
2°
10
°
2°
10°
0.310
0.040
0.330
—
7.88
1.02
8.38
—
2–5
MOTOROLA
MC10E1651
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
-B-
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
—
0.39
1.27 BSC
MAX
19.93
7.49
5.08
0.50
0.750
0.240
—
0.015
0.050 BSC
-T-
SEATING
PLANE
N
K
F
0.055
0.065
1.40
1.65
0.100 BSC
2.54 BSC
G
J
K
L
M
N
E
M
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
J 16 PL
0.25 (0.010)
F
G
0.300 BSC
15
0.040
7.62 BSC
15
1.01
0.51
°
°
0°
0°
M
S
D 16 PL
0.25 (0.010)
T
B
0.020
M
S
T
A
MOTOROLA
2–6
MC10E1651
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609
INTERNET: http://Design–NET.com
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MC10E1651/D
◊
相关型号:
MC100E166FNR2
100E SERIES, 9-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PQCC28, PLASTIC, LCC-28
MOTOROLA
MC100E167FNR2G
100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC28, LEAD FREE, PLASTIC, LCC-28
ONSEMI
©2020 ICPDF网 联系我们和版权申明