MC100ES6226FA [MOTOROLA]
2.5/3.3V Differential LVPECL 1:9 Clock Distribution Buffer and Clock Divider; 2.5 / 3.3V的差分LVPECL 1 ： 9时钟分配缓冲器和时钟分频器
| 型号： | MC100ES6226FA |
| 厂家： | 
MOTOROLA |
| 描述： | 2.5/3.3V Differential LVPECL 1:9 Clock Distribution Buffer and Clock Divider |
| 文件： | 总12页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.Order Number: MC100ES6226/D
Rev 1, 12/2001
SEMICONDUCTOR TECHNICAL DATA
The Motorola MC100ES6226 is a bipolar monolithic differential clock
distribution buffer and clock divider. Designed for most demanding clock
distribution systems, the MC100ES6226 supports various applications
that require a large number of outputs to drive precisely aligned clock
signals. Using SiGe technology and a fully differential architecture, the
device offers superior digitial signal characteristics and very low clock
skew error. Target applications for this clock driver are high performance
clock distribution systems for computing, networking and
telecommunication systems.
2.5V/3.3V DIFFERENTIAL
LVPECL 1:9 CLOCK
DISTRIBUTION BUFFER AND
CLOCK DIVIDER
Features:
• Fully differential architecture from input to all outputs
• SiGe technology supports near-zero output skew
• Selectable 1:1 or 1:2 frequency outputs
• LVPECL compatible differential clock inputs and outputs
• LVCMOS compatible control inputs
• Single 3.3V or 2.5V supply
• Max. 35 ps maximum output skew (within output bank)
• Max. 50 ps maximum device skew
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A
• Supports DC operation and up to 3 GHz (typ.) clock signals
• Synchronous output enable eliminating output runt pulse generation
and metastability
• Standard 32 lead LQFP package
• Industrial temperature range
Functional Description
MC100ES6226 is designed for very skew critical differential clock distribution systems and supports clock frequencies from
DC up to 3.0 GHz. Typical applications for the MC100ES6226 are primary clock distribution systems on backplanes of
high-performance computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and
OC-48 speed communication systems.
The MC100ES6226 can be operated from a 3.3V or 2.5V positive supply without the requirement of a negative supply line.
Each of the output banks of three differential clock output pairs may be independently configured to distribute the input frequency
or half of the input frequency. The FSEL0 and FSEL1 clock frequency selects are asychronous control inputs. Any changes of the
control inputs require a MR pulse for resynchronization of the ÷2 outputs.
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MC100ES6226
Bank A
V
CC
QA0
QA0
QA1
QA1
÷1
CLK
CLK
÷2
QA2
QA2
Bank B
QB0
QB0
MR
QB1
QB1
QB2
QB2
FSEL0
FSEL1
Bank C
QC0
QC0
QC1
QC1
QC2
QC2
Sync
OE
Figure 1. MC100ES6226 Logic Diagram
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
QC0
QC0
QC1
QA2
QA2
VCC
QA1
QA1
QA0
QA0
VCC
QC1
VCC
QC2
MC100ES6226
QC2
VCC
1
2
3
4
5
6
7
8
Figure 2. 32–Lead Package Pinout (Top View)
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TABLE 1: PIN CONFIGURATION
Pin
I/O
Input
Type
Function
CLK, CLK
LVPECL
Differential reference clock signal input
OE
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
Output enable
MR
Device reset
FSEL0, FSEL1
Output frequency divider select
QA[0-2], QA[0-2]
QB[0-2], QB[0-2]
QC[0-2], QC[0-2]
Output
LVPECL
Differential clock outputs (banks A, B and C)
GND
Supply
Supply
GND
VCC
Negative power supply
V
CC
Positive power supply. All V
correct DC and AC operation
pins must be connected to the positive power supply for
CC
TABLE 2: FUNCTION TABLE
Control
Default
0
1
OE
0
Qx[0-2], Qx[0-2] are active. Deassertion of OE can
be asynchronous to the reference clock without
generation of output runt pulses
Qx[0-2] = L, Qx[0-2] =H (outputs disabled).
Assertion of OE can be asynchronous to the
reference clock without generation of output runt
pulses
MR
0
Normal operation
Device reset (asynchronous)
FSEL0, FSEL1
00
See Following Table
TABLE 3: Output Frequency Select Control
FSEL1
QC0 to QC2
f = f
QC0:2 CLK
FSEL0
QA0 to QA2
QB0 to QB2
0
0
1
0
1
f
f
f
= f
f
f
= f
QA0:2 CLK
= f
QB0:2 CLK
= f
QB0:2 CLK
0
1
1
f
f
f
= f
÷ 2
÷ 2
÷ 2
QA0:2 CLK
QC0:2 CLK
= f
f
= f
QB0:2 CLK
÷ 2
÷ 2
= f
QC0:2 CLK
QA0:2 CLK
= f ÷ 2
f
f
= f
QB0:2 CLK
= f
QC0:2 CLK
QA0:2 CLK
a
TABLE 4: ABSOLUTE MAXIMUM RATINGS
Symbol
Characteristics
Min
-0.3
-0.3
-0.3
Max
Unit
V
Condition
V
CC
Supply Voltage
3.6
V
IN
DC Input Voltage
V
V
+0.3
V
CC
V
OUT
DC Output Voltage
DC Input Current
+0.3
V
CC
I
IN
±20
mA
mA
°C
I
DC Output Current
Storage temperature
±50
OUT
T
S
-65
125
a. Absolutemaximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
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TABLE 5: GENERAL SPECIFICATIONS
Symbol
Characteristics
Output termination voltage
Min
Typ
Max
Unit
V
Condition
a
- 2
CC
V
TT
V
MM
HBM
CDM
LU
ESD Protection (Machine model)
ESD Protection (Human body model)
ESD Protection (Charged device model)
Latch-up immunity
200
2000
1000
200
V
V
V
mA
pF
C
4.0
Inputs
IN
θ
Thermal resistance junction to ambient
JESD 51-3, single layer test board
JA
83.1
73.3
68.9
63.8
57.4
86.0
75.4
70.9
65.3
59.6
°C/W
°C/W
°C/W
°C/W
°C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
JESD 51-6, 2S2P multilayer test board
Thermal resistance junction to case
59.0
54.4
52.5
50.4
47.8
60.6
55.7
53.8
51.5
48.8
°C/W
°C/W
°C/W
°C/W
°C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
θ
23.0
26.3
°C/W
MIL-SPEC 883E
Method 1012.1
JC
b
Operating junction temperature
(continuous operation) MTBF = 9.1 years
0
110
°C
a. Output termination voltage V = 0V for V
TT
= 2.5V operation is supported but the power consumption of the device will increase.
CC
b. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are
specified up to 110°C junction temperature allowing the MC100ES6226 to be used in applications requiring industrial temperature range. It
is recommended that users of the MC100ES6226 employ thermal modeling analysis to assist in applying the junction temperature
specifications to their particular application.
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MC100ES6226
a
= 3.3V ± 5% and 2.5V ± 5%, T = 0°C to +110°C)
J
TABLE 6: DC CHARACTERISTICS (V
CC
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS control inputs (OE, FSEL0, FSEL1, MR)
V
Input voltage low
Input voltage high
V
V
= 3.3 V
= 2.5 V
0.8
0.7
V
V
IL
IH
IN
CC
CC
V
V
CC
V
CC
= 3.3 V
= 2.5 V
2.2
1.7
b
I
Input Current
±150
µA
V
IN
= V
or V = GND
CC IN
c
LVPECL clock inputs (CLK, CLK)
d
V
DC differential input voltage
Differential cross point voltage
Input high voltage
0.1
1.0
1.3
V
V
Differential operation
Differential operation
PP
e
V
CMR
V
-0.3
CC
V
TBD
TBD
TBD
IH
V
Input low voltage
TBD
IL
I
IN
Input Current
±150
µA
V = TBD or V = TBD
IN IN
LVPECL clock outputs (QA[2:0], QB[2:0], QC[2:0])
V
Output High Voltage
Output Low Voltage
V
V
-1.1
V
V
-0.8
V
V
Termination 50 to V
Termination 50 to V
OH
CC
CC
TT
TT
V
-1.8
-1.4
OL
CC
CC
Supply current
I
Maximum Quiescent Supply Current
without output termination current
65
110
400
mA
mA
GND pin
GND
I
Maximum Quiescent Supply Current
with output termination current
325
All V
Pins
CC
CC
a. AC characterisitics are design targets and pending characterization.
b. Input have internal pullup/pulldown resistors which affect the input current.
c. Clock inputs driven by LVPECL compatible signals.
d.
e.
V
is the minimum differential input voltage swing required to maintain AC characteristic.
PP
V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
(DC) specification.
PP
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a b
= 3.3V ± 5% and 2.5V ± 5%, T = 0°C to +110°C)
J
TABLE 7: AC CHARACTERISTICS (V
CC
Symbol
Characteristics
Min
0.2
1.0
Typ
Max
Unit
V
Condition
c
V
PP
Differential input voltage
(peak-to-peak)
0.3
1.3
d
V
CMR
Differential input crosspoint voltage
V
V
-0.3
V
CC
V
Differential output crosspoint voltage
V
-1.45
-1.1
V
X,OUT
O(P-P)
CC
CC
V
Differential output voltage (peak-to-peak)
f
< 300 MHz
0.45
0.3
TBD
0.72
0.55
0.37
0.95
0.95
0.95
V
V
V
O
f
f
< 1.5 GHz
< 2.7 GHz
O
O
e
f
Input Frequency
0
3000
MHz
ps
CLK
t
Propagation Delay CLK to Qx[]
475
500
800
Differential
Differential
PD
t
Output-to-output skew
(within QA[2:0])
(within QB[2:0])
(within QC[2:0])
(within device)
11
12
4
25
25
20
60
ps
ps
ps
ps
sk(O)
t
Output-to-output skew
(part-to-part)
325
ps
Differential
sk(PP)
t
Output cycle-to-cycle jitter
JIT(CC)
single frequency configuration
÷1/÷2 frequency configuration
TBD
TBD
FSEL0 = FSEL1
FSEL0 ≠ FSEL1
DC
Output duty cycle
Qx = ÷1, f < 300 MHz
48
45
50
50
52
55
%
%
DC = 50%
fref
O
O
Qx = ÷1, f > 300 MHz
O
Qx = ÷2, f < 300 MHz
49
47.5
50
50
51
52.5
%
%
O
Qx = ÷2, f > 300 MHz
O
t , t
r f
Output Rise/Fall Time
Output disable time
Output enable time
0.05
200
ns
ns
ns
20% to 80%
f
t
2.5 T + t
4.5 T + t
PD
T=CLK period
T=CLK period
PDL
PD
g
t
3 T + t
5 T + t
PD
PLD
PD
a. AC characterisitics are design targets and pending characterization.
b. AC characteristics apply for parallel output termination of 50Ω to V
.
TT
is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.
c.
d.
V
V
PP
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
(AC)
(AC) impacts the device propagation delay,
CMR
range and the input swing lies within the V
device and part-to-part skew.
(AC) specification. Violation of V
CMR
(AC) or V
PP
PP
e. The MC100ES6226 is fully operational up to 3.0 GHz and is characterized up to 2.7 GHz.
f. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high).
g. Propagation delay OE assertion to output enabled (active).
CLK
CLK
50%
OE
t
(OE to Qx)
PDL
t
(OE to Qx)
PLD
Qx
Qx
Outputs disabled
Figure 3. MC100ES6226 output disable/enable timing
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Z
O
= 50Ω
Z = 50Ω
O
Differential
Pulse Generator
Z = 50
DUT
MC100ES6226
R = 50Ω
T
R = 50Ω
T
V
TT
V
TT
Figure 4. MC100ES6226 AC test reference
APPLICATIONS INFORMATION
Maintaining Lowest Device Skew
to GND. If the spectral frequencies of the internally generated
switching noise on the supply pins cross the series resonant
point of an individual bypass capacitor, its overall impedance
begins to look inductive and thus increases with increasing
frequency. The parallel capacitor combination shown
ensures that a low impedance path to ground exists for
frequencies well above the noise bandwidth.
The MC100ES6226 guarantees low output-to-output bank
skew of 35 ps and a part-to-part skew of max. TBD ps. To
ensure low skew clock signals in the application, both outputs
of any differential output pair need to be terminated
identically, even if only one output is used. When fewer than
all nine output pairs are used, identical termination of all
output pairs within the output bank is recommended. If an
entire output bank is not used, it is recommended to leave all
of these outputs open and unterminated. This will reduce the
device power consumption while maintaining minimum
output skew.
V
V
CC
CC
MC100ES6226
33...100 nF
0.1 nF
Power Supply Bypassing
The MC100ES6226 is a mixed analog/digital product. The
differential architecture of the MC100ES6226 supports low
noise signal operation at high frequencies. In order to
Figure 5. V
CC
Power Supply Bypass
maintain its superior signal quality, all V
pins should be
CC
bypassed by high-frequency ceramic capacitors connected
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NOTES
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NOTES
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NOTES
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OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 873A-02
ISSUE A
4X
A
A1
0.20 (0.008) AB T–U
Z
32
25
1
–U–
V
–T–
B
AE
AE
P
B1
DETAIL Y
–Z–
V1
17
8
DETAIL Y
9
4X
0.20 (0.008) AC T–U
Z
9
NOTES:
S1
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
DETAIL AD
G
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
–AB–
–AC–
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
SEATING
PLANE
0.10 (0.004) AC
BASE
METAL
N
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
F
D
8X M
MILLIMETERS
DIM MIN MAX
7.000 BSC
INCHES
MIN MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
R
J
A
A1
B
3.500 BSC
7.000 BSC
3.500 BSC
1.400 1.600 0.055 0.063
0.300 0.450 0.012 0.018
1.350 1.450 0.053 0.057
0.300 0.400 0.012 0.016
SECTION AE–AE
E
C
B1
C
D
E
F
W
G
H
J
K
M
N
P
0.800 BSC
0.031 BSC
Q
H
K
X
0.050 0.150 0.002 0.006
0.090 0.200 0.004 0.008
0.500 0.700 0.020 0.028
12 REF
0.090 0.160 0.004 0.006
0.400 BSC 0.016 BSC
12 REF
DETAIL AD
Q
R
1
5
1
5
0.150 0.250 0.006 0.010
S
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
S1
V
V1
W
X
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MC100ES6226
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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Motorola, Inc. 2001.
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◊
MC100ES6226/D
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