MC14001UBCP [MOTOROLA]
UB-Suffix Series COMS Gates; UB-后缀系列COMS门
| 型号： | MC14001UBCP |
| 厂家： | 
MOTOROLA |
| 描述： | UB-Suffix Series COMS Gates |
| 文件： | 总7页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired. The UB set of CMOS gates are inverting
non–buffered functions.
•
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Linear and Oscillator Applications
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
•
•
Pin–for–Pin Replacements for Corresponding CD4000 Series UB Suffix
Devices
LOGIC DIAGRAMS
MC14001UB
Quad 2–Input
NOR Gate
MC14002UB
Dual 4–Input
NOR Gate
MC14011UB
Quad 2–Input
NAND Gate
L SUFFIX
CERAMIC
CASE 632
2
1
1
2
3
3
3
4
2
5
1
5
6
4
4
6
8
5
9
10
11
12
8
10
11
10
11
P SUFFIX
PLASTIC
CASE 646
9
9
12
13
12
13
13
NC = 6, 8
D SUFFIX
SOIC
CASE 751A
MC14012UB
Dual 4–Input
NAND Gate
MC14023UB
Triple 3–Input
NAND Gate
MC14025UB
Triple 3–Input
NOR Gate
1
1
2
ORDERING INFORMATION
2
3
9
2
9
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
Plastic
Ceramic
SOIC
1
8
3
8
3
4
5
9
4
6
4
5
11
6
T
= – 55° to 125°C for all packages.
A
5
11
10
11
12
13
12
13
10
12
13
10
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
agesto this high–impedance circuit. For proper
NC = 6, 8
V
V
= PIN 14
= PIN 7
DD
SS
operation, V and V
should be constrained
FOR ALL DEVICES
in out
to the range V
(V or V
)
V
DD
.
SS in out
Unused inputs must always be tied to an
appropriatelogic voltage level (e.g., either V
SS
or V ). Unused outputs must be left open.
DD
REV 3
1/94
Motorola, Inc. 1995
PIN ASSIGNMENTS
MC14001UB
MC14002UB
MC14011UB
Quad 2–Input NOR Gate
Dual 4–Input NOR Gate
Quad 2–Input NAND Gate
IN 1
IN 2
1
2
3
4
14
13
12
11
V
OUT
1
2
3
4
14
13
12
11
V
IN 1
IN 2
1
2
3
4
14
13
12
11
V
DD
A
DD
A
DD
OUT
A
IN 2
IN 1
IN 2
IN 3
IN 4
IN 2
A
D
D
A
A
A
A
B
A
D
D
OUT
IN 1
IN 4
OUT
A
IN 1
A
B
OUT
OUT
OUT
IN 3
OUT
OUT
OUT
B
D
C
B
B
D
C
IN 1
5
6
10
9
5
6
10
9
IN 2
IN 1
5
6
10
9
B
B
B
B
B
B
IN 2
IN 2
NC
IN 1
IN 2
IN 2
C
C
V
7
8
IN 1
V
7
8
NC
V
7
8
IN 1
SS
C
SS
SS
C
MC14023UB
Triple 3–Input NAND Gate
MC14025UB
Triple 3–Input NOR Gate
MC14012UB
Dual 4–Input NAND Gate
OUT
1
2
3
4
14
13
12
11
V
IN 1
IN 2
IN 1
IN 2
1
2
3
4
14
13
12
11
V
IN 1
IN 2
IN 1
IN 2
1
2
3
4
14
13
12
11
V
DD
A
DD
OUT
A
A
B
B
DD
A
A
B
B
IN 1
IN 2
IN 3
IN 4
IN 3
IN 2
IN 1
IN 3
IN 2
IN 1
A
A
A
A
B
C
C
C
C
C
C
IN 4
B
IN 3
B
5
6
10
9
IN 2
IN 3
5
6
10
9
OUT
IN 3
5
6
10
9
OUT
C
B
B
B
C
B
NC
IN 1
OUT
OUT
OUT
OUT
A
B
A
B
V
7
8
NC
V
7
8
IN 3
V
7
8
IN 3
A
SS
SS
A
SS
NC = NO CONNECTION
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
Symbol
Parameter
DC Supply Voltage
Value
– 0.5 to + 18.0
– 0.5 to V + 0.5
Unit
V
DD
V
V
V , V
in out
Input or Output Voltage (DC or Transient)
DD
± 10
l , l
in out
Input or Output Current (DC or Transient),
per Pin
mA
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
T
stg
– 65 to + 150
260
T
Lead Temperature (8–Second Soldering)
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
MOTOROLA CMOS LOGIC DATA
MC14001UB
19
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V
DD
or 0
V
in
= 0 or V
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
DD
Input Voltage
(V = 4.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.0
2.0
2.5
—
—
—
2.25
4.50
6.75
1.0
2.0
2.5
—
—
—
1.0
2.0
2.5
O
(V = 9.0 Vdc)
O
(V = 13.5 Vdc)
O
(V = 0.5 Vdc)
“1” Level
Source
Sink
I
5.0
10
15
4.0
8.0
12.5
—
—
—
4.0
8.0
12.5
2.75
5.50
8.25
—
—
—
4.0
8.0
12.5
—
—
—
Vdc
O
IH
(V = 1.0 Vdc)
O
(V = 1.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
OH
(V
OH
(V
OH
(V
OH
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
5.0
5.0
10
– 1.2
– 0.25
– 0.62
– 1.8
—
—
—
—
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
—
—
—
—
– 0.7
– 0.14
– 0.35
– 1.1
—
—
—
—
15
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
Input Current
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
Input Capacitance
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
µAdc
µAdc
DD
Total Supply Current**†
I
T
5.0
10
15
I
I
I
= (0.3 µA/kHz) f + I /N
DD
T
T
T
(Dynamic plus Quiescent,
Per Gate C = 50 pF)
= (0.6 µA/kHz) f + I /N
DD
= (0.8 µA/kHz) f + I /N
DD
L
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µH (per package), C in pF, V = (V
package.
– V ) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
SS
T
L
DD
MC14001UB
20
MOTOROLA CMOS LOGIC DATA
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
V
Vdc
DD
Characteristic
Symbol
Min
Typ #
Max
Unit
Output Rise Time
t
ns
TLH
t
t
t
= (3.0 ns/pF) C + 30 ns
= (1.5 ns/pF) C + 15 ns
= (1.1 ns/pF) C + 10 ns
5.0
10
15
—
—
—
180
90
65
360
180
130
TLH
TLH
TLH
L
L
L
Output Fall Time
t
ns
ns
THL
t
t
t
= (1.5 ns/pF) C + 25 ns
= (0.75 ns/pF) C + 12.5 ns
= (0.55 ns/pF) C + 9.5 ns
5.0
10
15
—
—
—
100
50
40
200
100
80
THL
THL
THL
L
L
L
Propagation Delay Time
t
, t
PLH PHL
t
t
t
, t
= (1.7 ns/pF) C + 30 ns
= (0.66 ns/pF) C + 22 ns
= (0.50 ns/pF) C + 15 ns
L
5.0
10
15
—
—
—
90
50
40
180
100
80
PLH PHL
L
L
, t
PLH PHL
, t
PLH PHL
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns
20 ns
V
DD
V
INPUT
DD
14
90%
50%
10%
INPUT
*
OUTPUT
PULSE
GENERATOR
0 V
t
t
PLH
PHL
V
C
OH
L
90%
50%
OUTPUT
INVERTING
10%
V
7
V
SS
OL
* All unused inputs of AND, NAND gates must be
t
t
TLH
THL
connected to V
.
DD
All unused inputs of OR, NOR gates must be
connected to V
.
SS
Figure 1. Switching Time Test Circuit and Waveforms
MC14001UB CIRCUIT SCHEMATIC
MC14002UB CIRCUIT SCHEMATIC
(1/2 of Device Shown)
V
V
14
DD
14
DD
3
10
2, 9
3, 10
4, 11
5, 12
1
2
8
9
1, 13
6
5
13
12
V
7
SS
4
7
11
V
SS
MOTOROLA CMOS LOGIC DATA
MC14001UB
21
MC14011UB CIRCUIT SCHEMATIC
(1/4 of Device Shown)
MC14012UB CIRCUIT SCHEMATIC
(1/2 of Device Shown)
MC14023UB CIRCUIT SCHEMATIC
(1/3 of Device Shown)
14 V
DD
14 V
DD
14 V
DD
1, 13
3, 4, 10, 11
6, 9, 10
1, 6, 8, 13
2, 9
3, 10
4, 11
5, 12
5, 1, 11
2, 5, 9, 12
4, 2, 12
3, 8, 13
7 V
SS
7 V
SS
7 V
SS
16
16
14
12
10
8.0
6.0
4.0
2.0
0
MC14025UB CIRCUIT SCHEMATIC
(1/3 of Device Shown)
V
= 15 Vdc
V
= 15 Vdc
b
DD
T
= +25
°
C
DD
Unused input
connected to
A
Unused input
connected to
V
One input only
Both inputs
14
12
10
8.0
6.0
4.0
2.0
0
V
.
SS
a
14 V
DD
.
SS
a
b
10 Vdc
10 Vdc
a T = +125
°
C
A
1, 3, 11
2, 4, 12
8, 5, 13
b T = –55°C
A
8.0
6.0
4.0
b
a
a
b
5.0 Vdc
5.0 Vdc
9, 6, 10
15 Vdc
10 Vdc
a
b
a
b
a
b
2.0
0
7 V
SS
0
2.0 4.0 6.0 8.0 10 12 14 16
0
2.0 4.0 6.0 8.0 10 12 14 16
, INPUT VOLTAGE (Vdc)
V
, INPUT VOLTAGE (Vdc)
V
in
in
Figure 2. Typical Voltage and
Current Transfer Characteristics
Figure 3. Typical Voltage Transfer
Characteristics versus
Temperature
10
0
–2.0
–4.0
c
a
15 Vdc
b
a
V
= –5.0 Vdc
GS
c
8.0
6.0
4.0
b
V
= 10 Vdc
GS
a
b
a
b
c
T = –55°C
A
= +25°C
= +125°C
c
T
A
T
A
a
b
c
T = –55°C
A
c
T
= +25°C
A
–6.0
–8.0
–10
T
= +125°C
A
b
–10 Vdc
a
c
c
–15 Vdc
2.0
b
b
5.0 Vdc
6.0
a
a
–2.0
0
–10
–8.0
–6.0
–4.0
0
0
2.0
4.0
8.0
10
V
, DRAIN VOLTAGE (Vdc)
V
, DRAIN VOLTAGE (Vdc)
DS
DS
Figure 4. Typical Output Source
Characteristics
Figure 5. Typical Output Sink
Characteristics
MC14001UB
22
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
1
9
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
7
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.280
0.200
0.020
0.065
MIN
19.05
6.23
3.94
0.39
1.40
MAX
19.94
7.11
5.08
0.50
1.65
0.750
0.245
0.155
0.015
0.055
–T–
SEATING
PLANE
K
F
G
J
K
0.100 BSC
2.54 BSC
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
G
N
M
D 14 PL
0.25 (0.010)
J 14 PL
0.25 (0.010)
L
M
N
0.300 BSC
7.62 BSC
0
15
0
15
M
S
T
A
M
S
T
B
0.020
0.040
0.51
1.01
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
ISSUE L
14
8
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
1
7
4. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
C
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.095
0.015
0.135
1.32
0.20
2.92
2.41
0.38
3.43
J
N
0.300 BSC
7.62 BSC
SEATING
PLANE
K
0
10
0
10
0.015
0.039
0.39
1.01
H
G
D
M
MOTOROLA CMOS LOGIC DATA
MC14001UB
23
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE F
Y14.5M, 1982.
–A–
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
14
1
8
7
–B–
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
INCHES
G
DIM
A
B
C
D
F
G
J
K
M
P
MIN
8.55
3.80
1.35
0.35
0.40
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
C
0.337
0.150
0.054
0.014
0.016
–T–
SEATING
PLANE
J
M
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
M
S
S
0.25 (0.010)
T
B
A
5.80
0.25
6.20
0.50
0.228
0.010
0.244
0.019
R
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
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into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
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are registered
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
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51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MC14001UB/D
◊
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Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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