MC14011BCP [MOTOROLA]
B-Suffix Series CMOS Gates; B-后缀系列CMOS门
| 型号： | MC14011BCP |
| 厂家： | 
MOTOROLA |
| 描述： | B-Suffix Series CMOS Gates |
| 文件： | 总11页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired.
•
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
Double Diode Protection on All Inputs Except: Triple Diode Protection
on MC14011B and MC14081B
Pin–for–Pin Replacements for Corresponding CD4000 Series B Suffix
Devices (Exceptions: MC14068B and MC14078B)
•
•
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
T
A
= – 55° to 125°C for all packages.
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
V
DD
– 0.5 to + 18.0
V , V
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
in out
l , l
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
T
stg
– 65 to + 150
260
T
Lead Temperature (8–Second Soldering)
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V and
in
V
out
should be constrained to the range V
SS
≤ (V or V ) ≤ V .
in out DD
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V or V ). Unused outputs must be left open.
SS DD
REV 3
1/94
Motorola, Inc. 1995
LOGIC DIAGRAMS
NOR
NAND
OR
AND
MC14001B
MC14011B
MC14071B
MC14081B
Quad 2–Input NOR Gate
Quad 2–Input NAND Gate
Quad 2–Input OR Gate
Quad 2–Input AND Gate
1
3
2
1
3
2
1
3
2
1
3
2
5
4
6
5
4
6
5
4
6
5
4
6
8
8
8
8
10
10
10
10
9
9
9
9
12
13
12
11
13
12
13
12
11
13
11
11
MC14025B
MC14023B
MC14075B
MC14073B
Triple 3–Input NOR Gate
Triple 3–Input NAND Gate
Triple 3–Input OR Gate
Triple 3–Input AND Gate
1
2
1
2
1
2
1
2
9
9
9
9
8
8
8
8
3
4
3
4
3
4
3
4
6
6
6
6
5
5
5
5
11
12
13
11
12
13
11
12
13
11
12
13
10
10
10
10
MC14002B
MC14012B
MC14072B
MC14082B
Dual 4–Input NOR Gate
Dual 4–Input NAND Gate
Dual 4–Input OR Gate
Dual 4–Input AND Gate
2
2
2
2
3
4
3
4
3
4
3
4
1
1
1
1
5
5
5
5
9
9
9
9
10
11
10
11
10
11
10
11
13
13
13
13
12
12
12
12
NC = 6, 8
NC = 6, 8
NC = 6, 8
NC = 6, 8
MC14078B
8–Input NOR Gate
MC14068B
8–Input NAND Gate
V
V
= PIN 14
= PIN 7
DD
SS
2
3
4
2
3
4
FOR ALL DEVICES
5
9
5
9
13
13
10
11
12
10
11
12
NC = 6, 8
NC = 6, 8
MC14001B
8
MOTOROLA CMOS LOGIC DATA
PIN ASSIGNMENTS
MC14001B
Quad 2–Input NOR Gate
MC14002B
Dual 4–Input NOR Gate
MC14011B
Quad 2–Input NAND Gate
MC14012B
Dual 4–Input NAND Gate
IN 1
IN 2
1
2
3
4
14
13
12
11
V
OUT
1
2
3
4
14
13
12
11
V
IN 1
IN 2
1
2
3
4
14
13
12
11
V
OUT
1
2
3
4
14
13
12
11
V
A
DD
A
DD
OUT
A
DD
A
DD
OUT
IN 2
IN 1
IN 2
IN 3
IN 4
IN 2
IN 1
IN 2
IN 3
IN 4
A
D
D
A
A
A
A
B
A
D
D
A
A
A
A
B
OUT
IN 1
IN 4
OUT
IN 1
IN 4
A
B
A
B
OUT
OUT
OUT
IN 3
OUT
OUT
OUT
IN 3
B
D
C
B
B
D
C
B
IN 1
5
6
10
9
5
6
10
9
IN 2
IN 1
5
6
10
9
5
6
10
9
IN 2
B
B
B
B
B
B
B
B
IN 2
IN 2
NC
IN 1
IN 2
IN 2
NC
IN 1
C
C
V
7
8
IN 1
V
7
8
NC
V
7
8
IN 1
V
SS
7
8
NC
SS
C
SS
SS
C
MC14023B
Triple 3–Input NAND Gate
MC14025B
Triple 3–Input NOR Gate
MC14068B
8–Input NAND Gate
MC14071B
Quad 2–Input OR Gate
IN 1
IN 2
IN 1
IN 2
1
2
3
4
14
13
12
11
V
IN 1
IN 2
IN 1
IN 2
1
2
3
4
14
13
12
11
V
NC
IN 1
IN 2
IN 3
1
2
3
4
14
13
12
11
V
IN 1
IN 2
1
2
3
4
14
13
12
11
V
DD
A
A
B
B
DD
A
A
B
B
DD
DD
A
IN 3
IN 2
IN 1
IN 3
IN 2
IN 1
OUT
IN 8
IN 7
IN 2
C
C
C
C
C
C
A
D
D
OUT
IN 1
A
OUT
OUT
OUT
B
D
C
IN 3
5
6
10
9
OUT
IN 3
5
6
10
9
OUT
IN 4
NC
5
6
10
9
IN 6
IN 5
IN 1
5
6
10
9
B
C
B
C
B
B
OUT
OUT
OUT
OUT
IN 2
IN 2
B
A
B
A
C
V
7
8
IN 3
V
7
8
IN 3
V
7
8
NC
V
7
8
IN 1
SS
A
SS
A
SS
SS
C
MC14072B
Dual 4–Input OR Gate
MC14073B
Triple 3–Input AND Gate
MC14075B
Triple 3–Input OR Gate
MC14078B
8–Input NOR Gate
OUT
1
2
3
4
14
13
12
11
V
IN 1
IN 2
IN 1
IN 2
1
2
3
4
14
13
12
11
V
IN 1
IN 2
IN 1
IN 2
1
2
3
4
14
13
12
11
V
NC
1
2
3
4
14
13
12
11
V
DD
A
DD
OUT
A
A
B
B
DD
A
A
B
B
DD
IN 1
IN 2
IN 3
IN 4
IN 3
IN 2
IN 1
IN 3
IN 2
IN 1
IN 1
IN 2
IN 3
OUT
IN 8
IN 7
A
A
A
A
B
C
C
C
C
C
C
IN 4
B
IN 3
B
5
6
10
9
IN 2
IN 3
5
6
10
9
OUT
IN 3
5
6
10
9
OUT
C
IN 4
NC
5
6
10
9
IN 6
IN 5
B
B
B
C
B
NC
IN 1
OUT
OUT
OUT
OUT
A
B
A
B
V
7
8
NC
V
7
8
IN 3
V
7
8
IN 3
V
SS
7
8
NC
SS
SS
A
SS
A
MC14081B
Quad 2–Input AND Gate
MC14082B
Dual 4–Input AND Gate
IN 1
IN 2
1
2
3
4
14
13
12
V
OUT
1
2
3
4
14
13
12
11
V
A
DD
A
DD
OUT
IN 2
IN 1
IN 2
IN 3
IN 4
A
D
D
D
C
A
A
A
A
B
OUT
IN 1
IN 4
A
B
OUT
11 OUT
10 OUT
IN 3
B
B
IN 1
5
6
5
6
10
9
IN 2
B
B
B
B
IN 2
9
8
IN 2
NC
IN 1
C
V
7
IN 1
V
SS
7
8
NC
SS
C
NC = NO CONNECTION
MOTOROLA CMOS LOGIC DATA
MC14001B
9
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V
DD
or 0
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
OH
OH
OH
15
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
Input Current
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
Input Capacitance
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
µAdc
µAdc
DD
Total Supply Current**†
I
T
5.0
10
15
I
I
I
= (0.3 µA/kHz) f + I /N
DD
T
T
T
(Dynamic plus Quiescent,
Per Gate, C = 50 pF)
= (0.6 µA/kHz) f + I /N
DD
= (0.9 µA/kHz) f + I /N
DD
L
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V
package.
– V ) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
SS
T
L
DD
MC14001B
10
MOTOROLA CMOS LOGIC DATA
B–SERIES GATE SWITCHING TIMES
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
V
Vdc
DD
Characteristic
Symbol
Min
Typ #
Max
Unit
Output Rise Time, All B–Series Gates
t
ns
TLH
t
t
t
= (1.35 ns/pF) C + 33 ns
L
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH
TLH
TLH
= (0.60 ns/pF) C + 20 ns
L
= (0.40 ns/PF) C + 20 ns
L
Output Fall Time, All B–Series Gates
t
ns
ns
THL
t
t
t
= (1.35 ns/pF) C + 33 ns
L
5.0
10
15
—
—
—
100
50
40
200
100
80
THL
THL
THL
= (0.60 ns/pF) C + 20 ns
L
= (0.40 ns/pF) C + 20 ns
L
Propagation Delay Time
t
, t
PLH PHL
MC14001B, MC14011B only
t
t
t
, t
= (0.90 ns/pF) C + 80 ns
5.0
10
15
—
—
—
125
50
40
250
100
80
PLH PHL
L
, t
= (0.36 ns/pF) C + 32 ns
L
PLH PHL
, t
= (0.26 ns/pF) C + 27 ns
PLH PHL
L
All Other 2, 3, and 4 Input Gates
t
t
t
, t
= (0.90 ns/pF) C + 115 ns
5.0
10
15
—
—
—
160
65
50
300
130
100
PLH PHL
L
, t
= (0.36 ns/pF) C + 47 ns
L
PLH PHL
, t
= (0.26 ns/pF) C + 37 ns
PLH PHL
L
8–Input Gates (MC14068B, MC14078B)
t
t
t
, t
= (0.90 ns/pF) C + 155 ns
5.0
10
15
—
—
—
200
80
60
350
150
110
PLH PHL
L
, t
= (0.36 ns/pF) C + 62 ns
L
PLH PHL
, t
PLH PHL
= (0.26 ns/pF) C + 47 ns
L
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns
20 ns
14
V
DD
V
DD
90%
50%
10%
INPUT
INPUT
*
0 V
PULSE
GENERATOR
OUTPUT
t
PHL
t
PLH
90%
50%
10%
V
V
OH
C
L
OUTPUT
INVERTING
OL
t
t
TLH
THL
t
t
PLH
PHL
V
V
OH
7
V
SS
OUTPUT
90%
50%
10%
NON–INVERTING
* All unused inputs of AND, NAND gates must be connected to V
.
OL
DD
.
t
t
THL
TLH
All unused inputs of OR, NOR gates must be connected to V
SS
Figure 1. Switching Time Test Circuit and Waveforms
MOTOROLA CMOS LOGIC DATA
MC14001B
11
CIRCUIT SCHEMATIC
NOR, OR GATES
MC14001B, MC14071B
One of Four Gates Shown
V
DD
14
V
DD
1, 6, 8, 13
2, 5, 9, 12
*
3, 4, 10, 11
MC14025B, MC14075B
One of Three Gates Shown
V
DD
V
7
SS
V
SS
1, 3, 11
* Inverter omitted in MC14001B
2, 4, 12
14
V
DD
*
MC14002B, MC14072B
One of Two Gates Shown
V
SS
9, 6, 10
V
DD
V
DD
3, 9
8, 5, 13
2, 10
7
V
SS
14
V
DD
V
SS
* Inverter omitted in MC14025B
*
1, 13
V
SS
5, 11
4, 12
SAME AS
ABOVE
7
V
SS
* Inverter omitted in MC14002B
V
MC14078B
DD
Eight Input Gate
2
3
14
V
DD
V
SS
SAME AS
ABOVE
4
5
13
SAME AS
ABOVE
9
10
SAME AS
ABOVE
11
12
7
V
SS
MC14001B
12
MOTOROLA CMOS LOGIC DATA
CIRCUIT SCHEMATIC
NAND, AND GATES
MC14011B, MC14081B
One of Four Gates Shown
14
V
DD
*
MC14023B, MC14073B
One of Three Gates Shown
3, 4, 10, 11
V
2, 5, 9, 12
1, 6, 8, 13
DD
7
V
SS
* Inverter omitted in MC14011B
2, 4, 12
1, 3, 11
14
V
DD
V
SS
*
V
DD
9, 6, 10
MC14012B, MC14082B
8, 5, 13
One of Two Gates Shown
V
DD
7
V
SS
V
SS
* Inverter omitted in MC14023B
14
V
DD
MC14068B
2, 10
3, 9
Eight Input Gate
V
DD
*
V
SS
1, 13
4, 12
5, 11
SAME AS
ABOVE
V
DD
2
3
7
V
SS
* Inverter omitted in MC14012B
V
SS
5
4
SAME AS
ABOVE
14
V
DD
V
SS
V
DD
9
10
SAME AS
ABOVE
13
11
12
SAME AS
ABOVE
7
V
SS
V
SS
MOTOROLA CMOS LOGIC DATA
MC14001B
13
TYPICAL B–SERIES GATE CHARACTERISTICS
N–CHANNEL DRAIN CURRENT
(SINK)
P–CHANNEL DRAIN CURRENT
(SOURCE)
– 10
5.0
– 9.0
– 8.0
– 7.0
– 6.0
– 5.0
– 4.0
4.0
3.0
T
= – 55°C
A
T
= – 55°C
A
– 40°C
– 40°C
+ 25°C
+ 25
°
C
+ 85°C
+ 85°C
2.0
1.0
+ 125°C
– 3.0
+ 125°C
– 2.0
– 1.0
0
0
0
1.0
2.0
3.0
4.0
5.0
0
– 1.0
– 2.0
– 3.0
– 4.0
– 5.0
V
, DRAIN–TO–SOURCE VOLTAGE (Vdc)
V , DRAIN–TO–SOURCE VOLTAGE (Vdc)
DS
DS
Figure 2. V
GS
= 5.0 Vdc
Figure 3. V = – 5.0 Vdc
GS
20
18
16
14
– 50
– 45
– 40
– 35
T
= – 55°C
A
– 40°C
+ 25
°
C
C
12
10
– 30
– 25
– 20
T = – 55°C
A
+ 85
°
– 40
+ 85
+ 125
°C
+ 125
°C
+ 25°C
8.0
°C
6.0
4.0
2.0
0
– 15
– 10
– 5.0
0
°
C
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
0
– 1.0 – 2.0 – 3.0 – 4.0 – 5.0 – 6.0 – 7.0 – 8.0 – 9.0 – 10
, DRAIN–TO–SOURCE VOLTAGE (Vdc)
V
, DRAIN–TO–SOURCE VOLTAGE (Vdc)
V
DS
DS
Figure 4. V
= 10 Vdc
Figure 5. V = – 10 Vdc
GS
GS
50
– 100
45
40
35
30
25
20
– 90
– 80
– 70
– 60
– 50
– 40
T
= – 55
°
C
A
– 40°
C
C
T
= – 55°C
A
+ 25
°
– 40
°C
+ 85
°C
+ 25°C
+ 125
°
C
+ 85
°C
15
10
5.0
0
– 30
+ 125°C
– 20
– 10
0
0
2.0
4.0
6.0
8.0
10
12
14
16
18
20
0
– 2.0 – 4.0 – 6.0 – 8.0 – 10 – 12 – 14 – 16 – 18 – 20
, DRAIN–TO–SOURCE VOLTAGE (Vdc)
V
, DRAIN–TO–SOURCE VOLTAGE (Vdc)
V
DS
DS
Figure 6. V
GS
= 15 Vdc
Figure 7. V = – 15 Vdc
GS
These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.
MC14001B
14
MOTOROLA CMOS LOGIC DATA
TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)
VOLTAGE TRANSFER CHARACTERISTICS
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
5.0
10
8.0
6.0
4.0
3.0
2.0
1.0
0
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
4.0
2.0
0
0
1.0
2.0
3.0
4.0
5.0
0
2.0
4.0
6.0
V , INPUT VOLTAGE (Vdc)
in
8.0
10
V
, INPUT VOLTAGE (Vdc)
in
Figure 8. V
DD
= 5.0 Vdc
Figure 9. V = 10 Vdc
DD
16
14
12
10
DC NOISE MARGIN
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit val-
ues of the input values V and V for the output(s) to be at a
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
IL
IH
fixed voltage V are given in the Electrical Characteristics
O
8.0
6.0
table. V and V are presented graphically in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
IL IH
4.0
2.0
0
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
0
2.0
4.0
6.0
8.0
10
V
, INPUT VOLTAGE (Vdc)
in
Figure 10. V
DD
= 15 Vdc
V
V
V
V
DD
out
DD
out
V
V
O
O
V
V
O
O
V
V
V
V
DD
DD
0
0
in
in
V
V
V
V
IH
IL
IH
IL
V
= 0 VOLTS DC
SS
(a) Inverting Function
(b) Non–Inverting Function
Figure 11. DC Noise Immunity
MOTOROLA CMOS LOGIC DATA
MC14001B
15
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
1
9
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
7
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.280
0.200
0.020
0.065
MIN
19.05
6.23
3.94
0.39
1.40
MAX
19.94
7.11
5.08
0.50
1.65
0.750
0.245
0.155
0.015
0.055
–T–
SEATING
PLANE
K
F
G
J
K
0.100 BSC
2.54 BSC
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
G
N
M
D 14 PL
0.25 (0.010)
J 14 PL
0.25 (0.010)
L
M
N
0.300 BSC
7.62 BSC
0
15
0
15
M
S
T
A
M
S
T
B
0.020
0.040
0.51
1.01
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
ISSUE L
14
8
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
1
7
4. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
C
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.095
0.015
0.135
1.32
0.20
2.92
2.41
0.38
3.43
J
N
0.300 BSC
7.62 BSC
SEATING
PLANE
K
0
10
0
10
0.015
0.039
0.39
1.01
H
G
D
M
MC14001B
16
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE F
Y14.5M, 1982.
–A–
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
14
1
8
7
–B–
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
INCHES
G
DIM
A
B
C
D
F
G
J
K
M
P
MIN
8.55
3.80
1.35
0.35
0.40
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
C
0.337
0.150
0.054
0.014
0.016
–T–
SEATING
PLANE
J
M
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
M
S
S
0.25 (0.010)
T
B
A
5.80
0.25
6.20
0.50
0.228
0.010
0.244
0.019
R
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,
Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
are registered
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609
INTERNET: http://Design–NET.com
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MC14001B/D
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