MC141511AT2_技术文档

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MC141511A

LCD Segment Driver

CMOS

The MC141511A is an LCD frontplane (segment) driver chip which in-

cludes a 656 x 8 display RAM. The MC68HC05L10 microcomputer is the

companion device which provides the backplane drive.

The MC68HC05L10, together with one MC141511A, may be used to

drive a 5248-pixel muxed-by-41 display or a 4096-pixel muxed-by-32 dis-

play. Larger displays may be driven by adding additional MC141511A.

The MC141511A is a low operating voltage version of MC141511. It is

pin to pin compatible to the MC141511.

MC141511AT2

TAB

See Application Note AN-HK-13A.

• Operating Supply Voltage Range -

Control Logic, RAM, and Latch (VDD Pin): 2.7V to 5.5V

Frontplane Drivers (VLCD Pin): 4.5V to 13.2V

• Operating Temperature Range: -20 to 70˚C

• Direct Interface with the MC68HC05L10

MCC141511A

DIE

• 656 x 8 Static RAM (Display RAM)

• 128 LCD Segment (Frontplane) Driving Signals

• 10-Bit Address Bus and 8-Bit Bidirectional Data Bus

• Selectable 1:32 or 1:41 Multiplex Ratios

ORDERING INFORMATION

• Available in Two Forms:

MCC141511A

MC141511AT2

BARE DIE

TAB

TAB (Tape Automated Bonding), 161 Contacts, 10 sprocket hole device

Die Form Without Gold Bumps, 159 Pads with 4.5 mil Pads Pitch

BLOCK DIAGRAM

D0-D7

A0-A9

R/W

Display RAM

BPCLK

BPSYNC

PHI2

LCD DATA LATCH

CE

LRS

V

LCD

LEVEL

SELECTOR

V

MS

SEGH

SEGL

SS

SEGMENT DRIVER

VDD

DRIVER OUTPUTS

REV 3

10/96

MOTOROLA

MC141511A

3–19

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Figure 1A. TAB Package Contact Assignment (Copper View)

MC141511A

3–20

MOTOROLA

Figure 1B. Chip Pad Assignment

MOTOROLA

MC141511A

3–21

MAXIMUM RATINGS*(Voltages Referenced to V , T = 25˚C)

SS

A

This device contains circuitry to protect the inputs

against damage due to high static voltages or elec-

tric ﬁelds; however, it is advised that normal precau-

tions to be taken to avoid application of any voltage

higher than maximum rated voltages to this high

impedance circuit. For proper operation it is recom-

Symbol

Parameter

Value

Unit

V

Supply Voltage

Input Voltage

-0.3 to +7.0

V

DD

V

-0.3 to +14.0

LCD

V

-0.3 to V +0.3

V

in

SS

DD

mended that V and V

be constrained to the

in

out

I

Current Drain Per Pin Excluding V and V

25

mA

˚C

range V < or = (V or V ) < or = V . Reliability

of operation is enhanced if unused input are con-

nected to an appropriate logic voltage level (e.g.,

DD

SS

in

out

DD

T

Operating Temperature

-20 to +70

-65 to +150

A

T

Storage Temperature Range

stg

either V

or V ). Unused outputs must be left

SS

DD

* Maximum Ratings are those values beyond which damage to the device may occur. Functional open. This device may be light sensitive. Caution

operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description should be taken to avoid exposure of this device to

section.

any light source during normal operation. This

device is not radiation protected.

ELECTRICAL CHARACTERISTICS (Voltage Referenced to V , T = 25˚C)

SS

A

Symbol

Parameter

Min

Typ

Max

Unit

Operating Voltage

Supply Voltage

LCD Voltage

V

2.7

4.5

-

5.5

13.2

V

DD

V

LCD

Supply Current

at V =5.5V (PHI2=3.685MHz)

DD

I

ACCESS

DISPLAY

-

25

15

200

30

20

uA

AC

DP

STANDBY (Using D bit of the MCU)

SB

ON

at V =3.0V (PHI2=1.25MHz)

DD

I

ACCESS

DISPLAY

-

17

10

200

30

20

uA

AC

DP

STANDBY (Using D bit of the MCU)

SB

ON

I

Supply Current at V

-

200

uA

LCD

V

Output Voltage, Iload 10.0uA

-

0.1

-

V

OL

V

-0.1

OH

LCD

V

Output High Voltage (Iload=1.6mA)

Output Low Voltage (Iload=1.6mA)

Input High Voltage

D7-D0

V

-0.8

-

V

OH

DD

V

-

0.4

OL

V

R/W, BPCLK, BPSYNC, PHI2, MS, CE, D7-D0

0.8xV

V

DD

V

IH

DD

SS

V

Input Low Voltage

V

0.2xV

V

IL

DD

V

Data Retention

2.0

-

V

R

I

Input Current

BPCLK, BPSYNC, R/W, PHI2, D7-D0

-

1

8

uA

pF

in

C

Capacitance

R/W, BPCLK, BPSYNC, PHI2, MS, CE, D7-D0

in

I

Output current (V =4.5V, V =0.5V)

D7-D0

+20

-

uA

OH

OL

-20

OL

MC141511A

3–22

MOTOROLA

%, V_SS=0V)

±10

AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE (V_DD=3.0V

Symbol

Parameter

Min

400

100

70

Max

Unit

ns

t

Write Cycle Time

-

CYCW

t

Address Set Up Time

Address Hold Time

Chip Select Pulse Width

AS

AH

CS

t

260

100

200

15

t

Write to Chip Select Delay Time

Data Setup Time

WCS

DSW

t

Input Hold Time

H

t

Write Hold Time from Chip Select

70

WH

t

CYCW

CE

t

AS

t

AH

CS

PHI2

R/W

D0-7

t

WCS

t

WH

t

DSW

t

H

Data in Stable

Figure 2. Write Cycle Timing

MOTOROLA

MC141511A

3–23

AC ELECTRICAL CHARACTERISTICS - READ CYCLE (V_DD=3.0V

±10

%, V_SS=0V)

Symbol

Parameter

Min

400

100

-

Max

Unit

ns

t

READ Cycle Time

-

CYCR

t

Address Setup Time

Data Delay Time (Read)

Output Hold Time

-

350

-

ns

AS

t

ns

DDR

t

10

ns

H

t

CYCR

CE

t

AS

DDR

PHI2

D0-7

t

H

Data Valid

Figure 3. Read Cycle Timing

MC141511A

3–24

MOTOROLA

PIN DESCRIPTIONS

V

AND V

LRS

DD

SS

The main dc power is supplied to the part by these two connec-

tions. V is the most-positive supply level for logic circuitry and V is

The left-right selection input deﬁnes the direction of the segment

driver display. See Figure 8.

DD

SS

ground.

0 or Low = SEG 0 - 127

1 or High = SEG 127 - 0

V

LCD

This supply connection provides the voltage level for the segment

MS

drivers and is connected to the Vout connection of the MC68HC05L10

MCU.

This input selects how display RAM is addressed. Either a 1:32 or

1:41 multiplex ratio is possible.

0 or Low = 1:32 multiplex addressing

1 or High = 1:41 multiplex addressing

V

, V

SEGH

SEGL

These inputs are connected to V2 and V3 of an external voltage

divider. See Figure 4.

R/W

This input indicates which direction the data is to be passed over

the data bus. When R/W is low, the LCD driver reads data from the data

bus (D0-D7). When R/W is high, the LCD driver writes data to the data

bus (D0-D7). This input is connected to R/W of MC68HC05L10.

D0 - D7

These connections form an eight bit wide bidirectional data bus

which are connected to D0 through D7 of the MC68HC05L10.

A0 - A9

TEST

These inputs form a ten-bit wide address bus for addressing the

display RAM and are connected to A0 through A9 of the

MC68HC05L10.

Allowing this connection to ﬂoat or connecting it to VSS (GND)

places the part in the normal mode of operation. This input has an on-

chip pulldown resistance of approximately 1M .

BPSYNC

This input is a periodic active-low signal from the MC68HC05L10

for timing synchronization. BPSYNC is connected to FRM of

MC68HC05L10. See Figure 5.

BPCLK

This input may be run as high as 4.096 kHz (50% duty cycle). It

provides the required frame frequency for the segment driver. It is con-

nected to BPCLK of the MC68HC05L10. Thus, the frequency is usually

2.048 kHz. See Figure 5.

PHI2

This input is a bus clock input that is used for data bus timing syn-

chronization. It is connected to P02 of MC68HC05L10.

V3

V2

SEG0 - SEG127

These 128 output lines provide the frontplane drive signals to the

LCD panel. These outputs are forced to a low level while display is

turned off. Any unused segment outputs should be left open.

CE

This is an active low chip enable input and is connected to either

CS1, CS2, CS3 or CS4 of the MC68HC05L10.

Figure 4. External Voltage Divider

MOTOROLA

MC141511A

3–25

Figure 5. Relationship between BPSYNC and BPCLK

LRS = 0

LRS = 1

b0

b7

7E 7F

FE FF

01

02 03

00

80

81 82

83

100 101 102 103

180 181 182 183

17E 17F

1FE 1FF

27E 27F

A BYTE

200 201 202 203 204 205 206 207

280

28F

b0

b7

Figure 6. Display RAM Conﬁguration

MC141511A

3–26

MOTOROLA

OPERATION OF LCD DRIVER

INTRODUCTION

The LCD driver clock is derived from the 2.048KHz BPCLK

and frame frequency is 64 Hz for 1:32 multiplex and 50 Hz for 1:41

multiplex ratio. See Figure 5.

The MC141511 is LCD driver with selectable 1: 32 or 1: 41 multi-

plex ratios. The device consists of the following functional blocks as

shown in the Block Diagram.

CONTROL LOGIC - accepts the control signals from the MCU and

generates internal signals for synchronisation.

GENERATION OF LCD BIAS LEVELS

Refer to Figure 4. In order to obtain optimum contrast for LCD

panels, the bias levels should be selected such that

DISPLAY RAM - stores the display data. Each bit of the display

RAM has one-to-one correspondence to a pixel of the LCD. The display

RAM is in vertical byte oriented format as shown in Figure 6 and the

way the display RAM is addressed depends on the multiplexing mode of

the LCD (Figure 8). With reference to Figure 6, the display RAM also

contains 16 bytes of memory which is in horizontal format ($280-$28F).

The display RAM is addressed when backplane reaches 41.

LEVEL SELECTOR - consists of a switching circuit to select

appropriate voltage levels from an external voltage divider. See ﬁgure 4.

SEGMENT DRIVERS - provides the segment driving signals to the

LCD frontplane. See Figure 7.

BIAS = R/(4R+R1) = 1/( MUX + 1)

V1/VLCD = 1/( MUX + 1)

V2/VLCD = 2/( MUX + 1)

V3/VLCD = ( MUX - 1)/( MUX + 1)

V4/VLCD = MUX /( MUX + 1)

Example: Mux = 41 ----- Bias = 1: 7.4,

R = 10K, R1 = 33K, VR = 100K

Mux = 32 ----- Bias = 1: 6.6,

R = 10K, R1 = 27K, VR = 100K

MOTOROLA

MC141511A

3–27

2 FRAMES = 1/32 OR 1/25 SEC

BPSYNC

(SIGNAL

FROM MCU,

FRM PIN)

1

2

3

4

N

1

2

3

4

N

1

2

V

LCD

V4

V3

COM (1)

V2

V1

GND

V

LCD

V4

V3

COM (2)

V2

V1

GND

V

LCD

V4

V3

SEG (X)

V2

V1

GND

V

LCD

V4

V3

SEG (X)- COM (1)

V2

V1

GND

-V1

-V2

-V3

-V4

-V

LCD

1 FRAME

V

LCD

V4

V3

SEG (X)- COM (2)

V2

V1

GND

-V1

-V2

-V3

-V4

-V

LCD

N = 32, 41

Figure. 7 Driving Waveform of 1:5 Bias, 1:32 or 1:41 Multiplex Ratio

MC141511A

3–28

MOTOROLA

$1C0 - $1CF

$200 - $27F

$280 - $2FF

$200 - $27F

$280 - $2FF

$300 - $37F

$380 - $3FF

$300 - $37F

$380 - $3FF

$400 - $47F

1 : 32

1 : 41

ONE SLAVE

$1C0 - $1CF

$1D0 - $1DF

$480 - $4FF

$500 - $57F

$580 - $5FF

$600 - $67F

$680 - $6FF

$200 - $27F

$280 - $2FF

$300 - $37F

$380 - $3FF

$400 - $47F

$200 - $27F

$280 - $2FF

$300 - $37F

$380 - $3FF

$400 - $47F

$480 - $4FF

$500 - $57F

$580 - $5FF

1 : 32

1 : 41

TWO SLAVES

$200 - $27F

$280 - $2FF

$300 - $37F

$380 - $3FF

$400 - $47F

$480 - $4FF

$500 - $57F

$580 - $5FF

1 : 32

$600 - $67F

$680 - $6FF

$700 - $77F

$780 - $7FF

$1C0 - $1CF

$200 - $27F

$280 - $2FF

$300 - $37F

$380 - $3FF

$400 - $47F

$1D0 - $1DF

$480 - $4FF

$500 - $57F

$580 - $5FF

$600 - $67F

$680 - $6FF

1 : 41

$1E0 - $1EF

$700 - $77F

$780 - $7FF

$800 - $87F

$880 - $8FF

$900 - $97F

THREE SLAVES

$200 - $27F

$280 - $2FF

$300 - $37F

$380 - $3FF

$400 - $47F

$480 - $4FF

$500 - $57F

$580 - $5FF

$600 - $67F

$800 - $87F

$680 - $6FF

$700 - $77F

$780 - $7FF

$880 - $8FF

$900 - $97F

$980 - $9FF

1 : 32

$1C0 - $1CF

$1D0 - $1DF

$1E0 - $1EF

$1F0 - $1FF

$200 - $27F

$280 - $2FF

$300 - $37F

$380 - $3FF

$400 - $47F

$480 - $4FF

$500 - $57F

$580 - $5FF

$600 - $67F

$680 - $6FF

$700 - $77F

$780 - $7FF

$800 - $87F

$880 - $8FF

$900 - $97F

$980 - $9FF

$A00 - $A7F

$A80 - $AFF

$B00 - $B7F

$B80 - $BFF

1 : 41

FOUR SLAVES

Figure 8. Display RAM Mapping for 1:32 and 1:41 Multiplex Ratio

MOTOROLA

MC141511A

3–29

PACKAGE DIMENSIONS

MC141511AT2

TAB PACKAGE DIMENSION

(DO NOT SCALE THIS DRAWING)

COPPER

POLYIMIDE

Reference: 98ASL00183A

Issue “A” released on 04/15/96

MC141511A

3–30

MOTOROLA

MC141511AT2

TAB PACKAGE DIMENSION

(DO NOT SCALE THIS DRAWING)

Reference: 98ASL00183A

Issue “A” released on 04/15/96

MOTOROLA

MC141511A

3–31

MC141511AT2 TAB PACKAGE DIMENSION

Millimeters

Inches

Millimeters

Inches

Dim

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

S

T

U

V

W

X

Y

Z

AA

AB

AC

AD

Min

Max

47.55

35.175

29.007

4.78

2.011

2

Min

Max

Dim

AE

AF

AG

AH

AJ

Min

21.25

1.95

0.85

9.75

6.85

4.75

1.95

0.085

0.35

0.6

Max

21.35

2.05

0.95

9.85

6.95

4.85

2.05

0.095

0.45

0.7

Min

Max

46.55

34.775

28.947

4.72

1.951

1

1.8327

1.3691

1.1396

0.1858

0.0768

0.0394

-

0.2941

0.3559

0.0189

0.0496

0.1949

0.8051

0.3850

0.9116

0.8870

0.9094

0.7854

-

1.8720

1.3848

1.1420

0.1882

0.0792

0.0787

-

0.3334

0.3953

0.0205

0.0504

0.1988

0.8091

0.3890

0.9156

0.8905

0.9134

0.7894

0.0079

0.033

0.8366

0.0768

0.0335

0.3839

0.2697

0.1870

0.0768

0.0033

0.0014

0.0236

0.0295

0.0689

0.0134

0.0059

0.5394

0.0480

0.0177

0.4469

0.0047

0.4862

0.8406

0.0807

0.0374

0.3878

0.2736

0.1909

0.0807

0.0037

0.0177

0.0276

0.0335

0.0728

0.0142

0.0075

0.5630

0.0520

0.0217

0.4508

0.0087

0.4902

AK

AL

-

AM

AN

AP

AR

AS

AT

AU

AV

AW

AX

AY

AZ

BA

BB

BC

BD

BE

BF

BG

7.469

9.04

0.48

1.26

4.95

20.45

9.78

23.155

22.53

23.1

19.95

-

0.686

0.068

0.579

8.469

10.04

0.52

1.28

5.05

20.55

9.88

23.255

22.62

23.2

20.05

0.2

0.838

0.063

0.629

0.6

0.7

0.75

1.75

0.34

0.15

13.7

1.22

0.45

11.35

0.12

12.35

0.85

1.85

0.36

0.19

14.3

1.32

0.55

11.45

0.22

12.45

0.027

0.0027

0.0227

0.0024

0.0247

NOTES:

1. Dimensioning and tolerancing per ANSI Y14.5M, 1982.

2. Controlling dimension: millimeter

3. Copper thickness: 1 oz

Reference: 98ASL00183A

Issue “A” released on 04/15/96

MC141511A

3–32

MOTOROLA

MC141511AT2

Reference: 98ASL00183A

Issue “A” released on 04/15/96

MOTOROLA

MC141511A

3–33

MCC141511A PAD COORDINATES

(UNIT: um)

Name

VDD

TEST

X

Y

Name

X

Y

Name

SEG86

SEG85

SEG84

SEG83

SEG82

SEG81

SEG80

SEG79

SEG78

SEG77

SEG76

SEG75

SEG74

SEG73

SEG72

SEG71

SEG70

SEG69

SEG68

SEG67

SEG66

SEG65

SEG64

SEG63

SEG62

SEG61

SEG60

SEG59

SEG58

SEG57

SEG56

SEG55

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

SEG41

SEG40

X

Y

Name

X

Y

-1874.62 -2498.76

-1738.66 -2498.76

SEG126

SEG125

SEG124

SEG123

SEG122

SEG121

SEG120

SEG119

SEG118

SEG117

SEG116

SEG115

SEG114

SEG113

SEG112

SEG111

SEG110

SEG109

SEG108

SEG107

SEG106

SEG105

SEG104

SEG103

SEG102

SEG101

SEG100

SEG99

SEG98

SEG97

SEG96

SEG95

SEG94

SEG93

SEG92

SEG91

SEG90

SEG89

SEG88

SEG87

2728.66

-2233.88

-2119.48

-2005.08

-1890.68

-1776.28

-1661.88

-1547.48

-1433.08

-1318.68

-1204.28

-1089.88

-975.48

-861.08

-746.68

-632.28

-517.88

-403.48

-289.08

-174.68

-60.28

2630.76

2516.36

2401.96

2287.56

2173.16

2058.76

1944.36

1829.96

1715.56

1601.16

1486.76

1372.36

1257.96

1143.56

1029.16

914.76

800.36

685.96

571.56

457.16

342.76

228.36

113.96

-0.44

-114.84

-229.24

-343.64

-458.04

-572.44

-686.84

-801.24

-915.64

-1030.04

-1144.44

-1258.84

-1373.24

-1487.64

-1602.04

-1716.44

-1830.84

-1945.24

-2059.64

-2174.04

-2288.44

-2402.84

-2517.24

-2631.64

2432.32

SEG39

SEG38

SEG37

SEG36

SEG35

SEG34

SEG33

SEG32

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

SEG23

SEG22

SEG21

SEG20

SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

-2728.66

2227.72

2113.32

1998.92

1884.52

1770.12

1655.72

1541.32

1426.92

1312.52

1198.12

1083.72

969.32

854.92

740.52

626.12

511.72

397.32

282.92

168.52

54.12

BPSYNC -1611.06 -2498.76

BPCLK

MS

PHI2

CE

RW

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

LRS

D0

D1

D2

-1483.46 -2498.76

-1355.86 -2498.76

-1228.26 -2498.76

-1100.66 -2498.76

-973.06

-845.46

-717.86

-590.26

-462.66

-335.06

-207.46

-79.86

-2498.76

47.74

175.34

302.94

430.54

558.14

685.74

813.34

940.94

1068.54

1196.14

1323.74

1451.12

1578.94

1706.54

1834.14

1979.78

54.12

168.52

282.92

397.32

511.72

626.12

740.52

854.92

-60.28

-174.68

-289.08

-403.48

-517.88

-632.28

-746.68

-861.08

-975.48

D3

D4

D5

D6

D7

VLCD

VSEGH

VSEGL

VSS

DUMPAD 4 2111.78

DUMPAD 3 2239.38

DUMPAD 2 2366.98

DUMPAD 1 2494.58

969.32

1083.72

1198.12

1312.52

1426.92

1541.32

1655.72

1770.12

1884.52

1998.92

2113.32

2227.72

-2728.66 -1089.88

-2728.66 -1204.28

-2728.66 -1318.68

-2728.66 -1433.08

-2728.66 -1547.48

-2728.66 -1661.88

-2728.66 -1776.28

-2728.66 -1890.68

-2728.66 -2005.08

-2728.66 -2119.48

-2728.66 -2233.88

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

SEG127

2619.54

SEG0

Die Size

: 240.0 x 212.0 mil²

Pad Pitch : 4.5 mil

Note : 1 mil ~ 25.4 m

DUMPAD 1-4: Dummy pad without connections to internal circuitry

MC141511A

3–34

MOTOROLA

TYPICAL APPLICATIONS

128 X 41 SINGLE PANEL LCD SYSTEM WITH MC68HC05L10

LCD

POWER

SUPPLY

BP0-BP40

41 X 128 dots LCD Panel

Trimmer for

Contrast

Control

SEG0-SEG127

+5V

SEG0-SEG127

BP0-BP40

VDD

VSS

VDD

VSS

VLCD

VOUT

V4

VSEGH

VSEGL

BPCLK

BPSYNC

CE

BPCLK

FRM

V1

MC141511A

CS1

MC68HC05L10

MS

LRS

R/W

PO2

R/W

PHI2

10K

30K

10K

A0-A9 D0-D7

D0-D7 A0-A9

+5V

V4

V3

V2

V1

8

10

Note

: Full capability of MC68HC05L10 can control up to four MC141511A slave LCD drivers with 41 x 512 dots LCD panel.

Refer to application note, MC68HC05L10 AN ENHANCED VERSION OF L9 FOR HANDHELD EQUIPMENT APPLI-

CATIONS (AN-HK-13A) for more details.

MOTOROLA

MC141511A

3–35


型号：	MC141511AT2
厂家：	MOTOROLA
描述：	LCD Segment Driver CMOS LCD段驱动CMOS 驱动 CD
文件：	总17页 (文件大小：287K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC141511AT2 [MOTOROLA]

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