MC141543P [MOTOROLA]
Advanced Monitor On-Screen Display; 高级监视器屏幕显示型号: | MC141543P |
厂家: | MOTOROLA |
描述: | Advanced Monitor On-Screen Display |
文件: | 总14页 (文件大小:473K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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by MC141543/D
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC DIP
CASE 648
CMOS
The MC141543 is a high performance HCMOS device designed to interface
with a microcontroller unit to allow colored symbols or characters to be
displayed on a color monitor. The on–chip PLL allows both multi–system
operation and self–generation of system timing. It also minimizes the MCU’s
burden through its built–in 493 bytes RAM. By storing a full screen of data and
control information, this device has a capability to carry out ‘screen–refresh’
without MCU supervision.
ORDERING INFORMATION
MC141543P
Plastic DIP
PIN ASSIGNMENT
Since there is no spacing between characters, special graphics–oriented
characters can be generated by combining two or more character blocks. There
are three different resolutions that users can choose. By changing the number
of dots per horizontal line to 320 (CGA), 480 (EGA) or 640 (VGA), smaller
characters with higher resolution can be easily achieved.
Special functions such as character bordering or shadowing, multi–level
windows, double height and double width, and programmable vertical length of
character can also be incorporated. Furthermore, neither massive information
update nor extremely high data transmission rate are expected for normal on–
screen display operation, and serial protocols are implemented in lieu of any
parallel formats to achieve minimum pin count.
V
V
1
2
3
4
5
16
15
14
13
12
V
SS(A)
SS
VCO
R
RP
)
G
B
DD(A
HFLB
FBKG
HTONE/
PWMCK
SS
SDA(MOSI)
SCL(SCK)
6
7
8
11
10
9
VFLB
V
DD
•
Three Selectable Resolutions: 320 (CGA), 480 (EGA) or 640 (VGA) Dots
per Line
•
•
•
•
Fully Programmable Character Array of 15 Rows by 30 Columns
493 Bytes Direct Mapping Display RAM Architecture
Internal PLL Generates a Wide–Ranged System Clock
For High–End Monitor Application, Maximum Horizontal Frequency is
110 kHz (70.4 MHz Dot Clock at 640 Mode)
Programmable Vertical Height of Character to Meet Multi–Sync
Requirement
•
•
•
•
•
•
•
•
•
Programmable Vertical and Horizontal Positioning for Display Center
128 Characters and Graphic Symbols ROM (Mask ROM is Optional)
10 x 16 Dot Matrix Character
Character–by–Character Color Selection
A Maximum of Four Selectable Colors per Row
Double Character Height and Double Character Width
Character Bordering or Shadowing
Three Fully Programmable Background Windows with Overlapping
Capability
•
Provides a Clock Output Synchronous to the Incoming H Sync for External
PWM
•
•
M_BUS (IIC) Interface with Address $7A
Single Positive 5 V Supply
REV 2
2/97
TN97022700
Motorola, Inc. 1997
BLOCK DIAGRAM
5
8
7
8
6
SDA(MOSI)
SCL(SCK)
SS
8
54
15
WADDR
DATA
MEMORY AND DATA
MANAGEMENT
DATA RECEIVER
RFG
3
WCOLOR
AND
CONTROL
RA,CA,DA
8
26
Z
9
BUS ARBITRATION
LOGIC
MCLK
ADDRC
26
13
CCOLORS
AND SELECT
Y
ROW
BUFFER
NROW
CHS
4
CWS
10
R
VFLB
VERTICAL
CONTROL
CIRCUIT
6
CHS
VERD
CRADDR
CRS
5
8
CH
4
LP
CHARACTER ROMS
3
2
5
5
10
RP
CHAR
HORD
HORIZONTAL
CONTROL
AND PLL
VCO
HFLB
SC CCLK
10–BIT SHIFT
REGISTERS
4
V
DD(A)
54
WADDR
1
V
(A)
SS
BACKGROUND
GENERATOR
W
3
13
CCOLORS
AND SELECT
COLOR ENCODER
9
15
V
DD
WCOLOR
AND CONTROL
16
V
SS
15
14
13
12
11
MC141543
2
MOTOROLA
ABSOLUTE MAXIMUM RATINGS Voltage Referenced to V
SS
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised that
normal precautions be taken to avoid applica-
tions of any voltage higher than the maximum
rated voltages to this high impedance circuit.
For proper operation it is recommended that
Symbol
Characteristic
Supply Voltage
Value
Unit
V
V
DD
– 0.3 to + 7.0
V
in
Input Voltage
V
V
– 0.3 to
+ 0.3
V
SS
DD
Id
Current Drain per Pin Excluding V
and V
SS
25
mA
DD
V
and V
out
in out DD
be constrained to the range V
≤
SS
in
(V or V ) ≤ V . Unused inputs must always
be tied to an appropriate logic voltage level (e.g.,
Operating Temperature Range
Storage Temperature Range
0 to 85
– 65 to + 150
°C
°C
Ta
eitherV
open.
or V ). Unusedoutputsmustbeleft
DD
SS
T
stg
NOTE: MaximumRatingsarethosevaluesbeyondwhichdamagetothedevicemayoccur.
Functional operation should be restricted to the limits in the Electrical Characteris-
tics tables or Pin Description section.
AC ELECTRICAL CHARACTERISTICS (V
DD
= V
= 5.0 V, V
= V
= 0 V, T = 25°C, Voltage Referenced to V
)
SS
DD(A)
SS
SS(A)
A
Symbol
Characteristic
Min
Typ
Max
Unit
Output Signal (R, G, B, FBKG and HTONE/PWMCK) C
= 30 pF, see
load
Figure 1
Rise Time
Fall Time
t
t
—
—
—
—
6
6
ns
ns
r
f
F
HFLB Input Frequency
—
—
110
kHz
HFLB
DC CHARACTERISTICS V
= V
= 5.0 V ± 10%, V
= V
= 0 V, T = 25°C, Voltage Referenced to V
SS(A) A SS
DD
DD(A)
SS
Symbol
Characteristic
Min
– 0.8
DD
Typ
Max
Unit
V
OH
High Level Output Voltage
= – 5 mA
V
—
—
V
I
out
Low Level Output Voltage
= 5 mA
V
OL
—
—
V
+ 0.4
V
SS
I
out
Digital Input Voltage (Not Including SDA and SCL)
V
Logic Low
Logic High
—
—
—
0.3 V
—
V
V
IL
DD
DD
DD
V
IH
0.7 V
DD
DD
DD
Input Voltage of Pin SDA and SCL in SPI Mode
Logic Low
Logic High
V
—
—
—
0.3 V
—
V
V
IL
V
IH
0.7 V
Input Voltage of Pin SDA and SCL in M_BUS Mode
Logic Low
Logic High
V
—
—
—
0.3 V
—
V
V
IL
V
IH
0.7 V
I
High–Z Leakage Current (R, G, B and FBKG)
– 10
—
+ 10
µA
II
II
I
Input Current (Not Including RP, VCO, R, G, B, FBKG and
HTONE/PWMCK)
– 10
—
—
—
+ 10
+ 15
µA
I
Supply Current (No Load on Any Output)
mA
DD
90%
10%
tf
90%
10%
tr
Figure 1. Switching Characteristics
MC141543
3
MOTOROLA
VFLB (Pin 10)
PIN DESCRIPTIONS
Similar to Pin 5, this pin inputs a negative polarity vertical
synchronize signal pulse.
V
(Pin 1)
SS(A)
This pin provides the signal ground to the PLL circuitry.
Analog ground for PLL operation is separated from digital
ground for optimal performance.
HTONE/PWMCK (Pin 11)
This is a multiplexed pin. When the PWMCK_EN bit is
cleared after power–on or by the MCU, this pin is HTONE
and outputs a logic high during windowing except when
graphics or characters are being displayed. It is used to low-
er the external R, G, and B amplifiers’ gain to achieve a
transparent windowing effect. If the PWMCK_EN bit is set to
1 via M_BUS or SPI, this pin is changed to a mode–depen-
dent clock output with 50/50 duty cycle and is synchronous
with the input horizontal synchronization signal at Pin 5. The
frequency is dependent on the mode in which the AMOSD is
currently running. The exact frequencies in the different reso-
lution modes are described in Table 1.
VCO (Pin 2)
Pin 2 is a control voltage input to regulate an internal oscil-
lator frequency. See the Application Diagram for the applica-
tion values used.
RP (Pin 3)
An external RC network is used to bias an internal VCO to
resonate at the specific dot frequency. The maximum voltage
at Pin 3 should not exceed 3.5 V at any condition. See the
Application Diagram for the application values used.
Table 1. PWM CLK Frequency
V
(Pin 4)
DD(A)
Pin 4 is a positive 5 V supply for PLL circuitry. Analog pow-
er for PLL is separated from digital power for optimal perfor-
mance.
Resolution
320 dots/line
480 dots/line
640 dots/line
Frequency
Duty Cycle
50/50
32 x H
48 x H
64 x H
f
f
f
50/50
HFLB (Pin 5)
50/50
This pin inputs a negative polarity horizontal synchronize
signal pulse to phase lock an internal system clock gener-
ated by the on–chip VCO circuit.
NOTE: H
f is the frequency of the input H sync on Pin 5.
Typically, this clock is fed into an external pulse width mod-
ulation module as its clock source. Because of the synchro-
nization between PWM clock and H sync, a better
performance on the PWM controlled functions can be
achieved.
SS (Pin 6)
This input pin is part of the SPI serial interface. An active
low signal generated by the master device enables this slave
device to accept data. This pin should be pulled high to termi-
nate the SPI communication. If M_BUS is employed as the
FBKG (Pin 12)
serial interface, this pin should be tied to either V
or V
.
DD
SS
This pin outputs a logic high while displaying characters or
windows when the FBKGC bit in the frame control register is
0, and output a logic high only while displaying characters
when the FBKGC bit is 1. It is defaulted to high–impedance
state after power–on, or when there is no output. An external
10 kΩ resistor pulled low is recommended to avoid level tog-
gling caused by hand effect when there is no output.
SDA (MOSI) (Pin 7)
Data and control messages are being transmitted to this
chip from a host MCU via one of the two serial bus systems.
With either protocol, this wire is configured as a uni–direc-
tional data line. (Detailed description of these two protocols
will be discussed in the M_BUS and SPI sections).
SCL (SCK) (Pin 8)
B,G,R (Pins 13,14,15)
A separate synchronizing clock input from the transmitter
is required for either protocol. Data is read at the rising edge
of each clock signal.
AMOSD color output is TTL level RGB to the host monitor.
These three signals are active high output pins that are in a
high–impedance state when AMOSD is disabled.
V
(Pin 9)
V
(Pin 16)
DD
SS
This is the power pin for the digital logic of the chip.
This is the ground pin for the digital logic of the chip.
MC141543
4
MOTOROLA
SYSTEM DESCRIPTION
DATA BYTES
CHIP ADDRESS
SDA
SCL
ACK
MC141543 is a full–screen memory architecture. Refresh
is performed by the built–in circuitry after a screenful of dis-
play data has been loaded through the serial bus. Only
changes to the display data need to be input afterward.
Serial data, which includes screen mapping address, dis-
play information, and control messages, are transmitted via
one of the two serial buses: M_BUS or SPI (mask option).
These two sets of buses are multiplexed onto a single set of
wires. Standard parts offer M_BUS transmission.
ACK
1
2–7
8
9
STOP CONDITION
START CONDITION
Data is received from the serial port and stored by the
memory management circuit. Line data is stored in a row
buffer for display and refreshing. During this storing and re-
trieving cycle, bus arbitration logic patrols the internal traffic
to make sure that no crashes occur between the slower seri-
al bus receiver and the fast ‘screen–refresh’ circuitry. After
the full–screen display data is received through one of the
serial communication interfaces, the link can be terminated if
a change of the display is not required.
The bottom half of the block diagram contains the hard-
ware functions for the entire system. It performs all the
AMOSD functions such as programmable vertical length
(from 16 lines to 63 lines), display clock generation (which is
phase locked to the incoming horizontal sync signal at Pin 5
HFLB), bordering or shadowing, and multiple windowing.
Figure 2. M_BUS Format
DATA TRANSMISSION FORMATS
After the proper identification by the receiving device, a
data train of arbitrary length is transmitted from the master.
There are three transmission formats from (a) to (c) as stated
below. The data train in each sequence consists of row ad-
dress (R), column address (C), and display information (I), as
shown in Figure 3. In format (a), display information data
must be preceded with the corresponding row address and
column address. This format is particularly suitable for updat-
ing small amounts of data between different rows. However,
if the current information byte has the same row address as
the one before, format (b) is recommended.
COMMUNICATION PROTOCOLS
M_BUS Serial Communication
row addr
col addr
info
This is a two–wire serial communication link that is fully
compatible with the IIC bus system. It consists of an SDA bi-
directional data line and an SCL clock input line. Data is sent
from a transmitter (master) to a receiver (slave) via the SDA
line, and is synchronized with a transmitter clock on the SCL
line at the receiving end. The maximum data rate is limited to
100 kbps and the default chip address is $7A.
Figure 3. Data Packet
For a full–screen pattern change that requires a massive
information update, or during power–up, most of the row and
column addresses of either (a) or (b) formats will be consec-
utive. Therefore, a more efficient data transmission format (c)
should be applied. This sends the RAM starting row and col-
umn addresses once only, and then treats all subsequent
data as display information. The row and column addresses
will be automatically incremented internally for each display
information data from the starting location.
The data transmission formats are:
(a) R – > C – > I – > R – > C – > I – > . . . . . . . . .
(b) R – > C – > I – > C – > I – > C – > I. . . . . . .
(c) R – > C – > I – > I – > I – > . . . . . . . . . . . . .
Operating Procedure
Figure 2 shows the M_BUS transmission format. The mas-
ter initiates a transmission routine by generating a start
condition followed by a slave address byte. Once the ad-
dress is properly identified, the slave will respond with an ac-
knowledge signal by pulling the SDA line low during the ninth
SCL clock. Each data byte that follows must be eight bits
long, plus the acknowledge bit, for a total of nine bits. Ap-
propriate row and column address information and display
data can be downloaded sequentially in one of the three
transmission formats described in the Data Transmission
Formats section. In the cases of no acknowlege or comple-
tion of data transfer, the master will generate a stop condition
to terminate the transmission routine. Note that the OSD_EN
bit must be set after all the display information has been sent,
in order to activate the AMOSD circuitry of MC141543 so that
the received information can be displayed.
To differentiate the row and column addresses when trans-
ferring data from master, the MSB (most significant bit) is set,
as in Figure 4: ‘1’ to represent row, and ‘0’ for column ad-
dress. Furthermore, to distinguish the column address be-
tween formats (a), (b), and (c), the sixth bit of the column
address is set to ‘1’ which represents format (c), and ‘0’ for
format (a) or (b). However, there is some limitation on using
mixed formats during a single transmission. It is permissible
to change the format from (a) to (b), or from (a) to (c), or from
(b) to (a), but not from (c) back to (a) or (b).
MC141543
5
MOTOROLA
BIT
4
FORMAT
ADDRESS
ROW
next Row n+1 on the memory map will appear on the screen
as n+2 and n+3 row space, and so on. Hence, it is not neces-
sary to load a row of blank data to compensate for the double
row. The user should minimize excessive rows of data in
memory in order to avoid overrunning the limited amount of
row space on the screen.
7
1
0
0
6
X
0
1
5
3
2
1
0
X
X
X
X
D
D
D
D
D
D
D
D
D
D
D
D
a, b, c
a, b
c
D
COLUMN
COLUMN
D
X: don’t care
D: valid data
For rows with double width alphanumeric symbols, only
the data contained in the even numbered columns of the
memory map are shown. Odd numbered columns are
treated in the same manner as double height rows.
Figure 4. Row & Column Address Bit Patterns
MEMORY MANAGEMENT
COLUMN
0
27 28 29 30 31
Internal RAM is addressed with row and column (coln)
numbers in sequence. The spaces between Row 0 and Coln
0 to Row 14 and Coln 29 are called display registers, and
each contains a character ROM address corresponding to a
display location on the monitor screen. Every data row is
associated with two control registers, which are located at
Coln 30 and 31 of their respective rows, to control the char-
acter display format of that row. In addition, three window
control registers for each of the three windows, together with
three frame control registers, occupy the first 13 columns of
Row 15.
The user should handle the internal RAM address location
with care, especially those rows with double length alphanu-
meric symbols. For example, if Row n is destined to be
double height on the memory map, the data displayed on
screen Rows n and n+1 will be represented by the data con-
tained in the memory address of Row n only. The data of the
0
DISPLAY REGISTERS
14
0
2
3
5
6
8 9
12
15 WINDOW 1 WINDOW 2 WINDOW 3 FRAME CRTL REG
WINDOW AND FRAME CONTROL REGISTERS
Figure 5. Memory Map
MC141543
6
MOTOROLA
Bits 2–0 R, G and B — These bits control the color of Win-
dow 1. Window 1 occupies Columns 0–2 of Row 15; Window
2 occupies Columns 3–5; and Window 3 occupies Columns
6–8. Window 1 has the highest priority, and Window 3 the
least. If window overlapping occurs, the higher priority win-
dow will cover the lower one, and the higher priority color will
take over on the overlap window area. If the start address is
greater than the end address, this window will not be dis-
played.
REGISTERS
Display Register
7
6
5
4
3
2
1
0
CCS0
CRADDR
Bit 7 CCS0 — This bit defines a specific character color
out of the two preset colors. Color 1 is selected if this bit is
cleared, and Color 2 otherwise.
Bit 6–0 CRADDR — These seven bits address the 128
characters or symbols residing in the character ROM.
Window 2 Registers
Row 15 Coln 3
Row Control Registers
Coln 30
7
6
5
4
3
2
1
0
ROW START ADDR
ROW END ADDR
ROW 15
COLN 3
MSB
MSB
LSB
LSB
7
6
5
4
3
2
1
0
R1
G1
B1
R2
G2
B2
CHS
CWS
COLN 30
Row 15 Coln 4
Bits 7–2 — Color 1 is determined by R1, G1, and B1; Color
2 by R2, G2, and B2.
Bit 1 CHS — This bit determines the height of a display
symbol. When it is set, the symbol is displayed in double
height.
7
6
5
4
3
2
1
0
COL START ADDR
ROW 15
COLN 4
WEN
CCS1
MSB
LSB
Bit 2 WEN — This bit enables the background Window 2
generation when it is set.
Bit 1 CCS1 — This additional color select bit provides the
characters residing within Window 2 with two extra color
selections, making a total of four selections for that row.
Bit 0 CWS — Bit 0 is similar to Bit 1; when this bit is set, the
character is displayed in double width.
Coln 31
7
6
5
4
3
2
1
0
Row 15 Coln 5
R3
G3
B3
R4
G4
B4
COLN 31
7
6
5
4
3
2
1
0
ROW 15
COLN 5
COL END ADDR
R
G
B
Bits 7–2 — Color 3 is determined by R3, G3, and B3; Color
4 by R4, G4, and B4.
MSB
LSB
Window 1 Registers
Row 15 Coln 0
Bit 2–0 R, G and B — These bits control the color of Win-
dow 2. Window 1 occupies Columns 0–2 of Row 15; Window
2 occupies Columns 3–5; and Window 3 occupies Columns
6–8. Window 1 has the highest priority, and Window 3 the
least. If window overlapping occurs, the higher priority win-
dow will cover the lower one, and the higher priority color will
take over on the overlap window area. If the start address is
greater than the end address, this window will not be dis-
played.
7
6
5
4
3
2
1
0
ROW START ADDR
LSB
ROW END ADDR
ROW 15
COLN 0
LSB
MSB
MSB
Row 15 Coln 1
Window 3 Registers
Row 15 Coln 6
7
6
5
4
3
2
1
0
COL START ADDR
ROW 15
COLN 1
WEN
CCS1
MSB
LSB
7
6
5
4
3
2
1
0
ROW START ADDR
ROW END ADDR
Bit 2 WEN — This bit enables the background Window 1
generation when it is set.
ROW 15
COLN 6
MSB
LSB
LSB MSB
Bit 1 CCS1 — This additional color select bit provides the
characters residing within Window 1 with two extra color
selections, making a total of four selections for that row.
Row 15 Coln 7
7
6
5
4
3
2
1
0
Row 15 Coln 2
COL START ADDR
ROW 15
COLN 7
WEN CCS1
PWMCK_EN
MSB
LSB
7
6
5
4
3
2
1
0
ROW 15
COLN 2
Bit 2 WEN — This bit enables the background Window 3
generation when it is set.
COL END ADDR
R
G
B
MSB
LSB
MC141543
7
MOTOROLA
Bit 1 CCS1 — This additional color select bit provides the
characters residing within Window 3 with two extra color
selections, making a total of four selections for that row.
Bit 0 PWMCK_EN — When this bit is set to 1, the HTONE/
PWMCK pin will be switched to a clock output which is syn-
chronous to the H sync and used as an external PWM (pulse
width modulation) clock source. Refer to the pin description
of HTONE/PWMCK for more information. After power–on,
the default value is 0.
Frame Control Register Row 15 Coln 12
6
5
4
3
2
1
0
7
FBKGC
COLN 12
X64 X32B
OSD_EN
SHADOW
BSEN
Bit 7 OSD_EN — The OSD circuit is activated when this bit
is set.
Bit 6 BSEN — This bit enables the character bordering or
shadowing function when it is set.
Row 15 Coln 8
Bit 5 SHADOW — Characters with black–edge shadowing
are selected if this bit is set; otherwise bordering prevails.
Bit 4 X64, Bit 3 X32B — This bit determines the number of
dots per horizontal line. There are 320 dots per horizontal
line if Bit X32B is clear, which is also the default power–on
state. Otherwise, 480 dots per horizontal sync line is chosen
when Bit X64 is clear, and 640 dots per horizontal sync line
when Bit X64 is set to 1. Refer to Table 2 for details.
Bit 0 FBKGC — Bit 0 determines the configuration of the
FBKG output pin. When it is clear, the FBKG pin outputs high
while displaying characters or windows; otherwise, the
FBKG pin outputs high only while displaying characters.
7
6
5
4
3
2
1
0
ROW 15
COLN 8
COL END ADDR
R
G
B
MSB
LSB
Bit 2–0 R, G and B — These bits control the color of Win-
dow 3. Window 1 occupies Columns 0–2 of Row 15; Window
2 occupies Columns 3–5; and Window 3 occupies 6–8. Win-
dow 1 has the highest priority, and Window 3 the least. If win-
dow overlapping occurs, the higher priority window will cover
the lower one, and the higher priority color will take over on
the overlap window area. If the start address is greater than
the end address, this window will not be displayed.
Table 2. Resolution Setting
Frame Control Registers
(X64, X32B)
Dots / Line
Resolution
( 0 , 0 )
320
( 1 , 0 )
320
( 0 , 1 )
480
( 1 , 1 )
640
Frame Control Register Row 15 Coln 9
CGA
CGA
EGA
VGA
7
6
5
4
3
2
1
0
VERTD
COLN 9
LSB
MSB
0
1
2
Bit 7–0 VERTD — These eight bits define the vertical start-
ing position. There are a total of 256 steps, with an increment
of four horizontal lines per step for each field. The value can-
not be zero anytime, and the default value is 4.
3
4
5
6
7
16 lines
22 lines
8
9
10
11
12
13
14
15
Frame Control Register Row 15 Coln 10
7
6
5
4
3
2
1
0
Built–in font
(10x16 matrix)
when CH=16
Display character
when CH=22
HORD
COLN 10
MSB
LSB
Bit 6–0 HORD — These bits define the horizontal starting
position for character display. Seven bits give a total of 128
steps and each increment represents a five–dot shift to the
right on the monitor screen. The value cannot be zero any-
time, the default value is 15.
25 lines
34 lines
Frame Control Register Row 15 Coln 11
6
5
4
3
2
1
0
7
COLN 11
CH5 CH4 CH3 CH2
CH1 CH0
Display character
when CH=25
Display character
when CH=34
Bit 5–0 CH5–CH0 — These six bits determine the dis-
played character height. It is possible to have a proper char-
acter height by setting a value greater than or equal to 16 on
a different horizontal frequency monitor. Setting a value be-
low 16 will not have a predictable result. Figure 6 illustrates
how this chip expands the built–in character font to the de-
sired height.
Figure 6. Variable Character Height
An IBM PC program called “AMOSD Font Editor” was writ-
ten for MC141543 editing purposes. This program generates
a set of S–Record or Binary record for the desired display
patterns to be masked onto the character ROM of the
MC141543.
MC141543
8
MOTOROLA
vertical delay =
In order to have better character display within windows, it
is suggested that the designed character font be placed in
the center of the 10 x 16 matrix with equal space on all four
sides. The character $00 is predefined for blank characters,
the character $7F is predefined for full–filled characters, and
the character $7E is a random dot pattern reserved for test-
ing.
VERTD x 4 + 1 H scan lines
variable number of H scan lines
VFLB
In order to avoid submersion of displayed symbols or char-
acters into a background of comparable colors, a feature of
bordering which encircles all four sides, or shadowing which
encircles only the right and bottom sides of an individual dis-
play character, are provided. Figure 7 shows how a character
is jacketed differently. To make sure that a character is bor-
dered or shadowed correctly, at least one blank dot should
be reserved on each side of the character font.
0
0
1
2
1
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
10
11
12
13
14
15
Bordering
Shadowing
Figure 7. Character Bordering and Shadowing
Frame Format and Timing
Figure 8 illustrates the positions of all display characters
on the screen relative to the leading edge of horizontal and
vertical flyback signals. The shaded area indicates the area
outside “safe viewing area” for the display characters. Notice
that there are two components in the equations stated in Fig-
ure 8 for horizontal and vertical delays: fixed delays from the
leading edge of HFLB and VFLB signals, regardless of the
values of HORD and VERTD (47 dots + phase detection
pulse width) and one H scan line for horizontal and vertical
delays, respectively; and variable delays determined by the
values of HORD and VERTD. Refer to Frame Control Reg-
isters Coln 9 and 10 for the definitions of VERTD and
HORD.
Phase detection pulse width is a function of the external
charge–up resistor, which is the 330 kΩ resistor in a series
with 2 kΩ to VCO pin in the Application Diagram. Dot fre-
quency is determined by the equation H freq x 320 if Bit
X32B is clear, and H freq x 480 if Bit X32B is set to 1 and Bit
X64 is 0, and H freq x 640 if both Bit X32B and Bit X64 are
set to 1. For example, dot frequency is 10.24 MHz if H freq is
32 kHz while Bit X32B is 0. If Bit X32B is 1 and Bit X64 is 0,
the dot frequency will be 15.36 MHz (one and a half of the
original one). If Bit X32B is 1 and Bit X64 is also 1, the dot
frequency will be 20.48 MHz (double of the original one).
. . . . . .
Figure 8. Display Frame Format
When double character width is selected for a row, only the
even–numbered characters will be displayed, as shown in
Row 2. Notice that the total number of horizontal scan lines in
the display frame is variable, depending on the chosen char-
acter height of each row. Care should be taken while config-
uring each row character height so that the last horizontal
scan line in the display frame always comes out before the
leading edge of VFLB of the next frame, to avoid wrapping
display characters of the last few rows in the current frame
into the next frame. The number of display dots in a horizon-
tal scan line is always fixed at 300, regardless of row charac-
ter width and the setting of Bits X32B and X64.
MC141543
9
MOTOROLA
Although there are 30 character display registers that can
be programmed for each row, not every programmed charac-
ter can be shown on the screen in 320–dot resolution. Usual-
ly only 24 characters can be shown in this resolution at most.
This is induced by the time that is required to retrace the H
scan line. In other resolutions, 480–dot and 640–dot, a total
of 30 characters can be displayed on the screen if the hori-
zontal delay register is set properly.
Figure 9 illustrates the timing of all output signals as a
function of window and fast–blanking features. Line 3 of all
three characters is used to illustrate the timing signals. The
shaded area depicts the window area. The characters on the
left and right appear identical except for the FBKGC bit. The
middle character does not have a window as its background.
Notice that signal HTONE/PWMCK is active only in the win-
dow area. Timing of the signal FBKG depends on the config-
uration of the FBKGC bit. The configuration of the FBKGC bit
affects only the FBKG signal timing; it has no effect on the
timing of HTONE/PWMCK. Waveform ‘R, G, or B’, which is
the actual waveform at R, G, or B pin, is the logical OR of
waveform ‘character R, G, or B’ and waveform ‘window R, G,
or B’. ‘Character R, G, or B’ and ‘window R, G, or B’ are inter-
nal signals for illustration purpose only. Also notice that
HTONE/PWMCK has exactly the same waveform as ‘win-
dow R, G, or B’.
FONT
Icon Combination
MC141543 contains 128–character ROM. The user can
create an on–screen menu based on those characters and
icons. Refer to Table 3 for icon combinations. Addresses $00
and $7F are predefined characters, and $7E is for testing.
They cannot be modified in any AMOSDs.
Table 3. Combination Map
ICON
ROM ADDRESS (HEX)
Volume Bar I
01, 02, 03, 04, 05, 06, 4A
Volume Bar II
Volume Bar III
Size
48, 49, 57
47
4F, 50
51, 52
53, 54, 55, 56
58,59
Position
Geometry
Contrast
Brightness
Horizontal Position
Horizontal Sizing
Vertical Position
Vertical Sizing
Pin Cushion
Deguassing
Video Mode
Trapezoid
5A, 5B
5C, 5D
5E, 5F
60, 61
62, 63
64, 65
66, 67
68, 69
6A, 6B
6C, 6D
6E, 6F
70, 71
72, 73
74, 75
76,77
3
Parallelogram
Rotation
Color Select
Video Level
Input Select
Recall
Save
78, 79
7A, 7B
7C, 7D
07, 08
Left/Right Arrows
INC/DEC sign
Speaker
ROM CONTENT
Figure 9. Timing of Output Signals as a Function
of Window and FBKGC Bit Features
Figures 10 – 13 show the ROM content of MC141543.
Mask ROM is optional for custom parts.
MC141543
10
MOTOROLA
Figure 10. ROM Address ($00 – $1F)
Figure 11. ROM Address ($20 – $3F)
MC141543
11
MOTOROLA
Figure 12. ROM Address ($40 – $5F)
Figure 13. ROM Address ($60 – $7F)
MC141543
12
MOTOROLA
DESIGN CONSIDERATIONS
Distortion
•
•
•
The dc supply path for Pin 9 (V ) should be separated
DD
from other switching devices.
The LC filter should be connected between Pin 9 and Pin
4. Refer to the values used in the Application Diagram.
Motorola’s MC141543P has a built–in PLL for multi–sys-
tem application. Pin 2 voltage is dc–based for the internal
VCO in the PLL. When the input frequency (HFLB) to Pin 5
increases, the VCO frequency will increase accordingly. This
forces the PLL to a higher locked frequency output. The fre-
quency should be equal to 320/480/640 x HFLB (depending
on resolution). This is the pixel dot clock.
Biasing and filter networks should be connected to Pin 2
and Pin 3. Refer to the recommended networks in the Ap-
plication Diagram.
•
Two small capacitors can be connected between Pins 2
and 3, and between Pins 3 and 4.
Display distortion is caused by noise on Pin 2. Positive
noise increases the VCO frequency above normal. The cor-
responding scan line will be shorter accordingly. In contrast,
negative noise causes the scan line to be longer. The net re-
sult will be distortion on the display, especially on the right
hand side of the display window.
Jittering
Most display jittering is caused by HFLB jittering on Pin 5.
Care must be taken if the HFLB signal comes from the fly-
back transformer. A short path and shielded cable are rec-
ommended for a clean signal. A small capacitor can be
added between Pin 5 and Pin 16 to smooth the signal. Refer
to the value used in the Application Diagram.
In order to have distortion–free display, the following rec-
ommendations should be considered:
•
Only analog part grounds (Pin 2 to Pin 4) can be con-
nectedtoPin1(V ).V andothergroundsshouldbe
SS(A) SS
connected to PCB common ground. The V
Display Dancing
and V
SS(A)
grounds should be totally separated (i.e. V
SS
is float-
Most display dancing is caused by interference of the seri-
al bus. It can be avoided by adding series resistors to the se-
rial bus.
SS(A)
ing). Refer to the Application Diagram for the ground con-
nections.
APPLICATION DIAGRAM
V
CC
ANALOG GROUND – FLOATING
100 µH
0.1 µF
100 µF
1
9
V
V
DD
SS(A)
V
0.1
CC
0.01
µF
10
µF
µ
F
2 k
2 k
R
2
16
240
240
V
100
100
100
VCO
SS
R
3.3 k
0.047
µ
33 pF
33 pF
1 k
1 k
1 k
F
15
14
13
12
G
3
4
RP
V
330 k
330 pF
B
240
G
B
DD(A)
5
6
HFLB
HFLB
SS
MPS2369
FBKG
330 pF
AMOSD
100
FBKG
IIC(SPI) BUS
100
100
7
8
11
10
HTONE
SDA(MOSI)
SCL(SCK)
HTONE
ANALOG GROUND
DIGITAL GROUND
VFLB
VFLB
DIGITAL GROUND – COMMON GROUND
MC141543
13
MOTOROLA
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP
CASE 648–08
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
PLANE
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
M
S
0.020
0.040
0.51
1.01
M
M
T
A
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
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