MC141800BT [MOTOROLA]
LIQUID CRYSTAL DISPLAY DRIVER, UUC237, 70 MM, TAB-237;
| 型号： | MC141800BT |
| 厂家： | 
MOTOROLA |
| 描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC237, 70 MM, TAB-237 驱动 接口集成电路 |
| 文件： | 总43页 (文件大小：744K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC141800B
Product Preview
LCD Segment / Common Driver
with Controller
CMOS
MC141800B is a CMOS LCD Driver which consists of 193 high voltage
LCD driving signals to drive 128 Segment and 65 Common display. It has
6800-series parallel interface, IIC serial interface and Serial Peripheral inter-
face (SPI) capability for operating with general MCU. Besides the general
LCD driver features, it has on chip voltage and oscillator circuit such that
minimize external component in applications.
MC141800BT
TAB
•
•
•
•
•
•
•
•
•
Single Supply Operation DVDD, 1.8 V - 3.5 V
Separate Analog Power Supply AVDD, 2.4 V - 3.5 V
Maximum 16.5V LCD Driving Output Voltage
Low Current Stand-by Mode (<1uA)
On Chip Internal DC/DC Converter / External Power Supply
4X / 5X DC-DC Converter
MCC141800BZ
Gold bump die
Internal Regulator
Internal Switch-cap / Internal Buffer Divider
8 bit 6800-series Parallel Interface, 1MHz IIC Serial Interface and
Serial Peripheral Interface (SPI)
On chip Oscillator
Graphic Mode Operation
ORDERING INFORMATION
MC141800BT 70 mm TAB
MCC141800BZ Gold BumpDie
•
•
•
•
•
•
•
•
•
•
•
•
Vertical Scrolling
1 to 65 Selectable Multiplex Ratio
1 : 7 / 1 : 8 / 1:9 Bias Ratio Software Selectable
Re-mapping of Row and Column Drivers
16 level Internal Contrast Control
Built-in Temperature Compensation Circuit
Low Power Smart Icon Mode (128 icons, <20uA)
Wide pad pitch for power supply pins tailor for COG applications
Operating Temperature Range : -30°C to 85°C
Standard TAB Package, Gold Bump Die
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Motorola, Inc. 1999
REV 01
06/99
Com0 to
Com64
Seg0~Seg127
Level
Selector
HV Buffer Cell Level Shifter
VLL6
65 Bit
VLL2
VCC
VDC
128 Bit Latch
Latch
OSC1
OSC2
VR
VF
Display
Timing
Generator
LCD Driving
Voltage Generator
C1P
C3P
4x and 5x
DC/DC Converter,
Voltage Regulator,
Internal Divider,
Contrast Control,
Temperature
C1N
C3N
VLL3A
VLL3D
C+
GDDRAM
65 x 128Bits
Compensation
C-
AVDD
AVSS
Command Decoder
DVSS
DVDD
Command Interface
Parallel / Serial Interface
RES CE D/C S/P
R/W
CLK
D0~D7
MOTOROLA
MC141800B
2
MC141800BT PIN ASSIGNMENT
(COPPER VIEW)
*
VDC and DVDD are shorted for TAB package
COPPER
ENCAPSULANT
DIE
POLYIMIDE
Normal Design TAB
MOTOROLA
MC141800B
3
COM55
COM56
.
SEG0
SEG1
SEG2
.
COM63
COM64A
.
DVSS
DVSS
DVSS
DVSS
DVSS
AVDD
OSC2
AVSS
AVSS
VCC
.
.
.
.
.
.
.
.
.
.
.
.
VCC
VCC
VCC
Gold Bump Size :
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
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.
.
.
.
.
.
Input Pad, 60 x 60 (µm)
Output Pad, 42 x 100 (µm)
DVSS
OSC1
VLL6
VLL5
VLL4
VLL3D
VLL3C
VLL3B
VLL3A
VLL3
VLL2
C-
RESERVED AREA:
COORDINATES
AREA
X
Y
-3946.2
-3846.2
-3846.2
-3946.2
-532.2
-532.2
-632.2
-632.2
C+
C3N
C3N
C3N
C3P
C3P
C3P
C2N
C2N
C2N
C2P
C2P
C2P
C2P
C1N
C1N
C1N
C1N
C1P
C1P
C1P
C1P
VR
A
Dimensions in µm
Note:
1.Reserved area contains dummy bumps for IC bumping process
alignment.
2.No conductive tracks should be laid underneath reserved area to
avoid short circuit.
.
.
.
.
.
.
.
.
VF
DVDD
DVDD
DVDD
VDC
VDC
CE
.
.
CLK
CLK
D0
D0
D1
D2
D3
D4
D5
D6
D7
R/W
DVSS
DVSS
D/C
RES
S/P
DVDD
DVDD
VDC
VDC
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
AREA A
.
.
.
.
.
COM31
SEG126
SEG127
.
.
.
.
.
COM22
MOTOROLA
MC141800B
4
MAXIMUM RATINGS* (Voltages Referenced to V , T =25°C)
SS
A
This device contains circuitry to protect the inputs
against damage due to high static voltages or elec-
tric fields; however, it is advised that normal precau-
tions to be taken to avoid application of any voltage
higher than maximum rated voltages to this high
impedance circuit. For proper operation it is recom-
Symbol
Parameter
Value
Unit
AV ,DV
Supply Voltage
Input Voltage
-0.3 to +4.0
-0.3 to +5.5
V
V
DD
DD
V
DC
V
V
-0.3 to V +16.5
V
CC
SS
SS
mended that V and V
be constrained to the
in
out
V
V
-0.3 to V +0.3
V
in
SS
DD
range V < or = (V or V ) < or = V . Reliability
SS
in
out
DD
of operation is enhanced if unused input are con-
nected to an appropriate logic voltage level (e.g.,
I
Current Drain Per Pin Excluding V and
25
mA
DD
V
SS
either V
or V ). Unused outputs must be left
SS
DD
T
Operating Temperature
-30 to +85
°C
°C
A
open. This device may be light sensitive. Caution
should be taken to avoid exposure of this device to
any light source during normal operation. This
T
Storage Temperature Range
-65 to +150
stg
* Maximum Ratings are those values beyond which damage to the device may occur. Functional
operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descrip-
tion section.
device is not radiation protected. If external V
is
CC
and
used, make sure V
is supplied after DV
CC
DD
AV
DD
is stable.
V
= AV = DV (DV = V of Digital and DC/DC circuit, AV = V of Analogue Circuit)
SS
SS SS SS SS SS SS
DV = Digital and DC/DC circuit, AV Analogue Circuit
DD
DD
ELECTRICAL CHARACTERISTICS (Voltage Referenced to VSS, DVDD=1.8 to 3.5V, AVDD=2.4 to 3.5V, TA=25°C)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
DV
AV
Logic and DC/DC Circuit Supply Voltage Range (Absolute value referenced to V
Other Analog Circuit Supply Voltage Range
DC/DC Circuit Supply Voltage Range
)
SS
1.8
2.4
2.4
3.0
-
-
3.5
3.5
5.5
V
V
V
DD
DD
V
DC
I
Access Mode Supply Current Drain
(AV + DV Pins)
V
=3.0V, Internal DC/DC Converter On, 5X DC/DC
DD
-
-
-
-
-
500
250
180
120
200
600
300
220
140
TBD
µA
µA
µA
µA
nA
AC
Converter Enabled, R/W accessing, T =1MHz,
Osc. Freq.=50KHz, Display On.
DD
DD
cyc
I
Display Mode Supply Current Drain
(AV + DV Pins)
V
=3.0V, Internal DC/DC Converter On, 5X Con-
DD
DP1
DP2
DP3
verter Enabled, Buffer Divider Enable, R/W Halt,
Osc. Freq.=55KHz, Display On, VR=10.5V
DD
DD
I
I
Display Mode Supply Current Drain
(AV + DV Pins)
V
=3.0V, Internal DC/DC Converter On, 4X Con-
DD
verter Enabled, Buffer Divider Enable, R/W Halt,
Osc. Freq.=55KHz, Display On, VR=8V
DD
DD
Display Mode Supply Current Drain
(AV + DV Pins)
V
=3.0V, Internal DC/DC Converter On, 5X Con-
DD
verter Enabled, Switch-Cap Divider Enable, R/W
Halt, Osc. Freq.=55KHz, Display On, VR=10.5V
DD
DD
I
Standby Mode Supply Current Drain
(AV + DV Pins)
V
=3.0V, Display off, Oscillator Disabled, R/W halt.
SB
DD
DD
DD
I
Icon Mode Supply Current Drain
(AV + DV Pins)
V
=3.0V, Internal Oscillator, Oscillator Enabled,
-
10
15
TBD
16.5
µA
ICON
DD
Display On, Icon On, R/W halt, Freq.=55KHz.
DD
DD
V
LCD Driving Internal DC/DC Converter Output
(V Pin)
Display On, DC/DC Converter Enabled, Osc. Freq.=
50KHz, Internal Regulator Enabled, Divider
Enabled.
7
V
CC
CC
V
V
LCD Driving Voltage Input (V Pin)
7
15
-
16.5
V
V
LCD
CC
Internal DC/DC Converter Disabled.
Output High Voltage
(D0-D7, OSC2)
I
=100µA
0.9*DV
DV
DD
OH1
out
DD
V
Output Low Voltage
(D0-D7, OSC2)
I
=100µA
0
0
-
-
0.1*DV
V
V
V
OL1
out
DD
V
LCD Driving Voltage Source (V Pin)
Internal Regulator Enabled (V voltage depends on
Int/Ext Contrast Control )
-
V
-0.5
R1
R2
R
R
CC
V
LCD Driving Voltage Source (V Pin)
Internal Regulator Disable.
Floating
-
R
Note : All above parameter is tested under NO LOADING condition. For detailed testing condition, please refer to the Testing Condition figure on P.36.
MOTOROLA
MC141800B
5
ELECTRICAL CHARACTERISTICS (Voltage Referenced to VSS, DVDD=1.8 to 3.5V, AVDD=2.4 to 3.5V, TA=25°C)
Symbol
Parameter
Test Condition
Min
Typ
Max
DV
Unit
V
Input high voltage
0.8*DV
-
V
IH1
DD
DD
(RES, OSC2, CLK, CE, D0-D7,R/W, D/C, S/P,
OSC1)
V
Input Low voltage
0
-
0.2*DV
V
IL1
D
(RES, OSC2, CLK, CE, D0-D7, R/W, D/C, S/P,
OSC1)
D
V
V
V
V
V
LCD Display Voltage Output
Internal Divider Enabled, 1:9 bias ratio
Internal Divider Enabled, 1:8 bias ratio
Internal Divider Enabled, 1:7 bias ratio
External Voltage Generator, Internal Divider Disable
-
-
-
-
-
V
-
-
-
-
-
V
V
V
V
V
LL6
LL5
LL4
LL3
LL2
R
(V , V , V , V , V
Pins)
Pins)
Pins)
Pins)
8/9*V
7/9*V
2/9*V
1/9*V
LL6
LL5
LL4
LL3
LL2
R
R
R
R
V
V
V
V
V
LCD Display Voltage Output
(V , V , V , V , V
-
-
-
-
-
V
-
-
-
-
-
V
V
V
V
V
LL6
LL5
LL4
LL3
LL2
R
7/8*V
6/8*V
2/8*V
1/8*V
LL6
LL5
LL4
LL3
LL2
R
R
R
R
V
V
V
V
V
LCD Display Voltage Output
(V , V , V , V , V
-
-
-
-
-
V
-
-
-
-
-
V
V
V
V
V
LL6
LL5
LL4
LL3
LL2
R
6/7*V
5/7*V
2/7*V
1/7*V
LL6
LL5
LL4
LL3
LL2
R
R
R
R
V
V
V
V
V
LCD Display Voltage Input
(V , V , V , V , V
7
0
0
0
0
-
-
-
-
-
V
V
V
V
V
V
LL6
LL5
LL4
LL3
LL2
CC
LL6
LL5
LL4
LL3
V
V
V
V
LL6
LL5
LL4
LL3
LL2
I
Output High Current Source
(D0-D7, OSC2)
V
=V -0.4V
50
-
-
µA
OH
out
DD
I
Output Low Current Drain
(D0-D7, OSC2)
V
=0.4V
-
-
-50
µA
OL
out
I
Output Tri-state Current Drain Source
(D0-D7, OSC2)
-1
-1
-
-
1
1
µA
µA
OZ
I /I
Input Current
IL IH
(RES, OSC2, CLK, D0-D7, R/W, D/C , S/P,
OSC1)
C
Input Capacitance
-
5
7.5
pF
IN
(OSC1, OSC2, all logic pins)
MOTOROLA
MC141800B
6
ELECTRICAL CHARACTERISTICS (Voltage Referenced to VSS, DVDD=1.8 to 3.5V, AVDD=2.4 to 3.5V, TA=25°C)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
Temperature Coefficient Compensation for Diode
Reference TC circuit
PTC0
PTC1
PTC2
PTC3
Flat Temperature Coefficient
Temperature Coefficient 1*
Temperature Coefficient 2*
(TC1=0, TC0=0, Internal Regulator Disabled.)
(TC1=0, TC0=1, Internal Regulator Enabled.)
(TC1=1, TC0=0, Internal Regulator Enabled.)
(TC1=1, TC0=1, Internal Regulator Enabled.)
-
-
-
-
0.00
-0.18
-0.22
-0.35
-
-
-
-
%
%
%
%
Temperature Coefficient 3*
* The formula for the temperature coefficient is:
1
VR at 50°C - VR at 0°C
50°C - 0°C
TC(%)=
X
X100%
VR at 25°C
MOTOROLA
MC141800B
7
AC ELECTRICAL CHARACTERISTICS (TA=25°C, Voltage referenced to VSS, AVDD=DVDD=3V)
Symbol
Parameter
Oscillation Frequency of Display timing generator 60Hz Frame Frequency
Either External Clock Input or Internal Oscillator
Test Condition
Min
Typ
Max
Unit
F
45
55
60
KHz
OSC
Enabled
F
Frame Frequency
Graphic Display Mode, Normal Frequency Mode,
65 - 50 MUX
-
-
-
-
-
-
-
-
-
F
-
-
-
-
-
-
-
-
-
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
FRM
OSC
15 * MUX
F
Graphic Display Mode, Half Frequency Mode,
65 - 50 MUX
OSC
30 * MUX
F
Graphic Display Mode, Normal Frequency Mode,
49 - 34 MUX
OSC
23 * MUX
F
OSC
Graphic Display Mode, Half Frequency Mode,
49 - 34 MUX
46 * MUX
F
OSC
Graphic Display Mode, Normal Frequency Mode,
33 - 2 MUX
30 * MUX
F
OSC
Graphic Display Mode, Half Frequency Mode,
33 -2 MUX
60 * MUX
F
OSC
6-Phase Low Power Icon Mode, Normal Frequency
Mode
960
6-Phase Low Power Icon Mode, Half Frequency
Mode
F
OSC
1920
F
1024
4-Phase Low Power Icon Mode, Normal Frequency
Mode
OSC
F
2048
4-Phase Low Power Icon Mode, Half Frequency
Mode
-
-
Hz
OSC
OSC
OSC
Internal Oscillator Frequency with internal feed-
back resistor
Internal Oscillator Enabled, Set Internal feedback
resistor and the default osc frequency.
50
TBD
90
KHz
Internal Oscillation Frequency with different value Internal Oscillator Enabled, V within operation
See Figure 1 for the relationship
DD
of external feedback resistor
range
400k
350k
250k
200k
150k
100k
50k
Oscillation
Frequency
(Hz)
100k
500k
1.0M
1.5M
2.0M
Resistor Value between OSC1 and OSC2 (Ω)
Figure 1. Internal Oscillator Frequency Relationship with External Resistor Value
MOTOROLA
MC141800B
8
TABLE 3. Parallel Timing Characteristics for Write Cycle (TA=-30 to 85°C, DVDD=1.8 to 3.5V, VSS=0V)
Symbol
Parameter
Min
200
18
12
42
15
78
78
-
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Clock Cycle Time
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
Enable Low Pulse Width
Enable High Pulse Width
Rise Time
-
-
-
-
-
-
-
-
-
-
-
cycle
t
AS
AH
t
-
t
-
DSW
DHW
t
-
PW
-
EL
PW
-
EH
t
9
9
R
t
Fall Time
-
F
R/W
D/C
t
AS
t
AH
CE
t
cycle
PW
EL
CLK
PW
EH
t
t
R
F
t
DHW
D0-D7
(Write data to driver)
Valid Data
t
DSW
Figure 2. Parallel 6800-series Interface Timing Characteristics for Write Cycle
MOTOROLA
MC141800B
9
TABLE 4. Parallel Timing Characteristics for Read Cycle (TA=-30 to 85°C, DVDD=1.8 to 3.5V, VSS=0V)
Symbol
Parameter
Min
1000
90
60
250
76
-
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Clock Cycle Time
Address Setup Time
Address Hold Time
Read Data Setup Time
Read Data Hold Time
Access Time
-
-
-
-
-
-
-
-
-
-
-
cycle
t
-
AS
AH
t
-
-
t
DSR
DHR
t
-
t
250
-
ACC
PW
Enable Low Pulse Width
Enable High Pulse Width
Rise Time
390
390
-
EL
PW
-
EH
t
44
44
R
t
Fall Time
-
F
R/W
D/C
t
AS
t
AH
CE
t
cycle
PW
EL
CLK
PW
EH
t
t
R
F
t
t
t
DHR
DSR
ACC
D0-D7
(Read data from driver)
Valid Data
Figure 3. Parallel 6800-series Interface Timing Characteristics for Read Cycle
MOTOROLA
MC141800B
10
TABLE 5. IIC Serial Timing Characteristics (TA=-30 to 85°C, DVDD=1.8 to 3.5V, VSS=0V)
100kHz
400kHz
1MHz
Symbol
Parameter
Unit
Min
10
Typ
Max
Min
2.5
Typ
Max
Min
1
Typ
Max
t
Clock Cycle Time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
µs
µs
ns
ns
µs
cycle
t
Start condition Hold Time
Data Hold Time
4.0
150
250
4.7
0.6
0.3
150
50
HSTART
t
150
100
0.6
HD
t
Data Setup Time
SD
SSTART
t
Start condition Setup Time (Only relevant for a
repeated Start condition)
0.3
t
Stop condition Setup Time
4.0
-
-
-
-
-
-
1000
300
-
0.6
-
-
-
-
-
-
0.3
-
-
-
-
-
-
µs
ns
ns
µs
SSTOP
t
Rise Time for data and clock pin
Fall Time for data and clock pin
Idle Time before a new transmission can start
300
300
-
150
150
-
R
t
-
-
-
F
t
4.7
1.3
0.6
IDLE
((
))
((
))
SDA
CLK
t
IDLE
t
HD
t
SSTART
t
F
t
t
SSTOP
HSTART
t
SD
t
R
t
cycle
Figure 4. IIC Serial Interface Timing Characteristics
MOTOROLA
MC141800B
11
((
))
((
))
SDA
(From controller)
((
))
((
))
SDA
(From Driver)
((
((
))
1 - 8
))
1
2
3
4
5
6
7
8
9
P
9
CLK
S
ACK
STOP
CONDITION
ACK
A1
D/C
(A0)
R/W
DATA
ACK
A2
START
CONDITION
ADDRESS
Figure 5. IIC Serial Interface Input Protocol (Write Data to Driver)
((
))
((
))
SDA
(From controller)
((
))
((
))
SDA
(From Driver)
((
))
((
))
1 - 8
1
2
3
4
5
6
7
8
9
P
9
CLK
S
ACK
STOP
CONDITION
ACK
A1
D/C
(A0)
R/W
DATA
ACK
A2
START
CONDITION
ADDRESS
Figure 6. IIC Serial Interface Output Protocol (Read Data from Driver)
TABLE 6. SPI Timing Characteristics for Write Cycle (TA=-30 to 85°C, DVDD=1.8 to 3.5V, VSS=0V)
Symbol
Parameter
Min
200
100
100
20
20
76
76
-
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Clock Cycle Time
Enable Lead Time
Enable Lag Time
Write Data Setup Time
Write Data Hold Time
Clock Low Time
Clock High Time
Rise Time
-
-
-
-
-
-
-
-
-
-
-
cycle
t
LEAD
t
-
LAG
t
-
DSW
DHW
CLKL
t
-
t
-
t
-
CLKH
t
20
20
R
t
Fall Time
-
F
) )
( (
CE
t
LEAD
t
t
R
F
t
LAG
t
cyc
CLK
) )
( (
t
t
t
CLKH
CLKL
t
DSW
DHW
) )
( (
) )
( (
LSB
MSB
Din
Figure 7. SPI Timing Characteristics for Write Cycle
MOTOROLA
MC141800B
13
TABLE 7. SPI Timing Characteristics for Read Cycle (TA=-30 to 85°C, DVDD=1.8 to 3.5V, VSS=0V)
Symbol
Parameter
Min
1000
500
500
-
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Clock Cycle Time
Enable Lead Time
Enable Lag Time
Read Data Valid Time
Read Data Hold Time
Access Time
-
-
-
-
-
-
-
-
-
-
-
-
-
cycle
t
LEAD
t
-
LAG
DVR
DHR
t
240
-
t
20
-
t
120
240
-
ACC
t
Disable Time
-
DIS
t
Clock Low Time
Clock High Time
Rise Time
380
380
-
CLKL
t
-
CLKH
t
100
100
R
t
Fall Time
-
F
) )
( (
CE
t
LEAD
t
t
R
F
t
LAG
t
cyc
CLK
) )
( (
t
t
CLKL
CLKH
t
DVR
) )
( (
Dout
MSB
LSB
) )
( (
t
ACC
t
DHR
t
DIS
Figure 8. SPI Timing Characteristics for Read Cycle
MOTOROLA
MC141800B
14
For internal oscillator with internal feedback resistor mode, this pin
should be left open. The driver will be operating in its default fre-
quency.
For external oscillator mode, OSC2 will be the input pin of the
external clock source. No external resistor is required for this mode.
PIN DESCRIPTIONS
S/P (Serial / Parallel Interface)
This pin is an input pin. The pin is sampled out when reset to
determine what type of interface is desired. The S/P pin input HIGH
for serial interface while input LOW for parallel interface.
C+ and C-
D/C (Data / Command)
If internal switch-cap divider is enabled, a 0.1 µF capacitor is required
to connect between these two pins. Otherwise, leave these pins open.
If parallel interface is selected, this input pin acknowledges the
LCD driver the input at D0-D7 is data or command. Input High for
data while input Low for command. If serial interface is selected, float
this pin.
VLL3A, VLL3B, VLL3C, VLL3D
If internal switch-cap divider is enabled with 1:7 bias selected, a 0.1
µF capacitor to AVSS is required on VLL3A and VLL3B pins. If inter-
nal switch-cap divider is enabled with 1:8 bias selected, a 0.1 µF
capacitor to AVSS is required on VLL3A, VLL3B and VLL3C pins. If
internal switch-cap divider is enabled with 1:9 bias selected, a 0.1 µF
capacitor to AVSS is required on each pin. Otherwise, leave these
pins open.
CLK (Input Clock)
This pin is normal Low clock input. If parallel interface is selected,
data on D0-D7 are latched at the falling edge of CLK. If IIC serial
interface is selected, data on SDA is latched at the falling edge of
CLK. If SPI is selected, data on Din and Dout are latched at the fall-
ing edge of CLK.
VLL6 - VLL2
RES (Reset)
Group of voltage level pins for driving the LCD panel. They can
either be connected to external driving circuit for external bias supply
or connected internally to built-in divider circuit. If internal buffer
divider is selected, leave these pins float. If internal switch-cap divider
is selected, a 0.1 µF capacitor to AVSS is required to each pin.
A Low input pulse to this pin resets the internal status of the driver
(same as power on reset). The minimum pulse width is 10 µs.
CE (Chip Enable)
If parallel interface is selected, this input pin is used for chip
enable. If IIC serial interface is selected, leave this pin float and it will
be internally tied to VDD.
C1N and C1P, C2N and C2P, C3N and C3P
If Internal 5X DC/DC Converter is enabled, a 0.1 µF capacitor is
required to connect these three pair of pins. If Internal 4X DC/DC
Converter is enabled, a 0.1 µF capacitor is required to connect C1P
and C1N, C3P and C3N pair of pins.
D0 - D7 (Data)
This bi-directional bus is used for data / command transferring. If
parallel interface is selected, D0 - D7 are connected directly to MCU
for data transfer. When serial interface is selected, D7 (IIC/SPI) is an
input pin to determine which type of serial interface is desired. The
IIC/SPI pin HIGH indicates IIC interface is used. The IIC/SPI pin
LOW indicates SPI is used.
When IIC serial interface is selected, D0 (SDA) is connected
directly to MCU for data transfer, D1 (A1) and D2 (A2) are used to
define the 2 bit programmable address. The address of this device is
0111xyab where x, y, a, b represent A2, A1, D/C and R/W respec-
tively.
V
and V
F
R
This is a feedback path for the gain control (external contrast con-
trol) of VLL1 to VLL6. For adjusting the LCD driving voltage, it
requires a feedback resistor placed between V and V , a gain con-
R
F
trol resistor placed between V and AVSS, a 4.7µF capacitor placed
F
between V and AVSS. (Refer to the Application Circuit)
R
COM0-COM63, COM64A and COM64B (Row Drivers)
These pins provide the row driving signal to LCD panel. Output is
0V during display off. COM64A and COM64B are icon lines with same
signal output so as to provide the flexability to have the icon line on
top or bottom of panel, or both top and bottom of the panel. COM64A/
B also serves as the common driving signal in the icon mode.
COM64A/B is special design icon line (128 icons). There are some
special commands to program it separately (e.g. Set Icon Mask,
Smart Icon Mode, Low Power Icon Mode)
When SPI is selected, D3 (Din) is used to write data / command
from MCU to driver and D4 (Dout) is used to read data / command to
MCU from driver.
Note that if the serial interface is used, float other data pins.
R/W (Read / Write)
If parallel interface is selected, this is an input pin. To read the dis-
play data RAM or the internal status (Busy / Idle), pull this pin High.
The R/W input Low indicates a write operation to the display data
RAM or to the internal setup registers. If serial interface is selected,
let this pin float.
SEG0-SEG127 (Column Drivers)
These 128 pins provide LCD column driving signal to LCD panel.
They output 0V during display off.
OSC1 (Oscillator Input)
AVDD and AVSS
AVDD is the positive supply to the LCD driver analog circuit. AVSS
is ground.
The oscillator of this LCD driver could be set, by software com-
mand, to work in three different modes. These modes are, internal
oscillator with external feedback resistor mode, internal oscillator
with internat feedback resistor mode, and external oscillator mode.
For internal oscillator with external feedback resistor mode, a
resistor should be connected between OSC1 and OSC2. The value
of this resistor could be used to fine tune the operating frequency
(15kHz to 250kHz) of the driver.
VCC
For using the Internal DC/DC Converter, a 0.1 µF capacitor from
this pin to AVSS is required. It can also be an external bias input pin if
Internal DC/DC Converter is not used. Power is supplied to the LCD
Driving Level Selector and HV Buffer Cell with this pin. Normally, this
pin is not intended to be a power supply to other component.
For internal oscillator with internal feedback resister mode and
external oscillator mode, OSC1 should be left open.
DVDD and DVSS
DVDD is supplied to the digital control and DC/DC circuit of the
driver using these two pins. DVSS is ground.
OSC2 (Oscillator Output / External Oscillator Input)
For internal oscillator with external resistor mode, this is an output
for the internal low power RC oscillator circuit. A resistor should be
connected between OSC1 and OSC2.
MOTOROLA
MC141800B
15
VDC
If internal DC/DC converter is used for boosting-up the voltage
input to VDC pin, user should input a suitable voltage to this pin to
satisfy the requirements of LCD device being driven. The input volt-
age of this pin can be independent to the driver’s logic supply volt-
age. The boosted up voltage is used internally and supplied to the
LCD Driving Level Selector and HV Buffer Cells. For the system hav-
ing only one power supply voltage, this pin should be connected to
DVDD.
If internal DC/DC converter is not used, it is recommended to tie
this pin to DVDD to avoid floating.
To ensure having a stable LCD driving capability, a 0.1 µF capaci-
tor is highly recommended to connected from this pin to AVSS.
MOTOROLA
MC141800B
16
OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER
Description of Block Diagram Module
MPU Serial Peripheral Interface
Command Decoder and Command Interface
The SPI consists of 4 communication bus : data input pin Din, data
output pin Dout, clock pin CLK and chip enable pin CE. The CLK
input serves as data latch signal (clock).
Data is transferred serially with most significant bit first, least sig-
nificant bit last. During the communication, the controller must input
Low CE before data transactions and must stay low for the rest of the
transaction. By default, the LCD driver will receive command from
MCU. If messages on the data pin are data rather than command,
This module determines whether the input data is interpreted as
data or command. Data is directed to this module based upon the
input of the D/C pin. If D/C high, data is written to Graphic Display
Data RAM (GDDRAM). D/C low indicates that the input at D0-D7 is
interpreted as a Command.
Reset is of same function as Power ON Reset (POR). Once RES
received the reset pulse, all internal circuitry will back to its initial sta-
tus. Refer to Command Description section for more information.
MCU should send Data Direction command (0100100X ) to control
0
the data direction and then one more command to define the number
of data bytes will be read / write. After these two continuous com-
mands are send, the following messages will be data rather than
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D0-
D7), R/W, D/C, CE and the CLK. The R/W input High indicates a
read operation from the Graphic Display Data RAM (GDDRAM). R/
W input Low indicates a write operation to Display Data RAM or
Internal Command Registers depending on the status of D/C input.
The CLK input serves as data latch signal (clock). Refer to AC oper-
ation conditions and characteristics section for Parallel Interface Tim-
ing Description.
command. For read operation (X = 1), MCU reads a group of data
0
from LCD driver through Dout pin. For write opearion (X = 0), MCU
0
writes a group of data to the LCD driver through Din pin. Refer to AC
operation conditions and characteristics section for Serial Peripheral
Interface Timing Description.
MPU Serial IIC Interface
The IIC interface consists of two communication bus : data pin
SDA and clock pin CLK. The CLK input serves as data latch signal
(clock). Before communication begins, a start condition must be
setup on the bus by the controller. To establish a start condition, the
controller must pull the data pin low while the clock pin is high.
After the start condition has been established for t
, an
HSTART
eight-bit address should be sent. The six most significant bits of the
address (0111xy) are used to uniquely define devices on the bus, the
7th bit is used as a data / command control: if it is 0, then the signal
on SDA is interpreted as a command; if it is 1, then data SDA is writ-
ten to GDDRAM. The least significant bit is a data direction read /
write control; if it is 0, then the controller writes data / command to the
driver; if it is 1, then the controller reads data / command from LCD
driver.
Data is transferred with the most significant bit first. Each byte has
to be followed by an acknowledge bit. The transmitter releases the
SDA high during the acknowledge clock pulse. The receiver has to
pull down the SDA during the acknowledge clock pulse.
To end communication, a stop condition should be set up on the
bus. A low to high transition of data pin while the clock pin is high
defines a stop condition. However, if a master still wishes to commu-
nicate on the bus, another start condition and address can be gener-
ated without a stop condition. Refer to AC operation conditions and
characteristics section for IIC Serial Interface Timing Description.
MOTOROLA
MC141800B
17
Column address 7FH
Column address 00H
Com0
(Com63)
Row 0
LSB
Page 1
MSB
LSB
Page 2
MSB
LSB
Page 8
MSB
Com63
(Com0)
Row 63
Row 64 LSB
Page 9
Com64 (icon)
Note : The configuration in parentheses represent the remapping of Rows and Columns in 65 MUX mode
Figure 9. Graphic Display Data RAM (GDDRAM) Address Map
MOTOROLA
MC141800B
18
Graphic Display Data RAM (GDDRAM)
external oscillator mode.
The GDDRAM is a bit mapped static RAM holding the bit pattern
to be displayed. The size of the RAM is determined by number of
row times the number of column (128x65 = 8320 bits). Figure 9 is a
description of the GDDRAM address map. For mechanical flexibility,
re-mapping on both Segment and Common outputs are provided.
In internal oscillator with external feedback resistor mode, the
oscillator frequency can be selected in the range of 15kHz to 250kHz
by the external resistor.
For external oscillator mode, external clock source must be fed
to OSC2 and leave OSC1 open. Software command, 7B Hex should
be sent after power-on.
To enter internal oscillator with internal feedback resistor mode,
software command 7C Hex followed by 08 Hex should be sent after
power-on. OSC1 and OSC2 should be left open in this mode.
Display Timing Generator
This module is an on chip low power RC oscillator circuitry (Figure
10). It could be set, by software command, to work in three different
modes, respectively, internal oscillator with external feedback resis-
tor mode, internal oscillator with internal feedback resistor mode, and
Oscillator enable
Internal Oscillator selected
enable1 enable2
Oscillation Circuit
enable
Buffer
MC141800B
External component
OSC2
OSC1
Feedback for internal oscillator
For external CLK input
Figure 10. Oscillator Circuitry
LCD Driving Voltage Generator and Internal Regulator
This module generates the LCD voltage needed for display output.
It takes a single supply input and generate necessary bias voltages.
It consists of :
65 Bit Latch / 128 Bit Latch
A register carries the display signal information. First 65 bits are
Common driving signals and other 128 bits are Segment driving sig-
nals. Data will be input to the HV-buffer Cell for bumping up to the
required level.
1. 4X and 5X DC-DC Converter
To generate the Vcc voltage. 4X DC-DC converter is used for LCD
panel which needs lower driving voltage for less power consump-
tion. 5X DC-DC converter is used for LCD panel which needs
higher driving voltage.
2. Internal Regulator
Feedback gain control for initial LCD voltage. it can also be used
with external contrast control.
Level Selector
Level Selector is a control of the display synchronization. Display
voltage can be separated into two sets and used with different
cycles. Synchronization is important since it selects the required LCD
voltage level to the HV Buffer Cell for output signal voltage pump.
3. Internal Divider
Divide the LCD display voltage (V -V ) from the Internal Regu-
HV Buffer Cell (Level Shifter)
LL2 LL6
lator output. This is a low power consumption circuit which can
save the most display current compare with traditional resistor lad-
der method.
HV Buffer Cell works as a level shifter which translates the low
voltage output signal to the required driving voltage. The output is
shifted out with an internal FRM clock which comes from the Display
Timing Generator. The voltage levels are given by the level selector
which is synchronized with the internal M signal.
4. Contrast Control Block
Software control of 16 voltage levels of LCD voltage.
All blocks can be individually turned off if external voltage genera-
tor is employed
5. Bias Ratio Selection circuitry
Software control of 1/7, 1/8 and 1/9 bias ratio to match the charac-
teristic of LCD panel.
6. Self adjust temperature compensation circuitry
Provide 4 different compensation grade selections to satisfy the
various liquid crystal temperature grades. The grading can be
selected by software control.
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
LCD Panel Driving Waveform
The following is an example of how the Common and Segment
drivers may be connected to a LCD panel. The waveforms shown in
Figure 11a and 11b illustrate the desired multiplex scheme.
In the power-up state, the default waveform will be type “B”.
Figure 11a. LCD Display Example “0”
MOTOROLA
MC141800B
19
TIME SLOT
. . .
. . .
. . .
. . .
1
2
3
4
5
6
7
8
9
65 1
2
3
4
5
6
7
8
9
65 1
2
3
4
5
6
7
8
9
65 1
2
3
4
5
6
7
8
9
65
VLL6
VLL5
VLL4
VLL3
VLL2
COM0
COM1
SEG0
VLL1
VLL6
VLL5
VLL4
VLL3
VLL2
VLL1
VLL6
VLL5
VLL4
VLL3
VLL2
VLL1
VLL6
VLL5
VLL4
VLL3
VLL2
SEG1
VLL1
M
Figure 11b. LCD Driving Signal from MC141800B (Waveform B)
MOTOROLA
MC141800B
20
Command Description
Set Vertical Scroll Value
This command is used to scroll the screen vertically with scroll value 0
to 63. With scroll value equals to 0, Row 0 of GDDRAM is mapped to
Com0 and Row 1 through Row 63 are mapped to Com1 through
Com63 respectively. With scroll value equal to 1, Row 1 of GDDRAM is
mapped to Com0, then Row 2 through Row 63 will be mapped to Com1
through Com62 respectively and Row 0 will be mapped to Com63.
Com64 is not affected by this command. This command need a follow-
ing Command word define the scrolling value.
Set Display On / Off (Display Mode / Stand-by Mode)
The “Display On” command turns the LCD Common and Segment
outputs on. This command starts the conversion of data in GDDRAM to
necessary waveforms on the Common and Segment driving outputs.
The on-chip bias generator is also turned on by this command. (Note :
“Oscillator On” should be sent before “Display On”.)
The “Display Off” command turns the display off and the states of the
LCD driver are as follow during display off :
1. All the Common and Segment outputs are fixed at V
2. The bias Internal DC/DC Converter is turned off.
3. The RAM and content of all registers are retained.
4. IC will accept new commands and data.
(V ).
SS
LL1
Set Display Frequency
In half display frequency mode, the display frame frequency will be
halved. Also, the operation frequency of analog circuitries will be halved
for power saving purpose.
The Oscillator is not affected by this command.
Save / Restore Column Address
Set GDDRAM Column Address
Save Column Address command is used to save a copy of the Col-
umn Address of GDDRAM. Restore Column Address command
restores the copy obtained from the previous execution of saving col-
umn address. This instruction is very useful for writing full graphics
characters that are larger than 8 pixels vertically.
This command positions the address pointer on a column location.
The address can be set to location 00H-7FH (128 columns). The col-
umn address will be increased automatically after a read or write opera-
tion. Refer to “Address Increment Table” and command “Set GDDRAM
Page Address” for further information.
Set Column (Segment) Mapping
Set GDDRAM Page Address
This instruction selects the mapping of Display Data RAM to Seg-
ment drivers for mechanical flexibility. There are 2 mappings to select:
1. Column 0 - Column 127 of GDDRAM mapped to Seg0-Seg127
respectively;
2. Column 0 - Column 127 of GDDRAM mapped to Seg127-Seg0
respectively.
This command positions the row address to 1 of 9 possible positions
in GDDRAM. Refer to figure 9.
Master Clear GDDRAM
This command is used to clear the content of the Display Data RAM
to zero. Issue this command followed by a dummy write data. The RAM
for icon line will not be affected by this command.
COM64 will not be affected by this command. Detail information
please refer to section “Display Output Description”.
Master Clear Icon
Set Row (Common) Mapping
This command is used to clear the Icon Data RAM to zero. Set the
page pointer to icon page (page 9) and then issue this command fol-
lowed by a dummy write data. The icon RAM data will be set to zero.
This instruction selects the mapping of Display Data RAM to Com-
mon Drivers for mechanical flexibility. There are 2 selected mappings:
1. Row 0 - Row x of GDDRAM to Common 0 - Common x respec-
tively;
2. Row 0 - Row x of GDDRAM to Common x - Common 0 respec-
tively.
(x+2 is the multiplex ratio)
COM64 will not be affected by this command. See section “Display
Output Description” for related information.
Set Page Mask Register
After this command is issued, the following command will be written
to the Page Mask Register. Page Mask is an 8-bit register. Each bit rep-
resents one of the 8 pages : page mask bit 0 represents Page 1, page
mask bit 1 represents Page 2,...etc.
Page Mask Enable/Disable
Set MUX Ratio
When the Page Mask is enabled, the display of those pages, with
page mask bit set, will be cleared. Meanwhile, the data in the display
RAM is retained.
This command is used to select MUX ratio from 2 to 65. Row 64 (icon
line) is not affected by this command and it will be turned on for normal
display. This command contains two commands bytes, the first byte
informs the driver that the second byte will be the no. of mux ratio.
e.g. second byte = 0H to turn on Row 0 and 64 (2 MUX)
second byte = 63H to turn on Row 0 to 64 (65 MUX)
The unused common pins output non-scanning signals.
Icon Mask Enable/Disable
When the Icon Mask is enabled, the display of the icons will be
cleared. Meanwhile, the data in the icon display RAM is retained.
Set Display Mode
Set Bias Ratio 1:8 or 1:9
This command sets the bais of 1:8 or 1:9 bias for the divider output.
The selection should match the characteristic of LCD Panel.
This command switches the driver to full display mode or icon dis-
play mode. When low power icon mode is selected, only icon line
(driven by COM64) will be on while Row 0 to Row 63 will be off.
Besides, the DC-DC converter and the Internal Regulator will be dis-
abled. VCC & all VLLs pins cannot have external bias voltage supply.
When normal display mode is selected, Row 0 to Row 64 will be
turned on.
Set Oscillator On/Off
This command is used to turn the Oscillator on or off and should be
executed for both internal or external oscillator. The setting for this com-
mand is not affected by command “Set Display On/Off”. See command
“Ext/Int Oscillator” for more information.
MOTOROLA
MC141800B
21
Set Internal / External Oscillator
This command is used to select either internal or external oscillator.
When internal oscillator is selected, either use internal or external OSC
resistor for oscillator. When external oscillator is selected, clock input
should be fed to OSC2 and OSC1 should be left open.
Increase / Decrease Contrast Level
If the internal contrast control is enabled, this command can be used
to increase or decrease the contrast level within the 16 contrast levels.
The contrast level starts from lowest value after POR.
feed clock input signal to OSC2 and leave OSC1 open.
Set Contrast Level
This command is to select one of the 16 contrast levels when internal
contrast control circuitry is in use. After power-on reset, the contrast
level is lowest.
Set Internal DC/DC Converter On/Off
This command is used to select the Internal DC/DC Converter to
generate the V
from AV . Disable the Internal DC/DC Converter if
CC
DD
external Vcc is provided.
Set Smart Icon Mode
This command is to set 4-Phase or 6-Phase smart icon modes which
for lower VDD or higher Von of panel. Refer to Smart Icon Mode Output
Description for detail.
Set 4X / 5X DC/DC Converter
This command selects the usage of 4X or 5X Converter when the
Internal DC/DC Converter is enabled.
Set Data Direction
Set Temperature Coefficient
This command is used to select 4 different LCD driving voltage tem-
perature coefficients to match various liquid crystal temperature grades.
This command is used in SPI mode only. It will be two continuous
commands, the first byte control the data direction and inform the LCD
driver the second byte will be number of data bytes will be read / write.
After these two commands sending out, the following messages will be
data.
Set Internal Regulator On/Off
Choose bit option 0 to disable the on chip Internal Regulator. Choose
bit option 1 to enable Internal Regulator which consists of the internal
contrast control circuits.
Set Internal Divider Type & 1:7 Bias Ratio
There are two internal divider types: Buffer divider and switch-cap
divider. This command is used to select one of them. Besides, this com-
mand can be set 1:7 bias ratio as well.
Set Internal Divider On/Off
If the Internal Divider is disabled, external bias can be used for V
LL6
to V
If the Internal Divider is enabled, the internal circuit will gener-
Internal Oscillator Frequency Adjustment
LL2.
ated the 1:7, 1:8, or 1:9 bias driving voltage.
This command is used to set the internal feedback resistor and to
fine tune the oscillator frequency to suit for differenct LCD characteriza-
tion. During POR, external feedback resistor is used and this command
cannot adjust the oscillator frequency if external feedback resistor is
used.
Set Internal Contrast Control On/Off
This command is used to adjust the delta voltage of the bias volt-
ages. With bit option = 1, the software selection for delta bias voltage
control is enabled. With bit option = 0, internal contrast control is dis-
abled.
Power Adjustment
This command is used to adjust the current consumption of the driver
to suit for different LCD display characterization.
End of Command
This command is used as extra write end command follows the last
byte of data / command written. This command is not available if serial
mode is selected.
COMMAND TABLE
Bit Pattern
0000X X X X
Command
Comment
Set GDDRAM Page Address using X X X X as address bits.
Set GDDRAM Page Address
3
2
1
0
3 2 1 0
X X X X =0000 : page 1 (POR)
3
2 1 0
X X X X =0001 : page 2
3
2 1 0
X X X X =0010 : page 3
3
2 1 0
X X X X =0011 : page 4
3
2 1 0
X X X X =0100 : page 5
3
2 1 0
X X X X =0101 : page 6
3
2 1 0
X X X X =0110 : page 7
3
2 1 0
X X X X =0111 : page 8
3
2 1 0
X X X X =1000 : page 9
3
2 1 0
0001X X X X
2 1 0
Set Contrast Level
With R/W pin input low, set one of the 16 available values to the
internal contrast register, using X X X X as data bits.
3
3
2 1 0
The contrast register is reset to 0000 during POR.
0010000X
0010001X
Set 4X / 5X DC-DC Converter
Set Column (Segment) Mapping
X =0: enable 4X Converter (POR)
0
0
X =1: enable 5X Converter
0
X =0: Col0 to Seg0 (POR)
0
0
X =1: Col0 to Seg127
0
MOTOROLA
MC141800B
22
COMMAND TABLE
Bit Pattern
Command
Comment
X =0: Row0 to Com0 (POR)
0010010X
Set Row (Common) Mapping
0
0
X =1: Row0 to Com63
0
0010011X
Reserved
0
0010100X
Set Display on/off
X =0: display off (POR)
0
0
0
0
0
X =1: display on
0
0010101X
Set Internal DC/DC Converter On/Off
Set Internal Regulator On/Off
Set Internal Divider On/Off
X =0: Internal DC/DC Converter Off (POR)
0
X =1: Internal DC/DC Converter On
0
0010110X
0010111X
X =0: Internal Regulator Off(POR)
0
X =1: Internal Regulator On
0
X =0: Internal Divider Off (POR)
0
X =1: Internal Divider On
0
When an external bias network is preferred, the internal divider
should be disabled.
0011000X
Set Internal Contrast Control On/Off
Set Display Frequency
X =0: Internal Contrast Control Off (POR)
0
0
X =1: Internal Contrast Control On
0
Internal contrast circuits can be disabled if external contrast cir-
cuits is preferred.
0011001X
0011010X
00110110
00110111
X =0 : normal display frequency (POR)
0
0
0
X =1 : half display frequency
0
Save/Restore GDDRAM Column
Address
X =0 : restore address
0
X =1 : save address
0
Master Clear GDDRAM
Master clear GDDRAM (64 x 128 bits), row 64 (icon line) will not
be cleared
Master Clear Icons
Master Clear of Icons
0011100X
Set Bias Ratio 1:8 or 1:9
X =0 : bias = 1 : 9 (POR)
0
0
X =1 : bias = 1 : 8
0
0011101X
Reserved
X =0 : Normal Operation (POR)
0
0
X =1 : Reserved
0
(Note : Make sure to set X =0 during application)
0
00111100
00111101
End of Command
Reserved
Write command to identify the end of command frame
0011111X
Set Display Mode
X =0 : low power icon display mode
0
0
X =1 : normal display mode (POR)
0
01000000
01000001
01000010
Set MUX Ratio
next command will define no. of MUX, 00X X X X X X
5 4 3 2 1 0
no. of mux=00111111 upon POR (65 MUX)
Set Page Mask Register
Set Vertical Scroll Value
next command will be written to page mask register
page mask register=0 upon POR
next command will define the scrolling value by RAM,
00X X X X X X .
5
4 3 2 1 0
X X X X X X = 00000000 upon POR
5
4 3 2 1 0
01000011
0100010X
Reserved
Page Mask Enable/Disable
X =0 : disable page mask (POR)
0
0
X =1 : enable page mask
0
0100011X
Icon Mask Enable/Disable
X =0 : disable icon mask (POR)
0
0
X =1 : enable icon mask
0
0100100X
Set Data Direction
(for SPI mode only)
X =0 : Write Data (POR)
0
0
0
X =1 : Read Data
0
next command will define the total number of data bytes will be
read / write
e.g. no. of data bytes = 01111111 for 128 bytes
0100101X
Reserved
Reserved
Reserved
010011X X
1
0
010100X X
1
0
MOTOROLA
MC141800B
23
COMMAND TABLE
Bit Pattern
Command
Comment
01010100
Reserved
01010101
Set Internal Divider Type & 1:7 Bias
Ratio
Next command (byte) on 0010X X X 0 defines the bias ratio &
3 2 1
internal divider type.
X X X = 000 : 1:8/1:9 bias ratio and buffer as HV divider.
3
2 1
X X X = 001 : 1:8/1:9 bias ratio and switch-cap as HV divider.
3
2 1
X X X = 100 : 1:7 bias ratio and buffer as HV divider.
3
2 1
X X X = 101 : 1:7 bias ratio and switch-cap as HV divider.
3
2 1
0101011X
01011000
01011001
Reserved
0
Reserved
Power Adjustment
Next command (byte) 0000X X X X defines the power adjust-
3 2 1 0
ment levels. Enable one of the 16 power adjustment levels using
X X X X as data bits. During POR, X X X X = 0100.
3
2
1
0
3 2 1 0
Note : 0001X X X X - 1111X X X X (Reserved)
3
2
1
0
3 2 1 0
0101101X
Reserved
0
010111X X
Reserved
1
0
01100X X X
Reserved
2
1
0
0
0110100X
Set Smart Icon Mode
X =1 : 4-Phase Smart Icon
0
X =0 : 6-Phase Smart Icon (POR)
0
0110101X
Reserved
0
011011X X
Set Temperature Coefficient
X X =00 : 0.00% (POR)
1 0
1
0
X X =01 : -0.18%
1
0
X X =10 : -0.22%
1
0
X X =11 : -0.35%
1
0
0111000X
Increase / Decrease Contrast Level
X =0: Decrease by one level
0
0
X =1: Increase by one level
0
(Note: increment/decrement wraps round among the 16 contrast
levels. Start at the lowest level when POR.
011100X X
Reserved
Reserved
Reserved
1
0
011101X X
1
0
0111011X
X =0: Normal Operation (POR)
0
0
X =1: Reserved
0
(Note : Make sure to set X =0 during application)
0
0111100X
0111101X
Reserved
0
Set Internal / External Oscillator
X =0: Internal oscillator (POR)
0
0
X =1: External oscillator.
0
01111100
Internal Oscillator Frequency Adjust-
ment
Next command 0000X X X X defines
3 2 1 0
00000100 : External feedback resistor (POR)
00001X X X : Internal feedback resistor
2
1 0
Enable one of the 9 internal oscillator frequencies using X X X
1 0
2
as data bits to fine tune the oscillator frequency. During POR,
X X X = 100.
2
1 0
01111101
Reserved
0111111X
Set Oscillator On / Off
X = 0 : oscillator Off (POR)
0
0
X = 1 : oscillator On.
0
This is the master control for oscillator circuitry. This command
should be issued after the “Set Internal / External Oscillator” com-
mand.
1X X X X X X X
5 4 3 2 1 0
Set GDDRAM Column Address
Set GDDRAM Column Address.
6
Use X X X X X X X as address bits.
6
5 4 3 2 1 0
MOTOROLA
MC141800B
24
Data Read / Write
To read data from the GDDRAM, input High to R/W pin and D/C pin in parallel mode or pull high at the 7th and 8th bit of the address in IIC
serial mode or send Data Direction command 01001001 in SPI mode. Data is valid at the falling edge of CLK. And the GDDRAM column
address pointer will be increased by one automatically.
To write data to the GDDRAM, input Low to R/W pin and High to D/C pin in parallel mode or pull low 7th bit and high 8th bit of the address in
IIC serial mode or send Data Direction command 01001000 in SPI mode. Data is latched at the falling edge of CLK. And the GDDRAM column
address pointer will be increased by one automatically. If parallel interface is selected, End of command should be followed after all data are
send out.
No auto address pointer increment will be performed for the Dummy Write Data after Master Clear GDDRAM. (Refer to the “Commands
Required for R/W Actions on RAM” Table)
Address Increment Table (Automatic)
D/C
0
R/W
Comment
Address Increment
Remarks
0
1
0
1
Write Command
Read Command
Write Data
No
0
No (invalid mode)
*1
*2
1
Yes
Yes
1
Read Data
*3
Address Increment is done automatically data read write. The column address pointer of GDDRAM is affected.
Remarks : *1. Only data is read from RAM.
*2. If write data is issued after Command Clear RAM, Address increase is not applied.
*3. Column Address will wrap round when overflow.
Commands Required for R/W Actions on RAM
R/W Actions on RAMs
Commands Required
Read/Write Data from/to GDDRAM.
Set GDDRAM Page Address
Set GDDRAM Column Address
Read/Write Data
(0000X X X X )*
3 2 1 0
(1X X X X X X X )*
6
5 4 3 2 1 0
(X X X X X X X X )
7
6 5 4 3 2 1 0
End of command
(00111100)
Save/Restore GDDRAM Column Address.
Master Clear GDDRAM
Save/Restore GDDRAM Column Address
End of command
(0011010X )
(00111100)
0
Set Clear Page GDDRAM (64 x 128 bits)
Dummy Write Data
(00110110)
(X X X X X X X X )
7
6 5 4 3 2 1 0
Master Clear Icon RAM
Set GDDRAM Page Address to Page 9
Master Clear Icon RAM (128 bits, row 64)
Dummy Write Data
(00001000)
(00110111)
(X X X X X X X X )
7
6 5 4 3 2 1 0
* No need to resend the command again if it is set previously.
The read / write action to the Display Data RAM does not depend on the display mode. This means the user can change the RAM content
whether the target RAM content is being displayed.
MOTOROLA
MC141800B
25
Display Output Description
This is an example of output pattern on the LCD panel. Figure 12b and 12c are data map of GDDRAM and the output pattern on the LCD
display with different command enabled.
COM0
Content of GDDRAM
PAGE 1 Upper Nibble 5 A 5 A 5 A 5 A 5 A - - - - - - - - - 5 A 5 A 5 A 5 A 5 A
Lower Nibble 5 A 5 A 5 A 5 A 5 A - - - - - - - - - 5 A 5 A 5 A 5 A 5 A
PAGE 2 Upper Nibble 3 3 C C 3 3 C C 3 3 - - - - - - - - - C C 3 3 C C 3 3 C C
Lower Nibble 3 3 C C 3 3 C C 3 3 - - - - - - - - - C C 3 3 C C 3 3 C C
PAGE 3 Upper Nibble 0 0 0 0 F F F F 0 0 - - - - - - - - - F F 0 0 0 0 F F F F
Lower Nibble F F F F 0 0 0 0 F F - - - - - - - - - 0 0 F F F F 0 0 0 0
PAGE 4 Upper Nibble F F F F F F F F 0 0 - - - - - - - - - F F 0 0 0 0 0 0 0 0
Lower Nibble F F F F F F F F 0 0 - - - - - - - - - F F 0 0 0 0 0 0 0 0
.
.
.
.
.
.
.
.
.
COM63
COM64
PAGE 9 Upper Nibble 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - 0 0 0 0 0 0 0 0 0 0
Lower Nibble 0 0 0 1 1 1 0 0 0 0 - - - - - - - - - 0 0 0 0 1 1 1 0 0 0
SEG0
SEG127
Figure 12b
Figure 12a
Icon Line
Column remap disable
Row re-map disable
Column remap enable
Row re-map disable
Column remap disable
Row re-map enable
Figure 12c. Examples of LCD display with different command enabled
MOTOROLA
MC141800B
26
Power Up Sequence (Commands Required)
Command Required
Command
POR Status
Remarks
Set Display Frequency
Set Int/Ext Oscillator
Set Oscillator Enable
Set MUX Ratio
0011001X
0111101X
Normal
Internal
Disable
65 MUX
*1
*1
*1
*1
0
Remarks :
0
0111111X
0
01000000
00X X X X X X
4 3 2 1 0
*1 -- Required only if desired status dif-
fer from POR.
*2 -- Effective only if Internal Contrast
Control is enabled.
*3 -- Effective only if Internal Regulator
is enabled.
*4 -- Clear / Write specify data into
GDDRAM before Display On
5
Set Bias Ratio
0011100X
1/9 bias
4X Converter
Disable
Off
TC=0%
*1
*1
*1
*1
*1, *3
*1, *3
0
Set Internal DC/DC Converter
Set DC/DC Converter Enable
Set Internal Regulator On
Set Temperature Coefficient
Set Internal Contrast Control On
Set Contrast Level
0010000X
0010101X
0010110X
0
0
0
011011X X
1
0
0011000X
Off
0
0001X X X X
Contrast Level = 0
Buffer divider
*1, *2, *3
3
2 1 0
Set Divider Type
01010101
000000X 0
1
Set Internal Divider On
Set Segment Mapping
Set Common Mapping
Set Master Clear GDDRAM
0010111X
Off
*1
0
0010001X
0010010X
00110110
00111100
00110111
00111100
0010100X
00111100
Seg. 0 = Col. 0
Com. 0 = Row 0
0
0
*4
*4
Set Clear Icon
Set Display On
End of Command
Off
0
MOTOROLA
MC141800B
27
Smart Icon Mode Output Description
There are two driving schemes of Smart Icon Mode for panel with different Von/Voff or AVDD
1) 4 - Phase Smart Icon : 1/4 ~ 3/4
:
Voff > AVDD * sqrt (1/4)
Von < AVDD * sqrt (3/4)
2) 6 - Phase Smart Icon : 1/6 ~ 3/6
Voff > AVDD * sqrt (1/6)
Von < AVDD * sqrt (3/6)
DVDD
COM (non icon)
DVSS
DVDD
COM64(icon)
SEG(on)
DVSS
DVDD
DVSS
DVDD
SEG(off)
DVSS
Figure 13a. LCD Driving Signal for 4 - Phase Smart Icon Mode
DVDD
COM (non icon)
DVSS
DVDD
COM64(icon)
SEG(on)
DVSS
DVDD
DVSS
DVDD
SEG(off)
DVSS
Figure 13b. LCD Driving Signal for 6 - Phase Smart Icon Mode
MOTOROLA
MC141800B
28
Application Circuit:
All Internal Analog Circuitry disabled at IIC Serial mode operation
AV
DV
V
DD
DD
CC
0.1µF
0.1µF
V
VLL4 VLL5 VLL6 VCC
AVDD AVSS
VLL2 VLL3
DVSS DVDD VDC
DD
D1/A1
D2/A2
IIC Address
CMOS
R
R
MPU/MCU
COM0 to
COM64
CLK
SCL
SDA
To LCD
Panel
MC141800B
D0/SDA
RES
SEG0 to
SEG127
V
DD
D7/IIC/SPI
VLL3A
VLL3B
VLL3C
VLL3D
EPROM
S/P
C+
C-
C1P C1N
C3P C3N C2P C2N
VF VR
OSC2 OSC1
470KΩ
R3
RAM
Remark :
1. R3 can be omitted for external oscillator.
2. RES should be at a known state.
3. VLL2 - VLL6 can be left open for internal divider is enabled.
4. R/W, CE, D/C and D3-D6 can be opened for IIC serial mode.
5. D1/A1 and D2/A2 should be at predefined state for device identification.
t
r
6. R is pull up resistance, R <
(R = 300 ohm for 1MHz, assume C
= 200pF)
bus
2 * C
bus
7. AV should be greater than or equal to DV
.
DD
DD
8. VLL3A - D, C+ and C- can be left open for internal buffer divider is enabled.
9. The component values stated above are for reference only. Adjustment is needed for dif-
ferent applications.
MOTOROLA
MC141800B
29
IIC Serial mode operation with minimum external components
DV
AV
DD
V
CC
DD
0.1µF
0.1µF
V
DVSS DVDD
VLL4 VLL5 VLL6 VCC
AVDD AVSS
VLL2 VLL3
DD
VDC
D1/A1
D2/A2
IIC Address
CMOS
MPU/MCU
R
R
COM0 to
COM64
CLK
SCL
SDA
To LCD
Panel
MC141800B
D0/SDA
RES
SEG0 to
SEG127
V
DD
D7/IIC/SPI
VLL3A
VLL3B
VLL3C
VLL3D
EPROM
C1P C1N
S/P
C+ C-
C2P C2N
VF VR
C3P C3N
OSC2 OSC1
RAM
Remark :
1. RES should be at a known state.
2. R/W, CE, D/C and D3-D6 can be open for IIC serial mode.
3. D1/A1 and D2/A2 should be at predefined state for device identification.
t
r
4. R is pull up resistance, R <
(R = 300 ohm for 1MHz, assume C
= 200pF)
bus
2 * C
bus
5. AV should be greater than or equal to DV
.
DD
DD
6. External high voltage and internal divider are used.
7. VLL3A -D, C+ and C- can be left open for internal buffer divider is enabled.
8. The component values stated above are for reference only. Adjustment is needed for dif-
ferent applications.
MOTOROLA
MC141800B
30
All Internal Analog Circuitry enabled at IIC Serial mode operation
DV
AV
DD
DD
0.1µF
0.1µF
0.1µF
DVSS DVDD
VDC
AVDD AVSS
VCC VLL2
VLL5
VLL6
D1/A1
VLL3 VLL4
V
DD
IIC Address
D2/A2
CMOS
MPU/MCU
R
R
COM0 to
COM64
SCL
SDA
CLK
D0/SDA
To LCD
Panel
MC141800B
RES
SEG0 to
SEG127
V
DD
D7/IIC/SPI
VLL3A
VLL3B
VLL3C
VLL3D
EPROM
C+ C-
C2P C2N
OSC2 OSC1
VF
VR
C3P C3N
C1P C1N
S/P
470KΩ
2MΩ
0.1µF
R3
0.1µF
0.1µF
4.7µF
0.1µF
2MΩ
RAM
Remark :
1. R3 can be omitted for external oscillator.
2. VR and VF can be left open for Internal Regulator disable and Contrast Disable.
3. C3P and C3N can be left open for 4X Converter.
4. RES should be at a known state.
5. R/W, CE, D/C and D3-D6 can be open for IIC serial mode.
6. D1/A1 and D2/A2 should be at predefined state for device identification.
t
r
7. R is pull up resistance, R <
(R = 300 ohm for 1MHz, assume C
= 200pF)
bus
2 * C
bus
8. AV should be greater than or equal to DV
.
DD
DD
9. VLL3A - D, C+ and C- can be left open for internal buffer divider is enabled.
10. The component values stated above are for reference only. Adjustment is needed for dif-
ferent applications.
MOTOROLA
MC141800B
31
All Internal Analog Circuitry disabled at SPI Serial mode operation
DV
AV
DD
V
CC
DD
0.1µF
0.1µF
DVSS DVDD
VLL4 VLL5 VLL6 VCC
VDC
AVDD AVSS
VLL2 VLL3
CMOS
MPU/MCU
COM0 to
COM64
RES
To LCD
Panel
CE
CLK
SCK
MC141800B
SEG0 to
SEG127
MOSI
MISO
D3/Din
D4/Dout
VLL3A
D7/IIC/SPI
VLL3B
VLL3C
VLL3D
C1P C1N C+ C-
C2P C2N
S/P
VR
C3P C3N
EPROM
VF
OSC2 OSC1
V
DD
470KΩ
R3
RAM
Remark :
1. R3 can be omitted for external oscillator.
2. RES should be at a known state.
3. VLL2 - VLL6 can be left open for internal divider is enabled.
4. R/W, D/C, D0-2 and D5-6 can be open for SPI serial mode.
5. AV should be greater than or equal to DV
.
DD
DD
6. VLL3A - D, C+ and C- can be left open for internal buffer divider is enabled.
7. The component values stated above are for reference only. Adjustment is needed for dif-
ferent applications.
MOTOROLA
MC141800B
32
All Internal Analog Circuitry enabled at SPI Serial mode operation
DV
AV
DD
DD
0.1µF
0.1µF
0.1µF
DVSS DVDD VDC
AVDD AVSS
VCC VLL2
VLL5
VLL6
VLL3 VLL4
CMOS
MPU/MCU
COM0 to
COM64
RES
To LCD
Panel
CE
CLK
SCK
MC141800B
SEG0 to
SEG127
MOSI
MISO
D3/Din
D4/Dout
VLL3A
D7/IIC/SPI
VLL3B
VLL3C
VLL3D
C1P C1N C+ C-
S/P
C2P C2N
VF
VR
C3P C3N
EPROM
OSC2 OSC1
V
DD
470KΩ
2MΩ
0.1µF
0.1µF
0.1µF
R3
4.7µF
0.1µF
2MΩ
RAM
Remark :
1. R3 can be omitted for external oscillator.
2. VR and VF can be left open for Internal Regulator disable and Contrast Disable.
3. C3P and C3N can be left open for 4x converter.
4. RES should be at a known state.
5. R/W, D/C, D0-2 and D5-6 can be open for SPI serial mode.
6. AV should be greater than or equal to DV
.
DD
DD
7. VLL3A - D, C+ and C- can be left open for internal buffer divider is enabled.
8. The component values stated above are for reference only. Adjustment is needed for dif-
ferent applications.
MOTOROLA
MC141800B
33
All Internal Analog Circuitry disabled at 6800 Parallel mode operation
DV
AV
DD
V
CC
DD
0.1µF
0.1µF
DVSS DVDD VDC
RES
VLL4 VLL5 VLL6 VCC
AVDD AVSS
VLL2 VLL3
COM0 to
COM64
CMOS
CE
D/C
MPU/MCU
with 6800
Parallel
To LCD
Panel
R/W
CLK
MC141800B
SEG0 to
SEG127
Interface
VLL3A
D0 .. D7
VLL3B
VLL3C
VLL3D
EPROM
S/P
C+ C-
C1P C1N
C2P C2N
C3N
VF
VR
C3P
OSC2 OSC1
470KΩ
R3
RAM
Remark :
1. R3 can be omitted for external oscillator.
2. RES should be at a known state.
3. VLL2 - VLL6 can be left open for internal divider is enabled.
4. AV should be greater than or equal to DV
.
DD
DD
5. VLL3A - D, C+ and C- can be left open for internal buffer divider is enabled.
6. The component values stated above are for reference only. Adjustment is needed for dif-
ferent applications.
MOTOROLA
MC141800B
34
All Internal Analog Circuitry enabled at 6800 Parallel mode operation
DV
AV
DD
DD
0.1µF
0.1µF
0.1µF
DVSS DVDD
RES
AVDD AVSS
VCC VLL2
VLL5
VLL6
VDC
VLL3 VLL4
COM0 to
COM64
CMOS
CE
MPU/MCU
with 6800
Parallel
To LCD
Panel
D/C
R/W
CLK
MC141800B
SEG0 to
SEG127
Interface
VLL3A
D0 .. D7
S/P
VLL3B
VLL3C
VLL3D
C+ C-
C1P C1N
C2P C2N
OSC2 OSC1
VF
VR
C3P C3N
EPROM
470KΩ
2MΩ
0.1µF
0.1µF
0.1µF
R3
4.7µF
0.1µF
2MΩ
RAM
Remark :
1. R3 can be omitted for external oscillator.
2. VR and VF can be left open for Internal Regulator disable and Contrast Disable.
3. C3P and C3N can be left open for 4x converter.
4. RES should be at a known state.
5. AV should be greater than or equal to DV
.
DD
DD
6. VLL3A - D, C+ and C- can be left open for internal buffer divider is enabled.
7. The component values stated above are for reference only. Adjustment is needed for dif-
ferent applications.
MOTOROLA
MC141800B
35
Testing Condition:
AV
DV
DD
DD
0.1µF
0.1
µF
0.1µF
AVDD AVSS
VCC
VLL2
VLL5
VLL3 VLL4
VLL6
DVSS DVDD
RES
VDC
COM0 to
COM64
CE
D/C
No Load
R/W
CLK
Tester
MC141800B
SEG0 to
SEG127
S/P
VLL3A
VLL3B
VLL3C
VLL3D
D0 .. D7
C1P C1N
C+ C-
C2P C2N
VF
VR
C3P C3N
OSC2 OSC1
2.1MΩ
2MΩ
680pF
0.1µF
0.1µF
0.1µF
R3
4.7µF
540KΩ
MOTOROLA
MC141800B
36
PACKAGE DIMENSIONS
MC141800BT
TAB PACKAGE DIMENSION - 1
(DO NOT SCALE THIS DRAWING)
Reference : 98ASL30026A
Issue “0” released on 29 Jun 98
MOTOROLA
MC141800B
37
PACKAGE DIMENSIONS
MC141800BT
TAB PACKAGE DIMENSION - 2
(DO NOT SCALE THIS DRAWING)
Reference : 98ASL30026A
Issue “0” released on 29 Jun 98
MOTOROLA
MC141800B
38
MCC141800B Die Pin Assignment
Top Side Edge
Bottom Side Edge
MOTOROLA
MC141800B
39
Die Pad Coordinate of MC141800B (Bottom Side Edge)
Bottom Side Edge
Bottom Side Edge
Name X (um) Y (um)
51 C2P
Pad
Name
X (um)
Y (um)
Pad
1 COM(22) -4926.00 -817.60
38.40 -867.80
144.40 -867.80
250.40 -867.80
356.40 -867.80
462.40 -867.80
568.40 -867.80
674.40 -867.80
780.40 -867.80
886.40 -867.80
992.40 -867.80
1098.40 -867.80
1204.40 -867.80
1310.40 -867.80
1416.40 -867.80
1522.40 -867.80
1628.40 -867.80
1734.40 -867.80
1840.40 -867.80
1946.40 -867.80
2052.40 -867.80
2158.40 -867.80
2264.40 -867.80
2370.40 -867.80
2836.40 -867.80
2942.40 -867.80
3048.40 -867.80
3154.40 -867.80
3260.40 -867.80
3366.40 -867.80
3472.40 -867.80
3578.40 -867.80
3694.60 -867.80
3796.20 -867.80
3900.20 -867.80
4001.80 -867.80
4103.40 -867.80
2
COM(23) -4850.00 -817.60
COM (24) -4774.00 -817.60
COM(25) -4698.00 -817.60
COM(26) -4622.00 -817.60
COM(27) -4546.00 -817.60
COM(28) -4470.00 -817.60
COM(29) -4394.00 -817.60
COM(30) -4318.00 -817.60
52 C2N
53 C2N
54 C2N
55 C3P
3
4
5
6
56 C3P
7
57 C3P
8
9
58 C3N
59 C3N
60 C3N
61 C+
10 COM(31) -4242.00 -817.60
11 VDC
12 VDC
13 DVDD
14 DVDD
15 S/P
-4142.20 -867.80
-4040.60 -867.80
-3939.00 -867.80
-3837.40 -867.80
-3735.80 -867.80
-3634.20 -867.80
-3532.60 -867.80
-3431.00 -867.80
-3329.40 -867.80
-3227.80 -867.80
-3126.20 -867.80
-3024.60 -867.80
-2923.00 -867.80
-2821.40 -867.80
-2719.80 -867.80
-2618.20 -867.80
-2516.60 -867.80
-2415.00 -867.80
-2313.40 -867.80
-2211.80 -867.80
-2110.20 -867.80
-2008.60 -867.80
-1907.20 -867.80
-1805.40 -867.80
-1703.80 -867.80
-1602.20 -867.80
-1500.60 -867.80
-1399.00 -867.80
-1233.60 -867.80
-1127.60 -867.80
-1021.60 -867.80
-915.60 -867.80
-809.60 -867.80
-703.60 -867.80
-597.60 -867.80
-491.60 -867.80
-385.60 -867.80
-279.60 -867.80
-173.60 -867.80
-67.60 -867.80
62 C-
63 VLL2
64 VLL3
65 DUM 1
66 DUM 2
67 DUM 3
68 DUM 4
69 VLL4
70 VLL5
71 VLL6
16 RES
17 D/C
18 DVSS
19 DVSS
20 R/W
21 D7
22 D6
72 OSC1
73 DVSS
74 VCC
75 VCC
76 VCC
77 VCC
78 AVSS
79 AVSS
80 OSC2
81 AVDD
82 DVSS
83 DVSS
84 DVSS
85 DVSS
86 DVSS
23 D5
24 D4
25 D3
26 D2
27 D1
28 D0
29 D0
30 CLK
31 CLK
32 CE
33 VDC
34 VDC
35 DVDD
36 DVDD
37 DVDD
38 VF
87 COM 64Y 4242.00 -817.60
88 COM (63) 4318.00 -817.60
89 COM (62) 4394.00 -817.60
90 COM (61) 4470.00 -817.60
91 COM (60) 4546.00 -817.60
92 COM (59) 4622.00 -817.60
93 COM (58) 4698.00 -817.60
39 VR
40 C1P
41 C1P
42 C1P
43 C1P
44 C1N
45 C1N
46 C1N
47 C1N
48 C2P
49 C2P
50 C2P
94 COM (57)
4774.00 -817.60
95 COM (56) 4850.00 -817.60
96 COM (55) 4926.00 -817.60
MOTOROLA
MC141800B
40
Die Pad Coordinate of MC141800B (Right and Left Side Edge)
Right Side Edge
Left Side Edge
Name X (um)
248 COM (64) -5438.40
Pad
Name
X (um) Y (um)
Pad
Y (um)
835.40
759.40
97 COM (32) 5438.40
98 COM (33) 5438.40
835.40
759.40
249 COM (0)
250 COM (1)
251 COM (2)
252 COM (3)
253 COM (4)
254 COM (5)
255 COM (6)
256 COM (7)
257 COM (8)
258 COM (9)
-5438.40
99 COM (34) 5438.40 683.40
-5438.40 683.40
100 COM (35) 5438.40
101 COM (36) 5438.40
102 COM (37) 5438.40
103 COM (38) 5438.40
607.40
531.40
455.40
379.40
-5438.40
-5438.40
-5438.40
-5438.40
607.40
531.40
455.40
379.40
104 COM (39) 5438.40 303.40
-5438.40 303.40
105 COM (40) 5438.40
106 COM (41) 5438.40
107 COM (42) 5438.40
108 COM (43) 5438.40
109 COM (44) 5438.40
227.40
151.40
75.40
-5438.40
-5438.40
-5438.40
227.40
151.40
75.40
-0.60
259 COM (10) -5438.40
260 COM (11) -5438.40
-0.60
-76.60
-76.60
110 COM (45) 5438.40 -152.60
111 COM (46) 5438.40 -228.60
112 COM (47) 5438.40 -304.60
113 COM (48) 5438.40 -380.60
114 COM (49) 5438.40 -456.60
115 COM (50) 5438.40 -532.60
261 COM (12) -5438.40 -152.60
262 COM (13) -5438.40 -228.60
263 COM (14) -5438.40 -304.60
264 COM (15)
265 COM (16) -5438.40 -456.60
266 COM (17) -5438.40 -532.60
-5438.40 -380.60
116 COM (51)
5438.40 -608.60
267 COM (18) -5438.40 -608.60
268 COM (19) -5438.40 -684.60
269 COM (20) -5438.40 -760.60
270 COM (21) -5438.40 -836.60
117 COM (52) 5438.40 -684.60
118 COM (53) 5438.40 -760.60
119 COM (54) 5438.40 -836.60
MOTOROLA
MC141800B
41
Die Pad Coordinate of MC141800B (Top Side Edge)
Top Sid e Ed ge
To p Side Ed ge
Name X (um)
To p Sid e Ed ge
Name X (um)
Pad
Name
X (um) Y (um)
472 6.00 8 17.6 0
46 50.00 8 17.6 0
4 574.00 8 17.6 0
4 49 8.00 8 17.6 0
4 42 2.00 8 17.6 0
4 34 6.00 8 17.6 0
42 70.00 8 17.6 0
4 19 4.00 8 17.6 0
4 118.00 8 17.6 0
4 04 2.00 8 17.6 0
3 96 6.00 8 17.6 0
3 89 0.00 8 17.6 0
3 814.00 8 17.6 0
373 8.00 8 17.6 0
3 66 2.00 8 17.6 0
358 6.00 8 17.6 0
3510.00 8 17.6 0
3 43 4.00 8 17.6 0
33 58.00 8 17.6 0
3 28 2.00 8 17.6 0
3 20 6.00 8 17.6 0
3 13 0.00 8 17.6 0
30 54.00 8 17.6 0
29 78.00 8 17.6 0
2 90 2.00 8 17.6 0
2 8 2 6 .0 0 8 17.6 0
2 750.00 8 17.6 0
26 74.00 8 17.6 0
259 8.00 8 17.6 0
252 2.00 8 17.6 0
2 44 6.00 8 17.6 0
23 70.00 8 17.6 0
2 29 4.00 8 17.6 0
2 218.00 8 17.6 0
2 14 2.00 8 17.6 0
2 06 6.00 8 17.6 0
199 0.00 8 17.6 0
1914.00 8 17.6 0
183 8.00 8 17.6 0
176 2.00 8 17.6 0
168 6.00 8 17.6 0
16 10 .0 0 8 17.6 0
153 4.00 8 17.6 0
14 58.00 8 17.6 0
138 2.00 8 17.6 0
13 0 6 .0 0 8 17.6 0
12 3 0 .0 0 8 17.6 0
1154 .0 0 8 17.6 0
10 78.00 8 17.6 0
100 2.00 8 17.6 0
Pad
Y (um)
Pad
Y (um)
120 SEG(0)
121 SEG(1)
170 SEG(50)
171 SEG(51)
172 SEG(52)
173 SEG(53)
174 SEG(54)
175 SEG(55)
176 SEG(56)
177 SEG(57)
178 SEG(58)
179 SEG(59)
18 0 SEG(60 )
18 1 SEG(61)
18 2 SEG(62 )
18 3 SEG(63 )
18 4 SEG(64 )
185 SEG(65)
18 6 SEG(66 )
187 SEG(67)
18 8 SEG(68 )
18 9 SEG(69 )
19 0 SEG(70)
19 1 SEG(71)
19 2 SEG(72)
19 3 SEG(73)
19 4 SEG(74)
19 5 SEG(75)
19 6 SEG(76)
197 SEG(77)
19 8 SEG(78)
19 9 SEG(79)
20 0 SEG(80 )
20 1 SEG(81)
20 2 SEG(82 )
20 3 SEG(83 )
20 4 SEG(84 )
2 05 SEG(85)
20 6 SEG(86 )
2 07 SEG(87)
20 8 SEG(88 )
20 9 SEG(89 )
210 SEG(90 )
2 11 S E G ( 9 1)
212 SEG(92 )
213 SEG(93 )
214 SEG(94 )
2 15 S E G ( 9 5)
2 16 S E G ( 9 6 )
2 17 S E G ( 9 7)
218 SEG(98 )
219 SEG(99 )
9 26 .00 817.60
850 .00 817.60
774 .00 817.60
6 98 .00 817.60
6 22 .00 817.60
546 .00 817.60
470 .00 817.60
3 94 .00 817.60
3 18 .00 817.60
2 42 .00 817.60
166 .00 817.60
90 .00 817.60
220 SEG(10 0)
221 SEG(10 1)
222 SEG(10 2)
223 SEG(10 3)
224 SEG(10 4)
2 25 SEG(10 5)
226 SEG(10 6)
2 27 SEG(10 7)
228 SEG(10 8)
229 SEG(10 9)
230 SEG(110)
231 SEG(111)
232 SEG(112)
233 SEG(113)
234 SEG(114)
2 35 SEG(115)
236 SEG(116)
2 37 SEG(117)
238 SEG(118)
239 SEG(119)
240 SEG(12 0)
241 SEG(12 1)
242 SEG(12 2)
243 SEG(12 3)
244 SEG(12 4)
2 4 5 SEG(12 5)
246 SEG(12 6)
2 47 SEG(12 7)
-2 874 .00 817.60
-2 950 .00 817.60
-30 26 .00 817.60
-3102 .00 817.60
-3 178 .00 817.60
-3 254 .00 817.60
-33 30 .00 817.60
-34 06 .00 817.60
-34 82 .00 817.60
-3558 .00 817.60
-36 34 .00 817.60
-3 710 .00 817.60
-3 786 .00 817.60
-38 62 .00 817.60
-39 38 .00 817.60
-40 14 .00 817.60
-40 90 .00 817.60
-4166 .00 817.60
-42 42 .00 817.60
-43 18 .00 817.60
-43 94 .00 817.60
-4 470 .00 817.60
-4 546 .00 817.60
-46 22 .00 817.60
-46 98 .00 817.60
-4 774 .0 0 8 17.6 0
-4 850 .00 817.60
-49 26 .00 817.60
122 SEG(2)
123 SEG(3)
124 SEG(4)
12 5 SEG(5)
126 SEG(6)
12 7 SEG(7)
128 SEG(8)
129 SEG(9)
130 SEG(10)
131 SEG(11)
132 SEG(12)
133 SEG(13)
134 SEG(14)
13 5 SEG(15)
136 SEG(16)
13 7 SEG(17)
138 SEG(18)
139 SEG(19)
140 SEG(20)
141 SEG(21)
142 SEG(22)
143 SEG(23)
144 SEG(24)
14 5 SEG(2 5)
146 SEG(26)
14 7 SEG(27)
148 SEG(28)
149 SEG(29)
150 SEG(30)
151 SEG(31)
152 SEG(32)
153 SEG(33)
154 SEG(34)
155 SEG(35)
156 SEG(36)
157 SEG(37)
158 SEG(38)
159 SEG(39)
160 SEG(40)
16 1 S E G ( 4 1)
162 SEG(42)
163 SEG(43)
164 SEG(44)
16 5 S E G ( 4 5)
16 6 S E G ( 4 6 )
16 7 S E G ( 4 7)
168 SEG(48)
169 SEG(49)
14 .00 817.60
-62 .00 817.60
-138 .00 817.60
-2 14 .00 817.60
-2 90 .00 817.60
-3 66 .00 817.60
-4 42 .00 817.60
-518 .00 817.60
-594 .00 817.60
-670 .00 817.60
-746 .00 817.60
-8 22 .00 817.60
-8 98 .00 817.60
-9 74 .0 0 8 17.6 0
-1050 .00 817.60
-1126 .00 817.60
-12 02 .00 817.60
-1278 .00 817.60
-1354 .00 817.60
-14 30 .00 817.60
-1506 .00 817.60
-1582 .00 817.60
-1658 .00 817.60
-1734 .00 817.60
-18 10 .00 817.60
-18 86 .00 817.60
-19 62 .00 817.60
-20 38 .00 817.60
-2114 .00 817.60
- 2 19 0 .0 0 8 17.6 0
-22 66 .00 817.60
-23 42 .00 817.60
-24 18 .00 817.60
- 2 4 9 4 .0 0 8 17.6 0
- 2 570 .0 0 8 17.6 0
- 2 6 4 6 .0 0 8 17.6 0
-2 722 .00 817.60
-2 798 .00 817.60
MOTOROLA
MC141800B
42
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different appli-
cations. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not con-
vey any license under its patent rights nor the rights of others.Motorola products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of unintended
or unauthorized application, Buyer shall indemnify and hold Motorola and its offices, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with
such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MC14180B
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