MC141805T_技术文档

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MC141805

LCD Segment / Common Driver

with Controller

CMOS

MC141805 is a CMOS LCD Driver which consists of 3 annunciator outputs

and 129 high voltage LCD driving signals (17 common and 112 segment). It

has parallel interface capability for operating with general MCU. Besides the

general LCD driver features, it has on chip LCD bias voltage generator circuits

such that limited external component is required during application.

MC141805T

TAB

•

Single Supply Operation, 2.4 V - 3.5 V

Operating Temperature Range : -30˚C to 85˚C

Low Current Stand-by Mode (<500nA)

On Chip Bias DC/DC Converter

8 bit Parallel Interface

Graphic Mode Operation

On Chip 112x17 Graphic Display Data RAM

Master clear RAM

112 Segment Drivers, 17 Common Drivers

1/16, 1/17 Multiplex Ratio

1:5 bias ratio

Re-mapping of Row and Column Drivers

Three Stand Alone Annunciator (Static Icon) Driver Circuits

Low Power Icon Mode Driven by Com16 in Special Driving Scheme

Selectable LCD Drive Voltage Temperature Coefficients

16 level Internal Contrast Control

ORDERING INFORMATION

MC141805T

TAB

External Contrast Control

Standard TAB (Tape Automated Bonding) Package

REV 4

2/98

MOTOROLA

MC141805

3–337

Block Diagram

Annun0

to

Annun2

Com0 to

Com16

BP

Seg0~Seg111

Level

Selector

HV Buffer Cell Level Shifter

Annunciator

Control

Circuit

VLL6

17 Bit

VLL2

VCC

112 Bit Latch

Latch

VR

OSC1

OSC2

Display

Timing

Generator

VF

LCD Driving

DC/DC Converter

C2P

C2N

C1P

C1N

Tripler,

Doubler,

Voltage Regulator,

Voltage Divider,

Contrast Control,

Temperature

GDDRAM

17 x 112Bits

C+

Compensation

C-

AVDD

AVSS

Command Decoder

DVSS

DVDD

Command Interface

Parallel Interface

D/C

RES

CS (CLK)

R/W

D0~D7

MC141805

3–338

MOTOROLA

MC141805T PIN ASSIGNMENT

(COPPER VIEW)

MOTOROLA

MC141805

3–339

This device contains circuitry to protect the inputs

against damage due to high static voltages or elec-

tric ﬁelds; however, it is advised that normal precau-

tions to be taken to avoid application of any voltage

higher than maximum rated voltages to this high

impedance circuit. For proper operation it is recom-

MAXIMUM RATINGS* (Voltages Referenced to V , T =25˚C)

SS

A

Symbol

AV ,DV

Parameter

Value

Unit

Supply Voltage

Input Voltage

-0.3 to +4.0

V

DD

V

-0.3 to V +10.5

SS SS

CC

mended that V and V

be constrained to the

in

out

V

-0.3 to V +0.3

V

in

SS

DD

range V < or = (V or V ) < or = V . Reliability

SS

in

out

DD

I

Current Drain Per Pin Excluding V and V

25

mA

˚C

of operation is enhanced if unused input are con-

nected to an appropriate logic voltage level (e.g.,

DD

SS

T

Operating Temperature

-30 to +85

-65 to +150

A

either V

or V ). Unused outputs must be left

SS

DD

T

Storage Temperature Range

stg

open. This device may be light sensitive. Caution

should be taken to avoid exposure of this device to

any light source during normal operation. This

device is not radiation protected.

* Maximum Ratings are those values beyond which damage to the device may occur. Functional

operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descrip-

tion section.

V

= AV = DV (DV = V of Digital circuit, AV = V of Analogue Circuit)

SS

DD

SS SS SS SS SS SS

= AV = DV (DV = V of Digital circuit, AV = V of Analogue Circuit)

DD

ELECTRICAL CHARACTERISTICS (Voltage Referenced to V , V =2.4 to 3.5V, T =25˚C)

SS

DD

A

Symbol

Parameter

Test Condition

Min

2.4

0

Typ

3.15

200

Max

3.5

Unit

V

Supply Voltage (Absolute value Reference to Vss) (Absolute value referenced to V

)

SS

DD

AC

I

Access Mode Supply Current Drain

(AV + DV Pins)

V

=3.0V, Internal DC/DC Converter On, Tripler

Enabled, Annunciator On/Off, R/W accessing,

=1MHz, Osc. Freq.=38.4kHz, Display On, 1/17

300

µA

DD

T

cyc

Mux Ratio

=3.0V, Internal DC/DC Converter On, Tripler

Enabled,

I

Display Mode Supply Current Drain

(AV + DV Pins)

V

0

75

165

µA

DP

DD

Annunciator On/Off, R/W halt, Osc. Freq.=38.4kHz,

Display On, 1/17Mux Ratio

I

Standby Mode Supply Current Drain

(AV + DV Pins)

0

300

5

500

10

nA

SB1

SB2

V

=3.0V, Display off, Oscillator Disabled, R/W halt.

DD

Annunciator Mode Supply Current Drain

(AV + DV Pins)

µA

V

=3.0V, Annunciator Mode, Internal Oscillator,

DD

Oscillator Enabled, Display Off, R/W halt, Int Osc.

Freq.=38.4kHz.

I

Icon Mode Supply Current Drain

(AV + DV Pins)

0

-

25

µA

SB3

V =3.0V, Icon Mode, Internal Oscillator, Oscillator

DD

Enabled, Display On, R/W halt, Freq.=38.4kHz.

DD

V

LCD Driving DC/DC Converter Output

Display On, Internal DC/DC Converter Enabled,

Tripler Enabled, Osc. Freq.=38.4KHz,

Regulator Enabled, Divider Enabled.

CC1

(V Pin)

3*AV

2*AV

10.5

V

CC

DD

LCD Driving DC/DC Converter Output

Display On, Internal DC/DC Converter Enabled,

Doubler Enabled, Osc. Freq.=38.4KHz,

Regulator Enabled, Divider Enabled.

CC2

(V Pin)

-

7

CC

LCD Driving Voltage Input (V Pin)

Internal DC/DC Converter Disabled.

5

-

10.5

V

LCD

OH1

CC

V

Output High Voltage

I

=100µA

0.9*V

V

DD

out

DD

(D0-D7, Annun0-2, BP, OSC2)

V

Output Low Voltage

(D0-D7, Annun0-2, BP, OSC2)

I

=100µA

0

-

0.1*V

V

OL1

out

DD

V

LCD Driving Voltage Source (V Pin)

Regulator Enabled (V voltage depends on TC and

Int/Ext Contrast Control )

V

CC

R1

R2

R

V

LCD Driving Voltage Source (V Pin)

Regulator Disabled.

Floating

-

R

MC141805

3–340

MOTOROLA

ELECTRICAL CHARACTERISTICS (Voltage Referenced to V , V =2.4 to 3.5V, T =25˚C)

SS

DD

A

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

V

Input high voltage

0.8*V

-

V

DD

V

IH1

DD

(RES, OSC2, CS, D0-D7, R/W, D/C, OSC1)

V

Input Low voltage

0

-

0.2*V

V

IL1

DD

(RES, OSC2, CS, D0-D7, R/W, D/C, OSC1)

V

LCD Display Voltage Output

Voltage Divider Enabled

Voltage Divider Disable

-

V

-

V

LL6

LL5

LL4

LL3

LL2

R

(V , V , V , V , V

Pins)

0.8*V

0.6*V

0.4*V

0.2*V

LL6 LL5 LL4 LL3 LL2

R

V

LCD Display Voltage Input

5

0

-

V

LL6

LL5

LL4

LL3

LL2

CC

(V , V , V , V , V

V

LL6 LL5 LL4 LL3 LL2

LL6

LL5

LL4

LL3

I

Output High Current Source

OH

(D0-D7, Annun0-2, BP, OSC2)

V

=V -0.4V

50

-

µA

out

DD

I

Output Low Current Drain

(D0-D7, Annun0-2, BP, OSC2)

OL

OZ

V

=0.4V

-50

out

I

Output Tri-state Current Drain Source

(D0-D7, OSC2)

-1

-

1

µA

I /I

Input Current

IL IH

(RES, OSC2, CS, D0-D7, R/W, D/C , OSC1)

R

Channel resistance between LCD driving signal During Display on, 0.1V apply between two termi-

-

10

kΩ

on

pins (SEG and COM) and driving voltage input

pins (V to V

nals, VCC within operating voltage range

)

LL6

LL2

V

Memory Retention Voltage (DV

)

DD

Standby mode, retain all internal conﬁguration

and RAM data

2

-

V

SB

C

Input Capacitance

5

7.5

pF

IN

(OSC1, OSC2, all logic pins)

Temperature Coefﬁcient Compensation*

Flat Temperature Coefﬁcient

Temperature Coefﬁcient 1*

Temperature Coefﬁcient 2*

Temperature Coefﬁcient 3*

PTC0

PTC1

PTC2

PTC3

TC1=0, TC2=0, Voltage Regulator Disabled

TC1=0, TC2=1, Voltage Regulator Enabled

TC1=1, TC2=0, Voltage Regulator Enabled

TC1=1, TC2=1, Voltage Regulator Enabled

-

0.0

-

%

-0.18

-0.22

-0.35

V

Internal Contrast Control

Regulator Enabled, Internal Contrast control

Enabled. (16 Voltage Levels Controlled by Soft-

ware. Each level is typically 2.25% of the Regula-

tor Output Voltage. )

-

± 18

-

%

CN

(V Output Voltage)

R

*The formula for the temperature coefﬁcient (TC) is :

1

VR at 50˚C - VR at 0˚C

50˚C - 0˚C

TC(%)=

X

X100%

VR at 25˚C

MOTOROLA

MC141805

3–341

AC ELECTRICAL CHARACTERISTICS (T =25˚C, Voltage referenced to V , AV =DV =3V)

A

SS

Test Condition

Oscillation Frequency of Display timing generator 60Hz Frame Frequency

DD

Symbol

Parameter

Min

Typ

Max

Unit

F

-

38.4

-

kHz

OSC

Either External Clock Input or Internal Oscillator

Enabled

F

Backplane Frequency of Annunciator

(Annun0-3, BP)

50% duty cycle

Annunciator on, Fosc=38.4KHz

-

30

60

-

Hz

ANN

Frame Frequency

Graphic Display Mode,

FRM

Timing generator freq. = 38.4kHz

Icon Mode, Timing generator freq. = 38.4kHz

TBD

OSC

Internal Oscillation Frequency with different value Internal Oscillator Enabled, V within operation

See Figure 1 for the relationship

DD

of feedback resistor

range

Note : F

F

= F

/ 640

/ 1280

FRM

ANN

OSC

90k

70k

50k

30k

10k

Oscillation

Frequency

(Hz)

100k

500k

1.0M

Resistor Value between OSC1 and OSC2 (Ω)

Figure 1. Internal Oscillator Frequency Relationship with External Resistor Value

1.5M

2.0M

MC141805

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MOTOROLA

TABLE 2a. Parallel Timing Characteristics (Write Cycle) (T =-30 to 85˚C, DV =2.4 to 3.5V, V =0V)

A

DD

SS

Symbol

Parameter

Min

600

290

5

Typ

Max

Unit

ns

t

Enable Cycle Time

Enable Pulse Width

Address Setup Time

Data Setup Time

Data Hold Time

-

cycle

t

ns

EH

t

ns

AS

DS

DH

t

290

20

ns

t

ns

t

Address Hold Time

20

ns

AH

t

cycle

CS

t

EH

R/W

t

AH

AS

D/C

t

DS

DH

D0-D7

Valid Data

Fire 3.Timing Characteristics (Write Cycle)

MOTOROLA

MC141805

3–343

TABLE 2b. Parallel Timing Characteristics (Read Cycle) (T =-30 to 85˚C, DV =2.4 to 3.5V, V =0V)

A

DD

SS

Symbol

Parameter

Min

600

290

5

Typ

Max

Unit

ns

t

Enable Cycle Time

Enable Pulse Width

Address Setup Time

Data Setup Time

Data Hold Time

-

cycle

t

-

ns

EH

t

-

ns

AS

DS

DH

t

-

290

ns

t

5

-

ns

t

Address Hold Time

20

ns

AH

t

cycle

CS

t

EH

R/W

t

AH

AS

D/C

t

DS

DH

D0-D7

Valid Data

Figure 4.Timing Characteristics (Read Cycle)

MC141805

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MOTOROLA

C+ and C-

PIN DESCRIPTIONS

If internal divider circuit is enabled, a 0.1 µF capacitor is required

to connect between these two pins.

D/C (Data / Command)

This input pin tell the LCD driver the input at D0-D7 is data or com-

mand. Input High for data while input Low for command.

VR and VF

This is a feedback path for the gain control (external contrast con-

trol) of VLL1 to VLL6. For adjusting the LCD driving voltage, it

requires a feedback resistor placed between VR and VF, a gain con-

trol resistor placed between VF and AVSS, a 10 µF capacitor placed

between VR and AVSS. (Refer to the Application Circuit)

CS (CLK) (Input Clock)

This pin is normal Low clock input. Data on D0-D7 are latched at

the falling edge of CS.

RES (Reset)

An active Low pulse to this pin reset the internal status of the

driver (same as power on reset). The minimum pulse width is 10 µs.

COM0-COM16 (Row Drivers)

These pins provide the row driving signal to LCD panel. Output

is 0V during display off. COM16 also serves as the common driving

signal in the icon mode.

D0-D7 (Data)

This bi-directional bus is used for data / command transferring.

SEG0-SEG111 (Column Drivers)

These 112 pins provide LCD column driving signal to LCD panel.

They output 0V during display off.

R/W (Read / Write)

This is an input pin. To read the display data RAM or the internal

status (Busy / Idle), pull this pin High. The R/W input Low indicates a

write operation to the display data RAM or to the internal setup regis-

ters.

BP (Annunciator Backplane)

This pin combines with Annun0-Annun2 pins to form annunciator

driving part. When the annunciator circuit is enabled, it will output

square wave of 30 Hz. It outputs low when oscillator is disabled.

OSC1 (Oscillator Input)

For internal oscillator mode, this is an input for the internal low

power RC oscillator circuit. In this mode, an external resistor of cer-

tain value should be connected between the OSC1 and OSC2 pins

for a range of internal operating frequencies (refer to Figure 1). For

external oscillator mode, OSC1 should be left open.

Annun0 - Annun2 (Annunciator Frontplanes)

These pins are three independent annunciator driving outputs.

The enabled annunciator outputs from its corresponding pin a 30Hz

square wave which is 180 degrees out of phase with BP. Disabled

annunciator output from its corresponding pin an square wave in-

phase with BP. When all annunciators are disabled, all these pins

output 0V.

OSC2 (Oscillator Output / External Oscillator Input)

For internal oscillator mode, this is an output for the internal low

power RC oscillator circuit. For external oscillator mode, OSC2 will

be an input pin for external clock and no external resistor is needed.

AVDD and AVSS

AVDD is the positive supply to the LCD bias Internal DC/DC Con-

verter. AVSS is ground.

VLL6 - VLL2

Group of voltage level pins for driving the LCD panel. They can

either be connected to external driving circuit for external bias supply

or connected internally to built-in divider circuit if internal divider is

enable. For Internal DC/DC Converter enabled, a 0.1 µF capacitor to

VCC

For using the Internal DC/DC Converter, a 0.1 µF capacitor from

this pin to AVSS is required. It can also be an external bias input pin

if Internal DC/DC Converter is not used. Power is supplied to the

LCD Driving Level Selector and HV Buffer Cell with this pin. Nor-

mally, this pin is not intended to be a power supply to other compo-

nent.

AV is required on each pin.

SS

C1N and C1P

If Internal DC/DC Converter is enabled, a 0.1 µF capacitor is

required to connect these two pins.

DVDD and DVSS

Power is supplied to the digital control circuit of the driver using

these two pins. DVDD is power and DVSS is ground.

C2N and C2P

If Internal DC/DC Converter and Tripler are enabled, a 0.1 µF

capacitor is required between these two pins. Otherwise, leave these

pins open.

MOTOROLA

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OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER

Description of Block Diagram Module

Command Decoder and Command Interface

MPU Parallel Interface

This module determines whether the input data is interpreted as

data or command. Data is directed to this module based upon the

input of the D/C pin. If D/C high, data is written to Graphic Display

Data RAM (GDDRAM). D/C low indicates that the input at D0-D7 is

interpreted as a Command.

Reset is of same function as Power ON Reset (POR). Once RES

received the reset pulse, all internal circuitry will back to its initial sta-

tus. Refer to Command Description section for more information.

The parallel interface consists of 8 bi-directional data lines (D0-

D7), R/W, and the CS. The R/W input High indicates a read opera-

tion from the Graphic Display Data RAM (GDDRAM). R/W input Low

indicates a write operation to Display Data RAM or Internal Com-

mand Registers depending on the status of D/C input. The CS input

serves as data latch signal (clock). Refer to AC operation conditions

and characteristics section for Parallel Interface Timing Description.

Graphic Display Data RAM (GDDRAM)

The GDDRAM is a bit mapped static RAM holding the bit pattern

to be displayed. The size of the RAM is determined by number of

row times the number of column (112x17 = 1904 bits). Figure 5 is a

description of the GDDRAM address map. For mechanical flexibility,

re-mapping on both Segment and Common outputs are provided.

Column address 00H

Column address 6FH

(or column address 77H)

(or column address 08H)

Com0

(Com15)

Row 0

LSB

Page 1

MSB

LSB

Page 2

MSB

Com15

(Com0)

Row 15

Row 16 LSB

Page 3

Com16

Note : The configuration in parentheses represent the remapping of Rows and Columns

Figure 5. Graphic Display Data RAM (GDDRAM) Address Map

MC141805

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MOTOROLA

Display Timing Generator

Annunciator Control Circuit

This module is an on chip low power RC oscillator circuitry (Fig-

ure 6). The oscillator frequency can be selected in the range of

15kHz to 50kHz by external resistor. One can enable the circuitry by

software command. For external clock provided, feed the clock to

OSC2 and leave OSC1 open.

The LCD waveform of the 3 annunciators and BP are generated

by this module. The 3 independent annunciators are enabled by soft-

ware command. Annunciator is also controlled by oscillator circuit.

Before turning the annunciators on, the oscillator must be on in

advance. Annunciator output waveform shown in Figure 7.

Oscillator enable

Internal Oscillator selected

enable1 enable2

Oscillation Circuit

enable

Buffer

MC141805

External component

OSC2

OSC1

Feedback for internal oscillator

For external CLK input

Figure 6. Oscillator Circuitry

DV

DD

BP

ANNUN1

ANNUN2

DV

SS

DD

DV

SS

DD

DV

SS

ANNUN1

ANNUN2

OSC

ON / OFF

DISABLE

ON

OFF

ON

OFF

ON / OFF

DISABLE

ENABLE

Figure 7. Annunciators and BP Display Waveform

LCD Driving Internal DC/DC Converter and Regulator

This module generates the LCD voltage needed for display output. It

takes a single supply input and generate necessary bias voltages. It

consists of :

1. Voltage Doubler and Voltage Tripler

To generate the Vcc voltage. Either Doubler or Tripler can be

enabled.

17 Bit Latch / 112 Bit Latch

A 129 bit long register which carry the display signal information.

First 17 bits are Common driving signals and other 112 bits are Seg-

ment driving signals. Data will be input to the HV-buffer Cell for bump-

ing up to the required level.

Level Selector

2. Voltage Regulator

Feedback gain control for initial LCD voltage. It can also be used with

external contrast control.

Level Selector is a control of the display synchronization. Display

voltage can be separated into two sets and used with different cycles.

Synchronization is important since it selects the required LCD voltage

level to the HV Buffer Cell for output signal voltage pump.

3. Voltage Divider

Divide the LCD display voltage (V -V ) from the regulator output.

LL2 LL6

This is a low power consumption circuit which can save the most dis-

play current compare with traditional resistor ladder method.

4. Self adjust temperature compensation circuitry

Provide 4 different compensation grade selections to satisfy the vari-

ous liquid crystal temperature grades. The grading can be selected

by software control.

HV Buffer Cell (Level Shifter)

HV Buffer Cell works as a level shifter which translates the low volt-

age output signal to the required driving voltage. The output is shifted

out with an internal FRM clock which comes from the Display Timing

Generator. The voltage levels are given by the level selector which is

synchronized with the internal M signal.

5. Contrast Control Block

Software control of 16 voltage levels of LCD voltage.

All blocks can be individually turned off if external DC/DC Converter

is employed.

MOTOROLA

MC141805

3–347

LCD Panel Driving Waveform

The following is an example of how the Common and Segment driv-

ers may be connected to a LCD panel. The waveforms shown in Figure

8a, 8b and 8c illustrate the desired multiplex scheme.

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

Figure 8a. LCD Display Example “0”

MC141805

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MOTOROLA

TIME SLOT

1 2 3 4

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

COM0

COM1

SEG0

SEG1

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

Figure 8b. LCD Driving Signal from MC141805

TIME SLOT

1 2 3 4

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

-VLL2

-VLL3

-VLL4

-VLL5

-VLL6

Seg0-Com0

“OFF” Pixel

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

-VLL2

-VLL3

-VLL4

-VLL5

-VLL6

Seg0-Com1

“On” Pixel

Figure 8c. Effective LCD waveform on LCD pixel

MOTOROLA

MC141805

3–349

Command Description

Set Display On/Off (Display Mode / Stand-by Mode)

Set Vertical Scroll Value

The Display On command turns the LCD Common and Segment

outputs on and has no effect to the annunciator output. This com-

mand starts the conversion of data in GDDRAM to necessary wave-

forms on the Common and Segment driving outputs. The on-chip

bias generator is also turned on by this command. (Note : “Set Oscil-

lator On” command should be sent before “Set Display On”)

This command maps the selected GDDRAM row (00H-0FH) to

Com0. With scroll value equals to 0, Row 0 of GDDRAM is mapped

to Com0 and Row 1 through Row 15 are mapped to Com1 through

Com15 respectively. With scroll value equal to 1, Row 1 of

GDDRAM is mapped to Com0, then Row 2 through Row 15 will be

mapped to Com1 through Com14 respectively and Row 0 will be

mapped to Com15.

The Display Off command turn the display off and the states of the

LCD driver are as follow during display off :

Save / Restore Column Address

1. The Common and Segment outputs are fixed at V

2. The bias Internal DC/DC Converter is turned off.

3. The RAM and content of all registers are retained.

4. IC will accept new commands and data.

The status of the Annunciators and Oscillator are not affected by

this command.

(V ).

With bit option = 1 in this command, the Save / Restore Column

Address command saves a copy of the Column Address of

GDDRAM. With a bit option = 0, this command restores the copy

obtained from the previous execution of saving column address. This

instruction is very useful for writing full graphics characters that are

larger than 8 pixels vertically.

LL1

SS

Note : DON’T USE ICON DISPLAY MODE DURING DISPLAY

OFF.

Set Column Mapping

This instruction selects the mapping of GDDRAM to Segment driv-

ers for mechanical flexibility. There are 2 mappings to select:

1. Column 0 - Column 111 of GDDRAM mapped to Seg0-Seg111

respectively;

2. Column 8 - Column 119 of GDDRAM mapped to Seg111-Seg0

respectively.

Set GDDRAM Column Address

This command positions the address pointer on a column location.

The address can be set to location 00H-77H (120 columns). The col-

umn address will be increased automatically after a read or write

operation. Refer to “Address Increment Table” and command “Set

GDDRAM Page Address” for further information.

Detail information please refer to section “Display Output Descrip-

tion”.

Set GDDRAM Page Address

This command positions the row address to 1 of 3 possible posi-

tions in GDDRAM. Refer to figure 5.

Set Row Mapping

This command selects the mapping of GDDRAM to Common Driv-

ers for mechanical flexibility. There are 2 mappings to select:

1. Row 0 - Row 15 of GDDRAM to Com0 - Com15 respectively;

2. Row 0 - Row 15 of GDDRAM to Com15 - Com0 respectively.

Output of Row 16 (Com16) will not be changed by this command.

See section “Display Output Description” for related information.

Master Clear GDDRAM

This command is to clear the content of page 1 and 2 of the Dis-

play Data RAM to zero. Issue this command followed by a dummy

write data.

Master Clear Icons

Set Annunciator Control Signals

This command is used to clear the data in page 3 of GDDRAM

which stores the icon line data. Before using this command, set the

page address to Page 3 by the command “Set GDDRAM Page

Address”. A dummy write data is also needed after this “Master Clear

Icons” command to make the clear icon action effective.

This command is used to control the active states of the 3 stand

alone annunciator drivers.

Set Oscillator Enable / Disable

This command is used to either turn on or off the oscillator. For

using internal or external oscillator, this command should be exe-

cuted. The setting for this command is not affected by command “Set

Display On/Off” and “Set Annunciator Control Signal”. See command

“Set Internal / External Oscillator” for more information

Set Display Mode

This command switch the driver to full display mode or low power

icon mode. In low power icon mode, only icons (driven by COM16)

and annunciators are displayed, and the DC-DC converter, the Inter-

nal DC/DC Converter and the regulator are disabled. Do select 1/17

Mux ratio before using the low power icon mode.

Set Internal / External Oscillator

This command is used to select either internal or external oscilla-

tor. When internal oscillator is selected, feedback resistor between

OSC1 and OSC2 is needed. For external oscillation circuit, feed

clock input signal to OSC2 and leave OSC1 open.

Note : DON’T USE ICON DISPLAY MODE DURING DISPLAY OFF.

Set Multiplex Ratio

In normal display mode, the multiplex ratio could be set to be 1/16

or 1/17. For 1/16 Mux Ratio, COM16 signal should not be connected

to the panel.

Set Internal DC/DC Converter On/Off

Use this command to select the Internal DC/DC Converter to gen-

erate the V

from AV . Disable the Internal DC/DC Converter if

CC

DD

Set Icon Mode A/B

external Vcc is provided.

In Icon mode A, on-pixels are stressed by a voltage with root-

mean-square value of 0.87xV , whereas off-pixels by 0.5xV . In

Set Voltage Doubler / Tripler

DD

icon mode B, on-pixels are stressed by a voltage with root-mean-

square value of 0.71xV , whereas off-pixels by 0.41xV . This

Use this command to choose Doubler or Tripler when the Internal

DC/DC Converter is enabled.

DD

command is used to control the contrast of the icon line (Com16)

under icon mode

MC141805

3–350

MOTOROLA

Set Internal Regulator On/Off

Increase / Decrease Contrast Level

Choose bit option 0 to disable the Internal Regulator. Choose bit

option 1 to enable Internal Regulator which consists of the internal

contrast control and temperature compensation circuits.

If the internal contrast control is enabled, this command is used to

increase or decrease the contrast level within the 16 contrast levels.

The contrast level starts from lowest value after POR.

Set Internal Voltage Divider On/Off

Set Contrast Level

If the Internal Voltage Divider is disabled, external bias can be

This command is to select one of the 16 contrast levels when inter-

nal contrast control circuitry is in use. After power-on reset, the con-

trast level is the lowest.

used for V

to V

If the Internal Voltage Divider is enabled, the

LL6

LL2.

internal circuit will generated the 1:5 bias driving voltage.

Set Internal Contrast Control On/Off

Set Temperature Coefficient

This command is used to turn on or off the intrernal control of delta

voltage of the bias voltages. With bit option = 1, the software selec-

tion for delta bias voltage control is enabled. With bit option = 0, inter-

nal contrast control is disabled.

This command can select 4 different LCD driving voltage tempera-

ture coefficients to match various liquid crystal temperature grades.

Those temperature coefficients are specified in Electrical Character-

istics Tables.

COMMAND TABLE

Bit Pattern

000000X X

Command

Comment

Set GDDRAM Page Address using X X as address bits.

Set GDDRAM Page Address

1

0

1 0

X X =00 : page 1 (POR)

1

0

X X =01 : page 2

1

0

X X =10 : page 3

1

0

0001X X X X

2 1 0

Set Contrast Level

With R/W pin input low, set one of the 16 available values to the

internal contrast register, using X X X X as data bits. The con-

3

2 1 0

trast register is reset to 0000 during POR.

0010000X

0010001X

0010010X

0010100X

0010101X

0010110X

Set Voltage Doubler / Tripler

Set Column Mapping

X =0 : Set Voltage Tripler (POR)

0

X =1 : Set Voltage Doubler

0

X =0 : Col0 to Seg0 (POR)

0

X =1 : Col8 to Seg111

0

Set Row Mapping

X =0 : Row0 to Com0

0

X =1 : Row0 to Com15

0

Set Display On/Off

X =0 : display off (POR)

0

X =1 : display on

0

Set Internal DC/DC Converter On/Off

Set Internal Regulator On/Off

X =0 : Internal DC/DC Converter off(POR)

0

X =1 : Internal DC/DC Converter on

0

X =0 : Internal Regulator off(POR)

0

X =1 : Internal Regulator on

0

When application uses a supply with built-in temperature compen-

sation, the regulator should be disabled.

0010111X

0011000X

Set Internal Voltage Divider On/Off

Set Internal Contrast Control On/Off

Set Display Mode

X =0 : Internal Voltage Divider off (POR)

0

X =1 : Internal Voltage Divider on

0

When an external bias network is preferred, the voltage divider

should be disabled.

X =0 : Internal Contrast Control off (POR)

0

X =1 : Internal Contrast Control on

0

Internal contrast circuits can be disabled if external contrast cir-

cuits is preferred.

0011001X

0011010X

X =0 : normal display mode (1/16 or 1/17 mux) (POR)

0

X =1 : low power icon display mode

0

Save/Restore GDDRAM Column

Address

X =0 : restore address

0

X =1 : save address

0

00110110

00110111

0011110X

Master Clear GDDRAM

Master Clear of Icons

Set Multiplex Ratio

Master clear page 1 and 2 of GDDRAM

Master Clear of icon line (Com16)

X =0 : 1/16 Mux ratio (POR)

0

X =1 : 1/17 Mux ratio

0

0011111X

Set Icon Mode A/B

X =0 : icon mode A (POR)

0

X =1 : icon mode B

0

MOTOROLA

MC141805

3–351

Bit Pattern

0100X X X X

Command

Comment

Use X X X X as number of lines to scroll.

Set Vertical Scroll Value

3

2

1

0

3 2 1 0

Scroll value = 0 upon POR

01100A A X

Set Annunciator Control Signals

A A =00 : select annunciator 1 (POR)

1

0

1 0

A A =01 : select annunciator 2

1

0

A A =10 : select annunciator 3

1

0

X =0 : turn selected annunciator off (POR)

0

X =1 : turn selected annunciator on

0

01101000

Reserved

011011X X

Set Temperature Coefﬁcient

X X = 00 : 0.00% (POR)

1 0

1

0

X X = 01 : -0.18%

1

0

X X = 10 : -0.22%

1

0

X X = 11 : -0.35%

1

0

0111000X

0111101X

0111111X

Increase / Decrease Contrast Value

Set External / Internal Oscillator

Set Oscillator Disable / Enable

X =0 : Decrease by one

0

X =1 : Increase by one

0

(Note: increment/decrement wraps round among the 16 contrast

levels. Start at the lowest level when POR.)

X =0: External oscillator (POR)

0

X =1: Internal oscillator.

0

For internal oscillator place a resistor between OSC1 and OSC2.

For external oscillator mode, feed clock input to OSC2.

X =0: oscillator master disable (POR)

0

X =1: oscillator master enable.

0

This is the master control for oscillator circuitry. This command

should be issued after the “External / Internal Oscillator” com-

mand.

1X X X X X X X

5 4 3 2 1 0

Set GDDRAM Column Address

Set GDDRAM Column Address.

6

Use X X X X X X X as address bits.

6

5 4 3 2 1 0

Data Read / Write

To read data from the GDDRAM, input High to R/W pin and D/C pin. Data is valid at the falling edge of CS. And the GDDRAM column

address pointer will be increased by one automatically.

To write data to the GDDRAM, input Low to R/W pin and High to D/C pin. Data is latched at the falling edge of CS. And the GDDRAM column

address pointer will be increased by one automatically.

No auto address pointer increment will be performed for the Dummy Write Data after Master Clear GDDRAM. (Refer to the “Commands

Required for R/W Actions on RAM” Table)

MC141805

3–352

MOTOROLA

Address Increment Table (Automatic)

D/C

0

R/W

Comment

Address Increment

Remarks

0

1

0

1

Write Command

Read Command

Write Data

No

0

No (invalid mode)

*1

*2

1

Yes

1

Read Data

*3

Address Increment is done automatically data read write. The column address pointer of GDDRAM is affected.

Remarks : *1. Only data is read from RAM.

*2. If write data is issued after Command Clear RAM, Address increase is not applied.

*3. Column Address will be wrapped round when overflow.

Power Up Sequence (Commands Required)

Command Required

POR Status

Remarks

Set External / Internal Oscillator

Set Voltage Tripler / Doubler

Internal DC/DC Converter On

Set Internal Regulator On

Set Temperature Coefﬁcient

Set Internal Contrast On

Set Contrast Level

Set Internal Voltage Divider On

Set Column Mapping

Set Row Mapping

External

Tripler

Off

TC=0%

Off

Contrast Level = 0

Off

Seg. 0 = Col. 0

Com. 0 = Row 0

Scroll Value = 0

Disable

*1

Remarks :

*1 -- Required only if desired status differ from POR.

*2 -- Effective only if Internal Contrast Control is enabled.

*3 -- Effective only if Regulator is enabled.

*1, *3

*1, *2, *3

*1

Set Vertical Scroll Value

Set Oscillator Enable

*1

Set Annunciator Control Signals

Master Clear GDDRAM

Dummy Write Data

Annnuciators all off

Random

*1

Set Display On

Off

MOTOROLA

MC141805

3–353

Commands Required for Display Mode Setup

Display Mode

Commands Required

Normal Display Mode

Set External / Internal Oscillator

Set Oscillator Enable,

Set Display On.

(0111101X )*

(01111111)*

(00101001)*

0

Icon Display Mode

Set Internal Oscillator

Set Oscillator Enable,

Set 1/17 Mux Ratio

Set Display Mode to Icon Display Mode

Set Display On.

(01111011)*

(01111111)*

(00111101)*

(00110011)*

(00101001)*

Annunciator Display

Standby Mode

Set External / Internal Oscillator

Set Oscillator Enable,

Set Annunciator On/Off.

(0111101X )*

(01111111)*

(01100A A X )*

1 0 0

0

Set Display Off,

Set Oscillator Disable.

(00101000)*

(01111110)*

Other Related Command with Display Mode : Set Column Mapping, Set Row Mapping, Set Vertical Scroll Value.

Commands Related to Internal DC/DC Converter :

Set Oscillator Disable / Enable, Set Internal Regulator On/Off, Set Temperature Coefficient, Set Internal Contrast Control On/Off, Increase /

Decrease Contrast Level, Set Internal Voltage Divider On/Off, Set Display On/Off, Set Internal / External Oscillator, Set Contrast Level, Set

Voltage Doubler / Tripler

Commands Required for R/W Actions on RAM

R/W Actions on RAMs

Commands Required

Read/Write Data from/to GDDRAM.

Set GDDRAM Page Address

Set GDDRAM Column Address

Read/Write Data

(000000X X )*

1 0

(1X X X X X X X )*

6

5 4 3 2 1 0

(X X X X X X X X )

7

6 5 4 3 2 1 0

Save/Restore GDDRAM Column Address.

Increase GDDRAM ColumnAddress by One

Master Clear GDDRAM

Save/Restore GDDRAM Column Address.

Dummy Read Data

(0011010X )

0

(X X X X X X X X )

7

6 5 4 3 2 1 0

Master Clear GDDRAM

Dummy Write Data

(00110110)

(X X X X X X X X )

7

6 5 4 3 2 1 0

* No need to resend the command again if it is set previously.

The read / write action to the Display Data RAM does not depend on the display mode. This means the user can change the RAM content

whether the target RAM content is being displayed.

MC141805

3–354

MOTOROLA

Display Output Description

COM0

This is an example of output pattern on the LCD panel. The following

table is a description of what is inside the CDDRAM, CGRAM and GD-

DRAM. Figure 9b and 9c are the output pattern on the LCD display with

different command enabled.

(Display Mode, Page Swapping, Scrolling, Column Re-map and Row

Re-map)

COM16

SEG0

SEG111

Figure 9a

Content of GDDRAM

PAGE 1

5

A

5

A

5

A

5

A

-

0

PAGE 2

3

C

3

C

-

3

C

3

C

Figure 9b

Column remap disable

Row re-map disable

Column remap enable

Row re-map disable

Column remap disable

Row re-map enable

Column remap disable

Row re-map disable

Scroll Value = 0Fh

Figure 9c. Examples of LCD display with different command enabled

MOTOROLA

MC141805

3–355

MC141805T TAB PACKAGE DIMENSION (1 OF 2)

98ASL10004A ISSUE 0

DO NOT SCALE THIS DRAWING

Copper Side

MC141805

3–356

MOTOROLA

MC141805T TAB PACKAGE DIMENSION (2 OF 2)

98ASL10004A ISSUE 0

DO NOT SCALE THIS DRAWING

MOTOROLA

MC141805

3–357

Application Circuit

16/17 MUX Display with Analog Circuitry enabled,Tripler enabled and 1:5 bias

DV

AV

DD

0.1µF

0.1µF 0.1µF

0.1µF 0.1µF 0.1µF 0.1µF

DVSS DVDD

AVDD AVSS

VLL2 VLL3

VLL4 VLL5 VLL6 VCC

COM0 to

COM16

RES

D/C

CS

SEG0 to

SEG111

To LCD

Panel

CMOS

MC141805

MPU/

MCU with

Parallel

Interface

Annun 0-2

and BP

R/W

D0~D7

OSC2 OSC1 C+

C- VF

VR C2P C2N C1P C1N

760kΩ

EPROM

RAM

1MΩ

0.1µF

200kΩ

0.1µF

4.7µF

0.1µF

560pF

Remark :

1. Capacitor between C2N and C2P can be omitted only if doubler is enable.

2. Resistor across OSC1 and OSC2 can be omitted if external oscillator is used.

3. VR and VF can be left open for Regulator disable, TC = 0% and Contrast Disable.

4. RES, CS, R/W and D/C should be at a known state.

5. CS line low at Standby Mode.

MC141805

3–358

MOTOROLA

Application Circuit

16/17 MUX Display with Analog Circuit disabled, External Bias

DV

AV

DD

V

CC

0.1µF

DVSS DVDD

AVDD AVSS

VLL2 VLL3

VLL4 VLL5 VLL6 VCC

COM0 to

COM16

RES

D/C

CS

SEG0 to

SEG111

To LCD

Panel

CMOS

MC141805

MPU/

MCU with

Parallel

Interface

Annun 0-2

and BP

R/W

D0~D7

OSC1 C+

C-

VF

VR

C2P C2N

C1N

OSC2

C1P

EPROM

RAM

External Clock

Remark :

1. Value of the resistors depends on the LCD panel characteristic.

2. RES, CS, R/W and D/C should be at a known state.

3. CS line low at Standby Mode.

MOTOROLA

MC141805

3–359

MC141805

3–360

MOTOROLA


型号：	MC141805T
厂家：	MOTOROLA
描述：	LIQUID CRYSTAL DISPLAY DRIVER, UUC166, TAB-166 驱动接口集成电路
文件：	总24页 (文件大小：253K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC141805T [MOTOROLA]

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