MC145151 [MOTOROLA]
Parallel-Input PLL Frequency Synthesizer; 并行输入锁相环频率合成器
| 型号： | MC145151 |
| 厂家： | 
MOTOROLA |
| 描述： | Parallel-Input PLL Frequency Synthesizer |
| 文件： | 总36页 (文件大小：718K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
by MC145151–2/D
SEMICONDUCTOR TECHNICAL DATA
CMOS
The devices described in this document are typically used as low–power,
phase–locked loop frequency synthesizers. When combined with an external
low–pass filter and voltage–controlled oscillator, these devices can provide all
the remaining functions for a PLL frequency synthesizer operating up to the
device’s frequency limit. For higher VCO frequency operation, a down mixer or
a prescaler can be used between the VCO and the synthesizer IC.
These frequency synthesizer chips can be found in the following and other
applications:
CATV
TV Tuning
AM/FM Radios
Two–Way Radios
Scanning Receivers
Amateur Radio
÷
R
OSC
φ
CONTROL LOGIC
÷
A
÷
N
÷
P/P + 1
VCO
OUTPUT
FREQUENCY
CONTENTS
Page
DEVICE DETAIL SHEETS
MC145151–2 Parallel–Input, Single–Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
MC145152–2 Parallel–Input, Dual–Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MC145155–2 Serial–Input, Single–Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MC145156–2 Serial–Input, Dual–Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MC145157–2 Serial–Input, Single–Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MC145158–2 Serial–Input, Dual–Modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FAMILY CHARACTERISTICS
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Frequency Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Phase Detector/Lock Detector Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DESIGN CONSIDERATIONS
Phase–Locked Loop — Low–Pass Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Crystal Oscillator Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Dual–Modulus Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
REV 1
8/95
Motorola, Inc. 1995
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC DIP
CASE 710
Interfaces with Single–Modulus Prescalers
28
28
1
The MC145151–2 is programmed by 14 parallel–input data lines for the
N counter and three input lines for the R counter. The device features consist of
a reference oscillator, selectable–reference divider, digital–phase detector, and
14–bit programmable divide–by–N counter.
The MC145151–2 is an improved–performance drop–in replacement for the
MC145151–1. The power consumption has decreased and ESD and latch–up
performance have improved.
DW SUFFIX
SOG PACKAGE
CASE 751F
1
ORDERING INFORMATION
•
•
•
•
•
•
•
•
•
•
•
•
Operating Temperature Range: – 40 to 85°C
Low Power Consumption Through Use of CMOS Technology
3.0 to 9.0 V Supply Range
On– or Off–Chip Reference Oscillator Operation
Lock Detect Signal
MC145151P2
Plastic DIP
MC145151DW2 SOG Package
PIN ASSIGNMENT
÷ N Counter Output Available
Single Modulus/Parallel Programming
f
1
2
28
27
LD
in
8 User–Selectable ÷ R Values: 8, 128, 256, 512, 1024, 2048, 2410, 8192
÷ N Range = 3 to 16383
“Linearized” Digital Phase Detector Enhances Transfer Function Linearity
Two Error Signal Options: Single–Ended (Three–State) or Double–Ended
Chip Complexity: 8000 FETs or 2000 Equivalent Gates
V
OSC
SS
DD
out
in
V
3
26
25
24
23
22
21
20
19
18
17
OSC
N11
N10
N13
N12
T/R
N9
out
PD
4
RA0
RA1
RA2
5
6
7
φ
8
R
φ
9
V
f
10
N8
V
N0 11
N1 12
N7
N6
N2 13
N3 14
16
15
N5
N4
REV 1
8/95
Motorola, Inc. 1995
MC145151–2 BLOCK DIAGRAM
RA2
RA1
RA0
14 x 8 ROM REFERENCE DECODER
14
OSC
out
LOCK
LD
PD
DETECT
OSC
14–BIT
÷
R COUNTER
in
PHASE
DETECTOR
A
out
f
in
14–BIT
÷
N COUNTER
14
V
PHASE
DETECTOR
B
DD
φ
V
φ
R
TRANSMIT OFFSET ADDER
T/R
f
V
N13
N11
N9
N7 N6
N4
N2
N0
NOTE: N0 – N13 inputs and inputs RA0, RA1, and RA2 have pull–up resistors that are not shown.
sure that inputs left open remain at a logic 1 and require only
an SPST switch to alter data to the zero state.
PIN DESCRIPTIONS
INPUT PINS
T/R
f
in
Frequency Input (Pin 1)
Transmit/Receive Offset Adder Input (Pin 21)
This input controls the offset added to the data provided at
the N inputs. This is normally used for offsetting the VCO
frequency by an amount equal to the IF frequency of the
transceiver. This offset is fixed at 856 when T/R is low and
gives no offset when T/R is high. A pull–up resistor ensures
that no connection will appear as a logic 1 causing no offset
addition.
Input to the ÷ N portion of the synthesizer. f is typically
in
derived from loop VCO and is ac coupled into the device. For
larger amplitude signals (standard CMOS logic levels) dc
coupling may be used.
RA0 – RA2
Reference Address Inputs (Pins 5, 6, 7)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider, as
defined by the table below.
Pull–up resistors ensure that inputs left open remain at a
logic 1 and require only a SPST switch to alter data to the
zero state.
OSC , OSC
in
out
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSC to ground and OSC
to ground.
in
out
Total
Divide
Value
OSC may also serve as the input for an externally–gener-
Reference Address Code
in
ated reference signal. This signal is typically ac coupled to
RA2
RA1
RA0
OSC , but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
in
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
128
256
512
1024
2048
2410
8192
reference mode, no connection is required to OSC
.
out
OUTPUT PINS
PD
out
Phase Detector A Output (Pin 4)
Three–state output of phase detector for use as loop–error
signal. Double–ended outputs are also available for this pur-
N0 – N11
pose (see φ and φ ).
V
R
N Counter Programming Inputs (Pins 11 – 20, 22 – 25)
Frequency f > f or f Leading: Negative Pulses
V
R
V
These inputs provide the data that is preset into the ÷ N
counter when it reaches the count of zero. N0 is the least sig-
nificant and N13 is the most significant. Pull–up resistors en-
Frequency f < f or f Lagging: Positive Pulses
V R V
Frequency f = f and Phase Coincidence: High–Imped-
V
R
ance State
MOTOROLA
MC145151–2 through MC145158–2
3
φ , φ
nally connected to the phase detector input. With this output
available, the ÷ N counter can be used independently.
R
V
Phase Detector B Outputs (Pins 8, 9)
These phase detector outputs can be combined externally
for a loop–error signal. A single–ended output is also avail-
LD
Lock Detector Output (Pin 28)
able for this purpose (see PD
).
out
If frequency f is greater than f or if the phase of f is
Essentially a high level when loop is locked (f , f of same
R V
phase and frequency). Pulses low when loop is out of lock.
V
R
V
leading, then error information is provided by φ pulsing low.
V
φ
R
remains essentially high.
POWER SUPPLY
If the frequency f is less than f or if the phase of f is
V
R
V
V
lagging, then error information is provided by φ pulsing low.
DD
R
Positive Power Supply (Pin 3)
φ
V
remains essentially high.
If the frequency of f = f and both are in phase, then both
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to V
V
R
φ
V
and φ remain high except for a small minimum time
.
R
SS
period when both pulse low in phase.
V
SS
Negative Power Supply (Pin 2)
f
V
N Counter Output (Pin 10)
The most negative supply potential. This pin is usually
ground.
This is the buffered output of the ÷ N counter that is inter-
TYPICAL APPLICATIONS
2.048 MHz
NC
NC
OSC
in
OSC
out
f
RA2 RA1
RA0
PD
in
VOLTAGE
CONTROLLED
OSCILLATOR
MC145151–2
out
N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
5 – 5.5 MHz
0 1 1 1 0 0 0 1 0 0 0 = 5 MHz
1 0 1 0 1 1 1 1 1 0 0 = 5.5 MHz
Figure 1. 5 MHz to 5.5 MHz Local Oscillator Channel Spacing = 1 kHz
LOCK DETECT SIGNAL
TRANSMIT: 440.0 – 470.0 MHz
RECEIVE: 418.6 – 448.6 MHz
(25 kHz STEPS)
“1”
“1”
“0”
CHOICE OF
DETECTOR
ERROR
OSC
RA2
RA1
RA0
LD
f
V
out
SIGNALS
PD
out
OSC
in
LOOP
FILTER
φ
VCO
X6
+ V
R
V
V
DD
SS
MC145151–2
f
V
REF. OSC.
10.0417 MHz
(ON–CHIP OSC.
OPTIONAL)
f
in
T: 73.3333 – 78.3333 MHz
R: 69.7667 – 74.7667 MHz
T/R
T: 13.0833 – 18.0833 MHz
R: 9.5167 – 14.5167 MHz
DOWN
MIXER
“0” “0” “1”
CHANNEL PROGRAMMING
N = 2284 TO 3484
RECEIVE
÷
TRANSMIT
(ADDS 856 TO
N VALUE)
÷
X6
60.2500 MHz
NOTES:
1. f = 4.1667 kHz; ÷ R = 2410; 21.4 MHz low side injection during receive.
R
2. Frequency values shown are for the 440 – 470 MHz band. Similar implementation applies to the 406 – 440 MHz band.
For 470 – 512 MHz, consider reference oscillator frequency X9 for mixer injection signal (90.3750 MHz).
Figure 2. Synthesizer for Land Mobile Radio UHF Bands
MC145151–2 Data Sheet Continued on Page 23
MC145151–2 through MC145158–2
4
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC DIP
CASE 710
Interfaces with Dual–Modulus Prescalers
28
28
1
The MC145152–2 is programmed by sixteen parallel inputs for the N and A
counters and three input lines for the R counter. The device features consist of
a reference oscillator, selectable–reference divider, two–output phase detector,
10–bit programmable divide–by–N counter, and 6–bit programmable ÷ A
counter.
The MC145152–2 is an improved–performance drop–in replacement for the
MC145152–1. Power consumption has decreased and ESD and latch–up
performance have improved.
DW SUFFIX
SOG PACKAGE
CASE 751F
1
ORDERING INFORMATION
MC145152P2
MC145152DW2 SOG Package
Plastic DIP
•
•
•
•
•
•
•
•
•
•
Operating Temperature Range: – 40 to 85°C
Low Power Consumption Through Use of CMOS Technology
3.0 to 9.0 V Supply Range
On– or Off–Chip Reference Oscillator Operation
Lock Detect Signal
PIN ASSIGNMENT
Dual Modulus/Parallel Programming
f
1
2
28
27
LD
in
8 User–Selectable ÷ R Values: 8, 64, 128, 256, 512, 1024, 1160, 2048
÷ N Range = 3 to 1023, ÷ A Range = 0 to 63
Chip Complexity: 8000 FETs or 2000 Equivalent Gates
See Application Note AN980
V
OSC
SS
DD
in
V
3
4
5
6
7
8
9
26
25
24
23
22
21
20
19
18
17
OSC
A4
A3
A0
A2
A1
N9
N8
N7
N6
out
RA0
RA1
RA2
φ
R
φ
V
MC
A5 10
N0 11
N1 12
N2 13
N3 14
16
15
N5
N4
REV 1
8/95
Motorola, Inc. 1995
MC145152–2 BLOCK DIAGRAM
RA2
RA1
RA0
12 x 8 ROM REFERENCE DECODER
12
OSC
out
LOCK
DETECT
LD
OSC
in
12–BIT
÷
R COUNTER
MC
φ
V
CONTROL
LOGIC
PHASE
DETECTOR
φ
R
f
in
6–BIT
A5
÷
A COUNTER
10–BIT
N2
÷
N COUNTER
A3 A2
A0
N0
N4 N5
N7
N9
NOTE: N0 – N9, A0 – A5, and RA0 – RA2 have pull–up resistors that are not shown.
Prescaling section). The A inputs all have internal pull–up
resistors that ensure that inputs left open will remain at a
logic 1.
PIN DESCRIPTIONS
INPUT PINS
f
in
OSC , OSC
in
out
Frequency Input (Pin 1)
Reference Oscillator Input/Output (Pins 27, 26)
Input to the positive edge triggered ÷ N and ÷ A counters.
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
f
is typically derived from a dual–modulus prescaler and is
ac coupled into the device. For larger amplitude signals
(standard CMOS logic levels) dc coupling may be used.
in
connected from OSC to ground and OSC
to ground.
in
out
OSC may also serve as the input for an externally–gener-
in
RA0, RA1, RA2
Reference Address Inputs (Pins 4, 5, 6)
ated reference signal. This signal is typically ac coupled to
OSC , but for larger amplitude signals (standard CMOS
in
These three inputs establish a code defining one of eight
possible divide values for the total reference divider. The
total reference divide values are as follows:
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC
.
out
OUTPUT PINS
Total
Divide
Value
Reference Address Code
φ , φ
R
V
RA2
RA1
RA0
Phase Detector B Outputs (Pins 7, 8)
These phase detector outputs can be combined externally
for a loop–error signal.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
64
If the frequency f is greater than f or if the phase of f is
128
256
512
1024
1160
2048
V
R
V
leading, then error information is provided by φ pulsing low.
φ
R
V
remains essentially high.
If the frequency f is less than f or if the phase of f is
V
R
V
lagging, then error information is provided by φ pulsing low.
R
φ
V
remains essentially high.
If the frequency of f = f and both are in phase, then both
and φ remain high except for a small minimum time
R
period when both pulse low in phase.
V
R
N0 – N9
φ
V
N Counter Programming Inputs (Pins 11 – 20)
The N inputs provide the data that is preset into the ÷ N
counter when it reaches the count of 0. N0 is the least signifi-
cant digit and N9 is the most significant. Pull–up resistors en-
sure that inputs left open remain at a logic 1 and require only
a SPST switch to alter data to the zero state.
MC
Dual–Modulus Prescale Control Output (Pin 9)
Signal generated by the on–chip control logic circuitry for
controlling an external dual–modulus prescaler. The MC
level will be low at the beginning of a count cycle and will
remain low until the ÷ A counter has counted down from its
programmed value. At this time, MC goes high and remains
high until the ÷ N counter has counted the rest of the way
down from its programmed value (N – A additional counts
since both ÷ N and ÷ A are counting down during the first
A0 – A5
A Counter Programming Inputs
(Pins 23, 21, 22, 24, 25, 10)
The A inputs define the number of clock cycles of f that
in
require a logic 0 on the MC output (see Dual–Modulus
MC145151–2 through MC145158–2
6
MOTOROLA
portion of the cycle). MC is then set back low, the counters
preset to their respective programmed values, and the above
sequence repeated. This provides for a total programmable
POWER SUPPLY
V
DD
Positive Power Supply (Pin 3)
divide value (N ) = N • P + A where P and P + 1 represent the
T
dual–modulus prescaler divide values respectively for high
and low MC levels, N the number programmed into the ÷ N
counter, and A the number programmed into the ÷ A counter.
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to V
.
SS
V
SS
Negative Power Supply (Pin 2)
LD
Lock Detector Output (Pin 28)
Essentially a high level when loop is locked (f , f of same
R V
phase and frequency). Pulses low when loop is out of lock.
The most negative supply potential. This pin is usually
ground.
TYPICAL APPLICATIONS
NO CONNECTS
“1”
“1”
“1”
150 – 175 MHz
5 kHz STEPS
LOCK DETECT SIGNAL
R2
10.24 MHz
NOTE 1
C
OSC
out
RA2
RA1
RA0
LD
R1
R1
φ
–
+
R
OSC
in
VCO
φ
V
MC33171
NOTE 2
MC145152–2
R2
C
MC
V
V
+ V
DD
f
in
SS
N9
N0 A5
A0
MC12017
CHANNEL PROGRAMMING
÷
64/65 PRESCALER
NOTES:
1. Off–chip oscillator optional.
2. The φ and φ outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter
R
V
Design page for additional information. The φ and φ outputs swing rail–to–rail. Therefore, the user should be careful
R
V
not to exceed the common mode input range of the op amp used in the combiner/loop filter.
Figure 1. Synthesizer for Land Mobile Radio VHF Bands
MOTOROLA
MC145151–2 through MC145158–2
7
RECEIVER 2ND L.O.
30.720 MHz
REF. OSC.
15.360 MHz
NO CONNECTS
(ON–CHIP OSC.
OPTIONAL)
RECEIVER FIRST L.O.
825.030 844.980 MHz
X2
“1”
“1”
“1”
LOCK DETECT SIGNAL
R2
→
C
(30 kHz STEPS)
OSC
RA2
RA1
RA0
LD
R1
R1
out
φ
–
+
R
OSC
in
X4
NOTE 6
VCO
φ
V
MC145152–2
NOTE 5
NOTE 7
V
V
+ V
DD
R2
C
MC
SS
f
X4
NOTE 6
TRANSMITTER
MODULATION
in
N9
N0 A5
A0
MC12017
TRANSMITTER SIGNAL
825.030 844.980 MHz
(30 kHz STEPS)
÷
64/65 PRESCALER
NOTE 6
CHANNEL PROGRAMMING
→
NOTES:
1. Receiver 1st I.F. = 45 MHz, low side injection; Receiver 2nd I.F. = 11.7 MHz, low side injection.
2. Duplex operation with 45 MHz receiver/transmit separation.
3. f = 7.5 kHz; ÷ R = 2048.
R
4. N
= N 64 + A = 27501 to 28166; N = 429 to 440; A = 0 to 63.
total
5. MC145158–2 may be used where serial data entry is desired.
6. High frequency prescalers (e.g., MC12018 [520 MHz] and MC12022 [1 GHz]) may be used for higher frequency VCO and f
implementations.
ref
7. The φ and φ outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page for
R
V
additionalinformation. The φ and φ outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode
R
V
input range of the op amp used in the combiner/loop filter.
Figure 2. 666–Channel, Computer–Controlled, Mobile Radiotelephone Synthesizer
for 800 MHz Cellular Radio Systems
MC145152–2 Data Sheet Continued on Page 23
MC145151–2 through MC145158–2
8
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC DIP
CASE 707
Interfaces with Single–Modulus Prescalers
18
The MC145155–2 is programmed by a clocked, serial input, 16–bit data
stream. The device features consist of a reference oscillator, selectable–refer-
ence divider, digital–phase detector, 14–bit programmable divide–by–N
counter, and the necessary shift register and latch circuitry for accepting serial
input data.
The MC145155–2 is an improved–performance drop–in replacement for the
MC145155–1. Power consumption has decreased and ESD and latch–up
performance have improved.
1
DW SUFFIX
SOG PACKAGE
CASE 751D
20
1
ORDERING INFORMATION
MC145155P2
MC145155DW2 SOG Package
Plastic DIP
•
•
•
•
•
•
•
•
Operating Temperature Range: – 40 to 85°C
Low Power Consumption Through Use of CMOS Technology
3.0 to 9.0 V Supply Range
On– or Off–Chip Reference Oscillator Operation with Buffered Output
Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
Lock Detect Signal
Two Open–Drain Switch Outputs
8 User–Selectable ÷ R Values: 16, 512, 1024, 2048, 3668, 4096, 6144,
8192
Single Modulus/Serial Programming
÷ N Range = 3 to 16383
“Linearized” Digital Phase Detector Enhances Transfer Function Linearity
Two Error Signal Options: Single–Ended (Three–State) or Double–Ended
Chip Complexity: 6504 FETs or 1626 Equivalent Gates
PIN ASSIGNMENTS
PLASTIC DIP
RA1
RA2
1
2
3
4
5
6
18
17
16
15
14
13
RA0
OSC
OSC
in
•
•
•
•
•
φ
V
out
out
φ
REF
R
V
SW2
SW1
ENB
DATA
CLK
DD
out
PD
V
7
8
9
12
11
10
SS
LD
f
in
SOG PACKAGE
RA1
RA2
1
2
20
19
RA0
OSC
OSC
in
φ
3
4
18
17
V
out
out
φ
REF
NC
R
V
5
6
16
15
DD
PD
V
SW2
SW1
ENB
DATA
CLK
out
SS
7
14
13
12
11
NC
LD
8
9
f
10
in
NC = NO CONNECTION
REV 1
8/95
Motorola, Inc. 1995
MC145155–2 BLOCK DIAGRAM
RA2
RA1
RA0
14 x 8 ROM REFERENCE DECODER
LOCK
DETECT
14
OSC
REF
out
LD
PD
OSC
14–BIT
14–BIT
÷
÷
R COUNTER
in
f
PHASE
DETECTOR
A
R
out
f
V
out
f
in
N COUNTER
14
PHASE
DETECTOR
B
φ
V
φ
R
V
DD
SW2
SW1
ENB
LATCH
LATCH
14
14–BIT SHIFT REGISTER
DATA
CLK
2–BIT SHIFT
REGISTER
information for the 14–bit ÷ N counter and the two switch sig-
nals SW1 and SW2. The entry format is as follows:
PIN DESCRIPTIONS
INPUT PINS
÷
N COUNTER BITS
f
in
Frequency Input (PDIP – Pin 9, SOG – Pin 10)
Input to the ÷ N portion of the synthesizer. f is typically
in
derived from loop VCO and is ac coupled into the device. For
larger amplitude signals (standard CMOS logic levels) dc
coupling may be used.
LAST DATA BIT IN (BIT NO. 16)
FIRST DATA BIT IN (BIT NO. 1)
RA0, RA1, RA2
Reference Address Inputs (PDIP – Pins 18, 1, 2;
SOG – Pins 20, 1, 2)
ENB
Latch Enable Input (PDIP – Pin 12, SOG – Pin 13)
When high (1), ENB transfers the contents of the shift reg-
ister into the latches, and to the programmable counter in-
puts, and the switch outputs SW1 and SW2. When low (0),
ENB inhibits the above action and thus allows changes to be
made in the shift register data without affecting the counter
programming and switch outputs. An on–chip pull–up esta-
blishes a continuously high level for ENB when no external
signal is applied. ENB is normally low and is pulsed high to
transfer data to the latches.
These three inputs establish a code defining one of eight
possible divide values for the total reference divider, as
defined by the table below:
Total
Divide
Value
Reference Address Code
RA2
RA1
RA0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
512
OSC , OSC
1024
2048
3668
4096
6144
8192
in
out
Reference Oscillator Input/Output (PDIP – Pins 17, 16;
SOG – Pins 19, 18)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSC to ground and OSC
to ground.
in
out
CLK, DATA
Shift Register Clock, Serial Data Inputs
(PDIP – Pins 10, 11; SOG – Pins 11, 12)
OSC may also serve as the input for an externally–gener-
in
ated reference signal. This signal is typically ac coupled to
OSC , but for larger amplitude signals (standard CMOS
in
Each low–to–high transition clocks one bit into the on–chip
16–bit shift register. The Data input provides programming
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC
.
out
MC145151–2 through MC145158–2
10
MOTOROLA
OUTPUT PINS
PD
SW1, SW2
Band Switch Outputs (PDIP – Pins 13, 14;
SOG – Pins 14, 15)
out
Phase Detector A Output (PDIP, SOG – Pin 6)
SW1 and SW2 provide latched open–drain outputs corre-
sponding to data bits numbers one and two. These outputs
can be tied through external resistors to voltages as high as
Three–state output of phase detector for use as loop error
signal. Double–ended outputs are also available for this pur-
pose (see φ and φ ).
V
R
15 V, independent of the V
supply voltage. These are
DD
Frequency f > f or f Leading: Negative Pulses
V
R
V
typically used for band switch functions. A logic 1 causes the
output to assume a high–impedance state, while a logic 0
causes the output to be low.
Frequency f < f or f Lagging: Positive Pulses
V
R
V
Frequency f = f and Phase Coincidence: High–Imped-
V
R
ance State
φ , φ
R
V
REF
out
Phase Detector B Outputs (PDIP, SOG – Pins 4, 3)
Buffered Reference Oscillator Output (PDIP, SOG –
Pin 15)
These phase detector outputs can be combined externally
for a loop–error signal. A single–ended output is also avail-
Buffered output of on–chip reference oscillator or exter-
nally provided reference–input signal.
able for this purpose (see PD
).
out
If frequency f is greater than f or if the phase of f is
V
R
V
leading, then error information is provided by φ pulsing low.
V
φ
R
remains essentially high.
POWER SUPPLY
If the frequency f is less than f or if the phase of f is
V
R
V
lagging, then error information is provided by φ pulsing low.
R
V
DD
φ
V
remains essentially high.
Positive Power Supply (PDIP, SOG – Pin 5)
If the frequency of f = f and both are in phase, then both
V
R
φ
V
and φ remain high except for a small minimum time
The positive power supply potential. This pin may range
R
period when both pulse low in phase.
from + 3 to + 9 V with respect to V
.
SS
LD
V
SS
Lock Detector Output (PDIP – Pin 8, SOG – Pin 9)
Negative Power Supply (PDIP, SOG – Pin 7)
Essentially a high level when loop is locked (f , f of same
R V
phase and frequency). LD pulses low when loop is out of
lock.
The most negative supply potential. This pin is usually
ground.
TYPICAL APPLICATIONS
4.0 MHz
UHF/VHF
TUNER OR
CATV
φ
FRONT END
–
+
R
f
in
MC12073/74
PRESCALER
MC145155–2
φ
V
1/2 MC1458*
DATA
CLK
ENB
CMOS
MPU/MCU
3
MC14489
KEYBOARD
LED DISPLAY
* The φ and φ outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page
R
V
foradditionalinformation.Theφ andφ outputsswingrail–to–rail. Therefore, theusershouldbecarefulnottoexceedthecommon
R
V
mode input range of the op amp used in the combiner/loop filter.
Figure 1. Microprocessor–Controlled TV/CATV Tuning System with Serial Interface
MOTOROLA
MC145151–2 through MC145158–2
11
2.56 MHz
φ
TO
AM/FM
OSCILLATORS
–
+
f
R
in
MC12019
20 PRESCALER
FM
OSC
MC145155–2
φ
V
÷
1/2 MC1458*
AM
OSC
DATA
CLK
ENB
CMOS
MPU/MCU
KEYBOARD
TO DISPLAY
* The φ and φ outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page
R
V
foradditionalinformation.Theφ andφ outputsswingrail–to–rail. Therefore, theusershouldbecarefulnottoexceedthecommon
R
V
mode input range of the op amp used in the combiner/loop filter.
Figure 2. AM/FM Radio Synthesizer
MC145155–2 Data Sheet Continued on Page 23
MC145151–2 through MC145158–2
12
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC DIP
CASE 738
Interfaces with Dual–Modulus Prescalers
20
1
The MC145156–2 is programmed by a clocked, serial input, 19–bit data
stream. The device features consist of a reference oscillator, selectable–refer-
ence divider, digital–phase detector, 10–bit programmable divide–by–N
counter, 7–bit programmable divide–by–A counter, and the necessary shift
register and latch circuitry for accepting serial input data.
The MC145156–2 is an improved–performance drop–in replacement for the
MC145156–1. Power consumption has decreased and ESD and latch–up
performance have improved.
DW SUFFIX
SOG PACKAGE
CASE 751D
20
1
ORDERING INFORMATION
MC145156P2
MC145156DW2 SOG Package
Plastic DIP
•
•
•
•
•
•
•
•
•
•
•
•
•
Operating Temperature Range: – 40 to 85°C
Low Power Consumption Through Use of CMOS Technology
3.0 to 9.0 V Supply Range
On– or Off–Chip Reference Oscillator Operation with Buffered Output
Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
Lock Detect Signal
PIN ASSIGNMENT
RA1
RA2
1
2
20
19
RA0
Two Open–Drain Switch Outputs
Dual Modulus/Serial Programming
OSC
in
φ
3
4
18
17
OSC
V
out
8 User–Selectable ÷ R Values: 8, 64, 128, 256, 640, 1000, 1024, 2048
÷ N Range = 3 to 1023, ÷ A Range = 0 to 127
“Linearized” Digital Phase Detector Enhances Transfer Function Linearity
Two Error Signal Options: Single–Ended (Three–State) or Double–Ended
Chip Complexity: 6504 FETs or 1626 Equivalent Gates
φ
REF
R
out
V
5
6
16
15
TEST
DD
PD
V
SW2
SW1
ENB
DATA
CLK
out
SS
7
14
13
12
11
MC
LD
8
9
f
10
in
REV 1
8/95
Motorola, Inc. 1995
MC145156–2 BLOCK DIAGRAM
RA2
RA1
RA0
12 x 8 ROM REFERENCE DECODER
12
LOCK
DETECT
12–BIT
÷
R COUNTER
OSC
in
LD
PD
OSC
REF
out
f
PHASE
DETECTOR
A
CONTROL LOGIC
R
out
out
f
V
MC
PHASE
DETECTOR
B
7–BIT
÷
A COUNTER
10–BIT
÷
N COUNTER
10
f
φ
in
V
φ
R
7
V
SW2
SW1
DD
ENB
LATCH
÷
A COUNTER LATCH
7
÷
N COUNTER LATCH
10
DATA
CLK
2–BIT SHIFT
REGISTER
7–BIT SHIFT REGISTER
10–BIT SHIFT REGISTER
PIN DESCRIPTIONS
÷
A COUNTER BITS
÷
N COUNTER BITS
INPUT PINS
f
in
Frequency Input (Pin 10)
Input to the positive edge triggered ÷ N and ÷ A counters.
LAST DATA BIT IN (BIT NO. 19)
FIRST DATA BIT IN (BIT NO. 1)
f
is typically derived from a dual–modulus prescaler and is
ac coupled into the device. For larger amplitude signals
(standard CMOS logic levels), dc coupling may be used.
in
ENB
Latch Enable Input (Pin 13)
RA0, RA1, RA2
When high (1), ENB transfers the contents of the shift reg-
ister into the latches, and to the programmable counter in-
puts, and the switch outputs SW1 and SW2. When low (0),
ENB inhibits the above action and thus allows changes to be
made in the shift register data without affecting the counter
programming and switch outputs. An on–chip pull–up esta-
blishes a continuously high level for ENB when no external
signal is applied. ENB is normally low and is pulsed high to
transfer data to the latches.
Reference Address Inputs (Pins 20, 1, 2)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider, as
defined by the table below:
Total
Divide
Value
Reference Address Code
RA2
RA1
RA0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
64
OSC , OSC
in
out
Reference Oscillator Input/Output (Pins 19, 18)
128
256
640
1000
1024
2048
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSC to ground and OSC
to ground.
in
out
OSC may also serve as the input for an externally–gener-
in
ated reference signal. This signal is typically ac coupled to
CLK, DATA
OSC , but for larger amplitude signals (standard CMOS
in
Shift Register Clock, Serial Data Inputs (Pins 11, 12)
logic levels) dc coupling may also be used. In the external
Each low–to–high transition clocks one bit into the on–chip
19–bit shift register. The data input provides programming in-
formation for the 10–bit ÷ N counter, the 7–bit ÷ A counter,
and the two switch signals SW1 and SW2. The entry format
is as follows:
reference mode, no connection is required to OSC
.
out
TEST
Factory Test Input (Pin 16)
Used in manufacturing. Must be left open or tied to V
SS
.
MC145151–2 through MC145158–2
14
MOTOROLA
OUTPUT PINS
PD
preset to their respective programmed values, and the above
sequence repeated. This provides for a total programmable
out
divide value (N ) = N P + A where P and P + 1 represent the
T
Phase Detector A Output (Pin 6)
dual–modulus prescaler divide values respectively for high
and low MC levels, N the number programmed into the ÷ N
counter, and A the number programmed into the ÷ A counter.
Three–state output of phase detector for use as loop–error
signal. Double–ended outputs are also available for this pur-
pose (see φ and φ ).
V
R
LD
Frequency f > f or f Leading: Negative Pulses
V
R
V
V
Lock Detector Output (Pin 9)
Frequency f < f or f Lagging: Positive Pulses
V
R
Essentially a high level when loop is locked (f , f of same
R V
phase and frequency). LD pulses low when loop is out of
lock.
Frequency f = f and Phase Coincidence: High–Imped-
V
R
ance State
φ , φ
R
V
SW1, SW2
Band Switch Outputs (Pins 14, 15)
Phase Detector B Outputs (Pins 4, 3)
These phase detector outputs can be combined externally
for a loop–error signal. A single–ended output is also avail-
SW1 and SW2 provide latched open–drain outputs corre-
sponding to data bits numbers one and two. These outputs
can be tied through external resistors to voltages as high as
able for this purpose (see PD
).
out
If frequency f is greater than f or if the phase of f is
V
R
V
15 V, independent of the V
supply voltage. These are
DD
leading, then error information is provided by φ pulsing low.
V
typically used for band switch functions. A logic 1 causes the
output to assume a high–impedance state, while a logic 0
causes the output to be low.
φ
R
remains essentially high.
If the frequency f is less than f or if the phase of f is
V
R
V
lagging, then error information is provided by φ pulsing low.
R
φ
V
remains essentially high.
REF
out
If the frequency of f = f and both are in phase, then both
V
R
Buffered Reference Oscillator Output (Pin 17)
φ
V
and φ remain high except for a small minimum time
R
Buffered output of on–chip reference oscillator or exter-
nally provided reference–input signal.
period when both pulse low in phase.
MC
POWER SUPPLY
Dual–Modulus Prescale Control Output (Pin 8)
V
DD
Signal generated by the on–chip control logic circuitry for
controlling an external dual–modulus prescaler. The MC
level will be low at the beginning of a count cycle and will
remain low until the ÷ A counter has counted down from its
programmed value. At this time, MC goes high and remains
high until the ÷ N counter has counted the rest of the way
down from its programmed value (N – A additional counts
since both ÷ N and ÷ A are counting down during the first por-
tion of the cycle). MC is then set back low, the counters
Positive Power Supply (Pin 5)
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to V
.
SS
V
SS
Negative Power Supply (Pin 7)
The most negative supply potential. This pin is usually
ground.
MOTOROLA
MC145151–2 through MC145158–2
15
TYPICAL APPLICATIONS
+ 12 V
LOCK DETECT SIGNAL
3.2 MHz
NOTES 1
AND 2
FM B +
+ 12 V
AM B +
+ V
OSC
OSC
RA2 RA1 RA0 LD SW1 SW2
in
out
OPTIONAL
LOOP
ERROR SIGNAL
PD
out
V
V
DD
–
+
φ
MC145156–2
R
SS
VCO
REF
φ
V
out
1/2 MC1458
NOTE 3
f
CLK
DATA
ENB
in
MC
KEY–
BOARD
CMOS MPU/MCU
MC12019
20/21 DUAL MODULUS PRESCALER
÷
TO DISPLAY DRIVER (e.g., MC14489)
NOTES:
1. For AM: channel spacing = 5 kHz, ÷ R = ÷ 640 (code 100).
2. For FM: channel spacing = 25 kHz, ÷ R = ÷ 128 (code 010).
3. Theφ andφ outputsarefedtoanexternalcombiner/loopfilter. SeethePhase–LockedLoop—Low–PassFilterDesignpage
R
V
for additional information. The φ and φ outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the
R
V
common mode input range of the op amp used in the combiner/loop filter.
Figure 1. AM/FM Radio Broadcast Synthesizer
3.2 MHz (NOTE 3)
VCO RANGE
NAV = 01
COM = 10
NAV: 97.300 – 107.250 MHz
COM–T: 118.000 – 135.975 MHz
COM–R: 139.400 – 157.375 MHz
LOCK DETECT SIGNAL
+ V
OSC
OSC
out
RA2 RA1 RA0 LD SW1 SW2
in
PD
out
V
V
DD
–
+
MC145156–2
φ
R
SS
VCO
REF
φ
V
out
MC33171
NOTE 5
f
CLK
DATA
ENB
in
MC
CMOS MPU/MCU
R/T
MC12016 (NOTES 2 AND 4)
40/41 DUAL MODULUS PRESCALER
÷
CHANNEL
SELECTION
TO DISPLAY DRIVER
(e.g., MC14489)
NOTES:
1. For NAV: f = 50 kHz, ÷ R = 64 using 10.7 MHz lowside injection, N
= 1946 – 2145.
total
R
For COM–T: f = 25 kHz, ÷ R = 128, N
For COM–R: f = 25 kHz, ÷ R = 128, using 21.4 MHz highside injection, N
= 4720 – 5439.
R
total
= 5576 – 6295.
R
total
2. A ÷ 32/33 dual modulus approach is provided by substituting an MC12015 for the MC12016. The devices are pin equivalent.
3. A 6.4 MHz oscillator crystal can be used by selecting ÷ R = 128 (code 010) for NAV and ÷ R = 256 (code 011) for COM.
4. MC12013 + MC10131 combination may also be used to form the ÷ 40/41 prescaler.
5. The φ and φ outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design
R
V
page for additional information. The φ and φ outputs swing rail–to–rail. Therefore, the user should be careful not to exceed
R
V
the common mode input range of the op amp used in the combiner/loop filter.
Figure 2. Avionics Navigation or Communication Synthesizer
MC145156–2 Data Sheet Continued on Page 23
MC145151–2 through MC145158–2
16
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC DIP
CASE 648
Interfaces with Single–Modulus Prescalers
16
1
The MC145157–2 has a fully programmable 14–bit reference counter, as well
as a fully programmable ÷ N counter. The counters are programmed serially
through a common data input and latched into the appropriate counter latch,
according to the last data bit (control bit) entered.
The MC145157–2 is an improved–performance drop–in replacement for the
MC145157–1. Power consumption has decreased and ESD and latch–up
performance have improved.
DW SUFFIX
SOG PACKAGE
CASE 751G
16
1
ORDERING INFORMATION
•
•
•
•
•
•
•
•
•
•
•
•
Operating Temperature Range: – 40 to 85°C
Low Power Consumption Through Use of CMOS Technology
3.0 to 9.0 V Supply Range
Fully Programmable Reference and ÷ N Counters
÷ R Range = 3 to 16383
MC145157P2
Plastic DIP
MC145157DW2 SOG Package
PIN ASSIGNMENT
÷ N Range = 3 to 16383
f
V
and f Outputs
R
OSC
in
1
2
16
15
φ
R
Lock Detect Signal
Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
“Linearized” Digital Phase Detector
Single–Ended (Three–State) or Double–Ended Phase Detector Outputs
Chip Complexity: 6504 FETs or 1626 Equivalent Gates
OSC
φ
V
out
f
3
4
14
13
REF
V
out
V
f
R
DD
out
PD
5
6
12
11
S/R
out
V
ENB
DATA
CLK
SS
LD
7
8
10
9
f
in
REV 1
8/95
Motorola, Inc. 1995
MC145157–2 BLOCK DIAGRAM
14–BIT SHIFT REGISTER
14
f
R
ENB
REFERENCE COUNTER LATCH
14
LOCK
DETECT
LD
PD
OSC
14–BIT
÷
R COUNTER
in
out
out
PHASE
DETECTOR
A
OSC
REF
out
PHASE
DETECTOR
B
φ
V
14–BIT
÷
N COUNTER
14
f
in
φ
R
÷
N COUNTER LATCH
14
f
V
1–BIT
CONTROL
S/R
DATA
CLK
S/R
out
14–BIT SHIFT REGISTER
if the control bit is at a logic low. A logic low on this pin allows
the user to change the data in the shift registers without
affecting the counters. ENB is normally low and is pulsed
high to transfer data to the latches.
PIN DESCRIPTIONS
INPUT PINS
f
in
Frequency Input (Pin 8)
OSC , OSC
in
out
Reference Oscillator Input/Output (Pins 1, 2)
Input frequency from VCO output. A rising edge signal on
this input decrements the ÷ N counter. This input has an
inverter biased in the linear region to allow use with ac
coupled signals as low as 500 mV p–p. For larger amplitude
signals (standard CMOS logic levels), dc coupling may be
used.
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSC to ground and OSC
to ground.
in
out
OSC may also serve as the input for an externally–gener-
in
ated reference signal. This signal is typically ac coupled to
CLK, DATA
OSC , but for larger amplitude signals (standard CMOS
in
Shift Clock, Serial Data Inputs (Pins 9, 10)
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC
.
Each low–to–high transition of the clock shifts one bit of
data into the on–chip shift registers. The last data bit entered
determines which counter storage latch is activated; a logic 1
selects the reference counter latch and a logic 0 selects the
÷ N counter latch. The entry format is as follows:
out
OUTPUT PINS
PD
out
Single–Ended Phase Detector A Output (Pin 5)
This single–ended (three–state) phase detector output
produces a loop–error signal that is used with a loop filter to
control a VCO.
Frequency f > f or f Leading: Negative Pulses
V
R
V
Frequency f < f or f Lagging: Positive Pulses
V
R
V
FIRST DATA BIT INTO SHIFT REGISTER
Frequency f = f and Phase Coincidence: High–Imped-
V
R
ance State
ENB
Latch Enable Input (Pin 11)
φ , φ
R
V
Double–Ended Phase Detector B Outputs (Pins 16, 15)
A logic high on this pin latches the data from the shift regis-
ter into the reference divider or ÷ N latches depending on the
control bit. The reference divider latches are activated if the
control bit is at a logic high and the ÷ N latches are activated
These outputs can be combined externally for a loop–error
signal. A single–ended output is also available for this pur-
pose (see PD
).
out
MC145151–2 through MC145158–2
18
MOTOROLA
If frequency f is greater than f or if the phase of f is
REF
out
V
R
V
leading, then error information is provided by φ pulsing low.
Buffered Reference Oscillator Output (Pin 14)
V
φ
remains essentially high.
R
This output can be used as a second local oscillator, refer-
ence oscillator to another frequency synthesizer, or as the
system clock to a microprocessor controller.
If the frequency f is less than f or if the phase of f is
V
R
V
lagging, then error information is provided by φ pulsing low.
R
φ
remains essentially high.
V
If the frequency of f = f and both are in phase, then both
S/R
out
V
R
φ
and φ remain high except for a small minimum time
Shift Register Output (Pin 12)
V
R
period when both pulse low in phase.
This output can be connected to an external shift register
to provide band switching, control information, and counter
programming code checking.
f , f
R
V
R Counter Output, N Counter Output (Pins 13, 3)
Buffered, divided reference and f frequency outputs. The
in
R
counter outputs respectively, allowing the counters to be
used independently, as well as monitoring the phase detector
inputs.
POWER SUPPLY
f
and f outputs are connected internally to the ÷ R and ÷ N
V
V
DD
Positive Power Supply (Pin 4)
The positive power supply potential. This pin may range
from +3 to +9 V with respect to V
.
SS
LD
V
Lock Detector Output (Pin 7)
SS
Negative Power Supply (Pin 6)
This output is essentially at a high level when the loop is
locked (f , f of same phase and frequency), and pulses low
when loop is out of lock.
The most negative supply potential. This pin is usually
ground.
R V
MC145157–2 Data Sheet Continued on Page 23
MOTOROLA
MC145151–2 through MC145158–2
19
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC DIP
CASE 648
Interfaces with Dual–Modulus Prescalers
16
1
The MC145158–2 has a fully programmable 14–bit reference counter, as well
as fully programmable ÷ N and ÷ A counters. The counters are programmed
serially through a common data input and latched into the appropriate counter
latch, according to the last data bit (control bit) entered.
The MC145158–2 is an improved–performance drop–in replacement for the
MC145158–1. Power consumption has decreased and ESD and latch–up
performance have improved.
DW SUFFIX
SOG PACKAGE
CASE 751G
16
1
ORDERING INFORMATION
•
•
•
•
•
•
•
•
•
•
•
•
•
Operating Temperature Range: – 40 to 85°C
Low Power Consumption Through Use of CMOS Technology
3.0 to 9.0 V Supply Range
Fully Programmable Reference and ÷ N Counters
÷ R Range = 3 to 16383
MC145158P2
Plastic DIP
MC145158DW2 SOG Package
PIN ASSIGNMENT
÷ N Range = 3 to 1023
Dual Modulus Capability; ÷ A Range = 0 to 127
OSC
in
1
2
16
15
φ
R
f
V
and f Outputs
R
OSC
φ
V
out
Lock Detect Signal
Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
“Linearized” Digital Phase Detector
Single–Ended (Three–State) or Double–Ended Phase Detector Outputs
Chip Complexity: 6504 FETs or 1626 Equivalent Gates
f
3
4
14
13
REF
out
V
V
f
R
DD
out
PD
5
6
12
11
MC
V
ENB
SS
LD
7
8
10
9
DATA
CLK
f
in
REV 1
8/95
Motorola, Inc. 1995
MC145158–2 BLOCK DIAGRAM
14–BIT SHIFT REGISTER
14
f
R
ENB
REFERENCE COUNTER LATCH
14
LOCK
DETECT
LD
PD
OSC
14–BIT
÷
R COUNTER
in
out
out
PHASE
DETECTOR
A
OSC
REF
out
CONTROL LOGIC
7–BIT
÷
A
10–BIT
÷
N
PHASE
DETECTOR
B
φ
V
f
in
COUNTER
COUNTER
φ
R
7
10
÷
A COUNTER
LATCH
÷
N COUNTER
LATCH
f
V
7
10
1–BIT
CONTROL
S/R
DATA
CLK
MC
7–BIT S/R
10–BIT S/R
PIN DESCRIPTIONS
÷
A
÷
N
INPUT PINS
f
in
Frequency Input (Pin 8)
Input frequency from VCO output. A rising edge signal on
this input decrements the ÷ A and ÷ N counters. This input
has an inverter biased in the linear region to allow use with
ac coupled signals as low as 500 mV p–p. For larger ampli-
tude signals (standard CMOS logic levels), dc coupling may
be used.
FIRST DATA BIT INTO SHIFT REGISTER
ENB
Latch Enable Input (Pin 11)
A logic high on this pin latches the data from the shift regis-
ter into the reference divider or ÷ N, ÷ A latches depending on
the control bit. The reference divider latches are activated if
the control bit is at a logic high and the ÷ N, ÷ A latches are
activated if the control bit is at a logic low. A logic low on this
pin allows the user to change the data in the shift registers
without affecting the counters. ENB is normally low and is
pulsed high to transfer data to the latches.
CLK, DATA
Shift Clock, Serial Data Inputs (Pins 9, 10)
Each low–to–high transition of the CLK shifts one bit of
data into the on–chip shift registers. The last data bit entered
determines which counter storage latch is activated; a logic 1
selects the reference counter latch and a logic 0 selects the
÷ A, ÷ N counter latch. The data entry format is as follows:
OSC , OSC
in
out
Reference Oscillator Input/Output (Pins 1, 2)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
÷
R
connected from OSC to ground and OSC
to ground.
in
out
OSC may also serve as the input for an externally–gener-
in
ated reference signal. This signal is typically ac coupled to
OSC , but for larger amplitude signals (standard CMOS log-
in
ic levels) dc coupling may also be used. In the external refer-
FIRST DATA BIT INTO SHIFT REGISTER
ence mode, no connection is required to OSC
.
out
MOTOROLA
MC145151–2 through MC145158–2
21
OUTPUT PINS
PD
dual–modulus prescaler divide values respectively for high
and low modulus control levels, N the number programmed
into the ÷ N counter, and A the number programmed into the
÷ A counter. Note that when a prescaler is needed, the dual–
modulus version offers a distinct advantage. The dual–
modulus prescaler allows a higher reference frequency at
the phase detector input, increasing system performance ca-
pability, and simplifying the loop filter design.
out
Phase Detector A Output (Pin 5)
This single–ended (three–state) phase detector output
produces a loop–error signal that is used with a loop filter to
control a VCO.
Frequency f > f or f Leading: Negative Pulses
V
R
R
R
V
V
Frequency f < f or f Lagging: Positive Pulses
V
f , f
R
V
Frequency f = f and Phase Coincidence: High–Imped-
V
R Counter Output, N Counter Output (Pins 13, 3)
ance State
Buffered, divided reference and f frequency outputs. The
in
and f outputs are connected internally to the ÷ R and
f
R
V
φ , φ
R
V
÷ N counter outputs respectively, allowing the counters to be
used independently, as well as monitoring the phase detector
inputs.
Phase Detector B Outputs (Pins 16, 15)
Double–ended phase detector outputs. These outputs can
be combined externally for a loop–error signal. A single–
ended output is also available for this purpose (see PD
).
out
If frequency f is greater than f or if the phase of f is
LD
V
R
V
Lock Detector Output (Pin 7)
leading, then error information is provided by φ pulsing low.
V
This output is essentially at a high level when the loop is
locked (f , f of same phase and frequency), and pulses low
when loop is out of lock.
φ
remains essentially high.
R
R V
If the frequency f is less than f or if the phase of f is
V
R
V
lagging, then error information is provided by φ pulsing low.
R
φ
V
remains essentially high.
REF
out
If the frequency of f = f and both are in phase, then both
and φ remain high except for a small minimum time
R
V
R
Buffered Reference Oscillator Output (Pin 14)
φ
V
period when both pulse low in phase.
This output can be used as a second local oscillator, refer-
ence oscillator to another frequency synthesizer, or as the
system clock to a microprocessor controller.
MC
Dual–Modulus Prescale Control Output (Pin 12)
POWER SUPPLY
This output generates a signal by the on–chip control logic
circuitry for controlling an external dual–modulus prescaler.
The MC level is low at the beginning of a count cycle and
remains low until the ÷ A counter has counted down from its
programmed value. At this time, MC goes high and remains
high until the ÷ N counter has counted the rest of the way
down from its programmed value (N – A additional counts
since both ÷ N and ÷ A are counting down during the first por-
tion of the cycle). MC is then set back low, the counters pre-
set to their respective programmed values, and the above
sequence repeated. This provides for a total programmable
V
DD
Positive Power Supply (Pin 4)
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to V
.
SS
V
SS
Negative Power Supply (Pin 6)
The most negative supply potential. This pin is usually
ground.
divide value (N ) = N P + A where P and P + 1 represent the
T
MC145151–2 through MC145158–2
22
MOTOROLA
MC14515X–2 FAMILY CHARACTERISTICS AND DESCRIPTIONS
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
These devices contain protection circuitry to
protect against damage due to high static
voltages or electric fields. However, precau-
tionsmustbetakentoavoidapplicationsofany
voltage higher than maximum rated voltages
to these high–impedance circuits. For proper
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
V
DD
– 0.5 to + 10.0
V , V
in out
Input or Output Voltage (DC or Transient)
except SW1, SW2
– 0.5 to V
DD
+ 0.5
V
operation, V and V
to the range V
SS
except for SW1 and SW2.
SW1 and SW2 can be tied through external
resistors to voltages as high as 15 V, indepen-
dent of the supply voltage.
should be constrained
≤ (V or V ) ≤ V
in out DD
V
Output Voltage (DC or Transient),
– 0.5 to + 15
V
in
out
out
SW1, SW2 (R
pull–up
= 4.7 kΩ)
I , I
in out
Input or Output Current (DC or Transient),
per Pin
± 10
mA
I
, I
Supply Current, V
DD
or V
SS
Pins
± 30
500
mA
mW
°C
DD SS
Unused inputs must always be tied to an
P
Power Dissipation, per Package†
Storage Temperature
D
appropriatelogicvoltagelevel(e.g.,eitherV
SS
orV ),exceptforinputswithpull–updevices.
DD
T
stg
– 65 to + 150
260
Unused outputs must be left open.
T
Lead Temperature, 1 mm from Case for
10 seconds
°C
L
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
†Power Dissipation Temperature Derating:
Plastic DIP: – 12 mW/°C from 65 to 85°C
SOG Package: – 7 mW/°C from 65 to 85°C
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 40°C
25°C
Max
85°C
Max
V
DD
V
Symbol
Parameter
Test Condition
Unit
Min
Max
Min
Min
V
Power Supply Voltage
Range
—
3
9
3
9
3
9
V
DD
ss
I
Dynamic Supply Current
f
= OSC = 10 MHz,
in
3
5
9
—
—
—
3.5
10
30
—
—
—
3
7.5
24
—
—
—
3
7.5
24
mA
in
1 V p–p ac coupled sine
wave
R = 128, A = 32, N = 128
I
Quiescent Supply Current
(not including pull–up
current component)
V
= V
DD
= 0 µA
or V
SS
3
5
9
—
—
—
800
1200
1600
—
—
—
800
1200
1600
—
—
—
1600
2400
3200
µA
SS
in
I
out
V
Input Voltage — f , OSC
in
Input ac coupled sine wave
—
500
—
500
—
500
—
mV p–p
V
in
in
V
IL
Low–Level Input Voltage
— f , OSC
in in
V
V
out
V
≥ 2.1 V
≥ 3.5 V
≥ 6.3 V square wave
Input dc
coupled
3
5
9
—
—
—
0
0
0
—
—
—
0
0
0
—
—
—
0
0
0
out
out
V
High–Level Input Voltage
V
≤ 0.9 V
≤ 1.5 V
≤ 2.7 V square wave
Input dc
coupled
3
5
9
3.0
5.0
9.0
—
—
—
3.0
5.0
9.0
—
—
—
3.0
5.0
9.0
—
—
—
V
V
V
IH
out
— f , OSC
V
out
in in
V
out
V
Low–Level Input Voltage
3
5
9
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
IL
— except f , OSC
in in
V
IH
High–Level Input Voltage
3
5
9
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
— except f , OSC
in in
I
Input Current (f , OSC )
V
V
= V
= V
or V
SS
9
9
± 2
± 50
± 2
± 25
± 2
± 22
µA
µA
in
in
in
in
DD
I
IL
Input Leakage Current
(Data, CLK, ENB —
without pull–ups)
—
– 0.3
—
– 0.1
—
– 1.0
in
SS
I
IH
Input Leakage Current (all
V
in
= V
9
—
0.3
—
0.1
—
1.0
µA
DD
inputs except f , OSC )
in in
(continued)
MOTOROLA
MC145151–2 through MC145158–2
23
DC ELECTRICAL CHARACTERISTICS (continued)
– 40°C
25°C
85°C
V
DD
V
Symbol
Parameter
Test Condition
Unit
Min
Max
Min
Max
Min
Max
I
IL
Pull–up Current (all inputs
with pull–ups)
V
in
= V
9
– 20
– 400
– 20
– 200
– 20
– 170
µA
SS
C
Input Capacitance
Low–Level Output
Voltage — OSC
out
—
—
10
—
10
—
10
pF
V
in
V
OL
I
V
≈ 0 µA
= V
DD
3
5
9
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
out
in
V
OH
High–Level Output
Voltage — OSC
I
V
≈ 0 µA
= V
SS
3
5
9
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
V
out
in
out
V
Low–Level Output
Voltage — Other Outputs
I
≈ 0 µA
≈ 0 µA
3
5
9
—
—
—
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
V
OL
out
V
OH
High–Level Output
Voltage — Other Outputs
I
3
5
9
2.95
4.95
8.95
—
—
—
2.95
4.95
8.95
—
—
—
2.95
4.95
8.95
—
—
—
V
out
V
Drain–to–Source
Breakdown Voltage —
SW1, SW2
R
= 4.7 kΩ
pull–up
—
15
—
15
—
15
—
V
(BR)DSS
I
Low–Level Sinking
Current — MC
V
= 0.3 V
= 0.4 V
= 0.5 V
3
5
9
1.30
1.90
3.80
—
—
—
1.10
1.70
3.30
—
—
—
0.66
1.08
2.10
—
—
—
mA
mA
mA
mA
mA
mA
mA
OL
out
V
out
V
out
I
High–Level Sourcing
Current — MC
V
= 2.7 V
= 4.6 V
= 8.5 V
3
5
9
– 0.60
– 0.90
– 1.50
—
—
—
– 0.50
– 0.75
– 1.25
—
—
—
– 0.30
– 0.50
– 0.80
—
—
—
OH
out
V
V
out
out
I
Low–Level Sinking
Current — LD
V
= 0.3 V
= 0.4 V
= 0.5 V
3
5
9
0.25
0.64
1.30
—
—
—
0.20
0.51
1.00
—
—
—
0.15
0.36
0.70
—
—
—
OL
out
V
V
out
out
I
High–Level Sourcing
Current — LD
V
= 2.7 V
= 4.6 V
= 8.5 V
3
5
9
– 0.25
– 0.64
– 1.30
—
—
—
– 0.20
– 0.51
– 1.00
—
—
—
– 0.15
– 0.36
– 0.70
—
—
—
OH
out
V
V
out
out
I
Low–Level Sinking
Current — SW1, SW2
V
= 0.3 V
= 0.4 V
= 0.5 V
3
5
9
0.80
1.50
3.50
—
—
—
0.48
0.90
2.10
—
—
—
0.24
0.45
1.05
—
—
—
OL
OL
OH
out
V
out
V
out
I
Low–Level Sinking
Current — Other Outputs
V
= 0.3 V
= 0.4 V
= 0.5 V
3
5
9
0.44
0.64
1.30
—
—
—
0.35
0.51
1.00
—
—
—
0.22
0.36
0.70
—
—
—
out
V
out
V
out
I
High–Level Sourcing
Current — Other Outputs
V
= 2.7 V
= 4.6 V
= 8.5 V
3
5
9
– 0.44
– 0.64
– 1.30
—
—
—
– 0.35
– 0.51
– 1.00
—
—
—
– 0.22
– 0.36
– 0.70
—
—
—
out
V
out
V
out
I
I
Output Leakage Current —
PD
out
V
= V
or V
SS
9
—
—
—
± 0.3
± 0.3
10
—
—
—
± 0.1
± 0.1
10
—
—
—
± 1.0
± 3.0
10
µA
µA
pF
OZ
out DD
Output in Off State
Output Leakage Current —
SW1, SW2
V
out
= V or V
9
OZ
DD SS
Output in Off State
C
Output Capacitance —
PD
out
PD — Three–State
—
out
out
MC145151–2 through MC145158–2
24
MOTOROLA
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 10 ns)
L
r
f
V
DD
V
Guaranteed Limit
Guaranteed Limit
25°C
– 40 to 85°C
Symbol
, t
Parameter
Unit
t
Maximum Propagation Delay, f to MC
in
3
5
9
110
60
35
120
70
40
ns
PLH PHL
(Figures 1 and 4)
t
Maximum Propagation Delay, ENB to SW1, SW2
(Figures 1 and 5)
3
5
9
160
80
50
180
95
60
ns
ns
ns
ns
ns
ns
PHL
t
w
Output Pulse Width, φ , φ , and LD with f in Phase with f
V
3
5
9
25 to 200
20 to 100
10 to 70
25 to 260
20 to 125
10 to 80
R
V
R
(Figures 2 and 4)
t
t
Maximum Output Transition Time, MC
(Figures 3 and 4)
3
5
9
115
60
40
115
75
60
TLH
Maximum Output Transition Time, MC
(Figures 3 and 4)
3
5
9
60
34
30
70
45
38
THL
t
, t
TLH THL
Maximum Output Transition Time, LD
(Figures 3 and 4)
3
5
9
180
90
70
200
120
90
t
, t
TLH THL
Maximum Output Transition Time, Other Outputs
(Figures 3 and 4)
3
5
9
160
80
60
175
100
65
SWITCHING WAVEFORMS
V
DD
INPUT
50%
— V
SS
t
w
t
t
PHL
PLH
50%
φ , φ , LD*
R V
OUTPUT
50%
* f in phase with f .
R
V
Figure 1.
Figure 2.
t
t
THL
TLH
ANY
OUTPUT
90%
10%
Figure 3.
V
DD
TEST POINT
15 k
TEST POINT
OUTPUT
Ω
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
C *
C *
L
L
* Includes all probe and fixture capacitance.
* Includes all probe and fixture capacitance.
Figure 4. Test Circuit
Figure 5. Test Circuit
MOTOROLA
MC145151–2 through MC145158–2
25
TIMING REQUIREMENTS (Input t = t = 10 ns unless otherwise indicated)
r
f
V
DD
V
Guaranteed Limit
Guaranteed Limit
25°C
– 40 to 85°C
Symbol
Parameter
Unit
f
Serial Data Clock Frequency, Assuming 25% Duty Cycle
3
5
9
dc to 5.0
dc to 7.1
dc to 10
dc to 3.5
dc to 7.1
dc to 10
MHz
clk
NOTE: Refer to CLK t
(Figure 6)
below
w(H)
t
Minimum Setup Time, Data to CLK
(Figure 7)
3
5
9
30
20
18
30
20
18
ns
ns
ns
ns
ns
µs
su
t
Minimum Hold Time, CLK to Data
(Figure 7)
3
5
9
40
20
15
40
20
15
h
t
su
Minimum Setup Time, CLK to ENB
(Figure 7)
3
5
9
70
32
25
70
32
25
t
Minimum Recovery Time, ENB to CLK
(Figure 7)
3
5
9
5
10
20
5
10
20
rec
t
Minimum Pulse Width, CLK and ENB
(Figure 6)
3
5
9
50
35
25
70
35
25
w(H)
t , t
r f
Maximum Input Rise and Fall Times — Any Input
(Figure 8)
3
5
9
5
4
2
5
4
2
SWITCHING WAVEFORMS
— V
DD
t
DATA
w(H)
50%
— V
DD
V
SS
CLK,
ENB
t
su
50%
t
h
V
*
SS
1
— V
V
DD
4 f
clk
LAST
CLK
FIRST
CLK
CLK
ENB
50%
SS
*Assumes 25% Duty Cycle.
t
t
su
rec
— V
V
DD
Figure 6.
50%
SS
PREVIOUS
DATA
LATCHED
t
t
f
t
ANY
OUTPUT
— V
DD
90%
10%
Figure 7.
V
SS
Figure 8.
MC145151–2 through MC145158–2
26
MOTOROLA
FREQUENCY CHARACTERISTICS (Voltages References to V , C = 50 pF, Input t = t =10 ns unless otherwise indicated)
SS
L
r
f
– 40°C
25°C
Max
85°C
Max
V
DD
V
Symbol
Parameter
Input Frequency
(f , OSC )
in in
Test Condition
Min
Max
Min
Min
Unit
f
i
R ≥ 8, A ≥ 0, N ≥ 8
= 500 mV p–p
ac coupled sine wave
3
5
9
—
—
—
6
15
15
—
—
—
6
15
15
—
—
—
6
15
15
MHz
V
in
R ≥ 8, A ≥ 0, N ≥ 8
3
5
9
—
—
—
12
22
25
—
—
—
12
20
22
—
—
—
7
20
22
MHz
MHz
V
= 1 V p–p ac coupled
in
sine wave
R ≥ 8, A ≥ 0, N ≥ 8
3
5
9
—
—
—
13
25
25
—
—
—
12
22
25
—
—
—
8
22
25
V
= V
DD
to V
SS
in
dc coupled square wave
NOTE: Usually, the PLL’s propagation delay from f to MC plus the setup time of the prescaler determines the upper frequency limit of the system.
in
The upper frequency limit is found with the following formula: f = P/(t + t ) where f is the upper frequency in Hz, P is the lower of the dual
P
set
modulus prescaler ratios, t is the f to MC propagation delay in seconds, and t
in
is the prescaler setup time in seconds.
P
set
For example, with a 5 V supply, the f to MC delay is 70 ns. If the MC12028A prescaler is used, the setup time is 16 ns. Thus, if the 64/65
ratio is utilized, the upper frequency limit is f = P/(t + t ) = 64/(70 + 16) = 744 MHz.
in
P
set
f
V
R
H
REFERENCE
OSC
÷
R
V
V
L
f
H
V
FEEDBACK
(f
÷
N)
V
V
in
L
H
*
HIGH IMPEDANCE
PD
out
V
V
L
H
φ
R
V
V
L
H
φ
V
V
V
L
H
LD
V
L
V
H
V
L
= High Voltage Level.
= Low Voltage Level.
* At this point, when both f and f are in phase, the output is forced to near mid–supply.
R
V
NOTE: The PD
generates error pulses during out–of–lock conditions. When locked in phase and frequency the output is high
and the voltage at this pin is determined by the low–pass filter capacitor.
out
Figure 9. Phase Detector/Lock Detector Output Waveforms
MOTOROLA
MC145151–2 through MC145158–2
27
DESIGN CONSIDERATIONS
PHASE–LOCKED LOOP — LOW–PASS FILTER DESIGN
K K
VCO
φ
A)
PD
out
VCO
ω
=
=
n
NR C
R
1
1
φ
—
—
R
C
Nω
n
ζ
φ
2K K
VCO
V
φ
1
F(s) =
R sC + 1
1
PD
B)
VCO
out
K K
VCO
φ
R
ω
ζ
=
1
n
NC(R + R )
1
2
φ
—
—
R
R
2
N
φ
=
0.5
ω
R C +
2
C
V
n
K K
VCO
φ
R sC + 1
2
F(s) =
(R + R )sC + 1
1
2
R
2
K K
PD
—
C)
φ
VCO
out
ω
ζ
=
n
NCR
C
1
R
R
1
_
+
φ
R
ω
R C
n 2
A
VCO
φ
V
=
2
1
ASSUMING GAIN A IS VERY LARGE, THEN:
R sC + 1
R
2
2
C
F(s) =
R sC
1
NOTE: Sometimes R is split into two series resistors, each R ÷ 2. A capacitor C is then placed from the midpoint to ground to further
1
1
C
filter φ and φ . The value of C should be such that the corner frequency of this network does not significantly affect ω .
V
R
R
V
C
n
The φ and φ outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode input range of the
op amp used in the combiner/loop filter.
DEFINITIONS:
N = Total Division Ratio in feedback loop
K
φ
K
φ
(Phase Detector Gain) = V /4π for PD
DD out
(Phase Detector Gain) = V /2π for φ and φ
DD
V
R
2π∆f
∆V
VCO
VCO
K
VCO
(VCO Gain) =
2πfr
10
for a typical design w (Natural Frequency) ≈
(at phase detector input).
n
Damping Factor: ζ
1
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.
Blanchard, Alain, Phase–Locked Loops: Application to Coherent Receiver Design. New York, Wiley–Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M., Design of Phase–Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
1987.
MC145151–2 through MC145158–2
28
MOTOROLA
CRYSTAL OSCILLATOR CONSIDERATIONS
C
values. The shunt load capacitance, C , presented
L L
across the crystal can be estimated to be:
The following options may be considered to provide a ref-
erence frequency to Motorola’s CMOS frequency synthe-
sizers.
C C
C1 • C2
in out
C =
L
+ C + C +
a o
C
+ C
C1 + C2
in
out
where
Use of a Hybrid Crystal Oscillator
C
= 5 pF (see Figure 11)
= 6 pF (see Figure 11)
C = 1 pF (see Figure 11)
in
out
a
O
C
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscilla-
tors provide very stable reference frequencies. An oscillator
capable of sinking and sourcing 50 µA at CMOS logic levels
C
= the crystal’s holder capacitance
(see Figure 12)
C1 and C2 = external capacitors (see Figure 10)
may be direct or dc coupled to OSC . In general, the highest
frequency capability is obtained utilizing a direct–coupled
in
C
a
square wave having a rail–to–rail (V
swing. If the oscillator does not have CMOS logic levels on
the outputs, capacitive or ac coupling to OSC may be used.
to V ) voltage
DD
SS
in
C
C
out
in
OSC , an unbuffered output, should be left floating.
out
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem Elec-
tronic Engineers Master Catalog, the Gold Book, or similar
publications.
Figure 11. Parasitic Capacitances of the Amplifier
R
L
C
S
S
S
Design an Off–Chip Reference
1
2
1
2
The user may design an off–chip crystal oscillator using
ICs specifically developed for crystal oscillator applications,
such as the MC12061 MECL device. The reference signal
C
O
from the MECL device is ac coupled to OSC . For large am-
plitude signals (standard CMOS logic levels), dc coupling is
in
R
X
e
e
2
1
used. OSC , an unbuffered output, should be left floating.
out
In general, the highest frequency capability is obtained with a
direct–coupled square wave having rail–to–rail voltage
swing.
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
Figure 12. Equivalent Crystal Networks
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an ap-
propriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 10.
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated com-
ponents must be located as close as possible to the OSC
in
and OSC
out
pins to minimize distortion, stray capacitance,
stray inductance, and startup stabilization time. In some
cases, stray capacitance should be added to the value for C
in
and C
.
out
Power is dissipated in the effective series resistance of the
FREQUENCY
R
f
SYNTHESIZER
crystal, R , in Figure 12. The drive level specified by the crys-
e
tal manufacturer is the maximum stress that a crystal can
withstand without damage or excessive shift in frequency. R1
in Figure 10 limits the drive level. The use of R1 may not be
necessary in some cases (i.e., R1 = 0 Ω).
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a func-
OSC
C1
OSC
out
in
R1*
C2
tion of voltage at OSC . (Care should be taken to minimize
out
loading.) The frequency should increase very slightly as the
dc supply voltage is increased. An overdriven crystal will de-
crease in frequency or become unstable with an increase in
supply voltage. The operating supply voltage must be re-
duced or R1 must be increased in value if the overdriven
condition exists. The user should note that the oscillator
start–up time is proportional to the value of R1.
* May be deleted in certain cases. See text.
Figure 10. Pierce Crystal Oscillator Circuit
For V
DD
= 5.0 V, the crystal should be specified for a load-
ing capacitance, C , which does not exceed 32 pF for fre-
L
quencies to approximately 8.0 MHz, 20 pF for frequencies in
the area of 8.0 to 15 MHz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping varia-
tions in stray and IC input/output capacitance, and realistic
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have devel-
oped expertise in CMOS oscillator design with crystals. Dis-
cussions with such manufacturers can prove very helpful
(see Table 1).
MOTOROLA
MC145151–2 through MC145158–2
29
Table 1. Partial List of Crystal Manufacturers
Address
Name
Phone
United States Crystal Corp.
Crystek Crystal
Statek Corp.
3605 McCart Ave., Ft. Worth, TX 76110
2351 Crystal Dr., Ft. Myers, FL 33907
512 N. Main St., Orange, CA 92668
(817) 921–3013
(813) 936–2109
(714) 639–7810
NOTE: Motorolacannotrecommendonesupplieroveranotherandinnowaysuggeststhatthisisacomplete
listing of crystal manufacturers.
N is the number programmed into the ÷ N counter, A is the
number programmed into the ÷ A counter, P and P + 1 are
the two selectable divide ratios available in the dual–modu-
RECOMMENDED READING
Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp.
E. Hafner, “The Piezoelectric Crystal Unit – Definitions and
Method of Measurement”, Proc. IEEE, Vol. 57, No. 2 Feb.,
1969.
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”, Electro–Technology, June, 1969.
P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May, 1966.
lus prescalers. To have a range of N values in sequence,
T
the ÷ A counter is programmed from zero through P – 1 for a
particular value N in the ÷ N counter. N is then incremented to
N + 1 and the ÷ A is sequenced from 0 through P – 1 again.
There are minimum and maximum values that can be
achieved for N . These values are a function of P and the
T
size of the ÷ N and ÷ A counters.
The constraint N ≥ A always applies. If A
= P – 1, then
max
= (P – 1) P + A or (P – 1) P since A
N
≥ P – 1. Then N
min
Tmin
DUAL–MODULUS PRESCALING
OVERVIEW
is free to assume the value of 0.
N
= N
P+ A
max
Tmax
max
The technique of dual–modulus prescaling is well estab-
lished as a method of achieving high performance frequency
synthesizer operation at high frequencies. Basically, the
approach allows relatively low–frequency programmable
counters to be used as high–frequency programmable
counters with speed capability of several hundred MHz. This
is possible without the sacrifice in system resolution and per-
formance that results if a fixed (single–modulus) divider is
used for the prescaler.
In dual–modulus prescaling, the lower speed counters
must be uniquely configured. Special control logic is neces-
sary to select the divide value P or P + 1 in the prescaler for
the required amount of time (see modulus control definition).
Motorola’s dual–modulus frequency synthesizers contain
this feature and can be used with a variety of dual–modulus
prescalers to allow speed, complexity and cost to be tailored
to the system requirements. Prescalers having P, P + 1 di-
vide values in the range of ÷ 3/÷ 4 to ÷ 128/÷ 129 can be con-
trolled by most Motorola frequency synthesizers.
To maximize system frequency capability, the dual–modu-
lus prescaler output must go from low to high after each
group of P or P + 1 input cycles. The prescaler should divide
by P when its modulus control line is high and by P + 1 when
its MC is low.
For the maximum frequency into the prescaler (f
VCOmax
the value used for P must be large enough such that:
),
1. f
divided by P may not exceed the frequency
VCOmax
capability of f (input to the ÷ N and ÷ A counters).
in
2. The period of f
divided by P must be greater than
VCO
the sum of the times:
a. Propagation delay through the dual–modulus pre-
scaler.
b. Prescaler setup or release time relative to its MC
signal.
c. Propagation time from f to the MC output for the
in
frequency synthesizer device.
Several dual–modulus prescaler approaches suitable for
use with the MC145152–2, MC145156–2, or MC145158–2
are:
A sometimes useful simplification in the programming
code can be achieved by choosing the values for P of 8, 16,
32, or 64. For these cases, the desired value of N results
T
when N in binary is used as the program code to the ÷ N and
T
MC12009
MC12011
MC12013
MC12015
MC12016
MC12017
MC12018
MC12022A
MC12032A
÷ 5/÷ 6
÷ 8/÷ 9
440 MHz
500 MHz
500 MHz
225 MHz
225 MHz
225 MHz
520 MHz
1.1 GHz
2.0 GHz
÷ A counters treated in the following manner:
a
1. Assume the ÷ A counter contains “a” bits where 2 ≥ P.
÷ 10/÷ 11
÷ 32/÷ 33
2. Always program all higher order ÷ A counter bits above
“a” to 0.
÷ 40/÷ 41
÷ 64/÷ 65
3. Assume the ÷ N counter and the ÷ A counter (with all the
higher order bits above “a” ignored) combined into a
single binary counter of n + a bits in length (n = number
of divider stages in the ÷ N counter). The MSB of this “hy-
pothetical”counter is to correspond to the MSB of ÷ Nand
the LSB is to correspond to the LSB of ÷ A. The system
divide value, N , now results when the value of N in
÷ 128/÷ 129
÷ 64/65 or ÷ 128/129
÷ 64/65 or ÷ 128/129
DESIGN GUIDELINES
The system total divide value, N
the application:
(N ) will be dictated by
T
total
T
T
binary is used to program the “new” n + a bit counter.
frequency into the prescaler
By using the two devices, several dual–modulus values
are achievable (shown in Figure 13).
N
=
= N P + A
T
frequency into the phase detector
MC145151–2 through MC145158–2
30
MOTOROLA
MC
DEVICE A
DEVICE
DEVICE B
B
DEVICE A
MC10131
MC12009
MC12011
MC12013
÷
÷
20/
÷
÷
21
51
÷
÷
32/
÷
÷
33
81
÷
40/
100/
80/
÷
÷
÷
41
MC10138
50/
80/
÷
101
81
÷
÷
÷
40/
÷
41
81
÷
64/÷
65
MC10154
OR
80/
OR
128/
÷
÷
÷
129
NOTE: MC12009, MC12011, and MC12013 are pin equivalent.
MC12015, MC12016, and MC12017 are pin equivalent.
Figure 13. Dual–Modulus Values
MOTOROLA
MC145151–2 through MC145158–2
31
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP
CASE 648–08
(MC145157–2, MC145158–D)
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
PLANE
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
M
S
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
P SUFFIX
PLASTIC DIP
CASE 707–02
(MC145155–2)
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
18
10
9
B
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
1
MILLIMETERS
INCHES
DIM
A
B
C
D
F
MIN
22.22
6.10
3.56
0.36
1.27
MAX
23.24
6.60
4.57
0.56
1.78
MIN
MAX
A
0.875
0.240
0.140
0.014
0.050
0.915
0.260
0.180
0.022
0.070
L
C
G
H
J
K
L
2.54 BSC
0.100 BSC
1.02
0.20
2.92
1.52
0.30
3.43
0.040
0.008
0.115
0.060
0.012
0.135
K
N
J
F
D
M
SEATING
PLANE
7.62 BSC
15
1.02
0.300 BSC
15
0.020 0.040
H
G
M
N
0°
°
0°
°
0.51
MC145151–2 through MC145158–2
32
MOTOROLA
P SUFFIX
PLASTIC DIP
CASE 710–02
(MC145151–2, MC145152–2)
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
28
1
15
14
B
MILLIMETERS
INCHES
DIM
A
B
C
D
F
MIN
36.45
13.72
3.94
0.36
1.02
MAX
37.21
14.22
5.08
0.56
1.52
MIN
MAX
1.435
0.540
0.155
0.014
0.040
1.465
0.560
0.200
0.022
0.060
L
A
C
N
G
H
J
K
L
2.54 BSC
0.100 BSC
1.65
0.20
2.92
2.16
0.38
3.43
0.065
0.008
0.115
0.085
0.015
0.135
J
H
G
M
K
SEATING
PLANE
15.24 BSC
15
1.02
0.600 BSC
15
0.020 0.040
F
D
0°
°
0°
°
M
N
0.51
P SUFFIX
PLASTIC DIP
CASE 738–03
(MC145156–2)
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
11
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
B
1
10
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
E
F
G
J
K
L
M
N
MIN
MAX
1.070
0.260
0.180
0.022
MIN
25.66
6.10
3.81
0.39
1.27 BSC
1.27
2.54 BSC
0.21
MAX
27.17
6.60
4.57
0.55
1.010
0.240
0.150
0.015
0.050 BSC
0.050
0.100 BSC
0.008
0.110
-T-
SEATING
PLANE
K
M
0.070
1.77
E
N
0.015
0.140
0.38
3.55
G
F
J 20 PL
2.80
0.300 BSC
15
0.040
7.62 BSC
15
0.51 1.01
D 20 PL
0.25 (0.010)
M
M
0.25 (0.010)
T
B
0°
°
0°
°
0.020
M
M
T
A
MOTOROLA
MC145151–2 through MC145158–2
33
DW SUFFIX
SOG PACKAGE
CASE 751D–04
(MC145155–2, MC145156–2)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
–A–
ANSI Y14.5M, 1982.
20
11
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
10X P
–B–
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
M
M
0.010 (0.25)
B
1
10
MILLIMETERS
INCHES
20X D
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
0.010 (0.25)
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
DW SUFFIX
SOG PACKAGE
CASE 751F–04
(MC145151–2, MC145152–2)
-A-
NOTES:
28
1
15
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
14X P
M
M
-B-
0.010 (0.25)
B
4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
14
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
28X D
M
M
S
S
0.010 (0.25)
T
A
B
R X 45°
MILLIMETERS
INCHES
C
DIM
A
B
C
D
F
G
J
K
M
P
R
MIN
17.80
7.40
2.35
0.35
0.41
1.27 BSC
0.23
0.13
MAX
18.05
7.60
2.65
0.49
0.90
MIN
MAX
0.711
0.299
0.104
0.019
0.035
-T-
0.701
0.292
0.093
0.014
0.016
0.050 BSC
0.009
0.005
-T-
SEATING
PLANE
26X G
K
F
0.32
0.29
0.013
0.011
8°
0.415
0.029
J
0°
8°
0°
10.05
0.25
10.55
0.75
0.395
0.010
MC145151–2 through MC145158–2
34
MOTOROLA
DW SUFFIX
SOG PACKAGE
CASE 751G–02
(MC145157–2, MC145158–2)
–A–
16
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
–B–
8X P
0.010 (0.25)
M
M
B
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
1
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
J
16X D
M
S
S
0.010 (0.25)
T
A
B
F
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
10.15
7.40
2.35
0.35
0.50
MAX
10.45
7.60
2.65
0.49
0.90
MIN
MAX
0.411
0.299
0.104
0.019
0.035
0.400
0.292
0.093
0.014
0.020
R X 45
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
M
SEATING
14X G
K
PLANE
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
MOTOROLA
MC145151–2 through MC145158–2
35
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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MC145151–2/D
◊
相关型号：
MC145151DW2
Parallel-Input PLL Frequency Synthesizer Interfaces with Single-Modulus Prescalers
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