MC145426 [MOTOROLA]
Universal Digital-Loop Transceiver; 通用数字环收发器
| 型号： | MC145426 |
| 厂家： | 
MOTOROLA |
| 描述： | Universal Digital-Loop Transceiver |
| 文件： | 总20页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
by MC145422/D
SEMICONDUCTOR TECHNICAL DATA
The MC145422 and MC145426 UDLTs are high–speed data transceivers
that provide 80 kbps full–duplex data communication over 26 AWG and larger
twisted–pair cable up to two kilometers in distance. Intended primarily for use in
digital subscriber voice/data telephone systems, these devices can also be
used in remote data acquisition and control systems. These devices utilize a
256 kilobaud modified differential phase shift keying burst modulation technique
for transmission to minimize RFI/ EMI and crosstalk. Simultaneous power
distribution and duplex data communication can be obtained using a single
twisted–pair wire.
These devices are designed for compatibility with existing, as well as
evolving, telephone switching hardware and software architectures.
The UDLT chip–set consists of the MC145422 Master UDLT for use at the
telephone switch linecard and the MC145426 Slave UDLT for use at the remote
digital telset and/or data terminal.
P SUFFIX
PLASTIC DIP
CASE 708
22
1
DW SUFFIX
SOG PACKAGE
CASE 751E
24
1
ORDERING INFORMATION
MC145422P
MC145426P
Plastic DIP
Plastic DIP
The devices employ CMOS technology in order to take advantage of their
reliable low–power operation and proven capability for complex analog/digital
LSI functions.
MC145422DW SOG Package
MC145426DW SOG Package
•
Provides Full–Duplex Synchronous 64 kpbs Voice/Data Channel and Two
8 kbps Signaling Data Channels Over One 26 AWG Wire Pair Up to Two
Kilometers
•
•
Compatible with Existing and Evolving Telephone Switch Architectures and
Call Signaling Schemes
Automatic Detection Threshold Adjustment for Optimum Performance Over
Varying Signal Attenuations
•
•
•
•
Protocol Independent
Single 5 V Power Supply
22–Pin PDIP, 24–Pin SOG Packages
Application Notes AN943, AN949, AN968, AN946, and AN948
MC145422 Master UDLT
•
•
Pin Controlled Power–Down and Loopback Features
Signaling and Control I/O Capable of Sharing Common Bus Wiring with
Other UDLTs
•
•
Variable Data Clock — 64 kHz to 2.56 MHz
Pin Controlled Insertion/Extraction of 8 kbps Channel into LSB of 64 kbps
Channel for Simultaneous Routing of Voice and Data Through PCM Voice
Path of Telephone Switch
MC145426 Slave UDLT
•
•
•
•
•
Compatible with MC145500 Series PCM Codec–Filters
Pin Controlled Loopback Feature
Automatic Power–Up/Power–Down Feature
On–Chip Data Clock Recovery and Generation
Pin Controlled 500 Hz D3 or CCITT Format PCM Tone Generator for
Audible Feedback Applications
REV 2
9/95
Motorola, Inc. 1995
PIN ASSIGNMENTS
MC145422 — MASTER
(PLASTIC PACKAGE)
MC145422 — MASTER
(SOG PACKAGE)
V
1
2
3
4
5
22
21
20
19
18
17
16
15
14
13
12
V
V
1
2
3
24
23
22
V
DD
SS
DD
SS
V
LO1
LO2
RE1
Rx
V
LO1
LO2
ref
LI
ref
LI
LB
NC
LB
4
5
6
7
21
20
19
18
NC
VD
RE1
VD
SI1
Rx
TDC/RDC
CCI
SI1
6
7
TDC/RDC
SO1
SI2
SO2
SE
8
Tx
SO1
SI2
SO2
SE
8
17
16
15
14
13
CCI
Tx
9
TE1
SIE
9
10
11
10
11
12
TE1
SIE
MSI
PD
MSI
PD
MC145426 — SLAVE
(PLASTIC PACKAGE)
MC145426 — SLAVE
(SOG PACKAGE)
V
1
2
3
4
5
22
21
20
19
18
17
16
15
14
13
12
V
V
1
2
3
4
5
6
24
23
22
21
20
V
DD
SS
DD
SS
V
LO1
LO2
RE1
Rx
V
LO1
LO2
NC
RE1
Rx
ref
LI
ref
LI
LB
NC
LB
VD
CLK
X2
VD
19
18
SI1
6
7
SO1
CLK
X2
SI1
7
8
SI2
SO2
Mu/A
PD
8
X1
SO1
17
16
9
Tx
SI2
SO2
Mu/A
PD
9
X1
15
14
13
10
11
TE1
TE
10
11
12
Tx
TE1
TE
NC = NO CONNECTION
MC145422•MC145426
MOTOROLA
2
MC145422 MASTER UDLT BLOCK DIAGRAM
SI1
SI2
+ 1
– 1
MODULATION
BUFFER
LO1
LO2
*
SE
RE1
RECEIVE
Rx
REGISTER
LB
*
PD
SIE
CCI
MSI
SEQUENCE
AND
CONTROL
*
*
VD CONTROL
VD
LI
SO1
SO2
DEMODULATION
BUFFER
*
Tx
TRANSMIT
TE1
TDC/RDC
REGISTER
* — SE controlled latch
MC145426 SLAVE UDLT BLOCK DIAGRAM
SI1
SI2
MODULATION
BUFFER
+ 1
– 1
LO1
LO2
LOOPBACK
CONTROL
Rx
RECEIVE
RE1
REGISTER
TONE
GEN.
Mu/A
CLK
LB
TE
POWER–
DOWN
CONTROL
SEQUENCE
AND
CONTROL
PD
X2
X1
OSC
VD CONTROL
VD
LI
SO1
SO2
DEMODULATION
BUFFER
*
TRANSMIT
REGISTER
Tx
TE1
MOTOROLA
MC145422•MC145426
3
ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to V
)
SS
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions be taken to
avoid applications of any voltage higher than
maximum rated voltages to this high imped-
ance circuit. For proper operation it is recom-
Rating
DC Supply Voltage
Voltage, Any Pin to V
Symbol
Value
Unit
V
– V
– 0.5 to + 9.0
V
DD
SS
V
I
– 0.5 to V
DD
+ 0.5
V
SS
DC Current, Any Pin (Excluding V
,
± 10
mA
DD
V
)
SS
mended that V and V
in out
be constrained to
≤ V .
DD
Operating Temperature
Storage Temperature
T
– 40 to + 85
°C
°C
A
the range V
≤ (V or V
)
SS
in out
T
stg
– 85 to + 150
Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage
level (e.g., either V
or V ).
DD
SS
RECOMMENDED OPERATING CONDITIONS (T = 0 to 70°C)
A
Parameter
Pins
Min
4.5
—
Max
5.5
Unit
V
DC Supply Voltage
V
DD
V
DD
V
DD
Power Dissipation (PD = V , V
DD DD
= 5 V)
80
mW
mW
kHz
%
Power Dissipation (PD = V , TE = V
SS
)
—
75
SS
MC145422 Frame Rate
MSI
—
7.9
—
8.1
MC145422 — MC145426 Frame Rate Slip (See Note 1)
CCI Clock Frequency (MSI = 8 kHz)
Data Clock Rate MC145422
0.25
2.048
2560
256
CCI
—
MHz
kHz
kHz
TDC, RDC
LO1, LO2
64
—
Modulation Baud Rate (See Note 2)
NOTES:
1. The MC145426 crystal frequency divided by 512 must equal the MC145422 MSI Frequency ± 0.25% for optimum operation.
2. Assumes crystal frequency of 4.096 MHz for the MC145426 and 2.048 MHz CCI for the MC145422.
DIGITAL CHARACTERISTICS (V
= 5 V, T = 0 to 70°C)
DD
A
Parameter
Min
3.5
—
Max
—
Unit
V
Input High Level
Input Low Level
Input Current
1.5
V
Except LI
LI
– 1.0
– 100
1.0
100
µA
Input Capacitance
—
7.5
pF
Output High Current (Except Tx on MC145422
and Tx and PD on MC145426)
V
OH
V
OH
= 2.5 V
= 4.6 V
– 1.7
– 0.36
—
—
mA
Output Low Current (Except Tx on MC145422
and Tx and PD on MC145426)
V
V
= 0.4 V
= 0.8 V
0.36
0.8
—
—
mA
µA
OL
OL
PD Output High Current (MC145426) (See Note 1)
PD Output Low Current (MC145426) (See Note 1)
Tx Output High Current
V
OH
V
OH
= 2.5 V
= 4.6 V
– 90
– 10
—
—
V
V
= 0.4 V
= 0.8 V
60
100
—
—
µA
OL
OL
V
OH
V
OH
= 2.5 V
= 4.6 V
– 3.4
– 0.7
—
—
mA
mA
Tx Output Low Current
V
V
= 0.4 V
= 0.8 V
1.7
3.5
—
—
OL
OL
Tx Input Impedance (TE1 = V , MC145422)
SS
100
4.0
—
4.4
– 18
± 1
3
kΩ
MHz
dBm0
µA
Crystal Frequency (MC145426, Note 2)
PCM Tone (TE = V , MC145426)
DD
– 22
—
Three–State Current (SO1, SO2, VD, Tx on MC145422, Tx on MC145426)
V
ref
Voltage (See Note 3)
2
V
X2 — Oscillator Output High Drive Current (MC145426) (See Note 4)
X2 — Oscillator Output Low Drive Current (MC145426) (See Note 4)
NOTES:
V
= 4.6 V
= 0.4 V
– 450
450
—
µA
OH
V
—
µA
OL
1. To overdrive PD from a low level to 3.5 V or a high level to 1.5 V requires a minimum of ± 800 µA drive capability.
2. The MC145426 crystal frequency divided by 512 must equal the MC145422 MSI frequency ± 0.25% for optimum performance.
3. V typically (9/20 V – V ).
ref SS
DD
4. Output drive when X1 is being driven from an external clock.
MC145422•MC145426
MOTOROLA
4
ANALOG CHARACTERISTICS (V
DD
= 5 V, T = 0 to 70°C)
A
Parameter
Min
4.5
Max
6.0
Unit
V p–p
mV
Modulation Differential Amplitude (R = 440 Ω)
LO1 to LO2
L
Modulation Differential DC Offset
Demodulator Input Amplitude (See Note)
Demodulator Input lmpedance
0
300
2.5
0.050
50
V peak
kΩ
150
NOTE: The input level into the demodulator to reliably demodulate incoming bursts. Input referenced to V
.
ref
MC145422 SWITCHING CHARACTERISTICS (V
= 5 V, T = 25°C, C = 50 pF)
A L
DD
Figure
No.
Parameter
Symbol
Min
—
Max
4
Unit
µs
Input Rise Time
All Digital Inputs
All Digital Inputs
1
1
t
r
Input Fall Time
t
f
—
4
µs
Pulse Width
TDC/RDC, RE1, MSI
1
t (H,L)
90
45
64
—
ns
w
CCI Duty Cycle
1
t (H,L)
w
55
%
Data Clock Frequency
Propagation Delay Time
TDC/RDC
—
t
2560
kHz
ns
DC
MSI to SO1, SO2 VD (PD = V
)
2
3
t
, t
—
—
90
90
DD
TDC to Tx
PLH PHL
MSI to TDC/RDC Setup Time
4
t
t
90
40
—
—
ns
ns
su3
su4
TE1/RE1 to TDC/RDC Setup Time
4
t
t
90
40
—
—
su3
su4
Rx to TDC/RDC Setup Time
Rx to TDC/RDC Hold Time
SI1, SI2 to MSI Setup Time
SI1, SI2 to MSI Hold Time
5
5
6
6
t
60
60
60
60
—
—
—
—
ns
ns
ns
ns
su5
t
h1
t
su6
t
h2
MC145426 SWITCHING CHARACTERISTICS (V
= 5 V, T = 25°C, C = 50 pF)
A L
DD
Figure
No.
Parameter
Symbol
Min
—
Max
4
Unit
µs
Input Rise Time
All Digital Inputs
All Digital Inputs
CLK
1
1
t
r
Input Fall Time
t
f
—
4
µs
Clock Output Pulse Width
Crystal Frequency
Propagation Delay Times
1
t (H,L)
w
3.8
4.0
4.1
µs
—
f
4.086
MHz
ns
X1
TE1 Rising to CLK (TE = V
DD
TE1 Rising to CLK (TE = V
)
)
7
7
7
8
8
8
9
9
t
p1
t
p1
t
p2
t
p3
t
p4
t
p4
t
p5
t
p6
– 50
438
—
50
538
40
40
50
538
90
90
SS
CLK to TE1 Falling
CLK to RE1 Rising
—
RE1 Falling to CLK (TE = V
DD
RE1 Falling to CLK (TE = V
)
)
– 50
438
—
SS
CLK to Tx
TE1 to SO1, SO2
—
Rx to CLK Setup Time
Rx to CLK Hold Time
5
5
6
6
t
60
60
60
60
—
—
—
—
ns
ns
ns
ns
su5
t
h1
SI1, SI2 to TE1 Setup Time
SI1, SI2 to TE1 Hold Time
t
su6
t
h2
MOTOROLA
MC145422•MC145426
5
SWITCHING WAVEFORMS
t
t
w(L)
w(H)
90%
50%
CLK, TDC, RDC, RE1, CCI, MSI
50%
10%
t
t
f
r
Figure 1.
70%
70%
MSI
t
PLH
t
PHL
70%
VD, SO1, SO2
30%
Figure 2.
70%
PLH
70%
TDC
t
t
PHL
70%
Tx
30%
Figure 3.
MC145422•MC145426
MOTOROLA
6
SWITCHING WAVEFORMS (continued)
70%
TE1, RE1, MSI
30%
t
su3
t
su4
70%
TDC, RDC
30%
Figure 4.
70%
TDC, RDC, CLK
30%
t
su5
t
h1
70%
30%
70%
30%
Rx
Figure 5.
t
su6
70%
TE1 (MC145426) OR
MSI (MC145422)
30%
t
h2
70%
30%
70%
30%
SI1, SI2
Figure 6.
MOTOROLA
MC145422•MC145426
7
SWITCHING WAVEFORMS (continued)
70%
TE1
CLK
30%
t
P2
t
P1
70%
70%
Figure 7.
70%
RE1
CLK
30%
t
P3
t
P4
70%
70%
Figure 8.
70%
70%
Tx
SO1, SO2
30%
30%
t
t
P6
P5
70%
70%
CLK
TE1
Figure 9.
MC145422•MC145426
MOTOROLA
8
PD
MC145422 MASTER UDLT PIN DESCRIPTIONS
Power–Down Input
V
DD
If held low, the UDLT ceases modulation. In power–down,
the only active circuit is that which is necessary to demodu-
late an incoming burst and output the signal and valid data
bits. Internal data transfers to the transmit and receive regis-
ters cease. When brought high, the UDLT powers up, and
waits three positive MSI edges or until the end of an incom-
ing transmission from the slave UDLT and begins transmit-
ting every MSI period to the slave UDLT on the next rising
edge of the MSI.
Positive Supply
Normally 5 V.
V
SS
Negative Supply
This pin is the most negative supply pin, normally 0 V.
V
ref
Reference Output
MSI
This pin is the output of the internal reference supply and
Master Sync Input
should be bypassed to V
No external dc load should be placed on this pin.
and V
by 0.1 µF capacitors.
DD
SS
This pin is the system sync and initiates the modulation on
the twisted pair. MSI should be approximately leading–edge
aligned with TDC/RDC.
LI
Line Input
SIE
This input to the demodulator circuit has an internal
100 kΩ resistor tied to the internal reference node so that an
external capacitor and/or line transformer may be used to
couple the input signal to the part with no dc offset.
Signal Insert Enable
This pin, when held high, inserts signal bit 2 received from
the slave into the LSB of the outgoing PCM word at Tx and
will ignore the SI2 pin and use in place the LSB of the incom-
ing PCM word at Rx for transmission to the slave. The PCM
word to the slave will have LSB forced low in this mode. In
this manner, signal bit 2 to/from the slave UDLT is inserted in
to the PCM words the master sends and receives from the
backplane for routing through the PABX for simultaneous
voice/data communication. The state of this pin is internally
latched if the SE pin is brought and held low.
LB
Loopback Control
A low on this pin disconnects the LI pin from internal cir-
cuitry, drives LO1, LO2 to V and internally ties the modu-
ref
lator output to the demodulator input which loops the part on
itself for testing in the system. The state of this pin is inter-
nally latched if the SE pin is brought and held low. Loopback
is active only when PD Is high.
TE1
Transmit Data Enable 1 Input
VD
This pin controls the outputting of data on the Tx pin. While
TE1 is high, the Tx data is presented on the eight rising
edges of TDC/RDC. TE1 is also a high–impedance control of
the Tx pin. If MSI occurs during this period, new data will be
transferred to the Tx output register in the ninth high period of
TDC/RDC after TE1 rises; otherwise, it will transfer on the
rising edge of MSI. TE1 and TDC/RDC should be approxi-
mately leading–edge aligned.
Valid Data Output
A high on this pin indicates that a valid line transmission
has been demodulated. A valid transmission is determined
by proper sync and the absence of detected bit errors. VD
changes state on the leading edge of MSI when PD is high.
When PD is low, VD changes state at the end of demodula-
tion of a line transmission. VD is a standard B–series CMOS
output and is high impedance when SE is held low.
Tx
SI1, SI2
Signaling Bit Inputs
Transmit Data Output
This three–state output presents new voice data during the
high periods of TDC/RDC when TE1 is high (see TE1).
Data on these pins is loaded on the rising edge of MSI for
transmission to the slave. The state of these pins is internally
latched if SE is held low.
CCI
Convert Clock Input
SO1, SO2
A 2.048 MHz clock signal should be applied to this pin. The
signal is used for internal sequencing and control. This signal
should be coherent with MSI for optimum performance but
may be asynchronous if slightly worse error rate perform-
ance can be tolerated.
Signaling Bit Outputs
These outputs are received signaling bits from the slave
UDLT and change state on the rising edge of MSI if PD is
high, or at the completion of demodulation if PD is low. These
outputs have standard B–series CMOS drive capability and
are high impedance if the SE pin is held low.
TDC/RDC
Transmit/Receive Data Clock
SE
This pin is the transmit and receive data clock and can be
64 kHz to 2.56 MHz. Data is output at the Tx pin while TE1 is
high on the eight rising edges of TDC/RDC after the rising
edge of TE1. Data on the Rx pin is loaded into the receive
register of the UDLT on the eight falling edges of TDC/RDC
after a positive transition on RE1. This clock should be ap-
proximately leading–edge aligned with MSI.
Signal Enable Input
If held high, the PD, LB, SI1, SI2, and SIE inputs and the
SO1, SO2, and VD outputs function normally. If held low, the
state of these inputs is latched and held internally while the
outputs are high impedance. This allows these pins to be
bussed with those of other UDLTs to a common controller.
MOTOROLA
MC145422•MC145426
9
Rx
SI1, SI2
Receive Data
Signaling Bit Inputs
Voice data is clocked into the UDLT from this pin on the
falling edges of TDC/RDC under the control of RE1.
Data on these pins is loaded on the rising edge of TE1 for
transmission to the master. If no transmissions from the
master are being received and PD is high, data on these pins
will be loaded into the part on an internal signal. Therefore,
data on these pins should be steady until synchronous
communication with the master has been established, as in-
dicated by the high on VD.
RE1
Receive Data Enable 1 Input
A rising edge on this pin will enable data on the Rx pin to
be loaded into the receive data register on the next eight fall-
ing edges of the data dock, TDC/RDC. RE1 and TDC/RDC
should be approximately leading–edge aligned.
SO1, SO2
Signaling Bit Outputs
LO1, LO2
Line Driver Outputs
These outputs are received signaling bits from the master
UDLT and change state on the rising edge of TE1. These
outputs have standard B–series CMOS output drive capa-
bility.
These outputs drive the twisted pair line with 256 kHz
modified DPSK bursts each frame and are push–pull. These
pins are driven to V when not modulating the line.
ref
PD
Power–Down Input/Output
MC145426 SLAVE UDLT PIN DESCRIPTIONS
This is a bidirectional pin with weak output drivers such
that it can be overdriven externally. When held low, the UDLT
is powered down and the only active circuitry is that which is
necessary for demodulation, TE1/RE1/CLK generation upon
demodulation, the outputting of data received from the mas-
ter, and updating of VD status. When held high, the UDLT is
powered up and transmits in response to transmissions from
the master. If no received bursts from the master have oc-
curred when powered up for 250 µs (derived from the internal
oscillator frequency), the UDLT will generate a free running
125 µs internal clock from the internal oscillator and will burst
a transmission to the master every other internal 125 µs
clock using data on the SI1 and SI2 pins and the last data
word loaded into the receive register. The weak output driv-
ers will try to force PD high when a transmission from the
master is demodulated and will try to force it low if 250 µs
have passed without a transmission from the master. This al-
lows the slave UDLT to self power–up and down in demand
powered loop systems.
V
DD
Positive Supply
Normally 5 V.
V
SS
Negative Supply
This pin is the most negative supply pin, normally 0 V.
V
ref
Reference Output
This pin is the output of the internal reference supply and
should be bypassed to V
No external dc load should be placed on this pin.
and V
by 0.1 µF capacitors.
DD
SS
LI
Line Input
This input to the demodulator circuit has an internal
100 kΩ resistor tied to the internal reference node (V ) so
that an external capacitor and/or line transformer may be
used to couple the signal to this part with no dc offset.
ref
TE
Tone Enable
LB
A high on this pin generates a 500 Hz square wave PCM
tone and inserts it in place of the demodulated voice PCM
word from the master for outputting to the Tx pin to the telset
mono–circuit. A high on TE will generate TE1 and CLK from
the internal oscillator when the slave is not receiving bursts
from the master so that the PCM square wave can be loaded
into the codec–filter. This feature allows the user to provide
audio feedback for the telset keyboard depressions except
during loopback. During loopback of the slave UDLT, CLK is
defeated so a tone cannot be generated in this mode.
Loopback Control
When this pin is held low and PD is high (the UDLT is re-
ceiving transmissions from the master), the UDLT will use
the 8 bits of demodulated PCM data in place of the 8 bits of
Rx data in the return burst to the Master, thereby looping the
part back on itself for system testing. SI1 and SI2 operate
normally in this mode. CLK will be held low during loopback
operation.
VD
Valid Data Output
TE1
Transmit Data Enable 1 Output
A high on this pin indicates that a valid line transmission has
been demodulated. A valid transmission is determined by
proper sync and the absence of detected bit errors.VD
changes state on the leading edge of TE1. If no transmissions
from the master have been received in the last 250 µs
(derived from the internal oscillator), VD will go low without
TE1 rising since TE1 is not generated in the absence of re-
ceived transmissions from the master (see TE pin descrip-
tion for the one exception to this).
This is a standard B–series CMOS output which goes
high after the completion of demodulation of an incoming
transmission from the master. It remains high for 8 CLK
periods and then low until the next burst from the master is
demodulated. While high, the voice data just demodulated is
output on the first eight rising edges of CLK at the Tx pin. The
signaling data just demodulated is output on SO1 and SO2
on TE1’s rising edge, as is VD.
MC145422•MC145426
MOTOROLA
10
Tx
BACKGROUND
Transmit Data Output
The MC145422 master and MC145426 slave UDLT trans-
ceiver ICs main application is to bidirectionally transmit the
digital signals present at a codec–filter digital–PABX back-
plane interface over normal telephone wire pairs. This allows
the remoting of the codec–filter in a digital telephone set and
enables each set to have a high speed data access to the
PABX switching facility. In effect, the UDLT allows each
PABX subscriber direct access to the inherent 64 kbps data
routing capabilities of the PABX.
This is a standard B–series CMOS output. Voice data is
output on this pin on the rising edges of CLK while TE1 is
high and is high impedance when TE1 is low.
X1
Crystal Input
A 4.096 MHz crystal is tied between this pin and X2. A
10 MΩ resistor across X1 and X2 and 25 pF capacitors from
The UDLT provides a means for transmitting and receiving
64 kbits of voice data and 16 kbps of signaling data in two–
wire format over normal telephone pairs. The UDLT is a two–
chip set consisting of a master and a slave. The master
UDLT replaces the codec–filter and SLIC on the PABX line
card, and transmits and receives data over the wire pair to
the teleset. The UDLT appears to the linecard and backplane
as if it were a PCM Codec–Filter and has almost the same
digital interface features as the MC145500 series codec–fil-
ters. The slave UDLT is located in the telset and interfaces
the codec–filter to the wire pair. By hooking two UDLTs back–
to–back, a repeater can also be formed. The master and
slave UDLTs operate in a frame synchronous manner, sync
being established at the slave by the timing of the master’s
transmission. The master’s sync is derived from the PABX
frame sync.
The UDLT operates using one twisted pair. Eight bits of
voice data and two bits of signaling data are transmitted and
received each frame in a half–duplex manner (i.e., the slave
waits until the transmission from the master is completely re-
ceived before transmitting back to the master). Transmission
occurs at 256 kHz bit rate using a modified form of DPSK.
This “ping– pong” mode will allow transmission of data at dis-
tances up to two kilometers before turnaround delay be-
comes a problem. The UDLT is so defined as to allow this
data to be handled by the linecard, backplane, and PABX as
if it were just another voice conversation. This allows existing
PABX hardware and software to be unchanged and yet pro-
vides switched 64 kbps voice or data communications
throughout its service area by simply replacing a subscrib-
er’s linecard and teleset. A feature in the master allows one
of the two signaling bits to be inserted and extracted from the
backplane PCM word to allow simultaneous voice and data
transmission through the PABX. Both UDLTs have a loop-
back feature by which the device can be tested in the user
system.
X1 and X2 to V
startup. X1 may be driven by an external CMOS clock signal
if X2 is left open.
are required for stability and to ensure
SS
X2
Crystal Output
This pin is capable of driving one external CMOS input and
15 pF of additional capacitance (see X1 pin description).
CLK
Clock Output
This is a standard B–series CMOS output which provides
the data clock for the telset codec–filter. It is generated by di-
viding the oscillator down to 128 kHz and starts upon the
completion of demodulation of an incoming burst from the
master. At this time, CLK begins and TE1 goes high. CLK will
remain active for 16 periods, at the end of which it will remain
low until another transmission from the master is demodu-
lated. In this manner, sync from the master is established in
the slave and any clock slip between the master and the
slave is absorbed each frame. CLK is generated in response
to an incoming burst from the master, however, if TE is
brought high, then CLK and TE1/RE1 are generated from the
internal oscillator until TE is brought low or an incoming burst
from the master is received. CLK is disabled when LB is held
low.
Rx
Receive Data Input
Voice data from the telset codec–filter is input on this pin
on the first eight falling edges of CLK after RE1 goes high.
Mu/A
Tone Digital Format Input
The slave UDLT has the additional feature of providing a
500 Hz Mu–Law or A–Law coded square wave to the codec–
filter when the TE pin is brought high. This can be used to
provide audio feedback in the telset during keyboard depres-
sions.
This pin determines if the PCM code of the 500 Hz square
wave tone, when TE is high, is Mu–Law (Mu/A = 1) or A–Law
(Mu/A = 0) format.
RE1
Receive Data Enable 1 Output
CIRCUIT DESCRIPTION
GENERAL
This is a standard B–series CMOS output which is the
inverse of TE1 (see TE1 pin description).
The UDLT consists of a modulator, demodulator, two inter-
mediate data buffers, sequencing and control logic, and
transmit and receive data registers. The data registers
interface to the linecard or codec–filter digital interface sig-
nals, the modulator and demodulator interface the twisted
pair transmission medium, while the intermediate data regis-
ters buffer data between these two sections. The UDLT is
LO1, LO2
Line Driver Outputs
These outputs drive the twisted pair line with 256 kHz
modified DPSK bursts each frame and are push–pull. These
pins are driven to V when the device is not modulating.
ref
MOTOROLA
MC145422•MC145426
11
intended to operate on a single 5 V supply and can be driven
by TTL or CMOS logic.
The CLK pin 128 kHz output is formed by dividing down
the 4.096 MHz crystal frequency by 32. Slippage between
the frame rate of the master (as represented by the comple-
tion of demodulation of an incoming transmission from the
master) and the crystal frequency is absorbed by holding the
16th low period of CLK until the next completion of demodu-
lation. This is shown in the slave UDLT timing diagram of Fig-
ure 11.
MASTER OPERATION
In the master, data from the linecard is loaded into the re-
ceive register each frame from the Rx pin under the control of
the TDC/RDC clock and the receive data enable, RE1. RE1
controls loading of eight serial bits, henceforth referred to as
the voice data word. Each MSI, these words are transferred
out of the receive register to the modulation buffer for subse-
quent modulation onto the line. The modulation buffer takes
the receive voice data word and the two signaling data input
bits on SI1 and SI2 loaded on the MSI transition and formats
the 10 bits into a specific order. This data field is then trans-
mitted in a 256 kHz modified DPSK burst onto the line to the
remote slave UDLT.
Upon demodulating the return burst from the slave, the de-
coded data is transferred to the demodulation buffer and the
signaling bits are stripped ready to be output on SO1 and
SO2 at the next MSI. The voice data word is loaded into the
transmit register as described in the TE1 pin description for
outputting via the Tx pin at the TDC/RDC data clock rate un-
der the control of TE1. VD is output on the rising edge of MSI.
Timing diagrams for the master are shown in Figure 10.
POWER–DOWN OPERATION
In the master when PD is low, the UDLT stops modulating
and only that circuitry necessary to demodulate the incoming
bursts and output the signaling and VD data bits is active. In
this mode, if the UDLT receives a burst from the slave, the
SO1, SO2, and VD pins will change state upon completion of
the demodulation instead of the the rising edge of MSI. The
state of these pins will not change until either three rising MSI
edges have occurred without the reception of a burst from
the slave or until another burst is demodulated, whichever
occurs first.
When PD is brought high, the master UDLT will wait either
three rising MSI edges or until the MSI rising edge following
the demodulation of an incoming burst before transmitting to
the slave. The data for the first transmission to the slave after
power–up is loaded into the UDLT during the RE1 period
prior to the burst in the case of voice, and on the present ris-
ing edge of MSI for signaling data.
SLAVE OPERATION
In the slave, the synchronizing event is the detection of an
incoming line transmission from the master as indicated by
the completion of demodulation. When an incoming burst
from the master is demodulated, several events occur. As in
the master, data is transferred from the demodulator to the
demodulation buffer and the signaling bits are stripped for
outputting at SO1 and SO2. Data in the receive register is
transferred to the modulation buffer. TE1 goes high loading in
data at SI1 and SI2, which will be used in the transmission
burst to the master along with the data in the transmit data
buffer, and outputting SO1, SO2, and VD. Modulation of the
burst begins four 256 kHz periods after the completion of de-
modulation.
While TE1 is high, voice data is output on Tx to the telset
codec–filter on the rising edges of the data clock output on
the CLK pin. On the ninth rising edge of CLK, TE1 goes low,
RE1 goes high, and voice data from the codec–filter is input
to the receiver register from the Rx pin on the next eight
falling edges of CLK. RE1 is TE1 inverted and is provided to
facilitate interface to the codec–filter.
In the slave, PD is a bidirectional pin with weak output
drivers such that it can be overdriven externally. When held
low, the UDLT slave is powered–down and only that circuitry
necessary for demodulation, TE1/RE1/CLK generation upon
demodulation, and the outputting of voice and signaling bits
is active. When held high, the UDLT slave is powered–up
and transmits normally in response to transmissions from the
master. If no bursts have been received from the master
within 250 µs after power–up (derived from the internal oscil-
lator frequency), the UDLT generates an internal 125 µs
free–running clock from the internal oscillator. The slave
UDLT then bursts a transmission to the master UDLT every
other 125 µs clock period using data loaded into the Rx pin
during the last RE1 period and SI1, SI2 data loaded in on the
internal 125 µs clock edge. The weak output drivers will try to
force PD high when a transmission from the master is demo-
dulated and will try to force it low if 250 µs have passed with-
out a transmission from the master. This allows the slave
UDLT to self power–up and down in demand power–loop
systems.
MC145422•MC145426
MOTOROLA
12
125 µs
MSI
IN
• • •
CCI/TDC/RDC
TE1
IN
IN
THREE–STATE
Tx
OUT
IN
RE1
VALID DATA
Rx
DON’T CARE
IN
IN
• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
DON’T CARE
• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
• •
VALID
SI1, SI2
VALID
SO1, SO2
VD
OUT
OUT
DEMODULATOR
SYNC
OUT (INTERNAL)
TRANSFER RECEIVE REGISTER TO MODULATION BUFFER, LATCH VALID DATA PIN,
LATCH SI1, SI2. TWO CCI CLOCKS LATER, TRANSFER RECEIVE REGISTER TO
MODULATION BUFFER, START MODULATION.
TRANSFER DEMODULATOR
DATA TO DEMODULATION
BUFFER
Figure 10. Master UDLT Timing
MOTOROLA
MC145422•MC145426
13
125 µs
DEMODULATOR
SYNC (INTERNAL)
•
•
•
•
NOTE 1
•
•
•
•
•
•
CLK (128 kHz)
•
•
•
•
••
••
••
• •
• •
• •
INTERNAL
2.048 MHz FROM XTAL
•
• • •
• • •
• • •
•
•
•
•
•
•
TE1
RE1
Tx
•
•
•
•
•
•
VOICE
HIGH IMPEDANCE
VOICE
DON’T CARE
Rx
SI1, SI2
DON’T CARE
SO1, SO2
VD
TRANSFER DEMODULATION BUFFER TO TRANSMIT REGISTER, GENERATE ENABLES,
LATCH SI1, SI2, OUTPUT Tx, SO1, SO2, OUTPUT VALID DATA, START 128 kHz CLOCK, START
MODULATION AFTER FOUR 256 kHz BAUD PERIODS.
DEMODULATION DATA TRANSFER TO
DEMODULATION BUFFER
NOTE: 1. Slip between master and slave is taken up in this period.
Figure 11. Slave UDLT Timing
MC145422•MC145426
MOTOROLA
14
Both the Differential–Phase Shift Keying and the Modified
Differential–Phase–Shift Keying waveforms are shown in
Figures 12 thru 14. The DPSK encodes data as phase rever-
sals of a 256 kHz carrier. A 0 is indicated by a 180° phase
shift between bit boundaries, while the signal continues in
phase to indicate a 1. This method needs no additional bits
to indicate the start of the burst.
The modified DPSK waveform actually used in the trans-
ceivers is a slightly modified form of DPSK, as shown in Fig-
ure 12. The phase–reversal cusps of the DPSK waveform
have been replaced by a 128 kHz half–cycle to lower the
spectral content of the waveform, which, save for some key
differences, appears quite similar to frequency shift keying.
The burst always begins and ends with a half–cycle of
256 kHz, which helps locate bit boundaries.
The bit pattern shown in Figure 13a shows a stable wave-
form due to the even number of phase changes or zeros. The
waveform shown in Figure 13b shows random data patterns
being modulated.
Figure 14 shows the “ping–pong” signals on 3000 feet of
26 AWG twisted–pair wire as viewed at LI of the master
UDLT and the slave UDLT.
DIFFERENTIAL–PHASE–SHIFT KEYING
MODIFIED DIFFERENTIAL–PHASE–SHIFT KEYING
1
0
1
0
1
0
1
0
0
1
Figure 12. Modified Differential Phase Shift Keying
13a. Bit Pattern — 1010101000
13b. Bit Pattern — Random
Figure 13. Typical Signal Waveforms at Demodulator
MOTOROLA
MC145422•MC145426
15
MASTER
SLAVE
BIT PATTERN — 1010101000
BIT PATTERN — RANDOM
Figure 14. Typical Signal Waveforms at Demodulator
MC145422•MC145426
MOTOROLA
16
Figure 15. Typical Multichannel Digital Line Card
MOTOROLA
MC145422•MC145426
17
Figure 16. Basic Digital Telset
MC145422•MC145426
MOTOROLA
18
MC145426
MC145502
Figure 17. Full–Featured Digital Telset
MOTOROLA
MC145422•MC145426
19
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 708–04
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
22
1
12
11
B
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MIN
27.56
8.64
3.94
0.36
1.27
MAX
28.32
9.14
5.08
0.56
1.78
MIN
MAX
1.115
0.360
0.200
0.022
0.070
L
1.085
0.340
0.155
0.014
0.050
A
N
C
2.54 BSC
0.100 BSC
1.02
0.20
2.92
1.52
0.38
3.43
0.040
0.008
0.115
0.060
0.015
0.135
K
10.16 BSC
15
1.02
0.400 BSC
15
0.040
0.020
H
G
F
D
J
SEATING
M
°
°
0°
0°
PLANE
0.51
DW SUFFIX
SOG PACKAGE
CASE 751E–04
–A–
NOTES:
24
13
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–B– 12X P
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.010 (0.25)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1
12
24X D
J
MILLIMETERS
INCHES
M
S
S
0.010 (0.25)
T
A
B
DIM
A
B
C
D
MIN
15.25
7.40
2.35
0.35
0.41
MAX
15.54
7.60
2.65
0.49
0.90
MIN
MAX
0.612
0.299
0.104
0.019
0.035
0.601
0.292
0.093
0.014
0.016
F
R X 45
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.23
0.13
0
0.32
0.29
8
0.009
0.005
0
0.013
0.011
8
C
K
–T–
SEATING
M
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
PLANE
22X G
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