MC14555 [MOTOROLA]
PCM Codec-Filter; PCM编码解码滤波器
| 型号： | MC14555 |
| 厂家： | 
MOTOROLA |
| 描述： | PCM Codec-Filter |
| 文件： | 总20页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MC145554/D
SEMICONDUCTOR TECHNICAL DATA
The MC145554, MC145557, MC145564, and MC145567 are all per channel
PCM Codec–Filters. These devices perform the voice digitization and
reconstruction as well as the band limiting and smoothing required for PCM
systems. They are designed to operate in both synchronous and asynchronous
applications and contain an on–chip precision voltage reference. The
MC145554 (Mu–Law) and MC145557 (A–Law) are general purpose devices
that are offered in 16–pin packages. The MC145564 (Mu–Law) and MC145567
(A–Law), offered in 20–pin packages, add the capability of analog loopback and
push–pull power amplifiers with adjustable gain.
L SUFFIX
CERAMIC PACKAGE
CASE 620
These devices have an input operational amplifier whose output is the input
to the encoder section. The encoder section immediately low–pass filters the
analog signal with an active R–C filter to eliminate very–high–frequency noise
from being modulated down to the pass band by the switched capacitor filter.
From the active R–C filter, the analog signal is converted to a differential signal.
From this point, all analog signal processing is done differentially. This allows
processing of an analog signal that is twice the amplitude allowed by a
single–ended design, which reduces the significance of noise to both the
inverted and non–inverted signal paths. Another advantage of this differential
design is that noise injected via the power supplies is a common–mode signal
that is cancelled when the inverted and non–inverted signals are recombined.
This dramatically improves the power supply rejection ratio.
MC145554/57
16
1
P SUFFIX
PLASTIC DIP
CASE 648
16
MC145554/57
1
DW SUFFIX
SOG PACKAGE
CASE 751G
16
1
MC145554/57
After the differential converter, a differential switched capacitor filter band
passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized
by the differential compressing A/D converter.
The decoder accepts PCM data and expands it using a differential D/A
converter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X
compensated by a differential switched capacitor filter. The signal is then filtered
by an active R–C filter to eliminate the out–of–band energy of the switched
capacitor filter.
L SUFFIX
CERAMIC PACKAGE
CASE 732
20
1
MC145564/67
These PCM Codec–Filters accept both long–frame and short–frame industry
standard clock formats. They also maintain compatibility with Motorola’s family
of TSACs and MC3419/MC34120 SLIC products.
The MC145554/57/64/67 family of PCM Codec–Filters utilizes CMOS due to
its reliable low–power performance and proven capability for complex
analog/digital VLSI functions.
P SUFFIX
PLASTIC DIP
CASE 738
20
1
MC145564/67
DW SUFFIX
SOG PACKAGE
CASE 751D
MC145554/57 (16–Pin Package)
20
•
•
•
•
•
•
•
•
Fully Differential Analog Circuit Design for Lowest Noise
Performance Specified for Extended Temperature Range of – 40 to + 85°C
Transmit Band–Pass and Receive Low–Pass Filters On–Chip
Active R–C Pre–Filtering and Post–Filtering
Mu–Law Companding MC145554
A–Law Companding MC145557
1
MC145564/67
On–Chip Precision Voltage Reference (2.5 V)
Typical Power Dissipation of 40 mW, Power Down of 1.0 mW at ± 5 V
MC145564/67 (20–Pin Package) — All of the Features of the MC145554/57 Plus:
•
•
•
•
Mu–Law Companding MC145564
A–Law Companding MC145567
Push–Pull Power Drivers with External Gain Adjust
Analog Loopback
REV 1
9/95 (Replaces ADI1517)
Motorola, Inc. 1995
PIN ASSIGNMENTS
MC145554, MC145557
MC145564, MC145567
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VF I +
X
VPO+
GNDA
VPO –
VPI
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
BB
BB
GNDA
VF I –
X
VF I +
X
VF
O
VF I –
X
GS
X
R
GS
X
V
TS
X
CC
VF
O
ANLB
FS
FS
X
R
R
R
V
TS
X
D
D
X
CC
FS
D
FS
X
BCLK / CLKSEL
R
BCLK
R
R
X
MCLK / PDN
R
D
X
MCLK
X
BCLK /CLKSEL
BCLK
X
R
MCLK /PDN
MCLK
X
R
FUNCTIONAL BLOCK DIAGRAM
MCLK
PDN
/
BCLK /
R
CLKSEL
R
GS
ANLB*
V
GNDA
V
FS
FS
MCLK
BCLK
X
X
CC
BB
X
R
X
INTERNAL SEQUENCING
AND CONTROL
–
+
TS
X
VF I–
X
RC ACTIVE
LOW–PASS
FILTER
5–POLE SC
LOW–PASS
FILTER
3–POLE
HIGH–PASS
AND S/H
VF I+
X
COMP
TRANSMIT
SHIFT
REG
SAR
REG
VPO+
–1
D
X
4
8
BAND–GAP
VOLTAGE
REF
*
RDAC
CDAC
–
+
VPO–
4
MUX
*
RECEIVE
SHIFT
REG
VPI*
RECEIVE
LATCH
8
D
R
RC ACTIVE
LOW–PASS
FILTER
5–POLE SC
LOW–PASS
FILTER
S/H
VF
O
R
* MC145564 and MC145567 only.
MC145554•MC145557•MC145564•MC145567
MOTOROLA
2
DEVICE DESCRIPTION
PIN DESCRIPTION
DIGITAL
FS
A codec–filter is used for digitizing and reconstructing the
human voice. These devices were developed primarily for
the telephone network to facilitate voice switching and trans-
mission. Once the voice is digitized, it may be switched by
digital switching methods or transmitted long distance (T1,
microwave, satellites, etc.) without degradation. The name
codec is an acronym from “COder” (for the A/D used to digi-
tize voice) and “DECoder” (for the D/A used for reconstruct-
ing voice). A codec is a single device that does both the A/D
and D/A conversions.
R
Receive Frame Sync
This is an 8 kHz enable that must be synchronous with
BCLK . Following a rising FS edge, a serial PCM word at
R
R
D
is clocked by BCLK into the receive data register. FS
R R
R
also initiates a decode on the previous PCM word. In the ab-
sence of FS , the length of the FS pulse is used to deter-
X
R
mine whether the I/O conforms to the Short Frame Sync or
Long Frame Sync convention.
To digitize intelligible voice requires a signal–to–distortion
ratio of about 30 dB over a dynamic range of about 40 dB.
This can be accomplished with a linear 13–bit A/D and D/A,
but will far exceed the required signal–to–distortion ratio at
amplitudes greater than 40 dB below the peak amplitude.
This excess performance is at the expense of data per sam-
ple. Methods of data reduction are implemented by com-
pressing the 13–bit linear scheme to companded 8–bit
schemes. There are two companding schemes used:
Mu–255 Law specifically in North America, and A–Law
specifically in Europe. These companding schemes are
accepted world wide. These companding schemes follow a
segmented or “piecewise–linear” curve formatted as sign bit,
three chord bits, and four step bits. For a given chord, all six-
teen of the steps have the same voltage weighting. As the
voltage of the analog input increases, the four step bits incre-
ment and carry to the three chord bits which increment.
When the chord bits increment, the step bits double their
voltage weighting. This results in an effective resolution of six
bits (sign + chord + four step bits) across a 42 dB dynamic
range (seven chords above zero, by 6 dB per chord).
Tables 3 and 4 show the linear quantization levels to PCM
words for the two companding schemes.
In a sampling environment, Nyquist theory says that to
properly sample a continuous signal, it must be sampled at a
frequency higher than twice the signal’s highest frequency
component. Voice contains spectral energy above 3 kHz, but
its absence is not detrimental to intelligibility. To reduce the
digital data rate, which is proportional to the sampling rate, a
sample rate of 8 kHz was adopted, consistent with a band-
width of 3 kHz. This sampling requires a low–pass filter to
limit the high frequency energy above 3 kHz from distorting
the in–band signal. The telephone line is also subject to
50/60 Hz power line coupling, which must be attenuated from
the signal by a high–pass filter before the A/D converter.
The D/A process reconstructs a staircase version of the
desired in–band signal, which has spectral images of the in–
band signal modulated about the sample frequency and its
harmonics. These spectral images, called aliasing compo-
nents, need to be attenuated to obtain the desired signal.
The low–pass filter used to attenuate these aliasing compo-
nents is typically called a reconstruction or smoothing filter.
The MC145554/57/64/67 PCM Codec–Filters have the
codec, both presampling and reconstruction filters, and a
precision voltage reference on–chip, and require no external
components.
D
R
Receive Digital Data Input
BCLK /CLKSEL
R
Receive Data Clock and Master Clock Frequency
Selector
If this input is a clock, it must be between 128 kHz and
4.096 MHz, and synchronous with FS . In synchronous
applications this pin may be held at a constant level; then
BCLK is used as the data clock for both the transmit and
receive sides, and this pin selects the assumed frequency of
R
X
the master clock (see Table 1 in Functional Description).
MCLK /PDN
R
Receive Master Clock and Power–Down Control
Because of the shared DAC architecture used on these
devices, only one master clock is needed. Whenever FS is
clocking, MCLK is used to derive all internal clocks, and the
MCLK /PDN pin merely serves as a power–down control. If
MCLK /PDN pin is held low or is clocked (and at least one
of the frame syncs is present), the part is powered up. If this
pin is held high, the part is powered down. If FS is absent
but FS is still clocking, the device goes into receive half–
channel mode, and MCLK (if clocking) generates the
X
X
R
R
X
R
R
internal clocks.
MCLK
Transmit Master Clock
X
This clock is used to derive the internal sequencing clocks;
it must be 1.536 MHz, 1.544 MHz, or 2.048 MHz.
BCLK
Transmit Data Clock
X
BCLK may be any frequency between 128 kHz and
X
4.096 MHz, but it should be synchronous with MCLK .
X
D
X
Transmit Digital Data Output
This output is controlled by FS and BCLK to output the
X
X
PCM data word; otherwise this pin is in a high–impedance
state.
FS
X
Transmit Frame Sync
This is an 8 kHz enable that must be synchronous with
BCLK . A rising FS edge initiates the transmission of a
X
X
MOTOROLA
MC145554•MC145557•MC145564•MC145567
3
serial PCM word, clocked by BCLK , out of D . If the FS
X
VPO+
X
X
pulse is high for more than eight BCLK periods, the D and
Voltage Power Output (Non–Inverted)
(MC145554/67 Only)
X
X
TS outputs will remain in a low–impedance state until FS
is brought low. The length of the FS pulse is used to deter-
X
X
X
This non–inverted output of the receive push–pull power
amplifier pair can drive 300 Ω to 3.3 V peak.
mine whether the transmit and receive digital I/O conforms to
the Short Frame Sync or to the Long Frame Sync conven-
tion.
POWER SUPPLY
GNDA
Analog Ground
TS
X
Transmit Time Slot Indicator
This terminal is the reference level for all signals, both ana-
log and digital. It is 0 V.
This is an open–drain output that goes low whenever the
D
output is in a low–impedance state (i.e., during the trans-
X
V
mit time slot when the PCM word is being output) for en-
abling a PCM bus driver.
CC
Positive Power Supply
V
is typically 5 V.
CC
ANLB
V
BB
Negative Power Supply
Analog Loopback Control Input (MC145564/67 Only)
When held high, this pin causes the input of the transmit
V
is typically – 5 V.
BB
RC active filter to be disconnected from GS and connected
X
to VPO+ for analog loopback testing. This pin is held low in
normal operation.
FUNCTIONAL DESCRIPTION
ANALOG INTERFACE AND SIGNAL PATH
The transmit portion of these codec–filters includes a low–
noise gain setting amplifier capable of driving a 600 Ω load.
Its output is fed to a three–pole anti–aliasing pre–filter. This
pre–filter incorporates a two–pole Butterworth active low–
pass filter, and a single passive pole. This pre–filter is fol-
lowed by a single ended–to–differential converter that is
clocked at 256 kHz. All subsequent analog processing uti-
lizes fully differential circuitry. The next section is a fully–dif-
ferential, five–pole switched capacitor low–pass filter with a
3.4 kHz passband. After this filter is a 3–pole switched–ca-
pacitor high–pass filter having a cutoff frequency of about
200 Hz. This high–pass stage has a transmission zero at dc
that eliminates any dc coming from the analog input or from
accumulated operational amplifier offsets in the preceding fil-
ter stages. The last stage of the high–pass filter is an auto-
zeroed sample and hold amplifier.
ANALOG
GS
X
Gain–Setting Transmit
This output of the transmit gain–adjust operational amplifi-
er is internally connected to the encoder section of the
device. It must be used in conjunction with VF I– and VF I+
to set the transmit gain for a maximum signal amplitude of
2.5 V peak. This output can drive a 600 Ω load to 2.5 V peak.
X
X
VF I–
X
Voice–Frequency Transmit Input (Inverting)
This is the inverting input of the transmit gain–adjust
operational amplifier.
One bandgap voltage reference generator and digital–to–
analog converter (DAC) are shared by the transmit and
receive sections. The autozeroed, switched–capacitor band-
gap reference generates precise positive and negative refer-
ence voltages that are independent of temperature and
power supply voltage. A binary–weighted capacitor array
(CDAC) forms the chords of the companding structure, while
a resistor string (RDAC) implements the linear steps within
each chord. The encode process uses the DAC, the voltage
reference, and a frame–by–frame autozeroed comparator to
implement a successive–approximation conversion algo-
rithm. All of the analog circuitry involved in the data con-
version — the voltage reference, RDAC, CDAC, and
comparator — are implemented with a differential architec-
ture.
VF I+
X
Voice–Frequency Transmit Input
(Non–Inverting)
This is the non–inverting input of the transmit gain–adjust
operational amplifier.
VF O
R
Voice–Frequency Receive Output
This receive analog output is capable of driving a 600 Ω
load to 2.5 V peak.
VPI
Voltage Power Input (MC145564/67 Only)
The receive section includes the DAC described above, a
sample and hold amplifier, a five–pole 3400 Hz switched
capacitor low–pass filter with sinX/X correction, and a two–
pole active smoothing filter to reduce the spectral com-
ponents of the switched capacitor filter. The output of the
smoothing filter is a power amplifier that is capable of driving
a 600 Ω load. The MC145564 and MC145567 add a pair of
power amplifiers that are connected in a push–pull configu-
ration; two external resistors set the gain of both of the
This is the inverting input to the first receive power ampli-
fier. Both of the receive power amplifiers can be powered
down by connecting this input to V
.
BB
VPO–
Voltage Power Output (Inverted) (MC145564/67 Only)
This inverted output of the receive push–pull power ampli-
fiers can drive 300 Ω to 3.3 V peak.
MC145554•MC145557•MC145564•MC145567
MOTOROLA
4
complementary outputs. The output of the second amplifier
may be internally connected to the input of the transmit anti–
aliasing filter by bringing the ANLB pin high. The power am-
plifiers can drive unbalanced 300 Ω loads or a balanced
600 Ω load; they may be powered down independent of the
remaining seven bits of the PCM word. The D and TS out-
X X
puts return to a high impedance state on the falling edge of
the eighth bit clock or the falling edge of FS , whichever
X
comes later. The receive PCM word is clocked into D on the
R
eight falling BCLK edges following an FS rising edge.
R
R
rest of the chip by tying the VPI pin to V
.
For Short Frame Sync operation, the frame sync pulses
must be one bit clock period long. On the first BCLK rising
BB
X
MASTER CLOCKS
edge after the falling edge of BCLK has latched FS high,
X
X
the D and TS outputs are enabled and the sign bit is pres-
X
X
Since the codec–filter design has a single DAC architec-
ture, only one master clock is used. In normal operation (both
ented on D . The next seven rising edges of BCLK clock
X
X
out the remaining seven bits of the PCM word; on the eighth
BCLK falling edge, the D and TS outputs return to a high
frame syncs clocking), the MCLK is used as the master
X
X
X
X
clock, regardless of whether the MCLK /PDN pin is clocking
R
impedance state. On the second falling BCLK edge follow-
R
or low. The same is true if the part is in transmit half–channel
ing an FS rising edge, the receive sign bit is clocked into
D . The next seven BCLK falling edges clock in the re-
R
mode (FS clocking, FS held low). But if the codec–filter is
X
R
R
R
in the receive half–channel mode, with FS clocking and FS
R
X
maining seven bits of the receive PCM word.
Table 2 shows the coding format of the transmit and re-
ceive PCM words.
held low, MCLK is used for the internal master clock if it is
R
clocking; if MCLKR is low, then MCLK is still used for the
X
internal master clock. Since only one of the master clocks is
used at any given time, they need not be synchronous.
The master clock frequency must be 1.536 MHz,
1.544 MHz, or 2.048 MHz. The frequency that the codec–
filter expects depends upon whether the part is a Mu–Law or
HALF–CHANNEL MODES
In addition to the normal full–duplex operating mode, these
codec–filters can operate in both transmit and receive half–
channel modes. Transmit half–channel mode is entered by
an A–Law part, and on the state of the BCLK /CLKSEL pin.
R
The allowable options are shown In Table 1. When a level
holding FS low. The VF O output goes to analog ground
R R
(rather than a clock) is provided for BCLK /CLKSEL, BCLK
is used as the bit clock for both transmit and receive.
but remains in a low impedance state (to facilitate a hybrid
interface); PCM data at D is ignored. Holding FS low while
R
X
R
X
clocking FS puts these devices in the receive half–channel
R
Table 1. Master Clock Frequency Determination
Master Clock Frequency Expected
mode. In this state, the transmit input operational amplifier
continues to operate, but the rest of the transmit circuitry is
disabled; the D and TS outputs remain in a high imped-
X
X
BCLK /CLKSEL
R
MC145554/64
MC145557/67
ance state. MCLK is used as the internal master clock if it is
R
Clocked, 1, or Open
1.536 MHz
1.544 MHz
2.048 MHz
clocking. If MCLK is not clocking, then MCLK is used for
R
X
the internal master clock, but in that case it should be syn-
chronous with FS . If BCLK is not clocking, BCLK will be
0
2.048 MHz
1.536 MHz
1.544 MHz
R
R
X
used for the receive data, just as in the full–channel operat-
ing mode. In receive half–channel mode only, the length of
FRAME SYNCS AND DIGITAL I/O
the FS pulse is used to determine whether Short Frame
R
Sync or Long Frame Sync timing is used at D .
R
These codec–filters can accommodate both of the industry
standard timing formats. The Long Frame Sync mode is
used byMotorola’s MC145500 family of codec–filters and the
UDLT family of digital loop transceivers. The Short Frame
Sync mode is compatible with the IDL (Interchip Digital Link)
serial format used in Motorola’s ISDN family and by other
companies in their telecommunication devices. These
POWER–DOWN
Holding both FS and FS low causes the part to go into
X
R
the power–down state. Power–down occurs approximately
2 ms after the last frame sync pulse is received. An alterna-
tive way to put these devices in power–down is to hold the
codec–filters use the length of the transmit frame sync (FS )
MCLK /PDN pin high. When the chip is powered down, the
D , TS , and GS outputs are high impedance, the VF O,
X X X R
VPO–, and VPO+ operational amplifiers are biased with a
trickle current so that their respective outputs remain stable
at analog ground. To return the chip to the power–up state,
X
R
to determine the timing format for both transmit and receive
unless the part is operating in the receive half–channel
mode.
In the Long Frame Sync mode, the frame sync pulses
must be at least three bit clock periods long. The D and TS
MCLK /PDN must be low or clocking and at least one of the
X
X
R
outputs are enabled by the logical ANDing of FS and
frame sync pulses must be present. The D and TS outputs
X X
X
BCLK ; when both are high, the sign bit appears at the D
will remain in a high–impedance state until the second FS
pulse after power–up.
X
X
X
output. The next seven rising edges of BCLK clock out the
X
Table 2. PCM Data Format
Mu–Law (MC145554/64)
A–Law (MC145557/67)
Level
+ Full Scale
+ Zero
Sign Bit
Chord Bits
0 0 0
Step Bits
0 0 0 0
1 1 1 1
1 1 1 1
0 0 0 0
Sign Bit
Chord Bits
0 1 0
Step Bits
1 0 1 0
0 1 0 1
0 1 0 1
1 0 1 0
1
1
0
0
1
1
0
0
1 1 1
1 0 1
– Zero
1 1 1
1 0 1
– Full Scale
0 0 0
0 1 0
MOTOROLA
MC145554•MC145557•MC145564•MC145567
5
MAXIMUM RATINGS (Voltage Referenced to GNDA)
Rating Symbol
This device contains circuitry to protect
against damage due to high static voltages or
electric fields; however, it is advised that
normal precautions be taken to avoid appli-
cation of any voltage higher than maximum
rated voltages to this high impedance circuit.
For proper operation it is recommended that
Value
Unit
DC Supply Voltage
V
to V
BB
– 0.5 to + 13
– 0.3 to + 7.0
– 7.0 to + 0.3
V
CC
V
V
to GNDA
to GNDA
CC
BB
Voltage on Any Analog Input or Output Pin
Voltage on Any Digital Input or Output Pin
V
V
– 0.3 to
V
V
BB
+ 0.3
CC
GNDA – 0.3 to
+ 0.3
V
and V
out
in out DD
be constrained to the range V
SS
in
≤ (V or V ) ≤ V
.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., V
V
CC
,
BB
Operating Temperature Range
Storage Temperature Range
T
– 40 to + 85
°C
°C
A
GNDA, or V ).
CC
T
stg
– 85 to + 150
POWER SUPPLY (T = – 40 to + 85°C)
A
Characteristic
Min
Typ
Max
Unit
DC Supply Voltage
V
V
4.75
– 4.75
5.0
– 5.0
5.25
– 5.25
V
CC
BB
Active Power Dissipation (No Load)
MC145554/57
MC145564/67
—
—
—
40
45
40
60
70
60
mW
MC145564/67, VPI = V
BB
Power–Down Dissipation (No Load)
MC145554/57
MC145564/67
—
—
—
1.0
2.0
1.0
3.0
5.0
3.0
mW
MC145564/67, VPI = V
BB
DIGITAL LEVELS (V
= 5 V ± 5%, V = – 5 V ± 5%, GNDA = 0 V, T = – 40 to + 85°C)
BB A
CC
Characteristic
Symbol
Min
—
Max
0.6
—
Unit
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
IL
V
IH
2.2
—
V
D
or TS , I
OL
= 3.2 mA
V
OL
0.4
V
X
X
D , I
X
= – 3.2 mA
= – 1.6 mA
V
OH
2.4
—
—
V
OH
OH
I
V
– 0.5
CC
Input Low Current
Input High Current
GNDA ≤ V ≤ V
in
I
– 10
– 10
– 10
+ 10
+ 10
+ 10
µA
µA
µA
CC
CC
CC
IL
GNDA ≤ V ≤ V
in
I
IH
Output Current in High Impedance State
GNDA ≤ D ≤ V
I
OZ
X
MC145554•MC145557•MC145564•MC145567
MOTOROLA
6
ANALOG ELECTRICAL CHARACTERISTICS
(V
CC
= + 5 V ± 5%, V
= – 5 V ± 5%, VF I – Connected to GS , T = – 40 to + 85°C)
BB
X
X
A
Characteristic
Min
—
Typ
± 0.05
20
Max
± 0.2
—
Unit
µA
Input Current (– 2.5 ≤ V ≤ + 2.5 V)
in
VF I+, VF I–
X X
AC Input Impedance to GNDA (1 kHz)
Input Capacitance
VF I+, VF I–
10
—
MΩ
pF
X
X
VF I+, VF I–
—
10
X
X
Input Offset Voltage of GS Op Amp
X
VF I+, VF I–
—
—
± 25
2.5
—
mV
V
X
X
Input Common Mode Voltage Range
Input Common Mode Rejection Ratio
VF I+, VF I–
– 2.5
—
—
X
X
VF I+, VF I–
65
dB
X
X
Unity Gain Bandwidth of GS Op Amp (R
≥ 10 kΩ)
≥ 10 kΩ)
—
1000
—
—
kHz
dB
X
load
DC Open Loop Gain of GS Op Amp (R
load
75
—
—
X
Equivalent Input Noise (C–Message) Between VF I+ and VF I– at GS
X
–20
—
—
dBrnC0
pF
X
X
Output Load Capacitance for GS Op Amp
0
100
X
Output Voltage Range for GS
R
R
= 10 kΩ to GNDA
= 600 Ω to GNDA
– 3.5
– 2.8
—
—
+ 3.5
+ 2.8
V
X
load
load
Output Current (– 2.8 V ≤ V
≤ + 2.8 V)
Output Impedance VF O (0 to 3.4 kHz)
GS , VF O
± 5.0
—
—
1
—
—
mA
Ω
out
X
R
R
Output Load Capacitance for VF O
0
—
—
500
± 100
pF
R
VF O Output DC Offset Voltage Referenced to GNDA
—
mV
dBC
R
Transmit Power Supply Rejection
Positive, 0 to 100 kHz, C–Message
Negative, 0 to 100 kHz, C–Message
45
45
—
—
—
—
Receive Power Supply Rejection
Positive, 0 to 100 kHz, C–Message
Positive, 4 kHz to 25 kHz
Positive, 25 kHz to 50 kHz
Negative, 0 to 100 kHz, C–Message
Negative, 4 kHz to 25 kHz
50
50
43
50
45
38
—
—
—
—
—
—
—
—
—
—
—
—
dBC
dB
dB
dBC
dB
dB
Negative, 25 kHz to 50 kHz
MC145564/67 Power Drivers
Input Current (– 1 V ≤ VPI ≤ + 1 V)
Input Resistance (– 1 V ≤ VPI ≤ + 1 V)
Input Offset Voltage (VPI Connected to VPO–)
Output Resistance, Inverted Unity Gain
Unity Gain Bandwidth, Open Loop
VPI
—
5
±0.05
10
±0.5
—
µA
MΩ
mV
Ω
VPI
VPI
—
—
—
0
—
±50
—
VPO+ or VPO–
VPO–
1
400
—
—
kHz
pF
Load Capacitance (∞ Ω ≥ R
load
≥ 300 Ω)
VPO+ or VPO– to GNDA
1000
—
Gain from VPO– to VPO+ (R
= 1.77 Vrms, +3 dBm0)
= 300 Ω, VPO+ to GNDA Level at VPO–
—
–1
V/V
load
Maximum 0 dBm0 Level for Better than ± 0.1 dB Linearity Over the
R
= 600 Ω
3.3
3.5
4.0
—
—
—
—
—
—
Vrms
load
R = 1200 Ω
load
Range – 10 dBm0 to + 3 dBm0 (For R
and VPO–)
between VPO+
load
R
= 10 kΩ
load
Power Supply Rejection of V
VPO+ or VPO– to GNDA
or V
BB
(VPO– Connected to VPI)
0 to 4 kHz
4 to 50 kHz
55
35
—
—
—
—
dB
dB
CC
Differential Power Supply Rejection of V
or V
BB
(VPO– Connected to VPI)
VPO+ to VPO–, 0 to 50 kHz
CC
50
—
—
MOTOROLA
MC145554•MC145557•MC145564•MC145567
7
ANALOG TRANSMISSION PERFORMANCE
(V
CC
= + 5 V ± 5%, V = – 5 V ± 5%, GNDA = 0 V, 0 dBm0 = 1.2276 Vrms = + 4 dBm @ 600 Ω, FS = FS = 8 kHz,
BB X R
BCLK = MCLK = 2.048 MHz Synchronous Operation, VF I – Connected to GS , T = – 40 to + 85°C Unless Otherwise Noted)
X
X
X
X
A
End–to–End
A/D
D/A
Characteristic
Unit
dB
Min
Max
Min
Max
Min
Max
Absolute Gain (0 dBm0 @ 1.02 kHz, T = 25°C, V
= 5 V, V = – 5 V)
BB
—
—
–0.25 – 0.25 – 0.25 + 0.25
A
CC
Absolute Gain Variation with Temperature
0 to 70°C
– 40 to + 85°C
—
—
—
—
—
—
± 0.03
± 0.06
—
—
± 0.03
± 0.06
dB
Absolute Gain Variation with Power Supply (V
CC
= 5 V, ± 5%,
—
—
—
± 0.02
—
± 0.02
dB
dB
V
= – 5 V, ± 5%)
BB
Gain vs Level Tone (Relative to – 10 dBm0, 1.02 kHz)
+ 3 to – 40 dBm0 – 0.4
– 40 to – 50 dBm0 – 0.8
– 50 to – 55 dBm0 – 1.6
+ 0.4
+ 0.8
+ 1.6
– 0.2
– 0.4
– 0.8
+ 0.2
+ 0.4
+ 0.8
– 0.2
– 0.4
– 0.8
+ 0.2
+ 0.4
+ 0.8
Gain vs Level Pseudo Noise CCITT G.712
(MC145557/67 A–Law Relative to – 10 dBm0)
– 10 to – 40 dBm0
– 40 to – 50 dBm0
– 50 to – 55 dBm0
—
—
—
—
—
—
– 0.25 + 0.25 – 0.25 + 0.25
– 0.30 + 0.30 – 0.30 + 0.30
– 0.45 + 0.45 – 0.45 + 0.45
dB
Total Distortion, 1.02 kHz Tone (C–Message)
+ 3 dBm0
0 to – 30 dBm0
– 40 dBm0
33
35
29
24
15
—
—
—
—
—
33
36
30
25
15
—
—
—
—
—
33
36
30
25
15
—
—
—
—
—
dBC
– 45 dBm0
– 55 dBm0
Total Distortion With Pseudo Noise CCITT G.714
(MC145557/67 A–Law)
– 3 dBm0
– 6 to – 27 dBm0
– 34 dBm0
27.5
35
33.1
28.2
13.2
—
—
—
—
—
28
—
—
—
—
—
28.5
36
34.2
30
—
—
—
—
—
dB
35.5
33.5
28.5
13.5
– 40 dBm0
– 55 dBm0
15
Idle Channel Noise (For End–End and A/D, Note 1)
(MC145554/64 Mu–Law, C–Message Weighted)
(MC145557/67 A–Law, Psophometric Weighted)
—
—
15
–70
—
—
15
– 70
—
—
7
– 83
dBrnC0
dBm0p
Frequency Response (Relative to 1.02 kHz @ 0 dBm0)
15 Hz
50 Hz
60 Hz
—
—
—
—
– 40
– 30
– 26
—
—
—
—
– 40
– 30
– 26
– 0.4
– 0.15
– 0.15
– 0.15
– 0.15
0
0
0
0
dB
200 Hz
– 1.0
300 to 3000 Hz – 0.3
0.3
– 0.15 + 0.15 – 0.15 + 0.15
3300 Hz – 0.70 + 0.3 – 0.35 + 0.15 – 0.35 + 0.15
3400 Hz – 1.6
0
– 28
– 60
– 0.8
—
—
0
– 14
– 32
– 0.8
—
—
0
– 14
– 30
4000 Hz
4600 Hz
—
—
In–Band Spurious
(1.02 kHz @ 0 dBm0, Transmit and Receive)
300 to 3000 Hz
—
–48
—
– 48
—
– 48
dBm0
dB
Out–of–Band Spurious at VF O (300 – 3400 Hz @ 0 dBm0 In)
R
4600 to 7600 Hz
7600 to 8400 Hz
8400 to 100,000 Hz
—
—
—
– 30
– 40
– 30
—
—
—
—
—
—
—
—
—
– 30
– 40
– 30
Idle Channel Noise Selective (8 kHz, Input = GNDA, 30 Hz Bandwidth)
Absolute Delay (1600 Hz)
—
—
–70
—
—
—
—
—
—
– 70
215
dBm0
µs
315
Group Delay Referenced to 1600 Hz
500 to 600 Hz
600 to 800 Hz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
220
145
75
40
75
– 40
– 40
– 40
– 30
—
—
—
—
—
90
µs
800 to 1000 Hz
1000 to 1600 Hz
1600 to 2600 Hz
2600 to 2800 Hz
2800 to 3000 Hz
105
155
—
—
125
175
Crosstalk of 1020 Hz @ 0 dBm0 from A/D or D/A (Note 2)
—
—
—
—
—
– 75
– 41
—
—
– 75
– 41
dB
dB
Intermodulation Distortion of Two Frequencies of Amplitudes
– 4 to – 21 dBm0 from the Range 300 to 3400 Hz
– 41
NOTES:
1. Extrapolated from a 1020 Hz @ – 50 dBm0 distortion measurement to correct for encoder enhancement.
2. Selectively measured while the A/D is stimulated with 2667 Hz @ – 50 dBm0.
MC145554•MC145557•MC145564•MC145567
MOTOROLA
8
DIGITAL SWITCHING CHARACTERISTICS
(V
CC
= 5 V ± 5%, V
= – 5 V ± 5%, GNDA = 0 V, All Signals Referenced to GNDA; T = – 40 to + 85°C, C = 150 pF Unless Otherwise
BB
A
load
Noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Master Clock Frequency
MCLK or MCLK
f
M
—
—
—
1.536
1.544
2.048
—
—
—
MHz
X
R
Minimum Pulse Width High or Low
Minimum Pulse Width High or Low
Minimum Pulse WIdth Low
MCLK or MCLK
t
w(M)
100
50
50
—
—
—
—
—
—
—
—
—
—
—
60
50
70
60
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
X
R
R
R
BCLK or BCLK
t
w(B)
X
FS or FS
t
—
X
w(FL)
Rise Time for all Digital Signals
Fall Time for all Digital Signals
Bit Clock Data Rate
t
r
50
t
f
—
50
BCLK or BCLK
f
B
128
50
20
20
80
20
20
50
20
0
4096
—
X
R
Setup Time from BCLK Low to MCLK High
t
su(BRM)
X
R
Setup Time from MCLK High to BCLK Low
t
su(MFB)
—
X
X
Hold Time from BCLK (BCLK ) Low to FS (FS ) High
t
h(BF)
—
X
R
X
R
Setup Time for FS (FS ) High to BCLK (BCLK ) Low for Long Frame
t
su(FB)
—
X
R
X
R
Delay Time from BCLK High to D Data Valid
t
140
140
140
140
—
X
X
d(BD)
Delay Time from BCLK High to TS Low
t
X
X
d(BTS)
Delay Time from the 8th BCLK Low of FS Low to D Output Disabled
t
d(ZC)
X
X
X
Delay Time to Valid Data from FS or BCLK , Whichever is Later
t
X
X
d(ZF)
su(DB)
Setup Time from D Valid to BCLK Low
t
R
X
Hold Time from BCLK Low to D Invalid
t
h(BD)
50
50
50
50
—
R
R
Setup Time from FS (FS ) High to BCLK (BCLK ) Low in Short Frame
t
su(F)
—
X
R
X
R
Hold Time from BCLK (BCLK ) Low to FS (FS ) Low in Short Frame
t
h(F)
—
X
R
X
R
Hold Time from 2nd Period of BCLK (BCLK ) Low to FS (FS ) Low in
Long Frame
t
h(BFI)
—
X
R
X
R
MOTOROLA
MC145554•MC145557•MC145564•MC145567
9
TS
X
t
t
t
t
d(ZC)
d(BTS)
w(M)
w(M)
MCLK
X
R
MCLK
t
t
su(MFB)
w(B)
t
t
w(B)
su(BRM)
BCLK
1
2
3
4
5
6
7
8
9
X
t
h(BF)
t
h(F)
t
su(F)
FS
X
t
t
d(BD)
d(ZC)
MSB
CH1
CH2
CH3
ST1
ST2
ST3
LSB
D
X
BCLK
FS
1
2
3
4
5
6
7
8
9
R
t
h(BF)
t
h(F)
t
su(F)
R
t
h(BD)
t
t
h(BD)
su(DB)
D
MSB
CH1
CH2
CH3
ST1
ST2
ST3
LSB
R
Figure 1. Short Frame Sync Timing
MC145554•MC145557•MC145564•MC145567
MOTOROLA
10
MCLK
X
R
MCLK
t
su(MFB)
t
su(BRM)
BCLK
2
3
4
8
9
X
X
1
5
6
7
t
su(FB)
t
h(BFI)
t
h(BF)
FS
t
d(ZF)
t
t
d(BD)
d(ZC)
t
t
d(ZC)
d(ZF)
D
MSB
CH1
CH2
CH3
ST1
ST3
LSB
X
ST2
1
2
3
4
5
6
7
8
9
BCLK
R
t
t
h(BFI)
h(BF)
t
su(FB)
FS
D
R
t
h(BD)
t
t
h(BD)
su(DB)
MSB
CH1
CH2
CH3
ST1
ST2
ST3
LSB
R
Figure 2. Long Frame Sync Timing
MOTOROLA
MC145554•MC145557•MC145564•MC145567
11
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
– 5 V
V
VF I +
X
BB
GNDA
ANALOG IN
VF I –
X
ANALOG OUT
+ 5 V
GS
VF
V
O
X
R
TX TIME SLOT
TS
X
FS
X
CC
MC145554/57
FS
R
D
D
BCLK
MCLK
R
X
X
X
BCLK / CLKSEL
R
MCLK / PDN
R
8 kHz
1
16
MODE
DDO
V
+ 5 V
DD
2
3
4
5
6
7
8
15
14
13
12
11
10
9
ADPCM OUT
EDO
EOE
DDE
1.544 MHz/
2.048 MHz
DDC
DDI
DIE
EDC
EDI
EIE
MC145532
ADCPM IN
POWER–DOWN
SPC
ADP
20.48 MHz
PD/RESET
V
SS
Figure 3. ADPCM Transcoder Application
MC145554•MC145557•MC145564•MC145567
MOTOROLA
12
MC33120
15
12
13
14
20
19
+ 5 V
V
V
DD
CC
EP
PDI/ST2
ST1
HOOK STATUS/
FAULT INDICATION
+
18
BP
5 µF, 16 V
MJD253
1N4002
V
DG
1N4002
– 48 V
9
+ 5 V
V
AG
100
1/4 W
MC145554/7
0.01
µF
1 k
9.1 k
9.1 k
1 k
4
17
50 V
V
CP
CC
48.5 k
10
8
3
12
16
5
8 kHz SYNC
V
RXI
FS
FS
FRO
X
TIP
RING
TSI
RSI
CN
5
R
4.7 k
20.6 k
47.4 k
10
7
BCLK
DATA CLOCK
MC145554 =
1.544 MHZ
MC145557 =
2.048 MHz
X
R
R
4
RFO
BCLK
MCLK
8
100
1/4 W
1 µF
9
1
µF
MCLK
D
X
X
11
7
15
14
11
6
TXO
CF
VF I–
X
0.01
µF
TO PCM HWY
10 k
3
GS
X
D
50 V
R
MJD243
BN
EN
49.0 k
16
2
13
1
300
Ω
VF I+
X
TS
X
1N4002
6
2
1
1.0 µF, 50 V
VQB
GNDA
V
BB
+
1N4002
– 48 V
V
20
Ω
EE
10 µF, 50 V
– 5 V
+
NOTE: Six resistors and two capacitors on the two–wire side can be 5% tolerance.
Figure 4. A Complete Single Party Channel Unit Using MC145554/57 PCM Codec–Filter and MC33120 SLIC
MOTOROLA
MC145554•MC145557•MC145564•MC145567
13
“S” TRANSCEIVER
LAP–D/LAP–B CONTROLLER
+ 5 V
MC145474P
+ 5 V + 5 V
MC145488
17
2
4
52, 2, 9
V
V
D0 10
D1 11
D2 12
D3 13
D4 14
D5 15
D6 16
D7 17
D8 18
D9 19
D10 20
D11 22
D12 23
D13 24
D14 25
D15 26
A1
A2
A3
A4
A5
A6
A7
TE/NT
DD
DD
33 k
+ 5 V
ISET
8
9
60, 44
59, 45
S INTERFACE
SYNC
CLK
RX
SYNC 0, 1
CLK 0, 1
TX 0, 1
7
Ω
7
7
Ω
Ω
21
20
TX+
TX–
10
11
7
55, 49
56, 48
47
+ 5 V
RX 0, 1
TX
7
Ω
DREQ 1
DREQ
5
46
+ 5 V
DGNT 1
DGRT
50 SCPE 1
15
14
13
12
53
1 kΩ
1 kΩ
2
SCPE 0
SEL
CLK
RX
RX+
RX–
57
SCP CLK
+ 5 V
54
MPU
BUS
SCP TXD
8
7
6
5
4
3
1
58
1 kΩ
1 kΩ
3
6
SCP RXD
TX
IRQ
V
SS
XTAL
RESET
EXTAL
19
15.36 MHz
A8 68
A9 67
A10 66
A11 65
A12 64
A13 63
A14 62
A15 61
OWN0 42
OWN1 43
MCLK 27
CS 28
30 pF
+ 5 V
30 pF
HANDSET
MC145554P
RJ–1
1
500
Ω
3
4
+ RCVR
(WHITE)
V
VF
O
CC
R
+ 5 V
12, 5
FS , FS
X
R
10, 7, 8, 9
500
0.1
Ω
MCLK, BCLK
10 kΩ
15
14
16
11
6
+ MIC (RED)
– RCVR
VF I–
D
X
X
R/W 29
AS 30
µF
GS
D
R
X
(WHITE)
13
1
VF I+
X
TS
– MIC (BLK)
X
LDS 31
UDS 32
RST 33
IACK 34
IRQ 36
DTACK 37
BERR 38
BR 39
2
V
GNDA
BB
CODEC–FILTER
– 5 V
51, 36, 21
V
SS
BG 40
BGACK 41
Figure 5. ISDN Voice/Data Terminal
MC145554•MC145557•MC145564•MC145567
MOTOROLA
14
Table 3. Mu–Law Encode–Decode Characteristics
Normalized
Digital Code
Encode
Decision
Levels
Normalized
Decode
Levels
1
2
3
4
5
6
7
8
Chord
Number
Number
of Steps
Step
Size
Sign
Chord Chord Chord Step
Step Step
Step
8159
7903
4319
4063
2143
2015
1055
991
511
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
8031
4191
2079
1023
495
231
99
8
16
256
7
6
5
4
3
2
1
16
16
16
16
16
16
128
64
32
16
8
479
239
223
103
95
4
35
33
31
15
1
2
1
3
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
0
NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes inversion of all magnitude bits.
MOTOROLA
MC145554•MC145557•MC145564•MC145567
15
Table 4. A–Law Encode–Decode Characteristics
Normalized
Digital Code
Encode
Decision
Levels
Normalized
Decode
Levels
1
2
3
4
5
6
7
8
Chord
Number
Number
of Steps
Step
Size
Sign
Chord Chord Chord Step
Step Step
Step
4096
3968
2176
2048
1088
1024
544
512
272
256
136
128
68
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
4032
2112
1056
528
264
132
66
7
16
128
6
5
4
3
2
16
16
16
16
16
32
64
32
16
8
4
64
1
2
2
1
0
NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes alternate bit inversion, as specified by CCITT.
MC145554•MC145557•MC145564•MC145567
MOTOROLA
16
PACKAGE DIMENSIONS
L SUFFIX
CERAMIC PACKAGE
CASE 620–09
(MC145554/57)
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
1
9
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
-B-
8
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
0.770
0.290
0.165
0.021
MIN
19.05
6.10
—
0.39
1.27 BSC
MAX
19.55
7.36
4.19
0.53
0.750
0.240
—
0.015
0.050 BSC
-T-
SEATING
PLANE
K
0.055
0.070
1.40
1.77
F
G
J
K
L
M
N
0.100 BSC
2.54 BSC
M
N
E
0.009
0.011
0.23
0.27
—
0.200
—
5.08
J 16 PL
G
F
0.300 BSC
15
0.035
7.62 BSC
15
0.39 0.88
D 16 PL
0°
°
0°
°
M
S
0.25 (0.010)
T
B
0.015
M
S
0.25 (0.010)
T
A
P SUFFIX
PLASTIC DIP
CASE 648–08
(MC145554/57)
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
B
8
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
M
S
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
2.54 BSC
1.27 BSC
0.21
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
0.100 BSC
0.050 BSC
0.008
C
L
S
SEATING
PLANE
–T–
K
M
0.015
0.130
0.305
10
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
M
T
A
MOTOROLA
MC145554•MC145557•MC145564•MC145567
17
DW SUFFIX
SOG PACKAGE
CASE 751G–02
(MC145554/57)
–A–
16
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
–B–
8X P
0.010 (0.25)
M
M
B
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
1
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
J
16X D
M
S
S
0.010 (0.25)
T
A
B
F
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
10.15
7.40
2.35
0.35
0.50
MAX
10.45
7.60
2.65
0.49
0.90
MIN
MAX
0.411
0.299
0.104
0.019
0.035
0.400
0.292
0.093
0.014
0.020
R X 45
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
M
SEATING
14X G
K
PLANE
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
L SUFFIX
CERAMIC PACKAGE
CASE 732–03
(MC145564/67)
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
20
1
11
10
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
MILLIMETERS
INCHES
A
DIM
A
B
C
D
F
MIN
23.88
6.60
3.81
0.38
1.40
MAX
25.15
7.49
5.08
0.56
1.65
MIN
MAX
0.990
0.295
0.200
0.022
0.065
0.940
0.260
0.150
0.015
0.055
L
C
F
G
H
J
K
L
2.54 BSC
0.100 BSC
0.51
0.20
3.18
1.27
0.30
4.06
0.020
0.008
0.125
0.050
0.012
0.160
N
J
7.62 BSC
0.300 BSC
H
K
M
G
M
N
0
15
0
15
D
0.25
1.02
0.010
0.040
SEATING
PLANE
MC145554•MC145557•MC145564•MC145567
MOTOROLA
18
P SUFFIX
PLASTIC DIP
CASE 738–03
(MC145564/67)
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
20
1
11
10
B
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
E
F
G
J
K
L
M
N
MIN
MAX
1.070
0.260
0.180
0.022
MIN
25.66
6.10
3.81
0.39
1.27 BSC
1.27
2.54 BSC
0.21
MAX
27.17
6.60
4.57
0.55
1.010
0.240
0.150
0.015
0.050 BSC
0.050
0.100 BSC
0.008
0.110
-T-
SEATING
PLANE
K
M
0.070
1.77
E
N
0.015
0.140
0.38
3.55
G
F
J 20 PL
2.80
0.300 BSC
15
0.040
7.62 BSC
15
0.51 1.01
D 20 PL
M
M
0.25 (0.010)
T
B
0°
°
0°
°
0.020
M
M
0.25 (0.010)
T
A
DW SUFFIX
SOG PACKAGE
CASE 751D–04
(MC145564/67)
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
10X P
–B–
M
M
0.010 (0.25)
B
1
10
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
20X D
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
0.010 (0.25)
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
MOTOROLA
MC145554•MC145557•MC145564•MC145567
19
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