MC145740F [MOTOROLA]
Dual Tone Multiple Frequency Line Interface; 双音多频线接口
| 型号： | MC145740F |
| 厂家： | 
MOTOROLA |
| 描述： | Dual Tone Multiple Frequency Line Interface |
| 文件： | 总12页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MC145740/D
SEMICONDUCTOR TECHNICAL DATA
Product Preview
20
F SUFFIX
SOG PACKAGE
CASE 751J
1
The MC145740 is a silicon gate HCMOS LSI designed for general purpose
Dual Tone Multiple Frequency (DTMF) communications, and contains a DTMF
signal generator and a receiver for all 16 standard digits.
The generator block has a differential line driver which drives a 600 Ω load
with 0 dBm level. The transmit signal level is adjusted in 1 dB steps by the
programmable attenuator.
ORDERING INFORMATION
MC145740F
SOG Package
The receiver block has an Auto Gain Control (AGC) amplifier to demodulate
50 dB (typ) dynamic range of DTMF signals to the hexadecimal codes.
The device also includes a serial control interface that permits a CPU to
exercise the following built–in features.
PIN ASSIGNMENT
•
•
•
•
•
•
•
Single Power Supply: 3.6 to 5.5 V
DTMF Generator and Receiver for All 16 Standard Digits
0 dBm Line Driver Into 600 Ω Load
AGC Amplifier
Programmable Transmit Attenuator
Serial Control Interface
TxA1
1
20
19
DSI
TxA2
RxA
2
V
V
DD
3
4
18
17
SS
AGC
out
CLK
V
5
6
16
15
EN
ref
Power Down Mode, Less Than 1 µA
FC1
DATA
FC2
X1
7
14
13
12
11
R/W
TD
8
X2
9
DV
V
10
V
DD
SS
BLOCK DIAGRAM
AGC
out
FC1
FC2
TIMING
CIRCUIT
HIGH–BAND
BPF
DV
TD
Rx GAIN
CONTROL
WITH AGC
AMP
ANTI–ALIAS
FILTER
DTMF
DETECTER
RxA
DSI
LOW–BAND
BPF
SMOOTHING
FILTER AND
Tx GAIN
EN
CLK
DATA
R/W
DTMF
GENERATOR
CONTROL REGISTER
AND
SERIAL INTERFACE
–
+
TxA2
TxA1
CONTROL
– 1
CLOCK
GENERATOR
X1
X2
V
V
V
ref
DD
SS
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 0
8/96
Motorola, Inc. 1996
MAXIMUM RATINGS (Voltages Referenced to V
Unless Otherwise Noted)
Value
SS
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields. However, it is advised
that normal precautions be taken to avoid
applications of any voltage higher than maxi-
mum rated voltages to this high impedance
circuit. For proper operation, it is recommended
Ratings
DC Supply Voltage
Symbol
Unit
V
V
CC
– 0.5 to + 7.0
Input Voltage, All Pins
DC Current Per Pin
V
– 0.5 to V
CC
+ 0.5
V
in
I
± 20
500
– 65 to + 150
mA
mW
°C
Power Dissipation
P
D
that V and V
in out
be constrained to the range
V
≤ (V or V ) ≤ V
.
Storage Temperature Range
T
stg
SS
in out
DD
Reliability of operation is enhanced if unused
logic inputs are tied to an appropriate logic volt-
age level (e.g., either V
or V ).
DD
SS
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
5
Max
Unit
V
DC Supply Voltage
V
CC
3.6
0
5.5
Input Voltage, All Pins
V
in
—
V
CC
V
Input Rise or Fall Time
t , t
0
—
500
—
ns
r
f
Crystal Frequency
f
—
3.5795
25
MHz
°C
osc
Operating Temperature Range
T
A
– 20
70
DC ELECTRICAL CHARACTERISTICS (V
CC
= 5 V ± 10%, T = – 20 to 70°C)
A
Parameter
Symbol
Condition
Min
3.15
—
Typ
—
Max
—
Unit
Input Voltage
H Level
L Level
H Level
L Level
V
IH
V
EN, CLK, DATA, R/W
Output Voltage
V
IL
—
1.1
—
V
OH
I
= 20 µA
V
– 0.1
V – 0.01
CC
V
OH
CC
DV, TD, DATA
V
OL
I
I
= – 20 µA
= – 2 mA
—
—
0.01
—
0.1
0.4
OL
OL
Input Current
R/W, DATA, EN, CLK
I
V
= V
or V
SS
—
—
—
—
—
± 1.0
5
± 10.0
—
µA
in
in
DD
Supply Current
I
I
DTMF Tx Mode
DTMF Rx Mode
Power Down 1
Power Down 2
mA
DD
8
—
Standby Current
—
—
500
1
µA
DD
MOTOROLA
MC145740
2
AC ELECTRICAL CHARACTERISTICS
DTMF TRANSMIT CHARACTERISTICS (V
CC
= 5 V ± 10%, T = – 20 to 70°C)
A
Parameter
Transmit Level
Symbol
Condition
Min
—
—
0
Typ
2.5
3.5
—
Max
—
—
3
Unit
Low Group
High Group
V
fl
Attenuator = 0 dB
dBm
f
V
R
= 3.579545 MHz
osc
V
fh
– V
TxA1
= 1.2 kΩ
TxA2
High Group Pre–Emphasis
DTMF Distortion
PE
DIST
∆fV
dB
%
L
—
– 1
—
5
—
1
DTMF Frequency Variation
—
%
Out–of–Band Energy
(See Figure 1)
V
OE
—
—
Setup Time
t
—
4
—
ms
osc
TRANSMIT ATTENUATOR CHARACTERISTICS (V
CC
= 5 V ± 10%, T = – 20 to 70°C)
A
Parameter
Attenuator Range
Attenuator Accuracy
Symbol
ARNG
AACC
Condition
Min
0
Typ
—
Max
15
0.5
1
Unit
dB
1 dB – 5 dB
6 dB – 9 dB
– 0.5
– 1
—
dB
—
10 dB – 15 dB
– 1.7
—
1
DTMF RECEIVER CHARACTERISTICS (V
CC
= 5 V ± 10%, T = – 20 to 70°C)
A
Parameter
Input Impedance
Symbol
RIDTMF
Condition
Min
50
Typ
—
Max
—
Unit
kΩ
Detect Signal Level (Each Tone)
Twist (High Group/Low Group)
Frequency Detect Band Width
Frequency Reject Band Width
– 48
– 10
—
0
dBm
dB
—
10
—
See Figure 3
± 1.5% ± 2 Hz
—
% fc
—
—
—
—
—
—
—
—
± 3.5
—
DTMF Detect Timing
(See Figure 2)
OFF to ON
TVD
CD1 = 0, CD0 = 1
CD1 = 1, CD0 = 0
CD1 = 1, CD0 = 1
CD1 = 0, CD0 = 1
CD1 = 1, CD0 = 0
CD1 = 1, CD0 = 1
20
30
40
20
30
20
ms
ON
—
—
ON to OFF
TVD
—
OFF
—
—
MOTOROLA
MC145740
3
SWITCHING CHARACTERISTICS (V
Parameter
= 5 V ± 10%, T = – 20 to 70°C, See Figure 4)
A
CC
Symbol
Number
Min
50
50
100
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
2
Unit
ns
Pulse Width (H)
EN, SCK
EN, SCK
t
1
2
wh
Pulse Width (L)
t
wl
ns
Clock Cycle
t
c
3
ns
Input Rise Time
t
r
4
µs
µs
ns
Input Fall Time
t
f
5
—
2
Recovery Time
Setup Time
EN to SCK
DATA to SCK
R/W Low to DATA
R/W High to DATA
SCK to DATA
EN to R/W
t
6, 18
7
50
50
100
50
50
50
50
50
—
—
—
—
—
—
—
—
—
50
50
rec
t
ns
su
9
12
8
Hold Time
t
ns
ns
h
d
10
14
15
13
17
DATA to R/W
R/W to DATA
EN to DATA
Read Data Delay Time
t
SCK to DATA
—
MOTOROLA
MC145740
4
f (Hz)
0
3.4 k 4 k
16 k
256 k
0
– 25
– 55
– 15 dB/OCT.
Figure 1. Out–of–Band Energy
DTMF TONE CHANGED WITHOUT SILENT PERIOD
“A”
“B”
“C”
“D”
RxA
t
1
10 mS
(NOTE 1)
on
TD
DV
t
t
off
(NOTE 2)
on
(NOTE 3)
D0 – D3
“A”
“B”
“C”
“D”
NOTES:
1. The high–to–low and low–to–high transition on the TD pin will appear immediately after the valid DTMF
tones are detected. The TD will also output a short H pulse when the device detects the DTMF tones
being changed without a silent period.
2. The high–to–low and low–to–high transition on the DV pin will appear after the programmed guard time
determined by two bits of serial data (CD1, CD0).
3. The device recognizes the DTMF tones changed without a silent period, and the four bits of data can
be read from the status register.
Figure 2. DTMF Detect Timing
DETECT MINIMUM
NO DETECT
NO DETECT
WIDTH
– 3.5%
+ 3.5%
– 1.5% – 2 Hz
+ 1.5% + 2 Hz
LO
Figure 3. DTMF Frequency Detect Band Width
MOTOROLA
MC145740
5
CONTROL REGISTER
1
(NOTE 1)
EN
(NOTE 6)
6
3
7
1
2
3
4
5
6
7
8
9
10
5
11
12
13
14
CLK
(LSB CLOCK)
7
2
9
1
4
8
T3
T2
T1
T0
A3
A2
A1
A0
CD1
CD0
SQ
M2
M1
M0
DATA
R/W
10
STATUS REGISTER
11
EN
(NOTE 6)
12
18
3
5
4
(NOTE 5)
1
2
3
1
0
1
2
1
CLK
17
2
5
13
D0
4
(NOTE 2)
D0
(NOTE 3)
HIGH IMPEDANCE
15
D1
16
D2
D3
D1
D2
D0
D1
DATA
14
(NOTE 4)
R/W
NOTES:
1. The data in front of the EN signal will be latched.
2. The latched data will be repeated until there is an EN pulse.
3. The detected data will be updated with the next EN pulse.
4. After the R/W pin becomes inactive, the data will be lost.
5. D1 corresponds to CLK1.
6. The EN and CLK signals need to be set at the logic low level when the R/W signal changes.
7. The CLK signal must be held low when the EN signal is high.
Figure 4. Serial Interface Timing
MOTOROLA
MC145740
6
(t ) is programmed by two bits of serial data (CD1, CD0) as
off
PIN DESCRIPTIONS
shown in Table 2. This feature improves the immunity to the
short noise and momentary dropouts. See Figure 2 for the
detailed timing diagram.
TxA1
Non–Inverting Analog Output (Pin 1)
This pin is the line driver non–inverting output. A + 7 dBm
(typ) differential output voltage can be obtained by connect-
ing a 1.2 kΩ load resistor between TxA1 and TxA2. Note that
the DSI input, if used, must be controlled for the output level
not to exceed the above signal level.
TD
Tone Detect (Pin 13)
This pin goes low immediately after valid DTMF tones are
detected, regardless of the guard time set by two bits of
serial data. This pin also outputs the short high pulse when
the device detects the change of DTMF tones without a silent
period. For a detailed description, see Figure 2.
TxA2
Inverting Analog Output (Pin 2)
This pin is the driver inverting output. Refer to TxA1.
RxA
R/W
DTMF Receive Input (Pin 3)
Read/Write Data Switch (Pin 14)
This pin is the DTMF signal input (AGC input).
This pin is used for controlling the input/output direction of
the DATA I/O pin.
AGC
out
AGC Output (Pin 4)
DATA
This pin is the AGC amplifier output. The signal received
from the RxA pin appears at this pin through the AGC amplifi-
er so that any signal receivers can be connected on this pin
to decode the non–DTMF signals. The AGC amplifier gain is
software programmable as shown in Table 3.
Serial Data Input/Output (Pin 15)
When the R/W pin is at logic low, the DATA pin works as
the 14–bit control register input which determines the func-
tion mode, DTMF tones, transmit level (or receiver gain lev-
el), detect time, and transmit squelch. When the R/W pin is at
logic high, the DATA pin works as the 4–bit status register
output which provides the hexadecimal codes corresponding
to the detected digit.
V
ref
Reference Analog Ground (Pin 5)
This pin provides the analog ground voltage, V /2, which
CC
is internally regulated from V
decoupled to GND with 0.1 µF and 100 µF capacitors.
. This pin should be
CC
EN
Enable Input (Pin 16)
FTLC1, FTLC2
Band–Pass Filter Test (Pins 6, 7)
When the R/W pin is held low, high level input to this pin
transfers the 14 bits of control register data to the mode
control logic, then the function mode is immediately
changed. When this pin is at logic low, the control register
and the mode control logic are isolated. Therefore, the
14 bits of data in the control register must not be changed
while EN is at logic high level.
These pins are high impedance filter outputs. They may be
used for testing the DTMF receive high and low band–pass
filter characteristics, and are reserved for manufacturer’s use
only. In normal operation, each pin is decoupled to V with
0.1 µF capacitors.
ref
When the R/W pin is held high, the rising edge of the EN
pin loads the DTMF data from the DTMF decoder into the
status register, and shifts out the first bit (LSB = D0) to the
DATA pin.
X1
Crystal Oscillator Output (Pin 8)
A 3.579545 MHz ± 0.1% crystal oscillator is tied to this pin
with the other end connected to X2.
CLK
X2
SPI Clock Input (Pin 17)
Crystal Oscillator Input (Pin 9)
This pin is the SPI clock input for the 14–bit control register
and the 4–bit status register. At the rising edge of CLK, the
14 bits of data are captured into the control register when
R/W is at logic low, and the 4 bits of data are shifted out from
the status register when R/W is at logic high.
A 3.579545 MHz ± 0.1% crystal oscillator is tied to this pin
with the other end connected to X1. X2 may be driven
directly from an appropriate external clock source. In this
case, X1 should be held open.
GND
Ground (Pins 10, 18)
DSI
Driver Summing Input (Pin 20)
Ground pins are connected to the system ground.
This pin is the inverting input of the line driver. An external
signal source may be connected to this pin through a series
V
CC
Power Supply (Pins 11, 19)
resistor R
, transmitting the signal from the TxA1 and
DSI
TxA2. The differential gain G
The digital supply pins are connected to the positive power
supply (5 V).
= (V
– V
)/V
DSI
is determined by the following equation:
TxA1 TxA2 DSI
G
= – 2 R /R , R – 20 kΩ
DV
DSI
F
DSI
F
DTMF Data Valid (Pin 12)
Note that the programmable transmit attenuator does not
affect this case.
This pin goes low when valid DTMF tones are detected.
The guard time of DTMF tone detection (t ) and release
The DSI pin should be held open when not in use.
on
MOTOROLA
MC145740
7
Single Tone Mode (M2 – M0 = 0, 1, 0)
SERIAL DATA INTERFACE
The transmitter generates one of the eight frequencies of
DTMF tones. The receiver is disabled.
REGISTER MAP DESCRIPTION
The timing diagram of the 14–bit control register input and
the 4–bit status register output is shown in Figure 4. When
the R/W pin is at logic low (write is selected), the control reg-
ister is enabled. The 14 bits of data are captured into the con-
trol register at the rising edge of SCK. The 14 bits of data in
the control register are transferred to the mode control logic
at logic high to the EN pin, and then the function mode is im-
mediately changed.
When the R/W pin is at logic high (read is selected), the
status register is enabled to read out the decoded DTMF
data. At the rising edge of EN, the four bits of data in the
DTMF decoder are loaded into the status register, and the
first bit (D0) is presented on the DATA pin. The next three bits
are shifted out by following rising edges of CLK (see Figure
4).
Power Down Mode (Mode 1: M2 – M0 = 0, 1, 1;
Mode 2: M2 – M0 = 1, 0, 0)
In Power Down Mode 1, all internal circuits except for the
oscillator are disabled, so that all output pins except for the
X1 are in high–impedance state. The device current is
decreased to 500 µA (max). In Power Down Mode 2, all inter-
nal circuits are disabled, so all output pins are in high imped-
ance state. The device current is decreased to 1 µA (max).
Analog Loopback Mode (M2 – M0 = 1, 0, 1)
The transmitter output is internally connected to the
receiver input.
FUNCTION MODE (M2 – M0)
TRANSMIT SQUELCH (SQ)
These three bits (M2 – M0) determine the function mode
shown in Table 1.
When the SQ bit is 1, the DTMF and single tone transmis-
sion are disabled (squelch is selected). However, the trans-
mit squelch does not affect the external signal input from
DSI.
Table 1. Function Mode Truth Table
M2
0
M1
0
M0
0
Function Mode
DTMF Receive
DTMF TONE DETECT/REJECT TIME (CD1, CD0)
0
0
1
DTMF Transmit
Single Tone Transmit
Power Down 1
0
1
0
The CD1 and CD0 bits determine DTMF tones detect time
(t ) and release time (t ) of the DV pin, as shown in
0
1
1
on
off
Table 2. The timing diagram is shown in Figure 2.
1
0
0
Power Down 2
1
0
1
Analog Loopback
Table 2. DTMF Detect Time Truth Table
DTMF Receive Mode (M2 – M0 = 0, 0, 0)
CD1
CD0
t
on
(ms)
t
off
(ms)
0
0
1
1
0
1
0
1
Reserved
The DTMF receiver is enabled. The transmitter is disabled.
20
20
DTMF Transmit Mode (M2 – M0 = 0, 0, 1)
30
40
30
20
The DTMF tone generator is enabled. The receiver is dis-
abled.
CONTROL REGISTER (R/W = “L”)
FUNCTION MODE
: 3 BITS
: 1 BIT
M2
SQ
CD1
A3
M1
M0
TRANSMIT SQUELCH
DTMF DETECT TIME
: 2 BITS
: 4 BITS
: 4 BITS
CD0
A2
TRANSMIT ATTENUATOR/AGC GAIN
TRANSMIT FREQUENCY
A1
T1
A0
T0
T3
T2
STATUS REGISTER (R/W = “H”)
RECEIVED TONE FREQUENCY
: 4 BITS
D3
D2
D1
D0
MOTOROLA
MC145740
8
TRANSMIT ATTENUATOR/AGC GAIN (A3 – A0)
TRANSMIT TONE FREQUENCY (T3 – T0)
The T3 – T0 bits determine DTMF tone frequencies trans-
mitted from TxA1 and TxA2 in DTMF transmit and analog
loopback mode, and determine the single tone frequency in
single tone mode. Tone frequency assignments for the
T3 – T0 bits are shown in Table 4.
The A3 – A0 bits determine the analog transmit level of
DTMF tones. The transmit attenuator range is controlled
from 0 to 15 dB in 1 dB steps as shown in Table 3. However,
this attenuator does not affect the external signal source
from DSI. These four bits also determine the AGC amplifier
gain in DTMF receive mode. In normal operation, “automatic”
may be selected so that the receiver’s gain is automatically
adjusted, corresponding to the input signal level.
RECEIVED TONE FREQUENCY (D3 – D0)
The D3 – D0 bits provide hexadecimal codes correspond-
ing to detected DTMF tones. Tone frequency assignments
for the D3 – D0 bits are shown in Table 4.
Table 3. Transmit Attenuator/AGC Gain Set Truth Table
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
A1
A0
Tx Attenuation (dB)
Rx AGC Gain (dB)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
– 5.0
– 2.5
0.0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
3
2.5
4
5.0
5
7.5
6
10.0
12.5
15.0
17.5
20.0
Clamp
Automatic
—
7
8
9
10
11
12
13
14
15
—
—
MOTOROLA
MC145740
9
Table 4. Tone Frequency Truth Table
Tone Frequency (Hz)
DTMF Tx/Rx Mode Frequency
Keyboard
Single Tone
Mode
Equivalent
T3/D3
T2/D2
T1/D1
T0/D0
High Group
Low Group
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
697
1
2
3
4
5
6
7
8
9
0
*
697
697
697
697
697
770
770
770
770
770
770
852
852
852
1336
1477
1336
1209
1477
1633
1633
1633
941
852
941
941
941
#
A
B
C
D
697
770
852
941
MOTOROLA
MC145740
10
APPLICATION CIRCUIT
10
Ω
600 : 600
R
DSI
TIP
TxA1
DSI*
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
600
Ω
*
100
µF
TxA2
RxA
V
CC
+ 5 V
RING
GND
CLK
0.1 µF
AGC
*
out
V
ref
FC1
FC2
X1
EN
0.1
0.1
µF
DATA
R/W
TD
µF
100
µF
0.1 µF
MCU
3.579545 MHz
X2
DV
GND
V
CC
Protection Network
Reference Analog Ground
System Ground
*
* The external devices (i.e., modem) may be connected on these pins, using the built–in line interface circuit.
MOTOROLA
MC145740
11
PACKAGE DIMENSIONS
F SUFFIX
SOG (SMALL OUTLINE GULL–WING) PACKAGE
CASE 751J–02
NOTES:
–A–
M
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.12 (0.006) PER
SIDE.
20
1
11
10
–B–
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
G
S 10 PL
M
M
0.13 (0.005)
B
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
12.55
5.10
–––
MAX
12.80
5.40
2.00
0.45
MIN
MAX
0.504
0.213
0.079
0.018
0.494
0.201
–––
C
0.35
0.014
G
J
K
L
M
S
1.27 BSC
0.050 BSC
K
0.10 (0.004)
0.18
0.55
0.05
0
0.23
0.85
0.20
7
0.007
0.022
0.002
0
0.009
0.033
0.008
7
D20 PL
L
–T– SEATING
PLANE
M
S
S
0.13 (0.005)
T
B
A
J
7.40
8.20
0.291
0.323
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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