MC145745FW [MOTOROLA]
V.21/V.23 Telemeter Modem; V.21 / V.23调制解调器遥测
| 型号： | MC145745FW |
| 厂家： | 
MOTOROLA |
| 描述： | V.21/V.23 Telemeter Modem |
| 文件： | 总16页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MC145745/D
SEMICONDUCTOR TECHNICAL DATA
Product Preview
The MC145745 is a selectable modem chip compatible with ITU V.21
(300 baud full duplex asynchronous) and V.23 mode 2 (1200 baud half duplex
asynchronous). The built–in differential line driver has the capability of driving
0 dBm into a 600 Ω load with a 5 V single power supply. This device also
includes a DTMF generator, DTMF receiver, call–progress tone detector,
answer tone generator, and a receive timing control circuit.
Besides having a clock generator with a crystal oscillator connected to it, the
device has a divider circuit to which input of a double frequency clock is possible
from external sources, such as from a microcontroller unit (MCU). The serial
control port (SCP) permits the MCU to access internal registers for exercising
the built–in features.
FW SUFFIX
SOIC
CASE 751M
28
1
ORDERING INFORMATION
MC145745FW SOIC
PIN ASSIGNMENT
A low consumption device, the MC145745 integrates various functions in a
small package. This modem IC is best suited for telemeter and other
applications of this type.
GND
1
2
28
27
V
CC
V
RxA
ref
3
26
25
24
23
22
21
20
19
18
17
•
•
•
•
•
•
•
•
•
Conforms to ITU V.21 and V.23 Recommendations
DTMF Generator and Receiver for all 16 Standard Digits
CDA
TLA
TxA1
4
TxA2
Capable of Driving 0 dBm into a 600 Ω Load (V
= 5 V)
CC
5
TEST 1
RxD
TEST 2
SCPEN
SCPCLK
SCP Rx
SCP Tx
RESET
PB3
Automatic Gain Control (AGC) Amplifier for the DTMF Receiver
Call–Progress Tone Detector
Four–Wire Serial Data Interface (SCP)
Programmable Transmission and Carrier Detection Levels
FSK/DTMF Analog Loopback Self–Test Function
Crystal Oscillator (3.579545 MHz) and Half Divider Circuit (7.159090 MHz)
for External Inputs
6
7
TxD
8
CD
CLKO
X1
9
10
X2 11
•
•
Operates in the Voltage Range of 3.3 – 5.5 V
Power Down Mode (I
CC
< 1 µA)
ECLK
PB2
12
PB0
PB1
13
14
16
15
GND
V
CC
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 0
7/96
Motorola, Inc. 1996
BLOCK DIAGRAM
4
Rx AMP
AND AGC
CONTROL
PB0 – PB3
CD
ANTI–ALIAS
AND
LOW–PASS
FILTER
DTMF
RECEIVER
RxA
CPT
DETECTOR
TIMING
CONTROL
CIRCUIT
CDA
LOOPBACK
PATH
TONE
GENERATOR
FSK
CARRIER
DETECTOR
V
ref
SMOOTHING
FILTER
AND
Tx GAIN
CONTROL
FSK V.21
MODEM
TxD
TxA2
TxA1
–
+
FSK V.23
MODEM
RxD
CLOCK
GENERATOR
CLKO
1/2
RESET
X1
X2
ECLK
TLA
V
GND
SCP Tx SCP Rx SCPEN SCPCLK
CC
MC145745
2
MOTOROLA
PIN DESCRIPTIONS
Pin
Location
Symbol
Type
Description
1, 14
GND
—
Ground — These are the ground pins of the digital and the analog circuits. The 0 V potential of the
device is determined by the input voltage at these pins.
2
3
V
—
—
Reference Analog Ground — This pin provides the analog ground voltage V /2, which is regulated
CC
ref
internally. This pin should be decoupled to GND with 0.1 µF and 100 µF capacitors.
CDA
Carrier Detect Level Adjustment — The detection level for FSK/call–progress tone is determined
according to the voltage at this pin. When V
= 5 V and the carrier detection level bit (BR3:b1) of the
CC
= 3.6 V and (BR3:b1) is 1, the CDA voltage is set to 1.25 V by the
SCP register is 0, or when V
internal divider.
CC
This voltage sets the detection levels at ON to OFF: – 44 dBm (typ) and OFF to ON: – 47 dBm (typ).
This high impedance pin should be decoupled to GND with a 0.1 µF capacitor.
The carrier detection level is proportional to the terminal voltage at this pin.
An external voltage may be applied to this pin to adjust the carrier detect threshold. The following
equations may be used to find the CDA voltage requirements for a given threshold voltage.
V
CDA
V
CDA
= 256 x V
= 362 x V
off
on
4
TLA
—
Transmit Level Adjustment — This pin is used to adjust the transmit carrier level which is determined
by the resistor (RTLA) connected between this pin and GND. The maximum level is obtained when
this pin is shorted to GND (RTLA = 0).
5, 24
6
TEST 1,
TEST 2
I/O
O
Test Pins 1 and 2 — These test pins are for manufacturer’s use only. These pins should be left open in
normal operation.
RxD
TxD
CD
Receive Data Output — This pin is the receive data output. When the device is in the FSK mode, logic
high on this pin indicates that the mark carrier frequency has been received from RxA, and the logic
low indicates that the space carrier frequency has been received.
7
8
I
Transmit Data Input — This pin is the transmit data input. When the device is in the FSK mode, logic
high on this pin generates the mark frequency at TxA1 and TxA2 output, and logic low generates the
space frequency.
O
Carrier Detect Output — This pin outputs at low level if a valid FSK, DTMF, or CPTD signal is
received. If the pin is at high level, the receive data output pin (RxD) is internally clamped at high level
to avoid erroneous output of received data caused by line noise.
9
CLKO
X1
O
O
I
Clock Output — This pin provides a buffered 3.58 MHz clock output that can drive one CMOS device
such as the MC74HC04.
10
11
12
13
Crystal Oscillator Circuit Output — A 3.579545 MHz ± 0.1% crystal oscillator is tied to this pin with the
other end connected to X2.
X2
Crystal Oscillator Circuit Input — A 3.579545 MHz ± 0.1% crystal oscillator is tied to this pin with the
other end connected to X1. X2 may be driven directly from an appropriate external clock source.
ECLK
PB0
I
External Clock Input — ECLK is the input of double frequency, 7.159090 MHz ± 0.1%, of the reference
clock. This pin must be connected to GND when not in use.
O
DTMF Receive Data Parallel Output 0 (LSB) — Pins 13, 16, 17, and 18 are the DTMF receive data
parallel output occurring together with the CD (Pin 8) data valid output. The outputs of these pins are
valid as long as the CD pin is low. In power down modes 1 and 2, the DTMF receiver is disabled and
these pins are in high impedance.
15, 28
V
—
O
I
Positive Power Supply — These are the power supply pins for the digital and the analog circuits.
These pins should be decoupled to GND with 0.1 µF and 100 µF capacitors.
CC
16, 17, 18 PB1, PB2,
PB3
DTMF Receive Data Parallel Outputs 1, 2, and 3 (MSB) — These pins are the DTMF receiver data
parallel outputs. See pin 13 for more details.
19
RESET
Reset — A high to low trigger pulse applied to this pin sets all the registers in the default state. It
should remain at high during normal operations.
20
21
22
23
SCP Tx
SCP Rx
SCPCLK
SCPEN
O
I
SCP Output Transmit — Refer to Serial Control Port (SCP Interface) for additional information.
SCP Receive Input — Refer to Serial Control Port (SCP Interface) for additional information.
SCP Clock — Refer to Serial Control Port (SCP Interface) for additional information.
SCP Enable — Refer to Serial Control Port (SCP Interface) for additional information.
I
I
MOTOROLA
MC145745
3
PIN DESCRIPTIONS (continued)
Pin
Location
Symbol
Type
Description
25
TxA2
O
Transmit Buffer Output 2 (Inverting) — This pin is the inverting output of the line driver. When V
=
CC
5 V, + 7 dBm (typ), differential output voltage (V
– V
), can be obtained with a load of 1.2 kΩ
TxA2
TxA1
between pins TxA1 and TxA2. In typical applications, the output level on the telephone line will be half
of the differential output (refer to Application Circuit).
26
27
TxA1
RxA
O
I
Transmit Buffer Output 1 (Non–Inverting) — This pin is the non–inverting output of the line driver.
Refer to TxA2.
Receive Signal Input — This pin is the analog signal input which has 500 kΩ input resistance (typ).
ABSOLUTE MAXIMUM RATINGS
Rating
This device contains circuitry to protect the
Symbol
Value
Unit
V
inputs against damage due to high static
voltages or electric fields. However, it is advised
that normal precautions be taken to avoid ap-
plications of any voltage higher than maximum
ratedvoltages to this high impedance circuit. For
DC Supply Voltage
DC Input Voltage
V
CC
– 0.5 to + 7.0
V
in
– 0.5 to V
+ 0.5
V
CC
DC Output Voltage
DC Input Current
V
out
– 0.5 to V
+ 0.5
V
CC
properoperation, itisrecommendedthatV and
in
I
in
± 20
mA
mA
mW
°C
V
V
be constrained to the range GND (V or
in
out
Reliability of operation is enhanced if unused
out
)
V
.
CC
DC Output Current
Power Dissipation
I
± 25
out
P
D
500
logic inputs are tied to an appropriate logic volt-
age level (e.g., either GND or V ).
CC
Storage Temperature Range
T
stg
– 65 to + 150
RECOMMENDED OPERATIONAL CONDITIONS
Parameter
Symbol
Min
3.3
0
Typ
5.0
Max
Unit
V
DC Supply Voltage
V
CC
5.5
DC Input Voltage
V
in
—
V
V
V
CC
DC Output Voltage
V
out
0
—
V
CC
Crystal Oscillation Frequency
External Input Frequency (ECLK)
Operating Temperature Range
f
—
3.579545
7.15909
25
—
—
MHz
osc
—
T
A
– 30
+ 85
°C
DC ELECTRICAL CHARACTERISTICS (V
CC
= + 3.3 to + 5.5 V, T = – 30 to + 85°C)
A
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
Input Voltage
High Level
Low Level
V
0.7 x V
—
—
V
IH
CC
(TxD, ECLK, RESET,
SCP Rx, SCPCLK,
SCPEN)
V
—
—
1.1
—
IL
Output Voltage
(RxD, CD, CLKO,
PB0–3, SCP Tx)
High Level
Low Level
V
OH
V
V
= V or V , I
IH IL out
= 20 µA
V
CC
– 0.1
V
– 0.01
in
CC
V
OL
= V or V
in
IH
IL
I
I
= 20 µA
—
—
0.01
—
0.1
0.4
out
out
= 2 mA
Input Leakage Current
(TxD, ECLK, RESET, SCP Rx,
SCPCLK, SCPEN)
I
in
V
in
= V or GND
CC
—
± 1.0
± 10.0
µA
Quiescent Supply
Current
V
= 5 V
I
I
I
FSK Mode, RTLA = 0
TxA1 and TxA2 open
—
7
—
mA
CC
CC
DTMF Receive Mode, no input
—
—
9
6
—
—
V
CC
= 3.6 V
FSK Mode, RTLA = 0
TxA1 and TxA2 open
CC
CC
DTMF Receive Mode, no input
Power–Down Mode 1
—
—
—
8
—
500
1.0
Power–Down Supply Current
—
—
µA
µA
Power–Down Mode 2
MC145745
4
MOTOROLA
AC ELECTRICAL CHARACTERISTICS
(V
= + 3.6 V ± 0.3 V, T = – 30 to + 85 C)
CC
A
TRANSMIT CARRIER CHARACTERISTICS
Characteristic
V.21 Carrier Frequency
Symbol
Conditions
Min
974
Typ
Max
986
Unit
Mark “1”
Space “0”
Mark “1”
Space “0”
Mark “1”
Space “0”
f
f
f
Oscillation Frequency:
3.579545 MHz (X2)
or 7.159090 MHz (ECLK)
980
Hz
1M
Originate Mode
f
1174
1644
1844
1294
2094
—
1180
1186
1656
1856
1306
2106
—
1S
V.21 Carrier Frequency
Answer Mode
1650
2M
f
1850
2S
V.23 Carrier Frequency
1300
1M
f
2100
1S
Transmit Carrier Level
Secondary Harmonic Level
Out–of–Band Level
V
O
Transmit Attenuator = 0 dB
4
dBm
dB
RTLA = 0, R = 1.2 kΩ
L
V
2h
—
– 40
—
V
TxA1
– V
TxA2
V
OE
Refer to Figure 1
dBm
TRANSMIT ATTENUATOR CHARACTERISTICS
Characteristic
Attenuation Range
Attenuator Accuracy
Symbol
Conditions
Min
Typ
Max
Unit
dB
0
—
15
1 – 5 dB
6 – 9 dB
10 – 15 dB
– 0.5
– 1
– 1.7
—
—
—
0.5
1
1
dB
RECEIVER CHARACTERISTICS (Includes Hybrid, Demodulator, and Carrier Detector)
Characteristic
Input Resistance
Symbol
Conditions
Min
50
– 48
—
Typ
500
—
Max
—
Unit
kΩ
R
V
IRX
Receive Carrier Amplitude
– 12
—
dBm
dBm
IRX
Carrier Detection
Threshold
OFF to ON
ON to OFF
V
CDA = 1.25 V
= 1.0 kHz
BR3 (b1) = 1
– 44
– 47
—
CDON
f
in
V
—
—
CDOFF
Hysteresis (V
– V
)
H
YS
2
—
dB
ms
CDON
CDOFF
Carrier Detection Timing OFF to ON
T
CD1 = 0, CD0 = 0, CD Pin
CD1 = 0, CD0 = 1, CD Pin
CD1 = 1, CD0 = 0, CD Pin
CD1 = 1, CD0 = 1, CD Pin
CD1 = 0, CD0 = 0, CD Pin
CD1 = 0, CD0 = 1, CD Pin
CD1 = 1, CD0 = 0, CD Pin
CD1 = 1, CD0 = 1, CD Pin
—
450
15
—
CDON
—
—
—
15
—
—
75
—
ON to OFF
T
—
30
—
CDOFF
—
30
—
—
15
—
—
10
—
CPTD CHARACTERISTICS
Characteristic
Symbol
Conditions
Min
—
Typ
400
330
Max
—
Unit
Hz
BPF Center Frequency
f
c
BPF Pass–Band Lower Cut–Off
Frequency
f
i
– 3 dB
—
—
Hz
BPF Pass–Band Upper Cut–Off
Frequency
f
h
– 3 dB
—
470
—
Hz
CPT Detection Level
VTD ON
VTD OFF
TTD ON
TTD OFF
V
CDA = 1.25 V
—
—
—
—
– 44
– 47
10
—
—
—
—
dBm
TDON
f
= 400 Hz
in
BR3 (b1) = 1
V
TDOFF
CPT Detection Timing
T
ms
TDON
T
25
TDOFF
MOTOROLA
MC145745
5
DTMF TRANSMIT CHARACTERISTICS
Characteristic
Tone Output Level
Symbol
Conditions
Min
—
Typ
Max
—
—
3
Unit
dBm
dBm
dB
Low Group
High Group
V
fl
Transmit Attenuator = 0 dB
RTLA = 0 Ω
= 3.579545 MHz
osc
Single Tone Mode
0
V
fh
—
1
f
High Group Pre–Emphasis
DTMF Distortion
P
E
0
—
R
V
= 1.2 kΩ
L
DIST
∆f
—
5
—
1
%
– V
TxA2
TxA1
DTMF Frequency Deviation
Out–of–Band Level
Setup Time
– 1
—
%
V
V
Refer to Figure 1
4
dB
OE
osc
t
—
—
ms
DTMF RECEIVER CHARACTERISTICS
Characteristic
Input Resistance
Symbol
Conditions
Min
50
Typ
500
—
Max
—
Unit
kΩ
Detection Signal Level (Each Tone)
Twist (High/Low Group)
BR3 = (0, 0, 1, 0)
– 48
– 10
0
dBm
dB
—
10
Frequency Detection Band Width
(Figure 3)
1.5% + 2 Hz
– 1.5% – 2Hz
—
—
—
—
Frequency Non–Detection Band Width
(Figure 3)
—
—
± 3.5%
DTMF Detection Timing
(Figure 2)
OFF to ON TDV
Delay
CD1 = 0 , CD0 = 0
CD1 = 0 , CD0 = 1
CD1 = 1 , CD0 = 0
CD1 = 0 , CD0 = 0
CD1 = 0 , CD0 = 1
CD1 = 1 , CD0 = 0
—
—
—
—
—
—
30
35
45
25
35
25
—
—
—
—
—
—
ms
ON
ON to OFF TDV
Delay
OFF
DEMODULATOR CHARACTERISTICS
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
V.21 Bit Bias
Receive Level = – 24 dBm
S/N = 4 dB
—
5
—
%
V.23 Bit Bias
Receive Level = – 24 dBm
S/N = 14 dB
—
—
10
—
—
%
V.21 Bit Error Rate
V.23 Bit Error Rate
Receive Level = – 24 dBm
S/N = 4 dB
511–Bit Pattern
0.00001
Receive Level = – 24 dBm
S/N = 14 dB
—
0.00001
—
511–Bit Pattern
MC145745
6
MOTOROLA
0
3.4 k 4 k
16 k
256 k
f (Hz)
0
– 25
– 15 dB/OCT.
– 55
Figure 1. Out–of–Band Level
V
on
V
off
RxA
t
t
off
on
CD
Figure 2. FSK, DTMF, and CPT Carrier Detection Timing
DETECT MINIMUM
WIDTH
NO–DETECT
NO–DETECT
– 3.5%
+ 3.5%
– 1.5% – 2 Hz
f
+ 1.5% + 2 Hz
o
Figure 3. DTMF Frequency Detection Bandwidth
MOTOROLA
MC145745
7
SCP TIMING CHARACTERISTICS
Ref.
No.
Characteristic
SCPEN Active Before Rising Edge of SCPCLK
SCPCLK Rising Edge Before SCPEN Active
Min
50
50
35
20
250
50
50
0
Max
—
—
—
—
—
—
—
50
30
—
—
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
SCP Rx Setup Time Before SCPCLK Rising Edge
SCP Rx Hold Time After SCPCLK Rising Edge
SCPCLK Period
4
5
6
SCPCLK Pulse Width (Low)
7
SCPCLK Pulse Width (High)
8
SCP Tx Active Delay Time
9
SCPCLK Falling Edge to SCP Tx High Impedance
SCPEN Inactive Before SCPCLK Rising Edge
SCPCLK Rising Edge Before SCPEN Inactive
SCPCLK Falling Edge to SCP Tx Valid Data
—
10
11
12
50
50
0
10
SCPEN
11
2
1
5
1
2
3
4
5
6
7
8
9
SCPCLK
SCP Rx
SCP Tx
7
4
6
3
D0
R/W
A2
A1
A0
D3
D2
D1
12
8
9
D0
D3
D2
D1
Figure 4. Serial Control Port Timing
MC145745
8
MOTOROLA
DEVICE DESCRIPTION
SERIAL CONTROL PORT (SCP INTERFACE)
The MC145745 is a selectable modem chip compatible
with V.21 (300 baud full duplex asynchronous) and V.23
mode 2 (1200 baud half duplex asynchronous). This device
includes a DTMF generator, DTMF receiver, call–progress
tone detector, answer tone generator, and a receive timing
control circuit. The built–in differential line driver has the
capability of driving 0 dBm into a 600 Ω load with a 5.0 V
single power supply. The MC145745 also includes a serial
control port (SCP) that permits an MCU to exercise the built–
in features.
The MC145745 is equipped with an SCP. The SCP is a
full–duplex four–wire interface with control and status in-
formation passed to and from the internal register. The SCP
is compatible with the Serial Peripheral Interface (SPI) of
single chip MCUs used in other standard Motorola devices.
The SCP consists of SCP Tx, SCP Rx, SCPCLK, and
SCPEN for transmitting control data, status data, and DTMF
receive data between the MCU and the MC145745. The
SCPCLK determines the transmission and reception data
rates, and the SCPEN governs when the data transaction is
to take place.
The operation/configuration of the MC145745 is pro-
grammed by setting the state of the internal register bit. The
control, status, and data information resides in 4–bit wide
registers which are accessed via the 8–bit SCP bus transac-
tion.
The MC145745 provides an SCP interface to access an in-
ternal byte register which controls the device operations;
such as function mode, carrier detect timing, transmit/receive
gain, and transmit tones.
The transmit and receive amplifiers’ gain is programmable
by SCP register setting (BR4). The TLA pin is also available
to adjust the transmit level that is determined by the resistor
(RTLA) value connected between the pin and GND. The
DTMF receiver amplifier includes a built–in AGC amplifier
which automatically adjusts the input amplifier gain corre-
sponding to the amplitude of the DTMF tone input signal. The
AGC dynamic range can be selected in four options. The
highest received sensitivity obtained is approximately
– 50 dBm when the dynamic range of the AGC amplifier is
maximized.
The first four bits of the 8–bit bus transaction are the read/
write direction and the register address. The next four bits
are the data written to or read from the internal registers.
The SCP interface is independent of the 3.58 MHz master
clock. It runs by using SCPCLK as the synchronizing signal.
SCP TRANSACTION
The SCP interface includes both read and write capabili-
ties, which together comprise the SCP transaction. These
SCP transaction functionalities are described below.
The tone generator, which can generate 16 DTMF tones,
is used at the terminal for transmission of the call and control
tones. In addition, a single tone can be generated for tests
and other uses.
Power down is amenable to software control by setting the
byte register BR2. While the device is in the power down
state, SCP still operates independently. There are two power
down options available: power down 1 (the system clock
operates alone) and power down 2 (the system clock stops).
The clock generator constitutes an oscillation circuit with a
3.58 MHz crystal connected between the X1 and X2 pins.
This device also has a 7.15909 MHz external clock input
(ECLK), which has a clock divider circuit for providing a
3.58 MHz clock to the internal circuits. If the ECLK pin is
used, the X2 pin should be held low. If the oscillation circuit
(X1 and X2) is used, the ECLK pin should be held low. This
device also has a clock buffer output (CLKO), which can be
used for providing a 3.58 MHz clock to the external device.
Table 1 shows the clock input and output relations in the dif-
ferent modes.
SCP Read
The SCP read action transaction is shown in Figure 5. Dur-
ing the SCP read action, the SCPEN pin must be in the low
position. After SCPEN high goes low, then at the first four
SCPCLK rising edges, Read/Write (R/W) bit and three ad-
dress bits (A0 – A2) are shifted into the intermediate buffer
register. If the read action is to be performed, the R/W bit
must be at 1. And then, at the following four SCPCLK falling
edges, the 4–bit chosen register data is shifted out on
SCP Tx. SCPEN must be restored to high after this trans-
action, before another falling edge of SCPCLK is en-
countered. While SCP Tx is in output mode, SCP Rx is
disregarded. Also, whenever SCP Tx is not transmitting data,
a high impedance condition is maintained.
Table 1. Clock Selection Truth Table
SCP Write
Input
Output
The SCP write action transaction is shown in Figure 6.
During the SCP write action, the SCPEN pin must be in the
low position. After SCPEN high goes low, then at the first four
SCPCLK rising edges, R/W and three address bits (A0 – A2)
are shifted into the intermediate buffer register. If the write
action is to be performed, the R/W bit must be at 0. And then,
at the following four SCPCLK rising edges, the 4–bit data is
shifted in from SCP Rx and written into the chosen register.
During the write operation, SCP Tx is in high impedance. If
the chosen register and/or the chosen bit are “read only,” the
write action to it has no effect.
ECLK
(Pin 12)
X2
(Pin 11)
CLKO
(Pin 9)
Function Mode
Power Down 1
Power Down 2
Other Mode
0
fext
0
fxtal
0
fxtal
fext/2
0
X
fext
0
0
0
fxtal
0
fxtal
fext/2
fext
MOTOROLA
MC145745
9
SCPEN
SCPCLK
DON’T CARE
DON’T CARE
SCP Rx
SCP Tx
R/W
A2
A1
A0
D3
D2
D1
D0
HIGH IMPEDANCE
Figure 5. Serial Control Port Read Operation
SCPEN
SCPCLK
DON’T CARE
DON’T CARE
SCP Rx
SCP Tx
R/W
A2
A1
A0
D3
D2
D1
D0
HIGH IMPEDANCE
Figure 6. Serial Control Port Write Operation
DESCRIPTION OF THE SCP TERMINAL
bits address one of seven byte–registers. The address bits
are shifted in MSB first. If the write action is chosen, the 4–bit
data is shifted in from SCP Rx at the next four SCPCLK rising
edges. If the read action is chosen, 4–bit data in the selected
register is shifted out on SCP Tx. SCP Rx is ignored while
SCPEN is high.
The SCP bus is made up of the following four pins.
SCP Tx (Pin 20)
The SCP Tx pin outputs the control, status, and data in-
formation from the 4–bit wide register. During the read action
transaction, a R/W bit and the three address bits are shifted
in from SCP Rx at four SCPCLK rising edges, subsequent to
SCPEN going low. After this, if a read operation is selected,
SCP Tx comes out of the high impedance state at the first
falling edge of SCPCLK, and outputs the first bit (MSB) of the
chosen register. The remaining three bits of the chosen reg-
ister are shifted out from SCP Tx at the following three
SCPCLK falling edges. After the last bit (LSB) is shifted out,
SCPEN must return to high. Then SCP Tx returns to the high
impedance condition.
SCPCLK (Pin 22)
The SCPCLK pin is an input of standard clock for hand-
shaking between SCP and MCU. After SCPEN comes low
and the SCP transaction occurs, data is shifted from SCP Rx
into the device at the rising edge of SCPCLK, and is shifted
out on SCP Tx at the falling edge of SCPCLK. When SCPEN
is high, SCPCLK is ignored (i.e., it may be continuous or it
can operate in the burst mode).
SCPEN (Pin 23)
SCP Rx (Pin 21)
When the SCPEN pin is held low, the SCP transaction is
enabled and control, status, and data information is trans-
ferred. If SCPEN is returned to high, the SCP action in prog-
ress is aborted, and the SCP Tx pin enters a high impedance
condition.
The SCP Rx pin is used to input control and data informa-
tion into the 4–bit wide register. Data is shifted in from
SCP Rx at SCPCLK rising edge, while SCPEN is low. The
first bit is the R/W bit (1 = read, 0 = write), and the next three
MC145745
10
MOTOROLA
SCP REGISTER MAP
BR0 V.23 Receive, Transmit Enable
BR1 DTMF CDON = 30 ms, DTMF CDOFF = 25 ms
FSK CDON = 450 ms, FSK CDOFF = 30 ms
The MC145745 register map is shown in Table 2. Seven of
the 4–bit wide byte registers (BR) are provided in the register
block. According to these published specifications, BR signi-
fies each register and the address of SCP data. R/W is the
read/write register, and RO is read only. If there is a high to
low pulse on the RESET pin or the power supply turns off,
this register returns to the default state.
BR2 FSK Mode
BR3 AGC Range = Maximum,
Carrier Detect Level: High
BR4 Transmission Gain = Maximum
BR5 DTMF Transmission: 941 Hz + 1633 Hz
BR6 DTMF Reception: Unknown
The default condition that occurs after a power reset is as
follows.
Table 2. SCP Register Map
Register
b3 (Bit 3: MSB)
Modem Choice
b2 (Bit 2)
FSK Channel
b1 (Bit1)
b0 (Bit 0: LSB)
BR0 (R/W)
BR1 (R/W)
Transmission Enable
Enable
0
1
V.23
V.21: Answer
V.23: Receive
V.21
V.21: Originate
V.23: Transmit
Disable
FSK CDT2
FSK CDT1
DTMF CDT2
DTMF CDT1
T
T
T
T
CDOFF
CDON
CDOFF
CDON
b3=0, b2=0 : 450 ms
b3=0, b2=1 : 15 ms
b3=1, b2=0 : 15 ms
b3=1, b2=1 : 75 ms
b3=0, b2=0 : 30 ms
b3=0, b2=1 : 30 ms
b3=1, b2=0 : 15 ms
b3=1, b2=1 : 10 ms
b1=0, b0=0 : 30 ms
b1=0, b0=1 : 35 ms
b1=1, b0=0 : 45 ms
b1=0, b0=0 : 25 ms
b1=0, b0=1 : 35 ms
b1=1, b0=0 : 25 ms
BR2 (R/W) (see Table 3)
BR3 (R/W)
Function Mode 4
AGC Range 2
Function Mode 3
AGC Range 1
Function Mode 2
Carrier Detect Level 1
High Level
Function Mode 1
Test
0
1
B3=0, b2=0 : – 5 to + 20 dB
B3=0, b2=1 : – 5 to + 15 dB
Normal
(Set when V
= 5 V)
CC
b3=1, b2=0 : – 5 to + 10 dB
b3=1, b2=1 : – 5 to + 5 dB
Low Level
Test Mode
(Set when V
= 3.6 V)
CC
BR4 (R/W) (see Table 4)
BR5 (R/W) (see Table 5)
BR6 (RO) (see Table 5)
NOTES:
Transmission Gain 4
Tone Transmission 4
DTMF Reception 4
Transmission Gain 3
Tone Transmission 3
DTMF Reception 3
Transmission Gain 2
Tone Transmission 2
DTMF Reception 2
Transmission Gain 1
Tone Transmission 1
DTMF Reception 1
1. BR0 (b0) is a non–working bit.
2. DTMF Loopback data is entered into BR5 and output from the parallel port.
MOTOROLA
MC145745
11
Table 3. Function Mode Setup
Register
FSK Mode
b3
0
b2
0
b1
b0
0
Comments
0
0
1
1
The device works as one of two FSK modes, V.21/V.23.
The FSK modulator is internally connected to the FSK demodulator.
The device works as the 400 Hz tone detector.
FSK Loopback
0
0
1
CPT Detect Mode
0
0
0
Answer Tone
0
0
1
The device works as the 2100 Hz answer tone generator.
Transmission Mode
DTMF Transmission
Mode
0
0
1
1
0
0
0
1
The device works as the DTMF generator. The receiver is disabled.
The device outputs one of the eight tones used for DTMF.
Single Tone
Transmission Mode
Power Down 1
0
0
1
1
1
0
1
1
0
0
1
0
Whole circuits except for the SCP and the oscillator circuit are disabled.
Whole circuits except for the SCP are disabled.
Power Down 2
DTMF Reception Mode
The device works as the DTMF receiver. The received DTMF tone is
demodulated to the 4–bit code, then output from the SCP interface
and/or the parallel port.
DTMF Loopback
1
0
0
1
The DTMF generator is internally connected to the DTMF receiver, then
the DTMF code written in BR5 is loopbacked to the parallel port (PB0 –
PB3).
Table 4. Transmission Attenuator Range
Transmission
Attenuator Range
b3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
b2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
b1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 dB
– 1 dB
– 2 dB
– 3 dB
– 4 dB
– 5 dB
– 6 dB
– 7 dB
– 8 dB
– 9 dB
– 10 dB
– 11 dB
– 12 dB
– 13 dB
– 14 dB
– 15 dB
MC145745
12
MOTOROLA
Table 5. Tone Generator/Receiver Data
Tone Generator
BR5/BR6
Setting or Data Output
Tone Receiver
Key
Input
High Group
Frequency (Hz)
Single Tone
(Hz)
Low Group
Frequency (Hz)
b3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
b2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
b1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D
1
2
3
4
5
6
7
8
9
0
*
941
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
1633
941
697
1209
1336
697
1477
697
1209
770
1336
770
1477
770
1209
852
1336
1336
1477
1336
1209
1477
1633
1633
1633
1477
1336
1209
#
A
B
C
1477
1633
1633
1633
MOTOROLA
MC145745
13
10
Ω
600 : 600
TxA1
TxA2
TIP
TxD
*
RxD
600
Ω
RING
CD
RxA
CDA
TLA
SCPEN
MCU
SCPCLK
SCP Rx
0.1 µF
SCP Tx
4
PB0 – PB3
TEST1
TEST2
RESET
+ 5 V
V
CLKO
ECLK
ref
100
100
µF
0.1 µF
MC145745
V
+ 5 V
X1
X2
CC
3.579545 MHz
µF
0.1 µF
GND
LINE PROTECTION CIRCUIT
SYSTEM GROUND
REFERENCE ANALOG GROUND
*
Figure 7. Application Circuit
MC145745
14
MOTOROLA
PACKAGE DIMENSIONS
FW SUFFIX
SOIC
CASE 751M–01
VIEW AB
A
–Y–
28
15
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. MAXIMUM MOLD PROTRUSION
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.65
(0.026).
B
–Z–
E
MILLIMETERS
INCHES
V X 45
5
DIM
A
B
C
C1
D
MIN
17.80
7.40
–––
MAX
18.03
7.62
MIN
MAX
0.710
0.300
0.104
0.096
0.020
0.414
0.028
1
14
0.701
0.291
–––
28X D
2.65
2.25
0.35
10.00
0.40
2.45
0.51
10.60
0.70
0.090
0.014
0.394
0.016
M
M
S
S
M
S
S
0.25 (0.010)
0.18 (0.007)
T
T
Z
Y
0.18 (0.007)
T
Y
Z
E
F
G
J
1.27 BSC
0.050 BSC
0.10
0.25
0.004
0.010
L
0.635 BSC
0.025 BSC
θ
V
W
X
–––
0.25
0.05
8
0.75
0.20
–––
0.010
0.002
8
0.030
0.008
VIEW AB
C
L
1.40 REF
0.055 REF
0.10 (0.004)
T
J
C
C1
SEATING
PLANE
–T–
W
4X
L
24X
G
W REF
F
θ
Z
MOTOROLA
MC145745
15
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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