MC33689 [MOTOROLA]
System Basis Chip with LIN transceiver; 系统基础芯片LIN收发器
| 型号： | MC33689 |
| 厂家： | 
MOTOROLA |
| 描述： | System Basis Chip with LIN transceiver |
| 文件： | 总18页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Rev: 2.71 Date: 15 Dec 2004
Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR
MC33689
TECHNICAL DATA
Product Preview
LIN System basis chip
System Basis Chip with
LIN transceiver
SILICON MONOLITHIC
INTEGRATED CIRCUIT
The LIN SBC is a monolithic integrated circuit combining many functions
frequently used by automotive LIN distributed slave nodes. It incorporates:
- Single voltage regulator with low power modes
- LIN physical interface.
- Wake up inputs.
- Triple high side driver
- Current sense op amp
Pin out SO32WB fine pitch
• Vdd: Low drop voltage regulator, current limitation, over temperature
detection, monitoring and reset function, current capability 50mA.
• Programmable window watchdog
• Three operational modes (normal, stop and sleep modes)
• Low current consumption in sleep and stop modes
• LIN physical interface compatible with LIN standard.
• Two external high voltage wake-up inputs
• Dual high side switches, relay driver capability, internal clamp, PWM
capability.
• Single low current high side switch, 50mA capability for switch bias and hall
sensor supply
1
2
32
31
30
29
28
27
26
TX
RX
NC
L1
NC
3
INT
CSB
MISO
4
L2
5
HS3
HS2
HS1
T-GND
T-GND
VS2
MOSI
SCLK
6
7
8
25 T-GND
24
9
T-GND
10
11
12
13
14
15
16
23
IN
Reset
22
LIN
GND
VS1
21
Wdc
e+
• Current sense amplifier
• Nominal DC operating voltage from 5.5 to 27V
• 40V maximum transient voltage
20
19 e-
NC
Vdd
Out
18
• Wake up capabilities (wake up inputs, LIN interface)
17 Vcc
aGND
Simplified Block Diagram
Vdd
5V/50mA
Vs1
Vbat
Voltage
Regulator
Reset
Reset
control
Window
Watchdog
Wdc
IN
Vs2
HS1
HS2
HS3
MOSI
MISO
SPI and
SCK
CSB
Mode
pre driver
Control
INT
Vcc
E-
L2
L1
amplifier
E+
Vs1
Out
TX
ORDERING INFORMATION
LIN
Operating
Temperature Range
LIN Physical Interface
Package
Device
RX
MC33689DWB/R2 TA = -40 to 125°C
SO-32
aGnd
Gnd
This document contains information on a product under development. Motorola reserves the right
© Motorola,Inc 2004
For More Information On This Product,
to change or discontinue this product without notice.
Go to: www.freescale.com
Freescale SMeCm33i6c89onductor, Inc.
1
MAXIMUM RATINGS
Ratings
Symbol
Min
Typ
Max
Unit
ELECTRICAL RATINGS
Supply Voltage at Vs1 and Vs2
- Continuous voltage
- Transient voltage (Load dump)
V
Vsupdc
Vsuptr
-0.3
27
40
Supply Voltage Vdd and Vcc
Logic Inputs: MOSI, SCK, CSB, IN, Tx
Logic output: MISO, INT, Rx, Reset
Output current Vdd
Vdd
Vinlog
Voutlog
Idd
-0.3
- 0.3
- 0.3
5.5
V
V
Vdd+0.3
Vdd+0.3
V
Internally limited
A
E+, E- input voltage
Ve+-
Ie+-
-0.3
-20
-0.3
-20
7
20
V
E+, E- input current
mA
V
Out output voltage
Vout
Iout
Vcc+0.3
20
Out output current
mA
L1 and L2
- DC Input voltage with a 33k resistor
- Transient input voltage (according to ISO7637
specification) and with external component (see fig-
ure 1 below).
Vlxdc
Vlxtr
-18V
-100
40
+100
V
V
HS1 and HS2 output
HS3
Vhs12
Vhs3
internally
clamped
Vs2+0.3
Vs2+0.3
V
-0.3
V
V
LIN
- DC voltage
Vbusdc
Vbustr
-18
-150
+40
+100
Transient input voltage (according to ISO7637
specification) and with external component (see fig-
ure 1 below).
ESD voltage (HBM 100pF, 1.5k)
(GND, T-GND and aGND pins connected together
and configured as ground)
- LIN, L1, L2
Vesdh
Vesdh
kV
kV
-4
-2
4
2
- All other pins
ESD voltage (HBM 100pF, 1.5k)
(GND pin configured as ground, T-GND and aGND
pins as I/O)
- LIN, L1, L2
- All other pins
-4
-2
4
2
ESD voltage (Machine Model) All pins
(GND, T-GND and aGND pins connected together
and configured as ground)
Vesdm
Vesdm
-200
200
V
V
ESD voltage (Machine Model) All pins
(GND pin configured as ground, T-GND and aGND
pins as I/O)
-150
150
THERMAL RATINGS
Junction Temperature
T
j
- 40
- 55
- 40
+150
+165
+85
80
°C
°C
Storage Temperature
T
s
Ambient Temperature (for info only)
Thermal resistance junction to ambient
T
a
°C
Rthj/a
°C/W
MC33689
2
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Figure 1. : Transient test pulses for LIN and Wake pins
Transient Pulse
1nF
Generator
(note)
L1 and L2
Gnd
10 k
Gnd
note: Waveform in accordance to ISO7637 part1, test pulses 1, 2, 3a and 3b.
MC33689
3
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2
ELECTRICAL CHARACTERISTICS
(V and V from 5.5V to 18V and T from -40°C to 125°C unless otherwise noted)
s1
s2
amb
Characteristics
Description
Symbol
Unit
Conditions
Min
Typ
Max
Vs1 and Vs2 pins (Device power supply)
Nominal DC Voltage range
5.5
18
40
27
7.5
V
V
Vsup
VsupLD
VsupJS
Input Voltage during Load Dump
Input Voltage during jump start
Load dump situation
V
Jump start situation (note 1)
Supply Current in Normal Mode (note 2)
5
mA
Iout at Vdd =10mA, LIN
recessive state
Isup(norm)
Supply Current in Sleep Mode (note 2)
Supply Current in Stop Mode (note 2)
30
60
40
75
uA
uA
Vdd off, Vsup<=13.5V
Isleep
Istop
Vdd ON with Iout<100uA,
Vsup<=13.5V
Supply voltage fall early warning thresh-
old
VSUVew
5.7
18
6
6.6
V
Normal mode, INT gener-
ated, bit VSUV set
VSUV flag hysteresis
VSUVhyst
VSOVw
1
V
V
guaranteed by design
Supply voltage over voltage warning
threshold
19.25
20.50
Normal mode, INT gener-
ated, bit VSOV set
VSOV flag hysteresis
VSOVhyst
220
mV
guaranteed by design
note 1: Device is fully functional. All functions are operating. Over temperature may occur.
note 2: Total current (IVs1+IVs2) measured at gnd pins.
Vdd (external 5V output for MCU supply). Specification with external capacitor 2uF<C<10uF and 200mOhms<=ESR<=1O ohm.
Normal mode. Capacitor value up to 47uF chemical can be used.
Vdd Output Voltage
Vddout
4.75
5
5.25
V
Idd from 2 to 50mA
5.5V< Vsup <27V
Dropout Voltage (note 1)
Vdddrop
100
200
mV
Idd = 50mA (note 1)
Vsup > 4.5V
Idd output current limitation (note 2)
Idd
50
110
135
200
160
mA
Internally limited
Over temperature pre warning (junction)
Tpre
120
°C
Normal mode, INT gener-
ated, Bit VddT set
guaranteed by design
Thermal Shutdown (junction)
Tsd
155
20
170
30
°C
Normal mode
guaranteed by design
Temperature threshold difference
45
°C
Normal mode (Tsd-Tpre)
guaranteed by design
Vsup range for Reset Active
Line Regulation
Vsupr
LR
3.5
V
0.5<Vdd<Vdd (Rst-th1)
5.5V<Vsup<27V, Idd=10mA
1mA<IIdd<50mA
20
40
150
150
mV
mV
Load Regulation
LD
note 1: measured when voltage has dropped 100mV below its nominal value.
note 2: total Vdd regulator current. A 5mA current for operational amplifier operation is included. Digital output supplied from Vdd.
Vdd: in Stop mode
Vdd Output Voltage (note 1)
Idd current capability (note 2)
Line regulation
Vddstop
Idds
4.75
4
5,00
8
5.25
14
V
Idd<=2mA
Stop mode
mA
mV
mV
LR-s
10
40
100
150
5.5V<Vsup<27V, Idd=2mA
1mA<IIdd<5mA
Load regulation
LD-s
note 1: when switching from Normal mode to Stop mode, or from Stop mode to Normal mode the output voltage can varies within the output
voltage specification.
note 2: when Idd is above Idds device enters reset mode
Reset: normal and stop modes (output pin only)
Reset threshold
Rst-th1
Ioh
4.50
0
4.68
-250
Vdd-0.2
0.9
V
µA
V
High Level Output current
Low Level Output Voltage (I0=1.5mA)
Vout>0.7Vdd
Vol
4.5V<Vsup<27V
MC33689
4
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(V and V from 5.5V to 18V and T from -40°C to 125°C unless otherwise noted)
amb
s1
s2
Characteristics
Description
Symbol
Unit
Conditions
Min
Typ
Max
Internally limited. Vdd<4V,
Vreset = 4.6V
Reset pull down current
Ipdw
1.5
8
mA
ms
Reset Duration after Vdd High
reset-dur
0.65
1
1.35
IN: input
High Level Input Voltage
Low Level Input Voltage
Input Current
Vih
Vil
Iin
0.7Vdd
-0.3
Vdd+0.3
0.3Vdd
10
V
V
-10
µA
0<VIN<Vdd
MISO: SPI output
Low Level Output Voltage
High Level Output Voltage
Tristated MISO Leakage Current
MOSI, SCLK, CSB: SPI input
High Level Input Voltage
Low Level Input Voltage
CSB Pull up current source
MOSI, SCK Input Current
Vol
0
Vdd-0.9
-2
1.0
Vdd
+2
V
V
I out = 1.5mA
I out = -250uA
0V<Vmiso<Vdd
Voh
uA
Vih
Vil
Iih
0.7Vdd
-0.3
Vdd+0.3
0.3Vdd
-20
V
-100
-10
uA
uA
Vi 1V to 3.5V
0<VIN<Vdd
Iin
10
SPI: DIGITAL INTERFACE TIMING
SPI operation frequency
SCLK Clock Period
Freq
tpCLK
0.25
250
125
125
4
MHz
ns
N/A
N/A
N/A
SCLK Clock High Time
SCLK Clock Low Time
twSCLKH
twSCLKL
ns
ns
Falling Edge of CS to Rising
Edge of SCLK
tlead
100
N/A
ns
Falling Edge of SCLK to CS Rising Edge
MOSI to Falling Edge of SCLK
Falling Edge of SCLK to MOSI
MISO Rise Time (CL = 220pF)
MISO Fall Time (CL = 220pF)
tlag
tSISU
tSIH
100
40
N/A
N/A
N/A
50
ns
ns
ns
ns
ns
40
trSO
tfSO
25
25
guaranteed by design
guaranteed by design
50
Time from Falling or Rising Edges of CS to:
- MISO Low Impedance
- MISO High Impedance
tSOEN
tSODIS
0
0
50
50
ns
ns
guaranteed by design
0.2 V1=<MISO>=0.8V1,
CL=100pF
guaranteed by design
Time from Rising Edge of SCLK to MISO
Data Valid
tvalid
50
MC33689
5
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(V and V from 5.5V to 18V and T
from -40°C to 125°C unless otherwise noted)
s1
s2
amb
Characteristics
Description
Symbol
Unit
Conditions
Min
Typ
Max
Figure 2. SPI Timing characteristic
Tpclk
CSB
Twclkh
Tlead
Tlag
SCLK
Twclkl
Tsih
Tsisu
MOSI
Undefined
Di 0
Don’t Care
Di 8
Don’t Care
Tvalid
Tsoen
Tsodis
MISO
Note:
Do 0
Do 8
Incoming data at MOSI pin is sampled by the SBC at SCLK falling edge.
Outcoming data at MISO pin is set by the SBC at SCLK rising edge (after Tvalid delay time)
INT: output pin
Low Level Output Voltage (I0=1.5mA)
High Level Output Voltage (I0=-250uA)
Vol
0
0.9
V
Voh
Vdd-0.9
Vdd
WDC: window watchdog configuration pin
kohms
%
External resistor range
Rext
10
100
15
Watchdog period accuracy with external
resistor
Excluding resistor accuracy.
Note 1
Wdcacc
-15
Watchdog period with external resistor
Watchdog period with external resistor
Wdp 10
10.558
99.748
ms
ms
R = 10 kohms. note 1
R = 100 kohms. note 1
Wdp 100
Watchdog period without external resis-
tor, Conf pin open
PWdoff
97
150
205
ms
Normal mode
note 1: watchdog timing period calculation formula: Twd = 0.991 * R + 0.648 (R in kohms and Twd in ms).
HS1 and HS2: High side output pin
Rdson at Ta=25°C, and Iout -150mA
Rdson at Ta=125°C, and Iout -150mA
Rdson at Ta=125°C, and Iout -120mA
Output current limitation
Ron25
Ron125
Ron3
Ilim
2
2.5
4.5
Ohms
Ohms
Ohms
mA
Vsup>9V
Vsup>9V
3
5.5<Vsup<9V
300
155
430
600
190
10
Over temperature Shutdown
Ovt
°C
note 1
Leakage current
Ileak
Vcl
uA
Output Clamp Voltage at Iout = -100mA
-6
V
MC33689
6
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MC33689
(V and V from 5.5V to 18V and T from -40°C to 125°C unless otherwise noted)
amb
s1
s2
Characteristics
Description
Symbol
Unit
Conditions
Min
Typ
Max
note 1: when over temperature occurs, switch is turned off and latched off. Flag is set in SPI.
HS3: High side output pin
Rdson at Tj=25°C, and Iout -50mA
Rdson at Ta=125°C, and Iout -50mA
Rdson at Ta=125°C, and Iout -30mA
Output current limitation
Ron25
Ron125
Ron3
Ilim
7
Ohms
Ohms
Ohms
mA
Vsup>9V
Vsup>9V
10
14
5.5<Vsup<9V
60
100
200
190
10
Over temperature Shutdown
Leakage current
Ovt
155
°C
note 1
Ileak
uA
note 1: when over temperature occurs, switch is turned off and latched off. Flag is set in SPI
SENSE CURRENT AMPLIFIER SECTION:
Rail to rail input voltage
Output voltage range
Output voltage range
Input bias current
-0.1
0.1
Vcc+0.1
Vcc-0.1
Vcc-0.3
250
V
V
Vimc
Vout1
Output current +- 1mA
Output current +-5 mA
Vout2
0.3
V
nA
Ib
Io
Input offset current
Input offset voltage
Supply voltage rejection ratio
Common mode rejection ratio
Gain bandwidth
-100
-15
60
100
15
nA
mV
dB
Vio
Guaranteed by design
Guaranteed by design
Guaranteed by design
SVR
70
dB
CMR
GBP
1
Mhz
V/us
°
Slew rate
SR
0.5
40
Phase margin
PHMO
For gain=1,load 100pF//
5kohms. Guaranteed by design
Open loop gain
OLG
85
dB
V
Guaranteed by design
L1, L2 inputs
Negative Switching Threshold
Vthn
2
2.5
2.7
2.5
3
3.2
3
3.5
3.7
5.5V<Vsup<6V
6V<Vsup<18V
18V<Vsup<27
Positive Switching Threshold
Vthp
2.7
3
3.5
3.3
4
4.2
3.8
4.5
4.7
V
5.5V<Vsup<6V
6V<Vsup<18V
18V<Vsup<27
Hysteresis
Vhyst
Iin
0.5
-10
8
1.3
10
38
V
5.5V<Vsup<27
-0.2V < Vin < 40V
Guaranteed by design
Input current
uA
us
Wake up Filter Time
Twuf
20
STATE MACHINE TIMING
Delay between CSB low to high transition
(at end of SPI stop command) and Stop
mode activation (Guaranteed by design)
Tstop-m
Tstop-nw
Tstop-M
1.4
6
12
5
30
50
us
us
us
Minimum Watchdog period
No watchdog selected
Maximum watchdog period
Interrupt low level duration
Tint
7
10
13
35
us
%
Internal oscillator frequency accuracy
Normal request mode time out
Osc-f1
NRtout
-35
97
All modes, for info only
Normal request mode
150
205
ms
Delay between SPI command and HS1,
HS2 or HS3 turn on (note 1, 2)
Normal mode
Vsup>9V, Vhs >= 0.2 Vs1
Ts-HSon
Ts-HSoff
Ts-NR2N
20
20
30
us
us
us
Delay between SPI command and HS1,
HS2 or HS3 turn off (note 1, 2)
Normal mode
Vsup>9V, Vhs <= 0.8 Vs1
Delay between Normal Request and Nor-
mal mode, after W/D trigger command
Normal request mode, Guar-
anteed by design
6
35
40
Delay between CSB wake up (CSB low
to high) and SBC normal request mode
(Vdd1 on & reset high)
Tw-csb
15
80
us
SBC in stop mode
MC33689
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MC33689
(V and V from 5.5V to 18V and T from -40°C to 125°C unless otherwise noted)
amb
s1
s2
Characteristics
Description
Symbol
Unit
Conditions
Min
Typ
Max
Delay between CSB wake up (CSB low
to high) and first accepted SPI command
Tw-spi
Ts-1stspi
T2csb
90
N/A
us
us
us
SBC in stop mode
Delay between INT pulse and 1st SPI
command accepted
30
15
N/A
In stop mode after wake up
The minimum time between two rising
edges on the CSB
note 1: when IN input is set to high, delay starts at falling edge of clock cycle #8 of the SPI command and start of device activation/deactivation.
30mA load on HS switches. Excluding rise or fall time due to external load.
note 2: when IN used to control HS switches, delays measured betxween IN and HS1 or HS2 on /off. 30mA load on HS switches. Excluding
rise or fall time due to external load.
Rx: LIN physical layer output
Low Level Voltage Output
High Level Voltage Output
Tx: LIN physical layer input
Low Level Voltage Input
High Level Voltage Input
Input Threshold Hysteresis
Pull-up Current Source
Vol
0
0.9
V
V
I in ≤ +1.5mA
I out ≤ 250uA
Voh
3.75
5.25
Vil
Vih
1.5
V
V
3.5
50
Vinhyst
Is
550
800
-20
mV
uA
-100
1V <V(Tx) < 3.5V
LIN: physical layer bus (Voltage Expressed versus Vsup Voltage)
Low Level Dominant Voltage
High Level Voltage (Tx high, Iout = 1uA)
Pull up Resistor to Vsup
Vlin-low
Vlin-high
Rpu
1.4
47
V
V
external bus pull 500 Ohms
Recessive state
Vsup-1
20
kohms
30
In normal mode. In sleep and
stop mode if not turned off by
SPI
uA
Pull up current source
Ipu
1.3
In sleep and stop mode with
30k disconnected
Over current shutdown threshold
Over current shutdown delay
Leakage Current to GND
Iov-cur
50
75
10
3
150
mA
us
Iov-delay
Guaranteed by design
Ibus-pas-
rec
0
20
1
uA
Recessive state, Vsup 8V to
18V, Vlin 8V to 18V
Gnd disconnected, Vgnd = Vsup, VLin at
-18V
Ibus no
gnd
-1
mA
uA
Leakage Current to GND, Vsup Discon-
nected, VLin at +18V
Ibus
1
10
Vsup disconnected
Vlin at +18V
Lin Receiver Vil (Tx high, Rx low)
Lin Receiver Vih (Tx high, Rx high)
LIN Receiver Threshold center
LIN Receiver Input Hysteresis
LIN wake up threshold
Lin-vil
Lin-vih
0
0.4VSUP
VSUP
0.6 VSUP
0.475
Lin-thres
LIN hyst
LIN wu
0.5
0.5
0.525
Vsup
Vsup
Vsup
(Lin-vih - Lin-vil) / 2
Lin-vih - Lin-vil
0.175
LIN physical layer: bus driver timing characteristics for normal slew rate (note 1)
Dominant propagation delay Tx to LIN
Dominant propagation delay Tx to LIN
Recessive propagation delay Tx to LIN
Recessive propagation delay Tx to LIN
tdom min
tdom max
trec min
trec max
dt1
50
50
50
50
-
us
us
us
us
us
Measurement threshold
58.1% Vsup
Measurement threshold
28.4% Vsup
Measurement threshold
42.2% Vsup
Measurement threshold
74.4% Vsup
Prop delay symmetry: tdom min - trec
max
-10.44
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Prop delay symmetry: tdom max - trec
min
dt2
-
11
us
note 1: Vsup from 7V to 18V, bus load R0 and C0 1nF/1k, 6.8nF/660, 10nF/500. Measurement thresholds: 50% of Tx signal to LIN signal
threshold defined in the column “condition”
LIN physical layer: bus driver timing characteristics for slow slew rate (note 1)
Dominant propagation delay Tx to LIN
Dominant propagation delay Tx to LIN
Recessive propagation delay Tx to LIN
Recessive propagation delay Tx to LIN
tdom min
tdom max
trec min
trec max
dt1s
100
100
100
100
-
us
us
us
us
us
us
Measurement threshold
61.6% Vsup
Measurement threshold
25.1% Vsup
Measurement threshold
38.9% Vsup
Measurement threshold
77.8% Vsup
Prop delay symmetry: tdom min - trec
max
-22
-
Prop delay symmetry: tdom max - trec
min
dt2s
23
note 1: Vsup from 7V to 18V, bus load R0 and C0 1nF/1k, 6.8nF/660, 10nF/500. Measurement thresholds: 50% of Tx signal to LIN signal
threshold defined in the column “condition”
LIN physical layer: bus driver fast slew rate
LIN high slew rate (programming mode)
Dv/Dt fast
13
V/us
Fast slew rate
LIN physical layer: receiver characteristics and wake up timings
Receiver dominant propagation delay
Receiver recessive propagation delay
Receiver prop delay symmetry
Bus wake up deglitcher
TrL
TrH
3.5
3.5
6
6
us
us
us
us
us
LIN low to Rx low. Note 2
LIN high to Rx high. note 2
TrL - TrH
Tr-sym
TpropWL
Twake
-2
2
30
70
20
90
Sleep and stop mode
Note 3
Bus wake up event reported
note 2: Measured between LIN signal threshold “Lin-vil” or “Lin-vih” and 50% of Rx signal.
note 3: Twake is typically 2 internal clock cycles after LIN rising edge detected. Ref to “LIN bus wake up behavior” figure. In sleep mode the
Vdd rise time is strongly dependant upon the decoupling capacitor at Vdd pin.
Figure 3. Test circuit for timing measurements
Vsup
R0 and C0: 1k/1nF, 660ohms/6.8nF and 500ohms/10nF
Vsup
Gnd
Tx
Rx
R0
C0
LIN
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Figure 4. timing measurements for normal slew rate
Tx
recessive state
Trec max
Vrec
LIN
74.4% Vsup
58.1% Vsup
Tdom min
60% Vsup
42.2% Vsup
40% Vsup
28.4% Vsup
Tdom max
Trec min
Rx
TrL
TrH
Figure 5. timing measurements for slow slew rate
Tx
recessive state
Trec max
Vrec
LIN
77.8% Vsup
61.6% Vsup
40% Vsup
Tdom min
60% Vsup
38.9% Vsup
25.1% Vsup
Tdom max
Trec min
Rx
TrL
TrH
Figure 6. LIN bus wake up behavior
SBC in stop mode
SBC in sleep mode
recessive level
Vsup
recessive level
Vsup
LIN
LIN
0.4Vsup
0.4Vsup
dominant level
dominant level
INT
Vdd
TpropWL
TpropWL
Twake
Twake
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STATE MACHINE
Vddlow (150ms) expired and VSUV = 0
Vdd high & Reset counter (1ms) expired & W/D not selected
Vdd high & Reset counter (1ms)
expired & W/D selected
Normal
Request
Reset
Vdd low OR (NR time
out occurs (150ms) &
W/D selected)
Vdd low OR (W/D fail &
W/D selected)
Power
Down
Normal
Vdd low
Stop
Wake up
Sleep
W/D selected means: external resistor between Wdc pin and gnd or Wdc pin open.
W/D not selected means Wdc pin connected to gnd.
W/D fail means: W/D trigger occurs in closed window or no SPI W/D trigger command.
Stop command means: SPI stop command.
Sleep command means: SPI sleep request followed by SPI sleep command.
Wake up means: L1 or L2 state change or LIN bus wake up or CSB rising edge.
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PIN DESCRIPTION
pin name
Pin number
function
Power supply pin. Supply for the voltage regulator and the internal logic.
Power supply pin. Supply for the high side switches.
Electrical ground pin pins for the device.
Analog ground pin for voltage regulator and sense amplifier.
Thermal ground pins for the device
Vs1
Vs2
13
10
GND
aGND
T-GND
Vdd
12
16
8,9,24,25
15
5V regulator output.
Reset
22
Reset output
Configuration pin for the watchdog. A resistor is connected to this pin.The resistor
value defines the watchdog period. If the pin is open, the W/D period is fixed (default
value). If this pin is tied to gnd the watchdog is disabled.
Wdc
21
Tx
Rx
32
31
11
Transmitter input of the LIN interface
Receiver output of the LIN interface
LIN bus line
LIN
HS1, HS2,
HS3
7,6,5
High side driver output 1, output 2 and output 3
L1, L2
Vcc
2,4
17
19
20
18
27
28
26
29
30
23
Wake input 1, wake up input 2
5V supply input of operational amplifier
Inverted input of the sense amplifier
Non inverted input of the sense amplifier
Output of the sense amplifier
E-
E+
Out
MOSI
MISO
SCLK
CSB
INT
SPI: Master Out Slave In pin
SPI: Master In Slave Out
SPI: Clock input pin
SPI: Device chip select pin
Interrupt output pin AND wake up event signalling in stop mode.
Direct input for PWM control of High Side switches 1 and 2
IN
Table 4-1.
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5
GENERAL DESCRIPTION
The LIN SBC is an integrated circuit dedicated to automotive applications. It includes the following functions:
- One full protected voltage regulator with 50mA total output current capability available at Vdd external pin, with under voltage
reset function.
- Programmable window watchdog function, INT output
- Wake up from Lx wake input and LIN bus
- LIN physical interface
- Two 150mA high side protected switches PWM capable for relay or lamp drive
- One 50mA high side protected switch for hall sensor or
- Current sense op amp
5.1
Device Supply
The device is supplied from the battery line through the Vs1 and VS2 pins. An external diode is required to protect against
negative transients and reverse battery. It can operate from 4.5V and under the jump start condition at 27V DC. Device
functionality is guaranteed down to 4.5V at VS1 and VS2 pins. This pin sustains standard automotive voltage conditions such as
load dump at 40V.
5.2
Over and under voltage warning.
If the voltage at VS1 exceed 20V typical or falls below 6V typical, the device generates an INT. VSOV or VSUV bits are set in
the SPI register. Information is latched until the bit is read AND the fault has disappeared. The interrupt is not maskable.
5.3
LIN physical interface:
The device contains an integrated LIN physical interface.
5.4
L1 and L2 inputs:
These pins are used to sense external switches and to wake up the device from sleep or stop mode. During normal mode the
state of these pins can be read through SPI.
5.5
HS1 and HS2:
These are two high side switches to drive load such as relays or lamps. They are protected against over current and over
temperature and include internal clamp circuitry for inductive load drive. Control is done through SPI. PWM capability is offered
through the IN input.
If PWM control is required, the internal circuitry which drive the internal high side switch is an AND function between the SPI
bit HS1 (or HS2) and the IN input. In order to have HS1 on, bit HS1 must be set and IN input must be tied to a micro controller
PWM ouptut to generate the PWM control signal (HS1 on when IN is high, HS1 off when IN is low). Same for HS2 output.
If not PWM control is required, IN input must be connected to Vdd or to a high logic level, then the control of HS1 and HS2 is
done through SPI only.
If over temperature occurs on any of the 3 switches, the faulty switch is turned off and latched off until HS1 (or HS2 or HS3) bit
is set to 1 in the SPI register. The failure is reported through SPI by HSst bit.
5.6
5.7
5.8
HS3:
This high side switch can be used to drive small lamps, hall sensor or switch pull up resistors. Control is done through SPI
Sense amplifier:
E+, E- and OUT are the 3 terminations of the current sense amplifier. The amplifier is enable in normal mode only.
Mode of operation
Mode are controlled by the mode1 and mode 2 bits in the SPI register. 3 modes are available: sleep, stop and normal.
The operation modes and the associated functions are described in the table below.
HS1
HS2
HS3
Opera-
tional
amplifier
Device
Mode
Voltage
Regulator
Wake up
capabilities
Watchdog
function
LIN
interface
Reset output
Low for typ 1ms, then
high (if Vdd above
threshold)
Recessive
only
Not
active
Reset
Vdd: ON
Vdd: ON
N/A
N/A
Disable
OFF
- High.
- Active low if Vdd
under voltage occurs
and if Normal Request
timeout (if W/D enable)
150ms time
out if W/D
enabled.
Transmit
and
Receive
Normal
Request
ONor
OFF
Not
active
Table 5-1.
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HS1
HS2
HS3
Opera-
tional
amplifier
Device
Mode
Voltage
Regulator
Wake up
capabilities
Watchdog
function
LIN
interface
Reset output
- High.
- Active low if Vdd
under voltage occurs
or if W/D fail (if W/D
enable)
Transmit
and
Receive
Window WD if
enabled.
ONor
OFF
Normal
Stop
Vdd: ON
N/A
Active
LIN and
state
change on
Lx inputs
Recessive
state with
Wake
Vdd ON,
limited current
capability
- Normally high.
- Active low if Vdd
under voltage occurs
Not
active
Disable
Disable
OFF
OFF
capability
Vdd OFF, (Set
to 5V after
wake up to
enter Normal
request)
Recessive
state with
Wake
LIN and
state
change on
Lx inputs
- Low
- Go to high after wake
up and Vdd within
spec
Not
active
Sleep
capability
Table 5-1.
Sleep and stop mode enter:
To safely enter sleep or stop mode and to ensure that these modes are not entered by noise issue during SPI transmission, a
dedicated sequence combining bit controlling the LIN bus and the device mode must be send twice.
Enter sleep mode: first and second SPI commands (with bit D6=1, D7=1, D5 =0 or 1, D1=0 and D0=0) 11x0_0000 must be
sent.
Enter stop mode: first and second SPI commands (with bit D6=1, D7=1, D5 =0 or 1, D1=0 and D0=1) 11x0_0001 must be
sent.
Sleep or stop mode is entered after the second SPI command. D5 bit must be set accordingly.
5.9
Window watchdog.
The window watchdog is configurable using external resistor at Wdc pin. The W/D is cleared through mode1 and mode 2 bit is
SPI register. If Wdc pin is left open a fixed watchdog period is selected (typ 150ms). If no watchdog function is required or to
disable the watchdog, the Wdc pin must be connected to gnd. The watchdog period is calculated by the following formula:
Twd = 0.991 * R +0.648 (with R in kohms and Twd in ms).
window closed
no watchdog clear allowed
window open
for watchdog clear
Twd * 50%
Twd * 50%
Watchdog period
Twd
Window watchdog operation
Watchdog clear:
The watchdog is cleared by SPI write command with following mode1 and mode2 bits.
Mode 2
Mode 1
Mode
Sleep mode (note 1)
Stop mode
0
0
1
1
0
1
0
1
Normal mode + W/D clear (note 2)
Normal mode
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Note 1: Special SPI command and sequence is implemented in order to avoid to go into sleep or stop mode with a single 8 bit
SPI command.
Note 2: When a zero is written to “Mode1” bit while “Mode2” bit is written as a one, after the SPI command is completed
“Mode1” bit is set to one and SBC stays in normal mode. In order to set the SBC in sleep mode, both “Mode1” and “Mode2” bits
must be written in the same 8 bits SPI command.
The W/D clear on normal request mode (150ms) has no window.
5.10
INT pin:
This pin is used to report fault to the MCU. Int pulse is generated in case of:
- Vdd regulator temperature pre warning
- high side switch 1, 2 or 3 thermal shutdown
- Vsup over voltage (20V typ)
- Vsup under voltage (6V typ).
If an INT is generated, when the next SPI read operation is performed bit D7 is set to 1. This mean that the bits (D6 to D0)
report the interrupt source.
In case of wake up from stop mode, INT is set low in order to signal to the MCU wake up event from L1, L2 or LIN bus.
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6
SPI INTERFACE AND REGISTER DESCRIPTION
6.1
Data format description
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Bit0
D0
MISO
MOSI
D7
D6
D5 D4
D3
D2
D1
The SPI is an 8 bits SPI. All bits are data bytes. The MSB is send first. The minimum time between two rising edges on the
CSB pin is 15us.
During an SPI communication the state of MISO reports the state of the SBC, at time of CSB high to low transitions. The status
flag are latched at CSB high to low transitions.
Following tables describe the SPI register bit meaning, “reset value” and “bit reset condition”.
D7
D6
D5
D4
D3
D2
D1
D0
W
R
LINSL2
LINSL1
LIN-PU
HS3
HS2
HS1
Mode2
Mode1
LINWU
or
LINFAIL
VSUV
BATFAIL
(note1)
INT
source
VSOV
VddT
HSst
L2
-
L1
-
Write Reset
value
0
0
0
0
0
0
Write Reset
condition
POR,
RESET
POR,
RESET
POR,
RESET
POR,
RESET RESET
POR,
POR
Note 1: The first SPI read, after reset, returns the BATFAIL flag state on bit D4.
D7 signals INT source. After INT occur, D7 read as a “1” means other bits report the INT source. D7 read as a “0” mean no INT
occurred and other bit report real time status.
6.2
Write control bits:
Mode control bits:
6.2.1
Mode 2
Mode 1
Description
0
0
1
1
0
1
0
1
Sleep mode
Stop mode
Normal mode + W/D clear
Normal mode
6.2.2
High side switches control bits:
HS1
Description
HS2
Description
HS3
Description
0
1
HS1 off
0
1
HS2 off
0
1
HS3 off
HS3 on
HS1 on (if IN = 1)
HS2 on (if IN = 1)
6.2.3
LIN pull up termination control bits:
LIN-PU
0
Description
30k pull up connected in sleep and stop mode
1
30k pull up disconnected in sleep and stop mode
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6.2.4
LIN slew rate control and device low power mode pre selection:
LINSL2
LINSL1
Description
0
0
0
1
Lin slew rate normal (baud rate up to 20kb/s)
Lin slew rate slow (baud rate up to 10kb/s)
Lin slew rate fast (for program download, baud rate up to
100kb/s)
1
1
0
1
Low power mode (sleep or stop mode) request, no change in
LIN slew rate
6.3
Read control bits:
6.3.1
Switch input wake up and real time status:
L2
0
Description
L2 input low
L1
0
Description
L1 input low
L2 input high or wake up by L2 (first
register read after wake up)
L1 input high or wake up by L1 (first register
read after wake up)
1
1
6.3.2
High side switch, voltage regulator and device supply status
VSUV
BATFAIL
HSst
Description
VddT
Description
Description
Vsup above 6V
Vsup below 6V
VSOV
Description
0
1
HS no over temp
0
1
No over temperature
0
0
1
Vsup below 19V
HS1,2 or 3 OFF
(over temp)
Vdd over temperature
pre warning
Vsup above
18V
1
6.3.3
LIN bus status
LINWU
LINFAIL
Description
0
1
No LIN bus wake up of failure
LIN bus wake up occurred or LIN over current of over temperature
6.3.4
Interrupt status
INT mask
Description
0
1
SPI word read reflects the flag state
SPI word read reflects the interrupt or wake up source
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