MC33887PNBR2 [MOTOROLA]
5.0 A H-Bridge with Load Current Feedback; 5.0 H桥与负载电流反馈
| 型号： | MC33887PNBR2 |
| 厂家： | 
MOTOROLA |
| 描述： | 5.0 A H-Bridge with Load Current Feedback |
| 文件： | 总28页 (文件大小：484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33887
Rev 9.0, 10/2004
SEMICONDUCTOR TECHNICAL DATA
33887
5.0 A H-Bridge with Load Current
Feedback
The 33887 is a monolithic H-Bridge Power IC with a load current feedback
feature making it ideal for closed-loop DC motor control. The IC incorporates
internal control logic, charge pump, gate drive, and low RDS(ON) MOSFET
5.0 A H-BRIDGE WITH LOAD
CURRENT FEEDBACK
output circuitry. The 33887 is able to control inductive loads with continuous
DC load currents up to 5.0 A, and with peak current active limiting between
5.2 A and 7.8 A. Output loads can be pulse width modulated (PWM-ed) at
frequencies up to 10 kHz. The load current feedback feature provides a
proportional (1/375th of the load current) constant-current output suitable for
monitoring by a microcontroller’s A/D input. This feature facilitates the design
of closed-loop torque/speed control as well as open load detection.
DH SUFFIX
VW (Pb-FREE) SUFFIX
CASE 979-04
A Fault Status output terminal reports undervoltage, short circuit, and
overtemperature conditions. Two independent inputs provide polarity control
of two half-bridge totem-pole outputs. Two disable inputs force the H-Bridge
outputs to tri-state (exhibit high impedance).
20-TERMINAL HSOP
PNB (Pb-FREE) SUFFIX
CASE 1503-01
The 33887 is parametrically specified over a temperature range of
36-TERMINAL PQFN
-40°C ≤ TA ≤ 125°C and a voltage range of 5.0 V ≤ V+ ≤ 28 V. The IC can also
be operated up to 40 V with derating of the specifications.
Bottom View
Features
DWB SUFFIX
CASE 1390-01
54-TERMINAL SOICW-EP
• 5.0 V to 40 V Continuous Operation
• 120 mΩ RDS(ON) H-Bridge MOSFETs
• TTL/CMOS Compatible Inputs
• PWM Frequencies up to 10 kHz
ORDERING INFORMATION
Temperature
• Active Current Limiting (Regulation) via Internal Constant OFF-Time
PWM (with Temperature-Dependent Threshold Reduction)
• Output Short Circuit Protection (Short to V+ or Short to GND)
• Undervoltage Shutdown
• Fault Status Reporting
• Sleep Mode with Current Draw ≤50 µA (Inputs Floating or Set to Match
Default Logic States)
Device
Package
Range (T )
A
MC33887DH/R2
PC33887VW/R2
MC33887PNB/R2
MC33887DWB/R2
20 HSOP
-40°C to 125°C
-40°C to 125°C
-40°C to 125°C
36 PQFN
54 SOICW-EP
• Pb-Free Packaging Designated by Suffix Codes VW and PNB
33887 Simplified Application Diagram
33887
V+
5.0 V
C
CP
V+
OUT1
IN
FS
MOTOR
OUT
EN
IN1
IN2
D1
D2
FB
OUT
OUT
OUT
OUT
OUT2
MCU
PGND
AGND
A/D
For More Information On This Product,
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© Motorola, Inc. 2004
Freescale Semiconductor, Inc.
V+
CCP
Charge Pump
EN
Low-Side
5.0 V
Regulator
Current Limit,
80
µA
Short Circuit
Sense, and
(each)
Current Feedback
Circuit
OUT1
OUT2
IN1
IN2
Gate Drive
D1
D2
Overtemperature
Control
Logic
Detection
25 µA
Undervoltage
Protection
FS
FB
AGND
PGND
Figure 1. 33887 Simplified Internal Block Diagram
33887
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Tab
1
20
19
18
17
16
15
14
13
12
11
AGND
FS
EN
IN2
D1
CCP
V+
OUT2
OUT2
D2
PGND
PGND
2
3
IN1
V+
4
5
V+
OUT1
OUT1
FB
PGND
PGND
6
7
8
9
10
Tab
HSOP TERMINAL DEFINITIONS
A functional description of each terminal can be found in the System/Application Information section, page 19.
Terminal
Terminal
Formal Name
Definition
Name
AGND
FS
1
Analog Ground
Low-current analog signal ground.
2
3
Open drain active LOW Fault Status output requiring a pullup resistor to 5.0 V.
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
Positive supply connections
Fault Status for H-Bridge
Logic Input Control 1
Positive Power Supply
IN1
4, 5, 16
V+
6, 7
8
OUT1
FB
H-Bridge Output 1
Output 1 of H-Bridge.
Feedback for H-Bridge
Current sensing feedback output providing ground referenced 1/375th (0.00266)
of H-Bridge high-side current.
9–12
13
PGND
D2
Power Ground
Disable 2
High-current power ground.
Active LOW input used to simultaneously tri-state disable both H-Bridge outputs.
When D2 is Logic LOW, both outputs are tri-stated.
14, 15
17
OUT2
H-Bridge Output 2
Output 2 of H-Bridge.
C
Charge Pump Capacitor
External reservoir capacitor connection for internal charge pump capacitor.
CP
18
D1
Disable 1
Active HIGH input used to simultaneously tri-state disable both H-Bridge outputs.
When D1 is Logic HIGH, both outputs are tri-stated.
19
20
IN2
EN
Logic Input Control 2
Enable
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN logic
LOW = Sleep Mode).
Tab/Pad
Thermal
Interface
Exposed Pad Thermal
Interface
Exposed pad thermal interface for sinking heat from the device.
Note Must be DC-coupled to analog ground and power ground via very low
impedance path to prevent injection of spurious signals into IC substrate.
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Transparent Top View of Package
28
27
26
25
24
23
22
21
20
19
1
2
NC
D2
NC
D1
IN2
EN
V+
V+
3
PGND
PGND
PGND
PGND
PGND
PGND
FB
4
5
6
7
NC
AGND
FS
8
9
10
NC
NC
PQFN TERMINAL DEFINITIONS
A functional description of each terminal can be found in the System/Application Information section, page 19.
Terminal
Name
Terminal
Formal Name
Definition
No internal connection to this terminal.
1, 7, 10, 16,
19, 28, 31
NC
No Connect
2
D1
Disable 1
Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.
3
4
IN2
EN
Logic Input Control 2
Enable
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
Logic input Enable control of device (i.e., EN logic HIGH = full operation,
EN logic LOW = Sleep Mode).
5, 6, 12, 13, 34, 35
V+
AGND
FS
Positive Power Supply
Analog Ground
Positive supply connections.
8
9
Low-current analog signal ground.
Fault Status for H-Bridge
Open drain active LOW Fault Status output requiring a pullup resistor to
5.0 V.
11
14, 15, 17, 18
20
IN1
OUT1
FB
Logic Input Control 1
H-Bridge Output 1
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
Output 1 of H-Bridge.
Feedback for H-Bridge
Current feedback output providing ground referenced 1/375th ratio of
H-Bridge high-side current.
21–26
27
PGND
D2
Power Ground
Disable 2
High-current power ground.
Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated.
29, 30, 32, 33
36
OUT2
H-Bridge Output 2
Output 2 of H-Bridge.
C
Charge Pump Capacitor
External reservoir capacitor connection for internal charge pump capacitor.
CP
Pad
Thermal
Interface
Exposed Pad Thermal
Interface
Exposed pad thermal interface for sinking heat from the device.
Note Must be DC-coupled to analog ground and power ground via very low
impedance path to prevent injection of spurious signals into IC substrate.
33887
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Transparent Top View of Package
PGND
PGND
PGND
PGND
NC
NC
NC
D2
NC
OUT2
OUT2
OUT2
OUT2
NC
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
.35
34
33
32
31
30
29
28
PGND
PGND
PGND
PGND
NC
NC
NC
FB
NC
OUT1
OUT1
OUT1
OUT1
NC
V+
V+
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
V+
V+
V+
V+
V+
V+
NC
NC
NC
NC
CCP
D1
IN2
EN
NC
NC
NC
NC
NC
IN1
FS
AGND
NC
NC
SOICW-EP TERMINAL DEFINITIONS
A functional description of each terminal can be found in the System/Application Information section, page 19.
Terminal
Terminal
Formal Name
Definition
Name
PGND
NC
1–4, 51–54
Power Ground
No Connect
High-current power ground.
5–7, 9, 14, 19–22,
27–29, 33–36, 41,
46, 48–50
No internal connection to this terminal.
8
Disable 2
Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated.
D2
10–13
OUT2
V+
H-Bridge Output 2
Output 2 of H-Bridge.
15 –18, 37–40
Positive Power Supply
Positive supply connections.
23
24
C
Charge Pump Capacitor
Disable 1
External reservoir capacitor connection for internal charge pump capacitor.
CP
D1
Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.
25
26
IN2
EN
Logic Input Control 2
Enable
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
Logic input Enable control of device (i.e., EN logic HIGH = full operation,
EN logic LOW = Sleep Mode).
30
31
AGND
FS
Analog Ground
Low-current analog signal ground.
Fault Status for H-Bridge
Open drain active LOW Fault Status output requiring a pullup resistor to
5.0 V.
32
42–45
47
IN1
OUT1
FB
Logic Input Control 1
H-Bridge Output 1
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
Output 1 of H-Bridge.
Feedback for H-Bridge
Current feedback output providing ground referenced 1/375th ratio of
H-Bridge high-side current.
Pad
Thermal
Interface
Exposed Pad Thermal
Interface
Exposed pad thermal interface for sinking heat from the device.
Note Must be DC-coupled to analog ground and power ground via very low
impedance path to prevent injection of spurious signals into IC substrate.
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
ELECTRICAL RATINGS
Supply Voltage
Symbol
Value
Unit
V+
40
-0.3 to 7.0
7.0
V
V
V
A
V
Input Voltage (Note 1)
V
IN
V FS
FS Status Output (Note 2)
Continuous Current (Note 3)
I
5.0
OUT
DH Suffix HSOP ESD Voltage
Human Body Model (Note 4)
Each Terminal to AGND
Each Terminal to PGND
Each Terminal to V+
V
V
V
V
V
±1000
±1500
±2000
±2000
±200
ESD1
ESD1
ESD1
ESD1
Each I/O to All Other I/Os
Machine Model (Note 5)
ESD2
VW Suffix HSOP ESD Voltage
Human Body Model (Note 4)
Machine Model (Note 5)
V
V
V
±2000
±200
V
V
ESD1
ESD2
PQFN ESD Voltage
V
V
Human Body Model (Note 4)
Machine Model (Note 5)
±2000
±200
ESD1
ESD2
SOICW-EP ESD Voltage
Human Body Model (Note 4)
Machine Model (Note 5)
V
V
±1600
±200
ESD1
ESD2
THERMAL RATINGS
Storage Temperature
T
-65 to 150
°C
°C
STG
Operating Temperature (Note 6)
T
Ambient
Junction
A
-40 to 125
-40 to 150
T
J
Peak Package Reflow Temperature During Solder Mounting (Note 7)
T
°C
SOLDER
220
260
240
HSOP
PQFN
SOICW-EP
Notes
1. Exceeding the input voltage on IN1, IN2, EN, D1, or D2 may cause a malfunction or permanent damage to the device.
2. Exceeding the pullup resistor voltage on the open Drain FS terminal may cause permanent damage to the device.
3. Continuous current capability so long as junction temperature is ≤ 150°C.
4. ESD1 testing is performed in accordance with the Human Body Model (C
= 100 pF, R
= 1500 Ω).
ZAP
ZAP
5. ESD2 testing is performed in accordance with the Machine Model (C
= 200 pF, R
= 0 Ω).
ZAP
ZAP
6. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief
nonrepetitive excursions of junction temperature above 150°C can be tolerated as long as duration does not exceed 30 seconds maximum.
(nonrepetitive events are defined as not occurring more than once in 24 hours.)
7. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
33887
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MAXIMUM RATINGS (continued)
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
THERMAL RESISTANCE (AND PACKAGE DISSIPATION) RATINGS (Note 8), (Note 9), (Note 10), (Note 11)
Junction-to-Board (Bottom Exposed Pad Soldered to Board)
R
°C/W
θJB
HSOP (6.0 W)
~5.0
~4.3
~8.0
PQFN (4.0 W)
SOICW-EP (2.0 W)
Junction-to-Ambient, Natural Convection, Single-Layer Board (1s)
(Note 12)
R
°C/W
°C/W
°C/W
θJA
HSOP (6.0 W)
~41
~TBD
~62
PQFN (4.0 W)
SOICW-EP (2.0 W)
Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p)
(Note 13)
R
θJMA
HSOP (6.0 W)
~30
PQFN (4.0 W)
~21.3
~TBD
SOICW-EP (2.0 W)
Junction-to-Case (Exposed Pad) (Note 14)
HSOP (6.0 W)
R
θJC
~0.5
~0.9
~1.5
PQFN (4.0 W)
SOICW-EP (2.0 W)
Notes
8. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking.
9. Exposed heatsink pad plus the power and ground terminals comprise the main heat conduction paths. The actual RθJB (junction-to-PC board)
values will vary depending on solder thickness and composition and copper trace thickness. Maximum current at maximum die temperature
represents ~16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the R
-total must be less than 5.0 °C/W
θJC
for maximum load at 70°C ambient. Module thermal design must be planned accordingly.
10. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface
of the board near the package.
11. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
12. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
13. Per JEDEC JESD51-6 with the board horizontal.
14. Indicates the average thermal resistance between the die and the exposed pad surface as measured by the cold plate method (MIL SPEC-
883 Method 1012.1) with the cold plate temperature used for the case temperature.
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER SUPPLY
Operating Voltage Range (Note 15)
Sleep State Supply Current (Note 16)
V+
5.0
–
–
25
–
40
50
20
V
I
µA
Q(sleep)
I
= 0 A, V = 0 V
EN
OUT
Standby Supply Current
= 0 A, V = 5.0 V
I
mA
Q(standby)
I
–
OUT
EN
Threshold Supply Voltage
Switch-OFF
V+
(thres-OFF)
4.15
4.5
4.4
4.75
–
4.65
5.0
–
V
V
V+
(thres-ON)
Switch-ON
V+
(hys)
150
mV
Hysteresis
CHARGE PUMP
Charge Pump Voltage
V+ = 5.0 V
V
- V+
V
V
CP
3.35
–
–
–
–
8.0 V ≤ V+ ≤ 40 V
20
CONTROL INPUTS
Input Voltage (IN1, IN2, D1, D2)
Threshold HIGH
V
3.5
–
–
–
–
1.4
–
IH
V
IL
Threshold LOW
V
HYS
0.7
1.0
Hysteresis
Input Current (IN1, IN2, D1)
I
I
µA
µA
INP
V
- 0.0 V
-200
–
-80
25
–
IN
Input Current (D2, EN)
INP
100
V
D2 = 5.0 V
Notes
15. Specifications are characterized over the range of 5.0 V ≤ V+ ≤ 28 V. Operation >28 V will cause some parameters to exceed listed min/max
values. Refer to typical operating curves to extrapolate values for operation >28 V but ≤ 40 V.
16.
I
is with sleep mode function enabled.
Q(sleep)
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect
the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUTS (OUT1, OUT2)
Output ON-Resistance (Note 17)
5.0 V ≤ V+ ≤ 28 V, T = 25°C
R
mΩ
DS(ON)
–
–
–
120
–
–
J
225
300
8.0 V ≤ V+ ≤ 28 V, T = 150°C
J
–
5.0 V ≤ V+ ≤ 8.0 V, T = 150°C
J
Active Current Limiting Threshold (via Internal Constant OFF-Time PWM) on
Low-Side MOSFETs (Note 18)
I
5.2
6.5
7.8
A
LIM
High-Side Short Circuit Detection Threshold
Low-Side Short Circuit Detection Threshold
Leakage Current (Note 19)
I
11
–
–
–
–
A
A
SCH
I
8.0
SCL
OUT(leak)
I
µA
V
V
= V+
–
–
100
30
200
60
OUT
OUT
= Ground
Output MOSFET Body Diode Forward Voltage Drop
= 3.0 A
V
V
F
I
–
–
2.0
OUT
Overtemperature Shutdown
Thermal Limit
°C
T
175
10
–
–
225
30
LIM
Hysteresis
T
HYS
HIGH-SIDE CURRENT SENSE FEEDBACK
Feedback Current
I
FB
I
I
I
I
I
= 0 mA
= 500 mA
= 1.5 A
= 3.0 A
= 6.0 A
–
–
600
1.68
4.62
9.24
18.48
µA
mA
mA
mA
mA
OUT
OUT
OUT
OUT
OUT
1.07
3.6
1.33
4.0
8.0
16
7.2
14.4
FAULT STATUS (Note 20)
Fault Status Leakage Current (Note 21)
IFS(
µA
leak
)
V
FS = 5.0 V
–
–
–
–
10
Fault Status SET Voltage (Note 22)
VFS(LOW)
V
IFS = 300 µA
1.0
Notes
17. Output-ON resistance as measured from output to V+ and ground.
18. Active current limitation applies only for the low-side MOSFETs.
19. Outputs switched OFF with D1 or D2.
20. Fault Status output is an open Drain output requiring a pullup resistor to 5.0 V.
21. Fault Status Leakage Current is measured with Fault Status HIGH and not SET.
22. Fault Status Set Voltage is measured with Fault Status LOW and SET with IFS = 300 µA.
33887
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency (Note 23)
f
–
–
10
–
–
kHz
kHz
µs
PWM
Maximum Switching Frequency During Active Current Limiting (Note 24)
f
20
MAX
Output ON Delay (Note 25)
V+ = 14 V
t
d(ON)
–
–
18
Output OFF Delay (Note 25)
V+ = 14 V
t
µs
d(OFF)
–
–
18
26
µs
µs
I
I
Output Constant-OFF Time for Low-Side MOSFETs (Note 26), (Note 27)
Blanking Time for Low-Side MOSFETs (Note 28), (Note 27)
t
t
15
20.5
LIM
LIM
a
b
12
16.5
21
Output Rise and Fall Time (Note 29)
V+ = 14 V, I = 3.0 A
t , t
µs
f
r
2.0
5.0
8.0
OUT
Disable Delay Time (Note 30)
Power-ON Delay Time (Note 31)
Wake-Up Delay Time (Note 31)
Output MOSFET Body Diode Reverse Recovery Time (Note 32)
Notes
t
–
–
–
8.0
5.0
5.0
–
µs
d(disable)
t
1.0
1.0
–
ms
pod
wud
t
–
ms
ns
t
100
rr
23. The outputs can be PWM-controlled from an external source. This is typically done by holding one input high while applying a PWM pulse
train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching frequency. See
Typical Switching Waveforms, Figures 11 through 18, pp. 15–16.
24. The Maximum Switching Frequency during active current limiting is internally implemented. The internal current limit circuitry produces a
constant-OFF-time pulse-width modulation of the output current. The output load’s inductance, capacitance, and resistance characteristics
affect the total switching period (OFF-time + ON-time) and thus the PWM frequency during current limit.
25. Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition
direction) of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from the midpoint of the input signal to the
90% point of the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from the midpoint of the input signal to the
10% point of the output response signal. See Figure 2, page 11.
26.
I
Output Constant-OFF Time is the time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the
LIM
output bridge.
27. Load currents ramping up to the current regulation threshold become limited at the ILIM value. The short circuit currents possess a di/dt that
ramps up to the I or I threshold during the ILIM blanking time, registering as a short circuit event detection and causing the shutdown
SCH
SCL
circuitry to force the output into an immediate tri-state latch-OFF. See Figures 6 and 7, page 12. Operation in Current Limit mode may cause
junction temperatures to rise. Junction temperatures above ~160°C will cause the output current limit threshold to progressively “fold back”,
or decrease with temperature, until ~175°C is reached, after which the TLIM thermal latch-OFF will occur. Permissible operation within this
foldback region is limited to nonrepetitive transient events of duration not to exceed 30 seconds. See Figure 5, page 11.
28.
I
Blanking Time is the time during which the current regulation threshold is ignored so that the short-circuit detection threshold
LIM
comparators my have time to act.
29. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 4, page 11.
30. Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See Figure 3,
page 11.
31. Parameter has been characterized but not production tested.
32. Parameter is guaranteed by design but not production tested.
33887
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Timing Diagrams
5.0
50%
50%
0
td(OFF)
td(ON)
90%
VPWR
10%
0
TIME
Figure 2. Output Delay Time
5.0 V
0 V
∞ Ω
0 Ω
Figure 3. Disable Delay Time
VPWR
tf
tr
90%
90%
10%
10%
0
Figure 4. Output Switching Time
6.5
Operation within this region must be
limited to nonrepetitive events
not to exceed 30 seconds
4.0
Thermal Shutdown
175
160
T , JUNCTION TEMPERATURE (oC)
150
J
Figure 5. Active Current Limiting Versus Temperature (Typical)
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>8A
6.5
Short Circuit Detection Threshold
Typical Current Limit Threshold
High Current Load Being Regulated via Constant-OFF-Time PWM
Active
Current
Limiting
on Low-Side
MOSFET
Moderate Current Load
0
IN1 or IN2
IN2 or IN1
IN1 or IN2
[1]
IN1 IN2
IN2 or IN1
[0]
[1]
[0]
[1]
[0]
[1]
[0]
Outputs
Outputs Operation
Outputs
Tri-Stated
Tri-Stated (per Input Control Condition)
Time
Figure 6. Operating States
I
Short Circuit Detection Threshold
8.0
6.5
SCL
t
t
= Output Constant-OFF Time
a
t
t
t
b
on
a
= I BlankingTime
bLIM
Hard short is detected during t
and output is latched-off.
b
Hard short occurs.
0.0
5.0
TIME
Figure 7. Example Short Circuit Detection Detail on Low-Side MOSFET
33887
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Electrical Performance Curves
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.0
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
Volts
Figure 8. Typical High-Side RDS(ON) Versus V+
0.13
0.128
0.126
0.124
0.122
0.12
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
Volts
Figure 9. Typical Low-Side RDS(ON) Versus V+
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9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
Volts
Figure 10. Typical Quiescent Supply Current Versus V+
33887
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Typical Switching Waveforms
Important For all plots, the following applies:
• Ch2=2.0 A per division
• LLOAD=533 µH @ 1.0 kHz
• LLOAD=530 µH @ 10.0 kHz
• RLOAD=4.0 Ω
Output Voltage
(OUT1)
Output Voltage
(OUT1)
I
OUT
I
OUT
Input Voltage
(IN1)
Input Voltage
(IN1)
V+=24 V
f
=1.0 kHz Duty Cycle=10%
V+=34 V
f
=1.0 kHz Duty Cycle=90%
PWM
PWM
Figure 11. Output Voltage and Current vs. Input Voltage at
V+ = 24 V, PMW Frequency of 1.0 kHz,
and Duty Cycle of 10%
Figure 13. Output Voltage and Current vs. Input Voltage at
V+ = 34 V, PMW Frequency of 1.0 kHz,
and Duty Cycle of 90%, Showing Device in
Current Limiting Mode
Output Voltage
(OUT1)
Output Voltage
(OUT1)
I
OUT
I
OUT
Input Voltage
(IN1)
Input Voltage
(IN1)
V+=24 V
f
= 1.0 kHz Duty Cycle = 50%
PWM
V+=22 V
f
=1.0 kHz Duty Cycle=90%
PWM
Figure 12. Output Voltage and Current vs. Input Voltage at
V+ = 24 V, PMW Frequency of 1.0 kHz,
Figure 14. Output Voltage and Current vs. Input Voltage at
V+ = 22 V, PMW Frequency of 1.0 kHz,
and Duty Cycle of 50%
and Duty Cycle of 90%
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Output Voltage
(OUT1)
Output Voltage
(OUT1)
I
OUT
I
OUT
Input Voltage
(IN1)
Input Voltage
(IN1)
V+=12 V
f
=20 kHz
Duty Cycle=50%
V+=24 V
f
=10 kHz
Duty Cycle=50%
PWM
PWM
Figure 15. Output Voltage and Current vs. Input Voltage at
V+ = 24 V, PMW Frequency of 10 kHz,
and Duty Cycle of 50%
Figure 17. Output Voltage and Current vs. Input Voltage at
V+ = 12 V, PMW Frequency of 20 kHz,
and Duty Cycle of 50% for a Purely Resistive Load
Output Voltage
(OUT1)
Output Voltage
(OUT1)
I
OUT
I
OUT
Input Voltage
(IN1)
Input Voltage
(IN1)
V+=12 V
f
=20 kHz
Duty Cycle=90%
V+=24 V
f
=10 kHz
Duty Cycle=90%
PWM
PWM
Figure 16. Output Voltage and Current vs. Input Voltage at
V+ = 24 V, PMW Frequency of 10 kHz,
Figure 18. Output Voltage and Current vs. Input Voltage at
V+ = 12 V, PMW Frequency of 20 kHz,
and Duty Cycle of 90%
and Duty Cycle of 90% for a Purely Resistive Load
33887
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Table 1. Truth Table
The tri-state conditions and the fault status are reset using D1 or D2. The truth table uses the following notations: L = LOW, H = HIGH,
X = HIGH or LOW, and Z = High impedance (all output power transistors are switched off).
Fault
Status Flag
Input Conditions
Output States
Device State
D1
L
IN1
H
L
IN2
L
OUT1
OUT2
EN
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D2
H
H
H
H
X
FS
H
H
H
H
L
Forward
Reverse
H
L
L
H
L
L
H
L
Freewheeling Low
Freewheeling High
Disable 1 (D1)
L
L
L
L
H
X
X
Z
H
X
X
X
Z
H
Z
Z
H
X
Z
Z
Z
Z
Z
Z
Z
H
Z
Z
X
H
Z
Z
Z
Z
Z
Z
Z
H
X
L
L
L
Disable 2 (D2)
IN1 Disconnected
IN2 Disconnected
D1 Disconnected
D2 Disconnected
Undervoltage (Note 33)
Overtemperature (Note 34)
Short Circuit (Note 34)
Sleep Mode EN
H
H
X
Z
H
H
L
L
X
X
X
X
X
X
X
X
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
L
L
L
H
H
EN Disconnected
Z
Notes
33. In the case of an undervoltage condition, the outputs tri-state and the fault status is SET logic LOW. Upon undervoltage recovery, fault status
is reset automatically or automatically cleared and the outputs are restored to their original operating condition.
34. When a short circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF independent of the input signals
and the fault status flag is SET logic LOW.
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
Numerous protection and operational features (speed,
Two independent inputs (IN1 and IN2) provide control of the
two totem-pole half-bridge outputs. Two disable inputs (D1 and
D2) provide the means to force the H-Bridge outputs to a high-
impedance state (all H-Bridge switches OFF). An EN terminal
controls an enable function that allows the 33887 to be placed
in a power-conserving sleep mode.
torque, direction, dynamic braking, PWM control, and closed-
loop control), in addition to the 5.0 A current capability, make
the 33887 a very attractive, cost-effective solution for
controlling a broad range of small DC motors. In addition, a pair
of 33887 devices can be used to control bipolar stepper motors.
The 33887 can also be used to excite transformer primary
windings with a switched square wave to produce secondary
winding AC currents.
The 33887 has undervoltage shutdown with automatic
recovery, active current limiting, output short-circuit latch-OFF,
and overtemperature latch-OFF. An undervoltage shutdown,
output short-circuit latch-OFF, or overtemperature latch-OFF
fault condition will cause the outputs to turn OFF (i.e., become
high impedance or tri-stated) and the fault output flag to be set
LOW. Either of the Disable inputs or V+ must be “toggled” to
clear the fault flag.
As shown in Figure 1, Simplified Internal Block Diagram,
page 2, the 33887 is a fully protected monolithic H-Bridge with
Enable, Fault Status reporting, and High-Side current sense
feedback to accommodate closed-loop PWM control. For a DC
motor to run, the input conditions need be as follows: Enable
input logic HIGH, D1 input logic LOW, D2 input logic HIGH, FS
flag cleared (logic HIGH), one IN logic LOW and the other IN
logic HIGH (to define output polarity). The 33887 can execute
dynamic braking by simultaneously turning on either both high-
side MOSFETs or both low-side MOSFETs in the output
H-Bridge; e.g., IN1 and IN2 logic HIGH or IN1 and IN2 logic
LOW.
Active current limiting is accomplished by a constant OFF-
time PWM method employing active current limiting threshold
triggering. The active current limiting scheme is unique in that it
incorporates a junction temperature-dependent current limit
threshold. This means the active current limiting threshold is
“ramped down” as the junction temperature increases above
160°C, until at 175°C the current will have been decreased to
about 4.0 A. Above 175°C, the overtemperature shutdown
(latch-OFF) occurs. This combination of features allows the
device to remain in operation for 30 seconds at junction
temperatures above 150°C for nonrepetitive unexpected loads.
The 33887 outputs are capable of providing a continuous DC
load current of 5.0 A from a 40 V V+ source. An internal charge
pump supports PWM frequencies to 10 kHz. An external pullup
resistor is required at the FS terminal for fault status reporting.
The 33887 has an analog feedback (current mirror) output
terminal (the FB terminal) that provides a constant-current
source ratioed to the active high-side MOSFET. This can be
used to provide “real time” monitoring of load current to facilitate
closed-loop operation for motor speed/torque control.
33887
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FUNCTIONAL TERMINAL DESCRIPTION
The outputs also have thermal shutdown (tri-state latch-OFF)
with hysteresis as well as short circuit latch-OFF protection.
PGND and AGND
Power and analog ground terminals should be connected
together with a very low impedance connection.
A disable timer (time tb) incorporated to detect currents that
are higher than current limit is activated at each output
activation to facilitate hard short detection (see Figure 7,
page 12).
V+
V+ terminals are the power supply inputs to the device. All V+
terminals must be connected together on the printed circuit
board with as short as possible traces offering as low
impedance as possible between terminals.
CCP
A filter capacitor (up to 33 nF) can be connected from the
charge pump output terminal and PGND. The device can
operate without the external capacitor, although the CCP
V+ terminals have an undervoltage threshold. If the supply
voltage drops below a V+ undervoltage threshold, the output
power stage switches to a tri-state condition and the fault status
flag is SET and the Fault Status terminal voltage switched to a
logic LOW. When the supply voltage returns to a level that is
above the threshold, the power stage automatically resumes
normal operation according to the established condition of the
input terminals and the fault status flag is automatically reset
logic HIGH.
capacitor helps to reduce noise and allows the device to
perform at maximum speed, timing, and PWM frequency.
EN
The EN terminal is used to place the device in a sleep mode
so as to consume very low currents. When the EN terminal
voltage is a logic LOW state, the device is in the sleep mode.
The device is enabled and fully operational when the EN
terminal voltage is logic HIGH. An internal pulldown resistor
maintains the device in sleep mode in the event EN is driven
through a high impedance I/O or an unpowered microcontroller,
or the EN input becomes disconnected.
Fault Status (FS)
The FS terminal is the device fault status output. This output
is an active LOW open drain structure requiring a pullup resistor
to 5.0 V. Refer to Table 1, Truth Table, page 17.
FB
IN1, IN2, D1, and D2
The 33887 has a feedback output (FB) for “real time”
monitoring of H-Bridge high-side current to facilitate closed-
loop operation for motor speed and torque control.
These terminals are input control terminals used to control
the outputs. These terminals are 5.0 V CMOS-compatible
inputs with hysteresis. The IN1 and IN2 independently control
OUT1 and OUT2, respectively. D1 and D2 are complementary
inputs used to tri-state disable the H-Bridge outputs.
The FB terminal provides current sensing feedback of the
H-Bridge high-side drivers. When running in the forward or
reverse direction, a ground referenced 1/375th (0.00266) of
load current is output to this terminal. Through the use of an
external resistor to ground, the proportional feedback current
can be converted to a proportional voltage equivalent and the
controlling microcontroller can “read” the current proportional
voltage with its analog-to-digital converter (ADC). This is
intended to provide the user with motor current feedback for
motor torque control. The resistance range for the linear
operation of the FB terminal is 100 <RFB <200 Ω.
When either D1 or D2 is SET (D1 = logic HIGH or D2 = logic
LOW) in the disable state, outputs OUT1 and OUT2 are both tri-
state disabled; however, the rest of the device circuitry is fully
operational and the supply IQ(standby) current is reduced to a few
milliamperes. Refer to Table 1, Truth Table, and STATIC
ELECTRICAL CHARACTERISTICS table, page 8.
OUT1 and OUT2
These terminals are the outputs of the H-Bridge with
integrated output MOSFET body diodes. The bridge output is
controlled using the IN1, IN2, D1, and D2 inputs. The low-side
MOSFETs have active current limiting above the ILIM threshold.
If PWM-ing is implemented using the disable terminal inputs
(either D1 or D2), a small filter capacitor (1.0 µF or less) may be
required in parallel with the external resistor to ground for fast
spike suppression.
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PERFORMANCE FEATURES
The current limiting threshold value is dependent upon the
Short Circuit Protection
device junction temperature. When -40°C ≤ TJ ≤ 160°C, ILIM is
between 5.2 A to 7.8 A. When TJ exceeds 160°C, the ILIM
current decreases linearly down to 4.0 A typical at 175°C.
Above 175°C the device overtemperature circuit detects TLIM
and overtemperature shutdown occurs (see Figure 5, page 11).
This feature allows the device to remain operational for a longer
time but at a regressing output performance level at junction
temperatures above 160°C.
If an output short circuit condition is detected, the power
outputs tri-state (latch-OFF) independent of the input (IN1 and
IN2) states, and the fault status output flag is SET logic LOW. If
the D1 input changes from logic HIGH to logic LOW, or if the D2
input changes from logic LOW to logic HIGH, the output bridge
will become operational again and the fault status flag will be
reset (cleared) to a logic HIGH state.
The output stage will always switch into the mode defined by
the input terminals (IN1, IN2, D1, and D2), provided the device
junction temperature is within the specified operating
temperature range.
Overtemperature Shutdown and Hysteresis
If an overtemperature condition occurs, the power outputs
are tri-stated (latched-OFF) and the fault status flag is SET to
logic LOW.
Active Current Limiting
To reset from this condition, D1 must change from logic
HIGH to logic LOW, or D2 must change from logic LOW to logic
HIGH. When reset, the output stage switches ON again,
provided that the junction temperature is now below the
overtemperature threshold limit minus the hysteresis.
The maximum current flow under normal operating
conditions is internally limited to ILIM (5.2 A to 7.8 A). When the
maximum current value is reached, the output stages are tri-
stated for a fixed time (t ) of 20 µs typical. Depending on the
a
time constant associated with the load characteristics, the
current decreases during the tri-state duration until the next
output ON cycle occurs (see Figures 7 and 13, page 12 and
page 15, respectively).
Note Resetting from the fault condition will clear the fault
status flag.
PACKAGE INFORMATION
The 33887 packages are designed for thermal performance.
The significant feature of these packages is the exposed pad on
which the power die is soldered. When soldered to a PCB, this
pad provides a path for heat flow to the ambient environment.
The more copper area and thickness on the PCB, the better the
power dissipation and transient behavior will be.
Figure 20 shows the thermal response with the device in the
HSOP package soldered on to the test PCB described in
Figure 19.
100
Example Characterization on a double-sided PCB: bottom
side area of copper is 7.8 cm2; top surface is 2.7 cm2 (see
Figure 19); grid array of 24 vias 0.3 mm in diameter.
10
Rth (°C/W)
1
0,1
0,001
0,01
0,1
1
10
t, Time (s)
100
1000
10000
Figure 20. 33887 Thermal Response, HSOP Package
Top Side
Figure 19. PCB Test Layout
Bottom Side
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APPLICATIONS
Figure 21 shows a typical application schematic. For
precision high-current applications in harsh, noisy
environments, the V+ by-pass capacitor may need to be
substantially larger.
DC
MOTOR
V+
33887
AGND
V+
C
+
CP
33 nF
47 µF
OUT2
EN
OUT1
FB
D2
+
1.0 µF
D1
100 Ω
FS
PGND
IN1
IN2
FB
IN2
IN1
FS
D1
D2
EN
Figure 21. 33887 Typical Application Schematic
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PACKAGE DIMENSIONS
DH SUFFIX
VW (Pb-FREE) SUFFIX
20-TERMINAL HSOP
PLASTIC PACKAGE
CASE 979-04
ISSUE C
PIN ONE ID
NOTES:
hX 45˚
EXPOSED
HEATSINK AREA
1. CONTROLLING DIMENSION: MILLIMETER.
2. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M, 1994.
E2
E3
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.150 PER SIDE. DIMENSIONS D AND E1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-.
20
1
D2
e
18X
D
A
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.178 TOTAL IN EXCESS
OF THE b DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. DATUMS -A- AND -B- TO BE DETERMINED AT
DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE TIEBAR
PROTRUSIONS. ALLOWABLE TIEBAR
PROTRUSIONS ARE 0.150 PER SIDE.
D1
e/2
10
11
B
E1
E4
E
BOTTOM VIEW
MILLIMETERS
M
bbb
C B
DIM
A
MIN
3.100
MAX
3.350
A1
A2 3.100
0.050 BSC
3.250
D
15.800 16.000
D1 12.270 12.470
D2 0.900 1.100
13.950 14.450
E1 10.900 11.100
A2
A
E
DATUM
PLANE
H
SEATING
PLANE
E2 2.500
E3 7.000
E4 2.700
2.700
7.200
2.900
1.100
DETAILY
C
L
L1
b
0.840
0.350 BSC
b
0.400
0.400
0.230
0.230
0.520
0.482
0.310
0.280
b1
c
b1
GAUGE
PLANE
c1
e
L1
c1
1.270 BSC
c
W
h
---
0
1.100
8
q
W
aaa
bbb
ccc
0.200
0.200
0.100
ccc D
A1
M
q
aaa
C A
L
D
(1.600)
DETAILY
SECTION W-W
33887
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PNB (Pb-FREE) SUFFIX
36-TERMINAL PQFN
NON-LEADED PACKAGE
CASE 1503-01
ISSUE O
9
A
DETAIL G
M
PIN 1
INDEX AREA
0.1
C
2X
9
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: F-PQFP-N.
4. COPLANARITY APPLIES TO LEADS AND CORNER
LEADS.
M
B
0.1
C
0.1
C
2X
2.20
1.95
2.2
2.0
0.05 C
4
(0.55)
0.05
0.00
6.5
5.5
C
SEATING PLANE
(0.8)
0.1
C A B
PIN 1
INDEX
DETAIL G
3.2
36
VIEW ROTATED 90˚ CW
0.6
0.4
2X
28
1
2
3.2
0.4
6.5
5.5
0.1
C A B
4.3
DETAIL N
19
10
0.37
0.23
40X
40X (0.175)
0.9
0.7
0.60
0.45
2X
4 PLACES
32X
32X
1.08
0.94
M
0.1
C A B
M
0.1
C A B
4.3
M
0.05
C
M
0.05
C
VIEW M M
DETAIL N
CORNER CONFIGURATION
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DWB SUFFIX
54-TERMINAL SOICW EXPOSED PAD
PLASTIC PACKAGE
CASE 1390-01
ISSUE B
10.3
5
9
7.6
7.4
C
NOTES:
2.65
2.35
B
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. DATUMS B AND C TO BE DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
4. THIS DIMENSION DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURRS. MOLD
FLASH, PROTRUSION OR GATE BURRS SHALL
NOT EXCEED 0.15 MM PER SIDE.THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
52X
1
54
0.65
PIN 1 INDEX
5. THIS DIMENSION DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH AND PROTRUSIONS SHALL
NOT EXCEED 0.25 MM PER SIDE.THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
6. THIS DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN
4
9
18.0
17.8
B
B
PROTRUSION AND ADJACENT LEAD SHALL NOT
LESS THAN 0.07 MM.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1 MM AND
0.3 MM FROM THE LEAD TIP.
9. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM.THIS DIMENSION IS
DETERMINED AT THE OUTERMOST EXTREMES
OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTER-LEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
27
28
SEATING
PLANE
A
5.15
2X 27 TIPS
54X
0.10 A
0.3
A B C
A
A
R0.08 MIN
MIN
0˚
C
C
0.25
GAUGE PLANE
(1.43)
0.1
0.0
0.9
0.5
8˚
0˚
0.30
A B C
SECTION B-B
4.8
4.3
(0.29)
BASE METAL
0.30
0.25
(0.25)
4.8
4.3
0.38
0.22
0.30
A B C
PLATING
6
M
0.13
A B C
8
SECTION A-A
ROTATED 90˚ CLOCKWISE
VIEW C-C
33887
24
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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NOTES
33887
25
MOTOROLA ANALOG INTEGRATED CIRFCoUIrTMDEoVrICeEIDnAfToArmation On This Product,
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Freescale Semiconductor, Inc.
NOTES
33887
26
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Freescale Semiconductor, Inc.
NOTES
33887
27
MOTOROLA ANALOG INTEGRATED CIRFCoUIrTMDEoVrICeEIDnAfToArmation On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be
provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license
under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
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could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or
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claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their
respective owners.
© Motorola, Inc. 2004
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