MC33972DWB [MOTOROLA]
Multiple Switch Detection Interface with Suppressed Wake-Up; 多交换检测接口与抑制唤醒
| 型号： | MC33972DWB |
| 厂家： | 
MOTOROLA |
| 描述： | Multiple Switch Detection Interface with Suppressed Wake-Up |
| 文件： | 总28页 (文件大小：506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Document order number: MC33972
Rev 3.0, 12/2004
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
33972
Multiple Switch Detection Interface
with Suppressed Wake-Up
The 33972 Multiple Switch Detection Interface with Suppressed Wake-Up is
designed to detect the closing and opening of up to 22 switch contacts. The
switch status, either open or closed, is transferred to the microprocessor unit
(MCU) through a serial peripheral interface (SPI). The device also features a
22-to-1 analog multiplexer for reading inputs as analog. The analog input
signal is buffered and provided on the AMUX output terminal for the MCU to
read.
MULTIPLE SWITCH
DETECTION INTERFACE WITH
SUPPRESSED WAKE-UP
The 33972 device has two modes of operation, Normal and Sleep. Normal
mode allows programming of the device and supplies switch contacts with
pullup or pulldown current as it monitors switch change of state. The Sleep
mode provides low quiescent current, which makes the 33972 ideal for
automotive and industrial products requiring low sleep state currents.
DWB SUFFIX
EW (Pb-FREE) SUFFIX
CASE 1324-02
Features
• Designed to Operate 5.5 V ≤ VPWR ≤ 26 V
• Switch Input Voltage Range -14 V to VPWR, 40 V Max
32-TERMINAL SOICW
• Interfaces Directly to Microprocessor Using 3.3 V/5.0 V SPI Protocol
• Selectable Wake-Up on Change of State
• Selectable Wetting Current (16 mA or 2.0 mA)
• 8 Programmable Inputs (Switches to Battery or Ground)
• 14 Switch-to-Ground Inputs
ORDERING INFORMATION
Temperature
Device
Package
Range (T )
A
MC33972DWB/R2
MC33972EW/R2
32 SOICW
-40°C to 125°C
• VPWR Standby Current 100 µA Typical, VDD Standby Current 20 µA
Typical
• Active Interrupt (INT) on Change-of-Switch State
• Pb-Free Packaging Designated by Suffix Code EW
33972 Simplified Application Diagram
V
DD
V
BAT
Power Supply
LVI
V
V
33972
BAT
Enable
SP0
SP1
V
PWR
Watchdog
Reset
MCU
V
DD
BAT
SP7
WAKE
SI
SCLK
CS
MOSI
SCLK
CS
SG0
SG1
SO
MISO
INT
INT
AMUX
AN0
SG12
SG13
GND
This document contains information on a new product.
Specifications and information herein are subject to change without notice.
For More Information On This Product,
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© Motorola, Inc. 2004
Freescale Semiconductor, Inc.
5.0 V
VPWR
VPWR VPWR
SP0
VPWR, VDD, 5.0 V
VPWR
VDD
16.0
2.0
mA
POR
Bandgap
Sleep PWR
mA
GND
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
To
+
4.0 V
Ref
2.0
mA
16.0
mA
–
SPI
Comparator
VPWR VPWR
SP7
16.0
mA
2.0
mA
5.0 V
VPWR
Oscillator
and
Clock Control
To
SPI
+
4.0 V
Ref
2.0
mA
16.0
mA
–
Comparator
5.0 V
Temperature
Monitor and
Control
5.0 V
VPWR
VPWR VPWR
SG0
5.0 V
125 kΩ
16.0
mA
2.0
mA
5.0 V
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
WAKE
To
+
4.0 V
Ref
–
SPI
WAKE Control
Comparator
VDD
125 kΩ
SPI Interface
and Control
INT
INT Control
VDD
MUX Interface
40 µA
CS
SCLK
SI
V
DD
SO
VPWR VPWR
SG13
16.0
mA
2.0
mA
VDD
Analog Mux
Output
+
–
AMUX
To
SPI
+
4.0 V
Ref
–
Comparator
Figure 1. 33972 Simplified Internal Block Diagram
33972
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GND
SI
SCLK
CS
SO
VDD
AMUX
INT
SP7
SP6
SP5
SP4
SG7
SG8
SG9
SG10
SG11
SG12
SG13
WAKE
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
3
4
SP0
SP1
SP2
SP3
SG0
SG1
SG2
SG3
SG4
SG5
SG6
VPWR
5
6
7
8
9
10
11
12
13
14
15
16
TERMINAL DEFINITIONS
A functional description of each terminal can be found in the System/Application Information section beginning on page 9.
Terminal
Terminal
Formal Name
Definition
Name
GND
SI
1
2
3
4
Ground
Ground for logic, analog, and switch to battery inputs.
SPI control data input terminal from MCU to 33972.
SPI control clock input terminal.
SPI Slave In
Serial Clock
Chip Select
SCLK
CS
SPI control chip select input terminal from MCU to 33972. Logic [0} allows data to be
transferred in.
5–8
25–28
SP0–3
SP4–7
Programmable Switches 0–7
Programmable switch-to-battery or switch-to-ground input terminals.
9–15,
18–24
SG0–6,
SG13–7
Switch-to-Ground Inputs 0–13 Switch-to-ground input terminals.
16
V
Battery Input
Battery supply input terminal. Terminal requires external reverse battery protection.
PWR
17
29
30
31
Wake-Up
Interrupt
Open drain wake-up output. Designed to control a power supply enable terminal.
Open-drain output to MCU. Used to indicate input switch change of state.
Analog multiplex output.
WAKE
INT
AMUX
Analog Multiplex Output
Voltage Drain Supply
V
3.3/5.0 V supply. Sets SPI communication level for SO driver.
DD
32
SO
SPI Slave Out
Provides digital data from 33972 to MCU.
33972
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
V
Supply Voltage
–
–
–
–
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 40
-0.3 to 50
V
V
V
V
V
DD
DC
DC
DC
DC
DC
CS, SI, SO, SCLK, INT, AMUX (Note 1)
WAKE (Note 1)
V
Supply Voltage (Note 1)
PWR
Switch Input Voltage Range
–
–
-14 to 40
6.0
Frequency of SPI Operation (VDD = 5.0 V)
MHz
V
ESD Voltage (Note 2)
VESD1
VESD2
±4000
±200
Human Body Model (Note 3), (Note 4)
Machine Model (Note 5)
THERMAL RATINGS
Operating Temperature
Ambient
°C
TA
TJ
-40 to 125
-40 to 150
-40 to 125
Junction
TC
Case
Storage Temperature
T
-55 to 150
1.7
°C
STG
PD
W
Power Dissipation (TA = 25°C) (Note 6)
Thermal Resistance
Junction to Ambient
Junction to Lead
°C/W
°C
R
74
25
JA
θ
R
JL
θ
Peak Package Reflow Temperature During Solder Mounting (Note 7)
TSOLDER
DWB Suffix
EW Suffix
240
245
Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. ESD data available upon request.
3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
4. All terminals when tested individually.
5. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
6. Maximum power dissipation at TJ = 150°C junction temperature with no heat sink used.
7. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions of 3.1 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Supply Voltage
V
Supply Voltage Range Quasi-Functional (Note 8)
Fully Operational
V
5.5
8.0
26
–
–
–
8.0
26
40
PWR(QF)
PWR(FO)
V
V
Supply Voltage Range Quasi-Functional (Note 8)
(
)
PWR QF
Supply Current
I
mA
PWR(ON)
All Switches Open, Normal Mode, Tri-State Disabled
–
2.0
4.0
Sleep State Supply Current
I
µA
PWR(SS)
Scan Timer = 64 ms, Switches Open
40
70
–
100
Logic Supply Voltage
V
3.1
5.25
V
DD
Logic Supply Current
I
mA
DD
All Switches Open, Normal Mode
–
–
0.25
10
0.5
20
Sleep State Logic Supply Current
Scan Timer = 64 ms, Switches Open
I
µA
DD(SS)
SWITCH INPUT
Pulse Wetting Current Switch-to-Battery (Current Sink)
I
I
12
12
15
16
18
18
mA
mA
mA
mA
%
PULSE
PULSE
Pulse Wetting Current Switch-to-Ground (Current Source)
Sustain Current Switch-to-Battery Input (Current Sink)
I
1.8
1.8
2.0
2.0
2.2
2.2
SUSTAIN
I
SUSTAIN
Sustain Current Switch-to-Ground Input (Current Source)
Sustain Current Matching Between Channels on Switch-to-Ground Inputs
I
MATCH
ISUS(MAX)
I
SUS(MIN)
-
–
2.0
1.4
4.0
2.0
X 100
ISUS(MIN)
Input Offset Current When Selected as Analog
Input Offset Voltage When Selected as Analog
I
-2.0
µA
OFFSET
V
mV
OFFSET
V
(SP&SGinputs) to AMUX Output
-10
–
2.5
10
10
30
Analog Operational Amplifier Output Voltage
V
mV
V
OL
Sink 250 µA
Analog Operational Amplifier Output Voltage
V
OH
Source 250 µA
V
- 0.1
–
4.0
–
–
DD
Switch Detection Threshold
V
3.70
-14
4.3
40
V
V
TH
Switch Input Voltage Range
V
IN
Temperature Monitor (Note 9), (Note 10)
Temperature Monitor Hysteresis (Note 10)
T
155
5.0
–
185
15
°C
°C
LIM
LIM(HYS)
T
10
Notes
8. Device operational. Table parameters may be out of specification.
9. Thermal shutdown of 16 mA pullup and pulldown current sources only. 2.0 mA current source/sink and all other functions remain active.
10. This parameter is guaranteed by design but is not production tested.
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions of 3.1 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE
Input Logic Voltage Thresholds (Note 11)
V
0.8
-10
–
–
2.2
10
V
INLOGIC
SCLK, SI, Tri-State SO Input Current
I
I
µA
SCLK, SI,
I
0 V to V
DD
SO(TRI)
µA
CS Input Current
I
I
CS
CS
-10
30
–
10
CS = V
DD
µA
V
CS Pullup Current
CS = 0 V
–
–
–
100
SO High-State Output Voltage
V
SO(HIGH)
I
= -200 µA
V
- 0.8
V
DD
SO(HIGH)
DD
SO Low-State Output Voltage
= 1.6 mA
V
V
SO(LOW)
I
–
0.4
SO(HIGH)
Input Capacitance on SCLK, SI, Tri-State SO (Note 12)
INT Internal Pullup Current
C
–
–
20
pF
µA
V
IN
–
15
40
100
INT Voltage
V
V
INT(HIGH)
V
- 0.5
–
V
INT = Open Circuit
DD
DD
V
INT Voltage
INT(LOW)
–
0.2
40
0.4
I
= 1.0 mA
INT
20
100
µA
WAKE Internal Pullup Current
I
WAKE(PU)
V
WAKE Voltage
V
WAKE(HIGH)
4.0
–
4.3
0.2
5.3
0.4
WAKE = Open Circuit
V
V
WAKE Voltage
V
V
WAKE(LOW)
WAKE(MAX)
I
WAKE = 1.0 mA
WAKE Voltage
–
–
40
Maximum Voltage Applied to WAKE Through External Pullup
Notes
11. Upper and lower logic threshold voltage levels apply to SI, CS, and SCLK.
12. This parameter is guaranteed by design but is not production tested.
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions of 3.1 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
SWITCH INPUT
Pulse Wetting Current Time
t
15
16
20
ms
PULSE(ON)
Interrupt Delay Time
Normal Mode
t
µs
INT-DLY
–
5.0
16
Sleep Mode Switch Scan Time
t
100
200
300
µs
SCAN
Calibrated Scan Timer Accuracy
Sleep Mode
t
%
SCAN TIMER
–
–
–
–
10
10
Calibrated Interrupt Timer Accuracy
Sleep Mode
t
%
INT TIMER
DIGITAL INTERFACE TIMING (Note 13)
Required Low-State Duration on VPWR for Reset (Note 14)
t
µs
RESET
–
–
–
10
–
VPWR ≤ 0.2 V
t
ns
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
LEAD
100
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
t
ns
ns
ns
LAG
50
16
–
–
–
–
SI to Falling Edge of SCLK
Required Setup Time
t
SI(SU)
Falling Edge of SCLK to SI
Required Hold Time
t
SI(HOLD)
20
–
–
5.0
5.0
–
–
–
SI, CS, SCLK Signal Rise Time (Note 15)
SI, CS, SCLK Signal Fall Time (Note 15)
t
t
ns
ns
ns
ns
ns
R(SI)
F(SI)
–
–
Time from Falling Edge of CS to SO Low Impedance (Note 16)
Time from Rising Edge of CS to SO High Impedance (Note 17)
Time from Rising Edge of SCLK to SO Data Valid (Note 18)
Notes
t
–
55
55
55
SO(EN)
t
–
–
SO(DIS)
t
–
25
VALID
13. These parameters are guaranteed by design. Production test equipment uses 4.16 MHz, 5.0 V SPI interface.
14. This parameter is guaranteed by design but not production tested.
15. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
16. Time required for valid output status data to be available on SO terminal.
17. Time required for output states data to be terminated at SO terminal.
18. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
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Timing Diagrams
CS
0.2 V
DD
t
t
LAG
LEAD
0.7 V
0.2 V
DD
SCLK
DD
t
t
SI(HOLD)
SI(SU)
0.7 V
0.2 V
DD
SI
MSB in
DD
t
t
VALID
SO(EN)
t
SO(DIS)
0.7 V
0.2 V
DD
SO
MSB out
LSB out
DD
Figure 2. SPI Timing Characteristics
V
V
PWR
DD
WAKE
INT
Wake-Up From Interrupt
Timer Expire
CS
Wake-Up From
Closed Switch
SGn
Power-Up
Normal Mode
Tri-State
Command
(Disable
Sleep
Command
Sleep Mode
Normal
Mode
Sleep Command
Normal
Mode
Sleep Command
Sleep Mode
Tri-State)
Figure 3. Sleep Mode to Normal Mode Operation
Switch state change with
CS LOW generates INT
Switch state change with
CS LOW generates INT
INT
CS
Latch switch status
on falling edge of CS
Rising edge of CS does not
clear INT because state change
occurred while CS was LOW
SGn
Switch open “0”
Switch closed “1”
1
1
0
0
1
0
SGn Bit in SPI Word
Switch
Status
Command
Switch
Status
Command
Switch
Status
Command
Switch
Status
Command
Switch
Status
Command
Switch
Status
Command
Figure 4. Normal Mode Interrupt Operation
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33972 device is an integrated circuit designed to provide
systems with ultra-low quiescent sleep/wake-up modes and a
robust interface between switch contacts and a
microprocessor. The 33972 replaces many of the discrete
components required when interfacing to microprocessor-
based systems while providing switch ground offset protection,
contact wetting current, and system wake-up.
switch inputs may be read as analog inputs through the analog
multiplexer (AMUX). Other features include a programmable
wake-up timer, programmable interrupt timer, programmable
wake-up/interrupt bits, and programmable wetting current
settings.
This device is designed primarily for automotive applications
but may be used in a variety of other applications such as
computer, telecommunications, and industrial controls.
The 33972 features 8-programmable switch-to-ground or
switch-to-battery inputs and 14 switch-to-ground inputs. All
FUNCTIONAL TERMINAL DESCRIPTION
SI
CS
The system MCU selects the 33972 to receive
The SI terminal is used for serial instruction data input. SI
communication using the chip select (CS) terminal. With the CS
in a logic LOW state, command words may be sent to the 33972
via the serial input (SI) terminal, and switch status information
can be received by the MCU via the serial output (SO) terminal.
The falling edge of CS enables the SO output, latches the state
of the INT terminal, and the state of the external switch inputs.
information is latched into the input register on the falling edge
of SCLK. A logic HIGH state present on SI will program a one
in the command word on the rising edge of the CS signal. To
program a complete word, 24 bits of information must be
entered into the device.
SO
Rising edge of the CS initiates the following operation:
1. Disables the SO driver (high impedance)
The SO terminal is the output from the shift register. The SO
terminal remains tri-stated until the CS terminal transitions to a
logic LOW state. All open switches are reported as zero, all
closed switches are reported as one. The negative transition of
CS enables the SO driver.
2. INT terminal is reset to logic [1], except when additional
switch changes occur during CS LOW. (See Figure 4 on
page 8.)
3. Activates the received command word, allowing the
33972 to act upon new data from switch inputs.
The first positive transition of SCLK will make the status data
bit 24 available on the SO terminal. Each successive positive
clock will make the next status data bit available for the MCU to
read on the falling edge of SCLK. The SI/SO shifting of the data
follows a first-in, first-out protocol, with both input and output
words transferring the most significant bit (MSB) first.
To avoid any spurious data, it is essential the HIGH-to-LOW
and LOW-to-HIGH transitions of the CS signal occur only when
SCLK is in a logic LOW state. Internal to the 33972 device is an
active pullup to VDD on CS.
In Sleep mode the negative edge of CS (VDD applied) will
INT
wake up the 33972 device. Data received from the device
during CS wake-up may not be accurate.
The INT terminal is an interrupt output from the 33972
device. The INT terminal is an open-drain output with an internal
pullup to VDD. In Normal mode, a switch state change will trigger
SCLK
the INT terminal (when enabled). The INT terminal and INT bit
in the SPI register are latched on the falling edge of CS. This
permits the MCU to determine the origin of the interrupt. When
two 33972 devices are used, only the device initiating the
interrupt will have the INT bit set. The INT terminal is cleared on
the rising edge of CS. The INT terminal will not clear with rising
edge of CS if a switch contact change has occurred while CS
was LOW.
The system clock (SCLK) terminal clocks the internal shift
register of the 33972. The SI data is latched into the input shift
register on the falling edge of SCLK signal. The SO terminal
shifts the switch status bits out on the rising edge of SCLK. The
SO data is available for the MCU to read on the falling edge of
SCLK. False clocking of the shift register must be avoided to
ensure validity of data. It is essential the SCLK terminal be in a
logic LOW state whenever CS makes any transition. For this
reason, it is recommended, though not necessary, that the
SCLK terminal is commanded to a logic LOW state as long as
the device is not accessed and CS is in a logic HIGH state.
When the CS is in a logic HIGH state, any signal on the SCLK
and SI terminals will be ignored and the SO terminal is tri-state.
In a multiple 33972 device system with WAKE HIGH and VDD
on (Sleep mode), the falling edge of INT will place all 33972s in
Normal mode.
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WAKE
GND
The WAKE terminal is an open-drain output and a wake-up
The GND terminal provides ground for the IC as well as
ground for inputs programmed as switch-to-battery inputs.
input. The terminal is designed to control a power supply
Enable terminal. In the Normal mode, the WAKE terminal is
LOW. In the Sleep mode, the WAKE terminal is HIGH. The
WAKE terminal has a pullup to the internal +5.0 V supply.
SP0:SP7
The 33972 device has 8 switch inputs capable of being
programmed to read switch-to-ground or switch-to-battery
contacts. The input is compared with a 4.0 V reference. When
programmed to be switch-to-battery, voltages greater than
4.0 V are considered closed. Voltages less than 4.0 V are
considered open. The opposite holds true when inputs are
programmed as switch-to-ground. Programming features are
defined in Table 1 through Table 6 in the Device Operation
section of this datasheet beginning on page 12. Voltages
greater than the VPWR supply voltage will source current
In Sleep mode with the WAKE terminal HIGH, falling edge of
WAKE will place the 33972 in Normal mode. In Sleep mode with
VDD applied, the INT terminal must be HIGH for negative edge
of WAKE to wake up the device. If VDD is not applied to the
device in Sleep mode, INT does not affect WAKE operation.
V
PWR
The VPWR terminal is battery input and Power-ON Reset to
the 33972 IC. The VPWR terminal requires external reverse
battery and transient protection. Maximum input voltage on
VPWR is 50 V. All wetting, sustain, and internal logic current is
provided from the VPWR terminal.
through the SP inputs to the VPWR terminal. Transient battery
voltages greater than 40 V must be clamped by an external
device.
SG0:SG13
V
DD
The SGn terminals are switch-to-ground inputs only. The
input is compared with a 4.0 V reference. Voltages greater than
4.0 V are considered open. Voltages less than 4.0 V are
considered closed. Programming features are defined in
Table 1 through Table 6 in the Device Operation section of this
datasheet beginning on page 12. Voltages greater than the
The VDD input terminal is used to determine logic levels on
the microprocessor interface (SPI) terminals. Current from VDD
is used to drive SO output and the pullup current for CS and INT
terminals. VDD must be applied for wake-up from negative edge
of CS or INT.
VPWR supply voltage will source current through the SG inputs
to the VPWR terminal. Transient battery voltages greater than
40 V must be clamped by an external device.
33972
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MCU INTERFACE DESCRIPTION
The 33972 device directly interfaces to a 3.3 V or 5.0 V
MC68HCXX
microcontroller unit (MCU). SPI serial clock frequencies up to
6.0 MHz may be used for programming and reading switch
input status (production tested at 4.16 MHz). Figure 5 illustrates
the configuration between an MCU and one 33972.
Microcontroller
33972
MOSI
SI
Shift Register
MISO
SCLK
SO
Serial peripheral interface (SPI) data is sent to the 33972
device through the SI input terminal. As data is being clocked
into the SI terminal, status information is being clocked out of
the device by the SO output terminal. The response to a SPI
command will always return the switch status, interrupt flag, and
thermal flag. Input switch states are latched into the SO register
on the falling edge of the chip select (CS) terminal. Twenty-four
bits are required to complete a transfer of information between
the 33972 and the MCU.
SCLK
CS
Parallel
Ports
INT
INT
33972
SI
SO
MC68HCXX
33972
SCLK
Microcontroller
CS
MOSI
MISO
SI
INT
Shift Register
24-Bit Shift Register
SO
Figure 6. SPI Parallel Interface with Microprocessor
SCLK
INT
Receive
Buffer
To Logic
MC68HCXX
Microcontroller
33972
CS
Parallel
Ports
MOSI
INT
SI
Shift Register
MISO
SO
Figure 5. SPI Interface with Microprocessor
SCLK
SCLK
Parallel
Ports
CS
Two or more 33972 devices may be used in a module
system. Multiple ICs may be SPI-configured in parallel or serial.
Figures 6 and 7 show the configurations. When using the serial
configuration, 48-clock cycles are required to transfer data in/
out of the ICs.
INT
INT
33972
SI
SO
SCLK
CS
INT
Figure 7. SPI Serial Interface with Microprocessor
33972
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DEVICE OPERATION
Normal Mode
Power Supply
Normal mode may be entered by the following events:
The 33972 is designed to operate from 5.5 V to 40 V on the
VPWR terminal. Characteristics are provided from 8.0 V to 16 V
for the device. Switch contact currents and the internal logic
supply are generated from the VPWR terminal. The VDD supply
• Application of VPWR to the IC
• Change-of-Switch State (when enabled)
• Falling Edge of WAKE
• Falling Edge of INT (with VDD = 5.0 V and WAKE at
Logic [1])
terminal is used to set the SPI communication voltage levels,
current source for the SO driver, and pullup current on INT and
CS.
• Falling Edge of CS (with VDD = 5.0 V)
VDD supply may be removed from the device to reduce
quiescent current. If VDD is removed while the device is in
Normal mode, the device will remain in Normal mode. If VDD is
• Interrupt Timer Expires
Only in Normal mode with VDD applied can the registers of the
33972 be programmed through the SPI.
removed in Sleep mode, the device will remain in Sleep mode
until wake-up input is received (WAKE HIGH to LOW, switch
input or interrupt timer expires).
The registers that may be programmed in Normal mode are
listed below. Further explanation of each register is provided in
subsequent paragraphs.
Removing VDD from the device disables SPI communication
and will not allow the device to wake up from INT and CS
terminals.
• Programmable Switch Register (Settings Command)
• Wake-Up/Interrupt Register (Wake-Up/Interrupt
Command)
Power-ON Reset (POR)
• Wetting Current Register (Metallic Command)
• Wetting Current Timer Register (Wetting Current Timer
Enable Command)
• Tri-State Register (Tri-State Command)
• Analog Select Register (Analog Command)
• Calibration of Timers (Calibration Command)
• Reset (Reset Command)
Applying VPWR to the device will cause a Power-ON Reset
and place the device in Normal mode.
Default settings from Power-ON Reset via VPWR or Reset
Command are as follows:
• Programmable Switch – Set to Switch to Battery
• All Inputs Set as Wake-Up
• Wetting Current On (16 mA)
• Wetting Current Timer On (20 ms)
• All Inputs Tri-State
• Analog Select 00000 (No Input Channel Selected)
Figure 4, page 8, is a graphical description of the device
operation in Normal mode. Switch states are latched into the
input register on the falling edge of CS. The INT to the MCU is
cleared on the rising edge of CS. However, INT will not clear on
rising edge of CS if a switch has closed during SPI
communication (CS LOW). This prevents switch states from
being missed by the MCU.
Modes of Operation
The 33972 has two operating modes, Normal mode and
Sleep mode. A discussion on Normal mode begins below.
A discussion on Sleep mode begins on page 18.
Programmable Switch Register
Inputs SP0 to SP7 may be programmable for switch-to-
battery or switch-to-ground. These inputs types are defined
using the settings command (Table 1). To set an SPn input for
switch-to-battery, a logic [1] for the appropriate bit must be set.
To set an SPn input for switch-to-ground, a logic [0] for the
appropriate bit must be set. The MCU may change or update
the Programmable Switch Register via software at any time in
Normal mode. Regardless of the setting, when the SPn input
switch is closed a logic [1] will be placed in the Serial Output
Response Register (Table 12, page 17).
Table 1. Settings Command
Settings Command
Not used
Battery/Ground Select
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
1
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
33972
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Wake-Up/Interrupt Register
The Wake-Up/Interrupt Register defines the inputs that are
allowed to wake the 33972 from Sleep mode or set the INT
terminal LOW in Normal mode. Programming the wake-up/
interrupt bit to logic [0] will disable the specific input from
generating an interrupt and will disable the specific input from
waking the IC in Sleep mode (Table 2). Programming the wake-
up/interrupt bit to logic [1] will enable the specific input to
generate an interrupt with switch change of state and will enable
the specific input as wake-up. The MCU may change or update
the Wake-Up/Interrupt Register via software at any time in
Normal mode.
Table 2. Wake-Up /Interrupt Command
Wake-Up/Interrupt Command
Command Bits
23 22 21 20 19 18 17 16
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
X
X
sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
Wetting Current Register
The 33972 has two levels of switch contact current, 16 mA
and 2.0 mA (see Figure 8). The metallic command is used to set
the switch contact current level (Table 3). Programming the
metallic bit to logic [0] will set the switch wetting current to
2.0 mA. Programming the metallic bit to logic [1] will set the
switch contact wetting current to 16 mA. The MCU may change
or update the Wetting Current Register via software at any time
in Normal mode.
Switch Contact Voltage
Wetting current is designed to provide higher levels of current
during switch closure. The higher level of current is designed to
keep switch contacts from building up oxides that form on the
switch contact surface.
16 mA Switch Wetting Current
2.0 mA Switch Sustain Current
20 ms Wetting Current Timer
Figure 8. Contact Wetting and Sustain Current
Table 3. Metallic Command
Metallic Command
Command Bits
23 22 21 20 19 18 17 16 15
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
X
X
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
X
sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
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Wetting Current Timer Register
Each switch input has a designated 20 ms timer. The timer
starts when the specific switch input crosses the comparator
threshold (4.0 V). When the 20 ms timer expires, the contact
current is reduced from 16 mA to 2.0 mA. The wetting current
timer may be disabled for a specific input. When the timer is
disabled, 16 mA of current will continue to flow through the
closed switch contact. With multiple wetting current timers
disabled, power dissipation for the IC must be considered.
The MCU may change or update the Wetting Current Timer
Register via software at any time in Normal mode. This allows
the MCU to control the amount of time wetting current is applied
to the switch contact. Programming the wetting current timer bit
to logic [0] will disable the wetting current timer. Programming
the wetting current timer bit to logic [1] will enable the wetting
current timer (Table 4).
Table 4. Wetting Current Timer Enable Command
Wetting Current Timer Commands
Command Bits
23 22 21 20 19 18 17 16
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
X
X
sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
Tri-State Register
The tri-state command is use to set the SPn or SGn input
node as high impedance (Table 5). By setting the Tri-State
Register bit to logic [1], the input will be high impedance
regardless of the metallic command setting. The comparator on
each input remains active. This command allows the use of
each input as a comparator with a 4.0 V threshold. The MCU
may change or update the Tri-State Register via software at any
time in Normal mode.
Table 5. Tri-State Command
Tri-State Commands
Command Bits
23 22 21 20 19 18 17 16
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
X
X
sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
33972
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Analog Select Register
The analog voltage on switch inputs may be read by the
MCU using the analog command (Table 6). Internal to the IC is
a 22-to-1 analog multiplexer. The voltage present on the
selected input terminal is buffered and made available on the
AMUX output terminal. The AMUX output terminal is clamped
to a maximum of VDD volts regardless of the higher voltages
present on the input terminal. After an input has been selected
as the analog, the corresponding bit in the next SO data stream
will be logic [0]. When selecting a channel to be read as analog,
the user must also set the desired current (16 mA, 2.0 mA, or
high impedance). Setting bit 6 and bit 5 to 0,0 selects the input
as high impedance. Setting bit 6 and bit 5 to 0,1 selects 2.0 mA,
and 1,0 selects 16 mA. Setting bit 6 and bit 5 to 1,1 in the
Analog Select Register is not allowed and will place the input as
an analog input with high impedance.
Analog currents set by the analog command are pullup
currents for all SGn and SPn inputs (Table 6). The analog
command does not allow pulldown currents on the SPn inputs.
Setting the current to 16 mA or 2.0 mA may be useful for
reading sensor inputs. Further information is provided in the
Applications section of this datasheet beginning on page 20.
The MCU may change or update the Analog Select Register via
software at any time in Normal mode.
Table 6. Analog Command
Analog Command
Not used
Current Select Analog Channel Select
23
0
22
0
21
0
20
0
19
0
18
1
17
1
16
0
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
0
3
0
2
0
1
0
0
0
X
X
X
16 mA 2.0mA
Table 7. Analog Channel
Bits 43210
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
Analog Channel Select
No Input Selected
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
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Calibration of Timers
In cases where an accurate time base is required, the user
may calibrate the internal timers using the calibration command
(Table 8). After the 33972 device receives the calibration
command, the device expects 512 µs logic [0] calibration pulse
on the CS terminal. The pulse is used to calibrate the internal
clock. No other SPI terminals should transition during this
512 µs calibration pulse. Because the oscillator frequency
changes with temperature, calibration is required for an
accurate time base. Calibrating the timers has no affect on the
quiescent current measurement. The calibration command
simply makes the time base more accurate. The calibration
command may be used to update the device on a periodic
basis.
Table 8. Calibration Command
Calibration Command
Command Bits
23
0
22
0
21
0
20
0
19
1
18
0
17
1
16
1
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
Reset
The reset command resets all registers to Power-ON Reset
(POR) state. Refer to Table 10, page 17, for POR states or the
paragraph entitled Power-ON Reset (POR) on page 12 of this
datasheet.
Table 9. Reset Command
Reset Command
Command Bits
23
0
22
1
21
1
20
1
19
1
18
1
17
1
16
1
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
33972
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SPI Command Summary
Table 10 below provides a comprehensive list of SPI
commands recognized by the 33972 and the reset state of each
register. Table 11 and Table 12 contain the Serial Output (SO)
data for input voltages greater or less than the threshold level.
Open switches are always indicated with a logic [0], closed
switches are indicated with logic [1].
Table 10. SPI Command Summary
MSB
Command Bits
Setting Bits
LSBI
23
22
0
21
0
20
19
18
17
0
16
0
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
Switch Status
Command
0
0
0
0
X
X
X
X
X
X
X
X
X
X
Settings Command
Bat=1, Gnd=0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
(Default state = 1)
Wake-Up/Interrupt Bit
Wake-Up=1
Non-Wake-Up=0
(Default state = 1)
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
X
X
X
X
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Metallic Command
Metallic = 1
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Non-metallic = 0
(Default state = 1)
0
0
0
0
0
1
0
1
X
X
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
16mA 2.0mA
Analog Command
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
Wetting Current Timer
Enable Command
Timer ON = 1
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
0
0
0
0
1
0
0
0
X
X
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Timer OFF = 0
(Default state = 1)
Tri-State Command
Input Tri-State=1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Input Active = 0
(Default state = 1)
Calibration Command
0
0
0
0
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(Default state –
uncalibrated)
Sleep Command
int
int
int
scan scan scan
0
0
0
1
0
1
0
1
1
1
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(Refer to Sleep Mode
on page 18.)
timer timer timer timer timer timer
Reset Command
X
X
X
X
X
X
them
flg
int
flg
SO Response Will
Always Send
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Table 11. Serial Output (SO) Bit Data
Input
Programmed
Voltage on
Input Terminal
Type of Input
SO SPI Bit
Switch to Ground
Switch to Ground
Switch to Battery
Switch to Battery
N/A
SPn < 4.0 V
SPn > 4.0 V
SPn < 4.0 V
SPn > 4.0 V
SGn < 4.0 V
SGn > 4.0 V
1
0
0
1
1
0
SP
SG
N/A
Table 12. Serial Output (SO) Response Register
them
flg
int
flg
SO Response Will
Always Send
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
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Example of Normal Mode Operation
Sleep Mode
Sleep mode is used to reduce system quiescent currents.
Sleep mode may be entered only by sending the sleep
command. All register settings programmed in Normal mode
will be maintained in Sleep mode.
The operation of the device in Normal Mode is defined by the
states of the programmable internal control registers. A typical
application may have the following settings:
• Programmable Switch – Set to Switch-to-Ground
• All Inputs Set as Wake-Up
• Wetting Current On (16 mA)
The 33972 will exit Sleep mode and enter Normal mode
when any of the following events occur:
• Wetting Current Timer On (20 ms)
• All inputs Tri-State-Disabled (comparator is active)
• Analog select 00000 (no input channel selected)
• Input Switch Change of State (when enabled)
• Interrupt Timer Expire
• Falling Edge of WAKE
• Falling Edge of INT (with VDD = 5.0 V and WAKE at
Logic [1])
• Falling Edge of CS (with VDD = 5.0 V)
With the device programmed as above, an interrupt will be
generated with each switch contact change of state (open-to-
close or close-to-open) and 16 mA of contact wetting current
will be source for 20 ms. The INT terminal will remain LOW until
switch status is acknowledged by the microprocessor. It is
critical to understand INT will not be cleared on the rising edge
of CS if a switch closure occurs while CS is LOW. The maximum
duration a switch state change can exist without
• Power-ON Reset (POR)
The VDD supply may be removed from the device during
Sleep mode. However removing VDD from the device in Sleep
mode will disable a wake-up from falling edge of INT and CS.
acknowledgement depends on the software response time to
the interrupt. Figure 4, page 8, shows the interaction between
changing input states and the INT and CS terminals.
Note In cases where CS is used to wake the device, the first
SO data message is not valid.
If desired the user may disable interrupts (wake up/interrupt
command) from the 33972 device and read the switch states on
a periodic basis. Switch activation and deactivation faster than
the MCU read rate will not be acknowledged.
The sleep command contains settings for two programmable
timers for Sleep mode, the interrupt timer and the scan timer, as
shown in Table 13 The interrupt timer is used as a periodic
wake-up timer. When the timer expires, an interrupt is
generated and the device enters Normal mode.
The 33972 device will exit the Normal mode and enter the
Sleep mode only with a valid sleep command.
Note The interrupt timer in the 33972 device may be
disabled by programming the interrupt bits to logic [1 1 1].
Table 14 shows the programmable settings of the Interrupt
timer.
Table 13. Sleep Command
Sleep Command
Command Bits
23
0
22
0
21
0
20
0
19
1
18
1
17
0
16
0
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
X
X
Table 14. Interrupt Timer
Bits 543
Interrupt Period
32 ms
000
001
010
011
100
101
110
111
64 ms
128 ms
256 ms
512 ms
1.024 s
2.048 s
No interrupt wake-up
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The scan timer sets the polling period between input switch
quiescent current is calculated by integrating the normal
reads in Sleep mode. The period is set in the sleep command
and may be set to 000 (no period) to 111 (64 ms). In Sleep
mode when the scan timer expires, inputs will behave as
programmed prior to sleep command. The 33972 will wake up
for approximately 125 µs and read the switch inputs. At the end
of the 125 µs, the input switch states are compared with the
switch state prior to sleep command. When switch state
changes are detected, an interrupt (when enabled; refer to
wake-up/interrupt command description on page 13) is
generated and the device enters Normal mode. Without switch
state changes, the 33972 will reset the scan timer, inputs
become tri-state, and the Sleep mode continues until the scan
timer expires again.
running current over scan period plus approximately 60 µA.
I=V/R or 0.270 V/100 Ω=2.7 mA
Table 15 shows the programmable settings of the Scan
timer.
Inputs active for
A
6.0 mV/100 Ω=60 µA
I=V/R or
125 µs out of 32 ms
Table 15. Scan Timer
Bits 210
000
Scan Period
No Scan
1.0 ms
Figure 9. Sleep Current Waveform
Temperature Monitor
001
010
2.0 ms
With multiple switch inputs closed and the device
programmed with the wetting current timers disabled,
considerable power will be dissipated by the IC. For this reason
temperature monitoring has been implemented. The
temperature monitor is active in the Normal mode only. When
the IC temperature is above the thermal limit, the temperature
monitor will do all of the following:
011
4.0 ms
100
8.0 ms
101
16 ms
110
32 ms
111
64 ms
• Generate an interrupt.
• Force all 16 mA pullup and pulldown current sources to
revert to 2.0 mA current sources.
• Maintain the 2.0 mA current source and all other
functionality.
Note The interrupt and scan timers are disabled in the
Normal mode.
Figure 3, page 8, is a graphical description of how the 33972
device exits Sleep mode and enters Normal mode. Notice that
the device will exit Sleep mode when the interrupt timer expires
or when a switch change of state occurs. The falling edge of INT
triggers the MCU to wake from Sleep state. Figure 9 illustrates
the current consumed during Sleep mode. During the 125 µs,
the device is fully active and switch states are read. The
• Set the thermal flag bit in the SPI output register.
The thermal flag bit in the SPI word will be cleared on rising
edge of CS provided the die temperature has cooled below the
thermal limit. When die temperature has cooled below thermal
limit, the device will resume previously programmed settings.
33972
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APPLICATIONS
Introduction
Metallic/Elastomeric Switch
The 33972’s primary function is the detection of open or
closed switch contacts. However, there are many features that
allow the device to be used in a variety of applications. The
following is a list of applications to consider for the IC:
Metallic switch contacts often develop higher contact
resistance over time owing to contact corrosion. The corrosion
is induced by humidity, salt, and other elements that exist in the
environment. For this reason the 33972 provides two settings
for contacts. When programmed for metallic switches, the
device provides higher wetting current to keep switch contacts
free of oxides. The higher current occurs for the first 20 ms of
switch closure. Where longer duration of wetting current is
desired, the user may send the wetting current timer command
and disable the timer. Wetting current will be continuous to the
closed switch. After the time period set by the MCU, the wetting
current timer command may be sent again to enable the timer.
The user must consider power dissipation on the device when
disabling the timer. (Refer to the paragraph entitled
• Sensor Power Supply
• Switch Monitor for Metallic or Elastomeric Switches
• Analog Sensor Inputs (Ratiometric)
• Power MOSFET/LED Driver and Monitor
• Multiple 33972 Devices in a Module System
The following paragraphs describe the applications in detail.
Sensor Power Supply
Temperature Monitor, page 19.)
Each input may be used to supply current to sensors external
to a module. Many sensors such as Hall effect, pressure
sensors, and temperature sensors require a supply voltage to
power the sensor and provide an open collector or analog
output. Figure 10 shows how the 33972 may be used to supply
power and interface to these types of sensors. In an application
where the input makes continuous transitions, consider using
the wake-up/interrupt command to disable the interrupt for the
particular input.
To increase the amount of wetting current for a switch
contact, the user has two options. Higher wetting current to a
switch may be achieved by paralleling SGn or SPn inputs. This
will increase wetting current by 16 mA for each input added to
the switch contact. The second option is to simply add an
external resistor pullup to the VPWR supply for switch-to-ground
inputs or a resistor to ground for a switch-to-battery input.
Adding an external resistor has no effect on the operation of the
device.
33972
Elastomeric switch contacts are made of carbon and have a
high contact resistance. Resistance of 1.0 kΩ is common. In
applications with elastomeric switches, the pullup and pulldown
currents must be reduced to prevent excessive power
dissipation at the contact. Programming for a lower current
settings is provided in the Device Operation Section beginning
on page 12 under Table 3, Metallic Command.
VBAT
SP0
VPWR
SP1
V
DD
MCU
VDD
VBAT
SP7
WAKE
SI
MOSI
SCLK
CS
SG0
SG1
SCLK
CS
Analog Sensor Inputs (Ratiometric)
V
V
PWR PWR
The 33972 features a 22-to-1 analog multiplexer. Setting the
binary code for a specific input in the analog command allows
the microcontroller to perform analog to digital conversion on
any of the 22 inputs. On rising edge of CS the multiplexer
connects a requested input to the AMUX terminal. The AMUX
terminal is clamped to max of VDD volts regardless of the higher
SO
MISO
INT
16
mA
2.0
mA
INT
16 mA
SG12
SG13
V
V
PWR PWR
Hall-Effect
Sensor
16
mA
2.0
mA
voltages present on the input terminal. After an input has been
selected as the analog, the corresponding bit in the next SO
data stream will be logic [0].
Reg
X
2.5 kΩ
IOC[7:0]
Input Capture
Timer Port
The input terminal, when selected as analog, may be
configured as analog with high impedance, analog with 2.0 mA
pullup, or analog with 16 mA pullup. Figure 11, page 21, shows
how the 33972 may be used to provide a ratiometric reading of
variable resistive input.
2.5 kΩ
Figure 10. Sensor Power Supply
33972
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conversion may be obtained. Using the equation yields the
following:
33972
VBAT
VBAT
SP0
SP1
VPWR
I1 x R1
I2 x R2
VDD
ADC =
x 225
MCU
VDD
2.0 mA x 2.0 kΩ
2.0 mA x 2.39 kΩ
ADC =
x 225
SP7
WAKE
SI
MOSI
SCLK
CS
ADC = 213 counts
SG0
SG1
SCLK
CS
V
V
PWR PWR
MISO
INT
SO
16
mA
2.0
mA
The ADC value of 213 counts is the value with 0% error
(neglecting the resistor tolerance and AMUX input offset
voltage). Now we can calculate the count value induced by the
mismatch in current sources. From a sample device the
maximum current source was measured at 2.05 mA and
minimum current source was measured at 1.99 mA. This yields
3% error in A/D conversion. The A/D measurement will be as
follows:
I1
INT
2.0 mA
SG12
AMUX
AN0
V
V
R
PWR PWR
1
Analog
Ports
16
mA
2.0
mA
Analog Sensor
or Analog Switch
SG13
I
2.02mA
1.99 mA x 2.0 kΩ
4.54 V to 5.02 V
ADC =
x 225
2.05 mA x 2.39 kΩ
V
REF(H)
REF(L)
2.39 kΩ
R
2
0.1%
ADC = 207 counts
V
This A/D conversion is 3% low in value. The error correction
factor of 1.03 may be used to correct the value:
Figure 11. Analog Ratiometric Conversion
ADC = 207 counts x 1.03
ADC = 213 counts
To read a potentiometer sensor, the wiper should be
grounded and brought back to the module ground, as illustrated
in Figure 11. With the wiper changing the impedance of the
-
An error correction factor may then be stored in E2 memory
and used in the A/D calculation for the specific input. Each input
used as analog measurement will have a dedicated calibrated
error correction factor.
sensor, the analog voltage on the input will represent the
position of the sensor.
Using the Analog feature to provide 2.0 mA of pullup current
to an analog sensor may induce error due to the accuracy of the
current source. For this reason, a ratiometric conversion must
be considered. Using two current sources (one for the sensor
and one to set the reference voltage to the A/D converter) will
yield a maximum error (owing to the 33972) of 4%.
Higher accuracy may be achieved through module level
calibration. In this example, we use the resistor values from
Figure 11 and assume the current sources are 4% from each
other. The user may use the module end-of-line tester to
calculate the error in the A/D conversion. By placing a 2.0 kΩ,
0.1% resistor in the end-of-line test equipment and assuming a
perfect 2.0 mA current source from the 33972, a calculated A/D
Power MOSFET/LED Driver and Monitor
Because of the flexible programming of the 33972 device, it
may be used to drive small loads like LEDs or MOSFET gates.
It was specifically designed to power up in the Normal mode
with the inputs tri-state. This was done to ensure the LEDs or
MOSFETs connected to the 33972 power up in the off-state.
The Switch Programmable (SP0–SP7) inputs have a source-
and-sink capability, providing effective MOSFET gate control.
To complete the circuit, a pulldown resistor should be used to
keep the gate from floating during the Sleep modes. Figure 12,
page 22, shows an application where the SG0 input is used to
monitor the drain-to-source voltage of the external MOSFET.
The 1.5 kΩ resistor is used to set the drain-to-source trip
voltage. With the 2.0 mA current source enabled, an interrupt
will be generated when the drain-to-source voltage is
approximately 1.0 V.
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pulled down to ground through an external resistor. The open
load is indicated by a logic [1] in the SO data bit.
VBAT
The analog command may be used to monitor the drain
voltage in the MOSFET ON state. By sourcing 2.0 mA of current
to the 1.5 kΩ resistor, the analog voltage on the SGn terminal
will be approximately:
V
V
PWR PWR
SG0
16
mA
2.0
mA
1.5 kΩ
100 kΩ
SG0
AMUX
VSGn = ISGn x 1.5 kΩ + VDS
+
To SPI
4.0 V Ref
-
Comparator
As the voltage on the drain of the MOSFET increases, so
does the voltage on the SGn terminal. With the SGn terminal
selected as analog, the MCU may perform the A/D conversion.
V
V
PWR
PWR
SG0
16
2.0
mA
mA
Using this method for controlling unclamped inductive loads
is not recommended. Inductive flyback voltages greater than
SP0
V
PWR may damage the IC.
+
To SPI
4.0 V
Ref
-
16
mA
Comparator
2.0 mA
The SP0:SP7 terminals of this device may also be used to
send signals from one module to another. Operation is similar
to the gate control of a MOSFET.
V
V
PWR PWR
SG13
For LED applications a resistor in series with the LED is
recommended but not required. The switch-to-ground inputs
are recommended for LED application. To drive the LED use
the following commands:
16
mA
2.0
mA
SG13
+
To SPI
4.0 V Ref
-
•
•
wetting current timer enable command –Disable SGn
wetting current timer.
metallic command –Set SGn to 16 mA.
Comparator
From this point forward the LED may be turned on and off using
the tri-state command:
Figure 12. MOSFET or LED Driver Output
The sequence of commands (from Normal mode with inputs
tri-state) required to set up the device to drive a MOSFET are
as follows:
•
•
tri-state command –Disable tri-state for SGn (LED ON).
tri-state command –Enable tri-state for SGn (LED OFF).
These parameters are easily programmed via SPI commands
in Normal mode.
•
•
•
•
wetting current timer enable command –Disable SPn
wetting current timer (refer to Table 4, page 14).
metallic command –Set SPn to 16 mA or 2.0 mA gate
drive current (refer to Table 3, page 13).
settings command –Set SPn as switch-to-battery (refer to
Table 1, page 12).
Multiple 33972 Devices in a Module System
Connecting power to the 33972 and the MCU for Sleep mode
operation may be done in several ways. Table 16 shows
several system configurations for power between the MCU and
the 33972 and their specific requirements for functionality.
tri-state command –Disable tri-state for SPn (refer to
Table 5, page 14).
Table 16. Sleep Mode Power Supply
After the tri-state command has been sent (tri-state disable),
the MOSFET gate will be pulled to ground. From this point
forward the MOSFET may be turned on and off by sending the
settings command:
MCU
VDD
33972
VDD
Comments
5.0 V
5.0 V
All wake-up conditions apply. (Refer to Sleep
Mode, page 18.)
•
•
settings command –SPn as switch-to-ground (MOSFET
ON).
settings command –SPn as switch-to-battery (MOSFET
OFF).
5.0 V
0 V
0 V
SPI wake-up is not possible.
5.0 V
Sleep mode not possible. Current from CS
pullup will flow through MCU to VDD that has
Monitoring of the MOSFET drain in the OFF state provides
open load detection. This is done by using an SGn input
comparator. With the SGn input in tri-state, the load will pull up
the SGn input to battery. With open load the SGn terminal is
been switched off. Negative edge of CS will put
33972 in Normal mode.
0 V
0 V
SPI wake-up is not possible.
33972
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Multiple 33972 devices may be used in a module system.
The 33972 IC has an internal 5.0 V supply from VPWR
terminal. A POR circuit monitors the internal 5.0 V supply. In the
event of transients on the VPWR terminal, an internal reset may
SPI control may be done in parallel or serial. However when
parallel mode is used, each device is addressed independently
(refer to MCU Interface Description, page 11). Therefore when
sending the sleep command, one device will enter sleep before
the other. For multiple devices in a system, it is recommended
that the devices are controlled in serial (S0 from first device is
connected to SI of second device). With two devices, 48 clock
pulses are required to shift data in. When the WAKE feature is
used to enable the power supply, both WAKE terminals should
be connected to the enable terminal on the power supply. The
INT terminals may be connected to one interrupt terminal on the
MCU or may have their own dedicated interrupt to the MCU.
occur. Upon reset the 33972 will enter Normal mode with the
internal registers as defined in Table 10, page 17. Therefore it
is recommended that the MCU periodically update all registers
internal to the IC.
Using the WAKE Feature
The 33972 provides a WAKE output and wake-up input
designed to control an enable terminal on system power supply.
While in the Normal mode, the WAKE output is LOW, enabling
the power supply. In the Sleep mode, the WAKE terminal is
HIGH, disabling the power supply. The WAKE terminal has a
passive pullup to the internal 5.0 V supply but may be pulled up
through a resistor to VPWR supply (see Figure 14, page 24)
The transition from Normal to Sleep mode is done by
sending the sleep command. With the devices connected in
serial and the sleep command sent, both will enter Sleep mode
on the rising edge of CS. When Sleep mode is entered, the
WAKE terminal will be logic [1]. If either device wakes up, the
WAKE terminal will transition LOW, waking the other device.
When the WAKE output is not used the terminal should be
pulled up to the VDD supply through a resistor as shown in
Figure 13, page 24.
A condition exists where the MCU is sending the sleep
command (CS logic [0]) and a switch input changes state. With
this event the device that detects this input will not transition to
Sleep mode, while the second device will enter Sleep mode. In
this case two switch status commands must be sent to receive
accurate switch status data. The first switch status command
will wake the device in Sleep mode. Switch status data may not
be valid from the first switch status command because of the
time required for the input voltage to rise above the 4.0 V input
comparator threshold. This time is dependant on the
impedance of SGn or SPn node. The second switch status
command will provide accurate switch status information. It is
recommended that software wait 10 ms to 20 ms between the
two switch status commands, allowing time for switch input
voltages to stabilize. With all switch states acknowledged by the
MCU, the sleep sequence may be initiated. All parameters for
Sleep mode should be updated prior to sending the sleep
command.
During the Sleep mode, a switch closure will set the WAKE
terminal LOW, causing the 33972 to enter the Normal mode.
The power supply will then be activated, supplying power to the
VDD terminal and the microprocessor and the 33972. The
microprocessor can determine the source of the wake-up by
reading the interrupt flag.
Cost and Flexibility
Systems requiring a significant number of switch interfaces
have many discrete components. Discrete components on
standard PWB consume board space and must be checked for
solder joint integrity. An integrated approach reduces solder
joints, consumes less board space, and offers wider operating
voltage, analog interface capability, and greater interfacing
flexibility.
33972
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VPWR
VDD
VDD
VBAT
VBAT
Power
Supply
33972
VPWR
VPWR
SP0
SP1
VDD
VDD
VBAT
MC68HCXX
Microprocessor
SP7
WAKE
CS
CS
SG0
SG1
INT
SI
INT
MOSI
MISO
SO
SCLK
SCLK
AN0
AMUX
SG12
SG13
Figure 13. Power Supply Active in Sleep Mode
VPWR VDD
VDD
VBAT
VBAT
Power
Supply
33972
VPWR
Enable
VPWR
SP0
SP1
VDD
WAKE
VDD
VBAT
MC68HCXX
Microprocessor
SP7
CS
CS
SG0
SG1
INT
SI
INT
MOSI
MISO
SO
SCLK
SCLK
AN0
AMUX
SG12
SG13
Figure 14. Power Supply Shutdown in Sleep Mode
33972
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PACKAGE DIMENSIONS
DWB SUFFIX
EW (Pb-FREE) SUFFIX
32-LEAD SOIC WIDE BODY
PLASTIC PACKAGE
CASE 1324-02
ISSUE A
10.3
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. DATUMS B AND C TO BE DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
7.6
7.4
C
B
2.65
2.35
5
9
4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURRS. MOLD FLASH,
PROTRUSION OR GATE BURRS SHALL NOT EXCEED
0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED
AT THE PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
30X
1
32
0.65
5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSIONS. INTERLEAD FLASH AND
PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER
SIDE. THIS DIMENSION IS DETERMINED AT THE
PLANEWHERETHEBOTTOMOFTHELEADSEXITTHE
PLASTIC BODY.
6. THIS DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4
MM PER SIDE. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD
SHALL NOT LESS THAN 0.07 MM.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM
THE LEAD TIP.
9. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. THIS DIMENSION IS
PIN 1 ID
4
11.1
10.9
C
L
9
B
B
16
17
SEATING
A
PLANE
5.15
2X 16 TIPS
0.3
32X
0.10
A
DETERMINED AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE
BAR BURRS, GATE BURRS AND INTER-LEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
A
B C
A
A
(0.29)
BASE METAL
0.25
0.19
(0.203)
R0.08 MIN
0.25
°
0
0.38
0.22
0.29
0.13
GAUGE PLANE
MIN
PLATING
6
M
M
0.13
C A
B
8
0.9
0.5
SECTION A-A
°
°
8
0
ROTATED 90 CLOCKWISE
°
SECTION B-B
33972
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NOTES
33972
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NOTES
33972
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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be
provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license
under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product
could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or
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MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their
respective owners.
© Motorola, Inc. 2004
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