MC44461B [MOTOROLA]
PICTURE-IN-PICTURE (PIP) CONTROLLER; 子母画面（ PIP ）控制器
| 型号： | MC44461B |
| 厂家： | 
MOTOROLA |
| 描述： | PICTURE-IN-PICTURE (PIP) CONTROLLER |
| 文件： | 总16页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document by MC44461/D
PICTURE–IN–PICTURE
(PIP) CONTROLLER
The MC44461 Picture–in–Picture (PIP) controller is a member of
Motorola’s low cost PIP family. It is NTSC compatible and contains all the
analog signal processing, control logic and memory necessary to provide for
the overlay of a small picture from a second non synchronized source onto
the main picture of a television. All control and setup of the MC44461 is via a
SEMICONDUCTOR
TECHNICAL DATA
2
standard two pin I C bus interface. The device is fabricated using BICMOS
technology. It is available in a 56–pin shrink dip (SDIP) package.
The main features of the MC44461 are:
• Two NTSC CVBS Inputs
• Switchable Main and PIP Video Signals
• Single NTSC CVBS Output Allows Simple TV Chassis Integration
• Two PIP Sizes; 1/16 and 1/9 Screen Area
• Freeze Field Feature
56
• Variable PIP Position in 64–X by 64–Y Steps
• PIP Border with Programmable Color
1
• Programmable PIP Tint and Saturation Control
• Automatic Main to PIP Contrast Balance
• Vertical Filter
B SUFFIX
PLASTIC PACKAGE
CASE 859
(SDIP)
• Integrated 64 k Bit DRAM Memory Resulting in Minimal RFI
• Minimal RFI Allows Simple Low Cost Application into TV
ORDERING INFORMATION
Operating
2
• I C Bus Control – No External Variable Adjustments Needed
Temperature Range
Device
Package
• Operates from a Single 5.0 V Supply
• Economical 56–Pin Shrink DIP Package
MC44461B T = –65° to +150°C
SDIP
J
For surface mount package availability, contact your local
Motorola sales office or authorized distributor.
Composite Video Simplified System Diagram
CV
CV
in
Tuner/IF
Video
Processor
R
G
B
CV
1
PIP
MC44461
Back Panel
Composite
Video Input
CV
2
IIC
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
Motorola, Inc. 1996
Rev 0
MC44461
MAXIMUM RATINGS
Rating
Symbol
Value
–0.5 to +6.0
–0.5 to +6.0
–0.5,
Unit
V
Power Supply Voltage
Power Supply Voltage
Input Voltage Range
V
DD
CC
V
V
V
IR
V
V
DD
+ 0.5
Output Current
I
O
160
mA
Power Dissipation
Maximum Power Dissipation @ 70°C
Thermal Resistance, Junction–to–Air
P
1.3
59
W
°C/W
D
R
θJA
Junction Temperature (Storage and Operating)
T
J
–65 to +150
°C
NOTE: ESD data available upon request.
ELECTRICAL CHARACTERISTICS (V
= V
= 5.0 V, T = 25°C, unless otherwise noted.)
DD A
CC
Characteristic
Symbol
Min
Typ
Max
Unit
POWER SUPPLY
Total Supply (Pins 8, 15, 43 and 50)
Total I
–
100
160
mA
Supply
VIDEO
Composite Video Input (Pin 34 or 36)
CVi
–
–
–
–
–
–
–
1.0
2.0
1.0
6.0
10
–
–
–
–
–
–
Vpp
Vpp
Vdc
dB
Composite Video Output (Pin 49, Unterminated)
Video Output DC Level (Sync Tip)
Video Gain
–
–
Video Frequency Response (Main Video to –1.0 dB)
Color Bar Accuracy
–
MHz
deg
dB
–
±4.0
Video Crosstalk (@ 75% Color Bars)
Main to PIP
PIP to Main
–
–
–
55
55
–
–
Output Impedance
–
–
5.0
–
Ω
HORIZONTAL TIMEBASE
Free Run HPLL Frequency (Pin 16)
–
–
–
–
–
–
–
–
–
–
15734
±400
±4.0
1.0
–
–
–
–
–
Hz
Hz
ns
µs
µs
HPLL Pull–In Range
HPLL Jitter
Burst Gate Timing (from Trailing Edge Hsync, Pin 24)
Burst Gate Width
4.0
VERTICAL TIMEBASE
Vertical Countdown Window
–
–
–
–
232/296
31
–
–
H lines
Vertical Sync Integration Time
µs
ANALOG TO DIGITAL CONVERTER
Resolution
–
–
–
–
–
–
–
–
–
–
–
–
6
–
–
–
–
–
–
Bits
LSB
LSB
MHz
kHz
Integral Non–Linearity
±1
Differential Non–Linearity
+2/–1
1.0
ADC – Y Frequency Response @ –5.0 dB
ADC – U, V Frequency Response @ –5.0 dB
200
4.773
Sample Clock Frequency (4/3 F
)
MHz
SC
2
MOTOROLA ANALOG IC DEVICE DATA
MC44461
ELECTRICAL CHARACTERISTICS (continued) (V
= V
= 5.0 V, T = 25°C, unless otherwise noted.)
DD A
CC
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL TO ANALOG CONVERTER
Resolution
–
–
–
–
–
–
–
–
–
–
–
6
–
–
–
–
Bits
LSB
LSB
Deg
dB
Integral Non–Linearity
±1
Differential Non–Linearity
+2/–1
±10
±6.0
Tint DAC Control Range (in 64 Steps)
Saturation DAC Control Range (in 64 steps)
NTSC DECODER
Color Kill Threshold
–
–
–
–
–
–
–24/–16
3.0 ±1.0
±0.5
–
–
–
dB
dB
dB
Threshold Hysteresis
ACC (Chroma Amplitude Change, +3.0 dB to –12 dB)
PIP CHARACTERISTICS
PIP Size
–
1/9 Screen Horizontal
1/9 Screen Vertical
1/16 Screen Horizontal
1/16 Screen Vertical
–
–
–
–
114
71
84
–
–
–
–
pels
lines
pels
lines
53
Border Size Horizontal
Border Size Vertical
–
–
–
–
–
–
–
–
–
–
3
2
–
–
–
–
–
pels
lines
MHz
%
Output PEL Clock (4 F
)
14.318
100
100
SC
Position Control Range Horizontal (% of Main Picture), 64 Steps
Position Control Range Vertical (% of Main Picture), 64 Steps
%
Figure 1. Representative Block Diagram
Decoder Clamp Caps
Filter PLL
ADC Mid–Ref
51
33
40
41
42
Filter
Tracking
28
31
Low Pass
Filter
Sync Sep
H PLL
36
34
H and V
Timebase
Video 1
Video 2
Input
Switch
Band Pass
Filter
Y
Y
Y
U V
6–Bit
ADC
37
49
NTSC
Decoder
1
2
3
4
5
Decoder ACC
Main Out
V
U
V
U
Clamp
6
H
in
3
V
in
PIP
Switch
SCL
Digital
Logic
6
57.28 MHz
0
°
90
°
38
39
7
Tint DAC
Sat DAC
SDA
Reset
Vert
Decoder Xtal
Decoder PLL
4X S/C
Osc + PLL
14.32 MHz
6
10
30
Vid 1/2 Sel
Multi Test
16 F
PLL
SC
6
16X S/C
Osc + PLL
44
45
NTSC
Encoder
3.0 MHz
LPF
Encoder Phase
Encoder ACC
U DAC
V DAC
Y DAC
Clamp
3.0 MHz
LPF
0°
90°
6
Memory
8.0 k x 8
DRAM
Y
U
V
4X S/C
Osc + PLL
3.0 MHz
LPF
6
46
47
52 53 54
Encoder
PLL
Encoder
Xtal
Encoder Clamp Caps
This device contains approximately 500,000 active transistors.
3
MOTOROLA ANALOG IC DEVICE DATA
MC44461
Figure 2. Application Circuit
5.0 V 5.0 V
1.0 k
Horiz In
Vert In
I C Ser Cl
1.0 k
1.0 k
2
1.0 k
2
I C Ser Data
0.01
0.01
1
2
56
H
MC44461
N/C
N/C
in
470 k
55
54
53
52
51
50
49
48
47
46
45
44
43
V
5.0 V
in
3
SCL
Encoder V Cap
Encoder U Cap
Endoder Y Cap
N/C
0.01
2.2 µF
4
SDA
5
Reset
Test Clk
0.1
47 k
6
5.0 V
100
10 µF
7
16 F
V
Filter
Video Out V
CC
SC
(dig)
75
8
Video Out
Analog Gnd
Video Out
DD
SS
1000
100
0.01
9
V
(dig)
0.1
µ
F
100 k
5.0 V
10
11
12
13
14
Video 1/2 Select
Encoder Xtal
Encoder PLL
Encoder ACC
Encoder Phase
10
µF
12
X3
N/C
N/C
N/C
1000
Video 1/2
Select Out
0.1
0.01
5.0 V
2700
0.068
V
V
(mem)
(mem)
Analog V
CC
5.0 V
DD
0.01
10
µ
F
15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Decoder V Cap
Decoder U Cap
Decoder Y Cap
Decoder PLL
Decoder Xtal
Decoder ACC
Video In 1
Analog Gnd
Video In 2
Filter PLL
10
µF
0.01
SS
0.01
0.01
0.01
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
68 k
0.22
12
X2
Video 1
0.1
Video 2
0.1
0.01
N/C
75
75
H PLL
Multi Test
Sync Sep
N/C
1.0 µF
12 k
0.0068
1.0 µF
X2 – 14.31818 MHz – Fox 143–20 or equivalent
X3 – 14.31818 MHz – Fox 143–20 or equivalent
NOTE: For proper noise isolation, Power Supply Pins 8, 14, 43 and 50 should be bypassed by both high and low
frequency capacitors. As a guideline, a 10 µF in parallel with a 0.1 µF at each supply pin is recommended.
4
MOTOROLA ANALOG IC DEVICE DATA
MC44461
PIN FUNCTION DESCRIPTION
Pin
Equivalent Internal Circuit
Description
1
Horizontal Reference In (H )
in
CMOS level pulse synchronous with TV horizontal retrace signal. This
pulse may be active high or low since there is a polarity selector bit in
an internal control register. This pulse should begin 0.5 to 0.75 µs after
the beginning of the main video H sync period. Its duty cycle should be
less than 50%.
1.0 k
1
2
Vertical Reference In (V )
in
CMOS level pulse synchronous with TV vertical retrace signal. This
pulse may be active high or low since there is a polarity selector bit in
an internal control register. This pulse should begin during the main
video vertical interval and have a duration of at least .5H.
1.0 k
1.0 k
2
3
3
4
Serial Clock (SCL)
2
CMOS level I C Compatible slave only clock input. 100 kHz Maximum
2
frequency. 50% duty cycle. See Figure 4 for timing. See I C Register
Description for internal register descriptions and addresses.
Serial Data (SDA)
1.0 k
2
CMOS level I C Compatible slave only data input/output. As an output
4
2
it is open collector. See Figure 4 for timing. See I C Register
Description for internal register descriptions and addresses.
5
Reset
5.0
The active low, Power On Reset initializes all internal registers to zero
2
and resets the I C interface. Minimum active low time required for
470 k
Power On Reset reset is 100 ms.
5
2.2
µF
6
Test Clock
5.0
47 k
6
7
PLL Filter
Filter for the 16X S/C PLL which is phase locked to the 4X S/C
oscillator.
7
100
1000
100
Pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. In an application, no connection should be made to these pins.
5
MOTOROLA ANALOG IC DEVICE DATA
MC44461
PIN FUNCTION DESCRIPTION (continued)
Pin
Equivalent Internal Circuit
Description
8
9
8
14, 43, 50 15, 35, 48
V
, V
DD SS
14, 43, 50
9
15, 35, 48
The four V
supply. The four V
pins must be externally connected to a 5.0 V (±5%)
DD
lines must externally connect to their respective
SS
bypass return(s) to ensure that no ground disturbances occur in
V
DD
operation. All supplies must be properly bypassed and isolated for the
application. Bypass capacitors of 10 µF in parallel with 0.1 µF for each
supply are recommended as a general guideline. The 0.1 µF, high
frequency bypass capacitors should be placed as close to the power
pins as practical.
V
V
M V
M V
SS
SS
DD
DD
An V
An Gnd
An Gnd
CC
Vid V
CC
10
Video 1/2 Select Output
High output level indicates that Video 1 is selected to be the main
picture video. Low output level indicates Video 2 is selected to be the
main picture video.
10
28
Sync Out
Outputs the video signal selected as the PIP to be filtered and applied
to the H and V timebase through the Sync In pin.
28
29
Sync In
PIP sync pulses are externally filtered and applied to the H and V
timebase to allow H and V synchronization.
29
30
Multi Test
2
Under control of I C bus output signals for test and adjustment are
provided through this pin.
30
10 k
31
H PLL
Connection for horizontal timebase PLL filter.
31
0.0068
1.0
12 k
µF
Pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. In an application, no connection should be made to these pins.
6
MOTOROLA ANALOG IC DEVICE DATA
MC44461
PIN FUNCTION DESCRIPTION (continued)
Pin
Equivalent Internal Circuit
Description
33
Filter PLL
The on board reference filter produces a phase shift which is
measured and applied to an internal filter PLL. This capacitor
connected to this pin stores the phase correction voltage for the PLL
which sets the 90° phase correction reference for the rest of the on
chip filters.
33
0.1
36 and 34
Video Input 1 and 2
Accepts ac coupled 1.0 Vpp composite video input usually from a
source generated inside the TV and an external video source.
Composite
Video
2.0 k
The series coupling capacitor also functions as the storage capacitor
for the clamp voltage for the input circuit. It is necessary to return the
input of this capacitor to ground through a dc low impedance to enable
this clamp function. R = 50 to 100 Ω is acceptable.
0.1
R
19 k
37
Decoder ACC
The Decoder ACC pin provides access to the internal chroma decoder
automatic gain control amplifier. The ACC capacitor filters the feedback
loop of this amplifier.
During PIP burst gate time a voltage proportional to the burst gate
magnitude is stored on the capacitor connected to this pin to
compensate for input chroma level variation and provide a constant
U and V output level to the A/D conversion stage.
37
0.22
38
Decoder Crystal
4X Sub–Carrier crystal used to synchronize the decoding of the PIP
UV information prior to A/D conversion, sub–sampling and storage in
the field memory.
The crystal frequency is 14.31818 MHz.
38
14.3 MHz
12
39
Decoder PLL
Connection for Decoder PLL filter.
39
2700
0.068
68 k
Pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. In an application, no connection should be made to these pins.
7
MOTOROLA ANALOG IC DEVICE DATA
MC44461
PIN FUNCTION DESCRIPTION (continued)
Pin
Equivalent Internal Circuit
Description
44
Encoder Phase
Phase difference of the main to encoded burst is sampled and applied
to the capacitor connected to this pin to shift the phase of the
re–encoded chrominance to match the main.
44
0.01
2.0 k
45
Encoder ACC
The Encoder ACC pin provides access to the internal chroma
reference sample and hold circuit, which stores the sampled value of
the main channel chroma burst amplitude on this external ACC
capacitor. The ACC amplifier matches the chroma amplitude of the
insert picture to that of the main picture.
45
0.1
46
Encoder PLL
Connection for Encoder PLL filter. See separate discussion for filter
values.
46
1000
0.1
µF
100 k
47
Encoder Crystal
4X Sub–Carrier crystal used to synchronize the encoding of the PIP
YUV from the field memory with the main video. The output from this
PLL is phase corrected to match the PIP video signal to the main video
at the PIP switch.
38
The crystal frequency is 14.31818 MHz.
14.3 MHz
12
49
Video Out
The selected Video 1/2 input is available at the Video Out mixed with
the PIP overlay when selected. This signal is a nominal 2.0 V
peak–to–peak signal unterminated. This connection is intended to
drive an external series 75 Ω load into a 75 Ω termination to ground to
provide a 1.0 Vpp signal at the termination.
49
75
4.8 k
Composite
Video
Pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. In an application, no connection should be made to these pins.
8
MOTOROLA ANALOG IC DEVICE DATA
MC44461
PIN FUNCTION DESCRIPTION (continued)
Pin
Equivalent Internal Circuit
Description
54, 53, 52,
42, 41, 40
Encoder and Decoder YUV Caps
During the internal H rate clamping time the YUV reference levels are
set by the charge on the capacitors attached to these pins. The
nominal value of these capacitors should be 0.01 µF.
0.01
Pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. In an application, no connection should be made to these pins.
SOFTWARE CONTROL OF THE MC44461
2
Communications to and from the MC44461 follows the I C
2) The second byte defines the sub–address register,
within the MC44461, to be updated; $00 through $0B.
3) The third byte is the data for that register.
interface protocol defined by the Philips Corporation. In
simple terms, the I C is a two line, multi–master, bidirectional
bus used for data transfer. Although an I C system can be
multi–master, the MC44461 never functions as a master.
The MC44461 has a write address of $24 and a flag read
2
2
The communication begins when a start sequence (data
line taken low while the clock line is high) is initiated by the
master (MCU) and detected by the MC44461, generating an
internal reset. The first byte is then generated, and if the
address is correct ($24), an acknowledge is generated by the
MC44461, which tells the master to continue to send data.
The second byte is then entered, followed by an
acknowledge. The third byte is the operative data which is
stored in the designated register, followed by the third
acknowledge. Writing to multiple registers in a single write
operation is permitted in the MC44461. The sub–address is
auto–incremented while receiving n – data bytes + Ack,
ending with the stop sequence. The sub–address of the 11
registers are at $00 through $0B.
2
address of $25. A block diagram of the I C interface is shown
in Figure 3. Writing to the MC44461 registers can cause
momentary jitter or other undesirable effects to the TV
screen, writing should be done only during the vertical
retrace (before line 20).
Write to Control Registers
A write cycle consists of three bytes, with three
acknowledge bits.
1) The first byte is always the write address for the
MC44461 ($24).
2
Figure 3. I C Bus Interface and Decoder
Reset
Start Bit
Recognition
Clock Counter
5
6
Clock
Data
Chip
Address
Latch
Read/
Write
Latch
8–Bit Shift Register
Acknowledge
Sub–Address
Latches
19 Registers
Flag Data
9
MOTOROLA ANALOG IC DEVICE DATA
MC44461
2
Figure 4. I C Data Transfer
SDA
SCL
MSB
1
MSB
2
7
8
9
1
2
7
8
9
ACK
ACK
Start
Condition
Stop
Condition
S
Slave Address
R/
A
Sub–Address
A
Data
A
P
W
Data Transferred
(n Bytes + Acknowledge)
A = Acknowledge
S = Start
P = Stop
2
I C REGISTER DESCRIPTIONS
Base write address = 24h
Base read address = 25h
Border Color Register
Sub–address = 02h
Border Color Bits (BC0–2) – D0–D2
These Bits control the color of the border. Note that when
using one of the saturated border colors it is possible to get
objectionable dot crawl at the edge of the border in some TVs
unless appropriate comb filtering is used in the TV circuitry.
Read Register
There are two active bits in the single read byte available
from the MC44461 as follows:
Write Vertical Indicator (WVI0) – D7
When 0 indicates that the write operation specified by the
2
last I C command has been completed.
BC (2:0)
000
Border Color
PIP Sync Detect Bit (PSD0) – D1
Black
When 0 indicates that the PIP video H pulses are present
and the horizontal timebase oscillator is within acceptable
limits.
001
White 70%
No Border (clear)
No Border (clear)
Blue
010
011
Write Registers
100
Read Start Position/Write Start Position Registers
Sub–address = 00h
101
Green
Write Raster Position Start Bits (WPS0–2) – D0–D2
Establishes the horizontal beginning of the PIP and its
black level measurement gate. This beginning may be varied
by approximately 3.0 µs. The position of this pulse may be
observed through the Multi Test Pin 30 (See Test Mode
Register Sub–address 03h).
110
Red
111
White
Test Mode/Main Vertical and Horizontal Polarity Register
Sub–address = 03h
Internal Test Mode Register (ITM0–2) – D0–D2
Sets the Multi Test Pin output to provide one of several
internal signals for test and production alignment. Also
controls the test memory address counter.
Read Raster Position Bits (RPS0–3) – D4–D7
Establishes the clamp gate position for the black level
reference for the main picture. This position may be varied by
approximately 5.0 µs. The position of this pulse may be
observed through the Multi Test Pin 30 (See Test Mode
Register Sub–address 03h).
ITM (2:0)
000
Multi–Test I/O and Function
Input – Analog Test mode
Input – Digital Test mode
Output – Sync Detect
Output – PIP Switch
Pip Switch Delay/Vertical Filter Register
Sub–address = 01h
001
PIP Switch Delay Bits (PSD0–3) – D0–D3
010
Delays the start of PIP on time relative to the PIP picture.
These bits are used to center the PIP border and PIP picture
in the horizontal direction.
011
100
Output – PIP H Detect
Output – PIP V Detect
Output – PIP Clamp
Vertical Filter Bit (VFON) – D4
101
When the filter is activated (VFON = 1) a three line
weighted average is taken to provide the data stored in the
field memory.
110
111
Output – Main Clamp
10
MOTOROLA ANALOG IC DEVICE DATA
MC44461
Main vertical polarity select bit (MVP0) – D6
PIP Y Position Register
Selects polarity of active level of vertical reference input.
0 = positive going, 1 = negative going.
Sub–address = 07h
Y Position Bits (YPS0–5) – D0–D5
Main horizontal polarity select bit (MHP0) – D7
Selects polarity of active level of horizontal reference
input. 0 = positive going, 1 = negative going.
Moves the PIP start position from the top to the bottom
edge of the display in 64 steps. There is protection circuitry to
prevent the PIP from interfering with the main picture sync
pulses.
PIP Freeze/PIP Size/Main and PIP Video Source Register
Sub–address = 04h
PIP Chroma Level Register
Sub–address = 08h
PIP Freeze Bit (STIL0) – D4
When set to one, the most recently received field is
continuously displayed until the freeze bit is cleared.
Chroma (C0–5) – D0–D5
The color of the PIP can be adjusted to suit viewer
preference by setting the value stored in these bits. A total of
64 steps varies the color from no color to maximum. This
control acts in conjunction with the auto phase control.
PIP Size Bit (PSI90) – D5
Switches the PIP size between 1/16 main size (when 0)
and 1/9 main size (when 1).
PIP Tint Level Register
Sub–address = 09h
Main Video Source Select Bit (MSEL0) – D6
Selects which video input will be applied to the PIP switch
as the main video out.
Tint (T0–5) – D0–D5
An auto phase control compares the main color burst to
the internally generated pseudo color burst so that the tints
are matched. In addition to this, the tint of the PIP can be
varied ±10° in a total of 64 steps by changing the value of
these bits to suit viewer preference.
PIP Video Source Select Bit (PSEL0) – D7
Selects which video input will be applied to the video
decoder to provide the PIP video.
MSEL/PSEL
Function
PIP Luma Delay Register
Sub–address = 0Ah
0
Video 1 Input to Main/
Video 1 Input to PIP
Y Delay (YDL0–2) – D0–D2
1
Video 2 Input to Main/
Video 2 Input to PIP
Since the Chroma passes through a bandpass filter and
the color decoder, it is delayed with respect to the Luma
signal. Therefore, to time match the Luma and Chroma these
bits are set to a single value determined to be correct in the
application.
PIP On/PIP Blank Register
Sub–address = 05h
PIP On Bit (PON0) – D0
Pip Fill/Test Register
When on (1) turns the PIP on.
Sub–address = 0Ch
PIP Blanking Bit (PBL0) – D4
PIP Fill Bits (PIPFILL0–1) – D0–D1
May be used to fill the PIP with one of three selectable
solid colors
When on (1) sets the PIP to black. If the PIP is off, then it
will be black if it is turned on. Overrides all other settings of
the PIP control.
Test Register Bits (INTC0 and MACR0) – D6–D7
Used for production test only.
PIP X Position Register
Sub–address = 06h
Function Control of the MC44461
X Position Bits (XPS0–5) – D0–D5
The registers of the MC44461 may be programmed via the
I C bus. At power up, the registers are in an undefined state.
The Setup Value given in the Register Table represents a
nominal start point. The setup will put a 1/9 size PIP, with
white borders, in the lower right corner of the screen.
Moves the PIP start position from the left to the right
edge of the display in 64 steps. There is protection circuitry
to prevent the PIP from interfering with the main picture
sync pulses.
2
11
MOTOROLA ANALOG IC DEVICE DATA
MC44461
2
I C REGISTER TABLE
Data Bit
Sub–
Setup
D7
D6
D5
D4
RPS0
VFON
–
D3
D2
WPS2
PSD2
BC2
ITM2
–
D1
WPS1
PSD1
BC1
ITM1
–
D0
WPS0
PSD0
BC0
ITM0
–
address
Values
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
45h
1Ah
07h
02h
20h
01h
34h
24h
20h
20h
02h
–
RPS3
RPS2
RPS1
–
–
–
–
PSD3
–
–
–
–
–
MHP0
MVP0
–
–
–
PSEL0
MSEL0
PSI90
–
STIL0
PBL0
XPS4
YPS4
C4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PON0
XPS0
YPS0
C0
XPS5
YPS5
C5
T5
XPS3
YPS3
C3
T3
–
XPS2
YPS2
C2
XPS1
YPS1
C1
T4
T2
T1
T0
–
–
YDL2
–
YDL1
–
YDL0
–
–
–
–
00h
–
–
–
–
–
–
CIRCUIT DESCRIPTION
The MC44461 Picture–in–Picture (PIP) controller is
composed of an analog section, logic section and an
8192 x 8–bit DRAM array. A block diagram showing details of
all of these sections is shown in the Representative Block
Diagram.
decoder section. These filters are tracked to a master GmC
cell using subcarrier as a reference. A single–ended
transconductance stage with relatively large signal handling
ability (>2.5 Vpp @ 4.5 V V ) is used to avoid potential
CC
noise problems.
The analog section includes an Input Switch, Sync
Processor, Filters, PLLs, NTSC Decoder, ADC, DACs, NTSC
Encoder and Output Switch. All necessary controls are
provided by registers in the logic section. These registers are
Figure 5. NTSC Decoder
U
V
BG
H
2
set by external control through the I C Bus.
In operation, the MC44461 overlays a single PIP on the
main video in either a 1/9th or 1/16th size. In 1/9th, the PIP is
152 samples (114 Y, 19 V, 19 U) by 70 lines and occupies
8094 bytes of the 8192 byte DRAM. The 1/16 size is 112
samples (84 Y, 14 V, 14 U) by 52 lines and occupies 4452
bytes of the DRAM. An extra line of data is stored for each
PIP size to allow for interlace disorder correction. The 6:1:1
samples are formatted by the logic section as follows in order
to efficiently utilize memory:
Switching
Color
Killer
PLL
Filter
Mult 1
Mult 2
XVCO/
Divide
In
ACC
Byte 1: Y0(5:0), V(1:0)
90°
0°
Byte 2: Y1(5:0), V(3:2)
Byte 3: Y2(5:0), V(5:4)
Byte 4: Y3(5:0), U(1:0)
The NTSC Decoder (Figure 5) consists of two multipliers,
a voltage controlled 4 X S/C crystal oscillator/divider,
Automatic Color Control (ACC) block, Color Kill circuit and
necessary switching. During Burst Gate time, the ACC block
in the NTSC Decoder is calibrated with respect to burst
magnitude by applying the output of multiplier 1 to the
reference input of the ACC block. The result is U and V
outputs which are 0.6 V ± 0.5 dB for burst amplitudes varying
from –12 dB to 3.0 dB. The second multiplier serves as a
phase detector during color burst to match the 90 degree
output from the XVCO to the 180 degree color burst and feed
Byte 5: Y4(5:0), U(3:2)
Byte 6: Y5(5:0), U(5:4)
Refer to the block diagram. Both the video inputs are
applied to an input switch which is controlled by the I C bus
2
interface. Either of the inputs is applied to the PIP processing
circuitry and either to the main video signal path of the output
switch. The signal applied to the PIP processor also provides
the vertical sync reference to the PIP processor.
The PIP output from the switch is applied to a 1.0 MHz
cutoff low pass GmC biquad filter to extract the luminance
signal and a similar bandpass filter to pass chroma to the
12
MOTOROLA ANALOG IC DEVICE DATA
MC44461
blue or transparent (no border). In a system without an
a correction current to the PLL filter. The phase is correct
when the two signals are 90 degrees out of phase.
During the H drive time, the output of the multipliers is fed
to the YUV clamp, filtered to 200 KHz and input along with the
Y signal to the multiplexer.
The YUV samples are fed through a multiplexer to a single
six bit A/D converter. The A/D is a flash type architecture and
is capable of digitizing at a 20 MHz sample rate. It is
comprised of an internal bandgap source voltage reference,
a 64 tap resistor ladder comparator array, a binary encoder
and output latches. Once the multiplexer has switched,
sufficient time is provided to allow the A/D converter to settle
before the reading is latched. The encoder code is
determined from the values of any comparators which are not
metastable.
adaptive comb filter, borders which contain no chroma give
the best results. Also built into the read logic is a PIP fill mode
which allows the PIP window to be filled with either a solid
green, blue or red color as an aid in aligning the PIP analog
color circuitry.
Because the DAC output video will be referenced during
back porch time, the read processor zeroes the luminance
value and sets the bipolar U and V values to mid–range
during periods outside the PIP window to ensure clamping at
correct levels. Since the PIP window is positioned relative to
the main picture’s vertical and horizontal sync, a safety
feature turns off the window if the window encroaches upon
the sync period, thus preventing erroneous clamping.
The Y, U and V DACs are all three of the same design. A
binary weighted current source is used, split into two, three
bit levels. In the three most significant bits, the current
sources are cascaded to improve the matching to the three
least significant current sources. Analog transmission gates,
switched by the bi–phase outputs of the data latches, feed
the binary currents to the single ended current mirror. The
output current is subsequently clamped and filtered for
processing buy the NTSC Encoder.
The multiplexer and A/D converter receive and convert the
YUV data at a 4F /3 rate for a 1/9th size picture or F
a 1/16th size picture. The samples are taken in the following
way to simplify the control logic:
for
SC
SC
Y,V,Y,U,Y,V,Y,U
To provide a 6:1:1 format, one of three U and V samples is
saved to memory giving a luminance sample rate of 2F /3
SC
for a 1/9th picture and F /2 for a 1/16 picture. In the vertical
SC
The outputs of the U and V DACS are buffered and burst
flag pulses added to both signals. The U burst flag is fixed to
generate a –180° color burst at the modulator output. The V
burst flag is variable under the control of an internal register
direction, one line of every 3 (1/9th picture) or 4 (1/16th
picture) are saved. In order to avoid objectionable artifacts, a
piece–wise vertical filter is used to take a weighted average
on the luminance samples. For three lines (1/9th size) the
weight is 1/4 + 1/2 + 1/4 and for four lines (1/16 size) it is
1/4 + 1/4 + 1/4 + 1/4. This filter also delays the luma samples
correcting for the longer chroma signal path through the
decoder.
2
set through the I C bus to provide a variable tint. Saturation is
controlled by varying a register which sets the reference
2
voltage to the U and V DACs. This is also under I C bus
control. By oversampling the U and V DACs, it was possible
to use identical post–DAC filtering for Y, U and V, thereby
reducing the delay inequalities between Y and UV and also
simplifying the design. After filtering, the U and V signals are
clamped to an internal reference voltage during horizontal
blanking periods and fed to the U and V modulators. In the
NTSC Decoder, the Y, U and V signals were scaled to use the
entire A/D range. Gain through the NTSC Encoder is set to
properly match these amplitudes.
The phase of the re–encoded chrominance must match
that of the incoming main video signal at the input to the PIP
switch, so a separate first order PLL is placed within the loop
of the main video signal burst PLL. The first order PLL
compares the phase of the main burst with that of the
encoded burst and moves the oscillator phase so that they
match. A special phase shift circuit allowing a continuous
range of 180° was developed to do this.
The amplitude of the re–encoded chrominance signal
must also match that of the main video signal. To do this, a
synchronous amplitude comparator looks at both burst
signals and adjusts the chrominance amplitude in the
modulator section of the NTSC encoder. The Y signal from
the YDAC is compared to the main video signal at black level
during back porch time and clamped to this same black level
voltage. The PIP chrominance and luminance are then
added together and fed to the PIP output switch through a
buffered output.
Finally the logic incorporates a field generator to
determine the current field in order to correct interlace
disorders arising from a single field memory.
A separate process runs in the logic section to create the
PIP window on the main picture. Control signals are
generated and sent to the memory controller to read data
from the field memory. Data from the eight bit memory are
then de–multiplexed into a six bit YUV format, borders are
added, blanking is generated for the video clamps and sent to
the Y, U and V DACs. Since the PIP display is based on a
data clock, it is important to minimize the main display clock
skew on a line by line basis. Skew is minimized in the
MC44461 by reclocking the display timebase to the nearest
rising or falling edge of a 16F
clock. This produces a
SC
maximum line to line skew of approximately 8.0 ns which is
not perceptible to the viewer. The PIP write logic also
incorporates a field generator for use by the memory
controller for interlace disorder correction. Interlace disorder
can occur when the line order of the two fields of the PIP
image is swapped due to a mismatch with the main picture
field or due to an incomplete field being displayed from
memory. The main and PIP field generators, along with
monitoring, when the PIP read address passes the PIP write
address, allows the read address to the memory to be
modified to correct for interlace disorder.
The read logic can provide various border colors: black,
75% white (light gray), 50% white (medium gray), red, green,
13
MOTOROLA ANALOG IC DEVICE DATA
MC44461
OUTLINE DIMENSIONS
B SUFFIX
PLASTIC PACKAGE
CASE 859–01
(SDIP)
ISSUE O
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
-A-
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
56
29
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
2.065
0.560
0.200
0.022
MIN
51.69
13.72
3.94
0.36
0.89 BSC
MAX
52.45
14.22
5.08
-B-
2.035
0.540
0.155
0.014
1
28
L
0.56
0.035 BSC
F
0.032
0.070 BSC
0.300 BSC
0.008
0.115
0.046
0.81
1.778 BSC
7.62 BSC
0.20
2.92
1.17
H
G
H
J
K
L
C
0.015
0.135
0.38
3.43
0.600 BSC
15
0.040
15.24 BSC
15
0.51 1.02
-T-
SEATING
PLANE
M
N
0°
°
0°
°
K
0.020
N
G
M
F
E
D 56 PL
J 56 PL
M
S
M
S
B
0.25 (0.010)
T
A
0.25 (0.010)
T
14
MOTOROLA ANALOG IC DEVICE DATA
MC44461
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
15
MOTOROLA ANALOG IC DEVICE DATA
MC44461
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609
INTERNET: http://Design–NET.com
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MC44461/D
◊
相关型号：
©2020 ICPDF网 联系我们和版权申明