MC44864M [MOTOROLA]
PLL TUNING CIRCUIT WITH 1.3 GHz PRESCALER AND D/A CONVERTERS; 1.3 GHz的预分频器和D / A转换器PLL调谐电路
| 型号： | MC44864M |
| 厂家： | 
MOTOROLA |
| 描述： | PLL TUNING CIRCUIT WITH 1.3 GHz PRESCALER AND D/A CONVERTERS |
| 文件： | 总12页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document by MC44864/D
PLL TUNING CIRCUIT
WITH 1.3 GHz PRESCALER
AND D/A CONVERTERS
The MC44864 is a tuning circuit for TV applications. This device contains
a PLL section and a DAC section and is MCU controlled through an I C Bus.
2
The PLL section contains all the functions required to control the VCO of a
TV tuner. The IC generates the tuning voltage and the additional control
signals, such as band switching voltages.
The D/A section generates three additional varactor voltages to feed all of
the varactors of the tuner with individually optimized control voltages
(automatic tuner adjustment). The MC44864 is manufactured on a single
silicon chip using Motorola’s high density bipolar process, MOSIAC
(Motorola Oxide Self–Aligned Implanted Circuits).
SEMICONDUCTOR
TECHNICAL DATA
• Complete Single Chip System for MPU Control
• Selectable ÷8 Prescaler Accepts Frequencies up to 1.3 GHz
• 15 Bit Programmable Divider Accepts Input Frequencies up to 165 MHz
• Programmable Reference Divider
20
1
• 3–State Phase/Frequency Comparator
M SUFFIX
PLASTIC PACKAGE
CASE 967
• Operational Amplifier for Direct Varactor Control with Low Saturation
Voltage
• Four Output Buffers (15 mA)
(EIAJ–20)
• Output Options for 62.5 kHz, Reference Frequency and the
Programmable Divider
• The HF Input is Symmetrical
• Three 6 Bit DACs for Automatic Tuner Adjustment Allowing Use of
PIN CONNECTIONS
Non–Matched Varactors
• Better Tuner Performances Through Optimum Filter Response
2
• I C Bus Controlled
1
2
20
19
18
17
16
15
14
XTAL
PHO
Gnd
SDA
SCL
• Four Chip Addresses for the PLL Section
• Four Chip Addresses for the D/A Section
3
Amp In
• ESD Protected to MIL–STD–883C, Method 3015.7
4
V
B
B
B
B
CC2
7
5
3
1
(2,000 V, 1.5 kΩ, 150 pF)
5
V
TUN
DA1
MOSAIC is a trademark of Motorola, Inc.
6
MAXIMUM RATINGS (T = 25°C, unless otherwise noted.)
A
DA2
DA3
7
Rating
Power Supply Voltage (V
Band Buffer “Off” Voltage
Band Buffer “On” Current
Pin
9
Value
6.0
15
Unit
V
8
13 CA
)
9
12
11
V
Gnd
HF
CC1
CC1
10
14 – 17
14 – 17
4
V
HF
1
2
20
mA
V
Operational Amplifier Power Supply
Voltage (V
36
(Top View)
)
CC2
Operational Amplifier Short Circuit Duration
(0 to V
5 – 8
Continuous
S
)
CC2
Storage Temperature
–
–
–65 to +150
0 to +70
°C
°C
ORDERING INFORMATION
Operating
Operating Temperature Range
NOTE: ESD data available upon request.
Temperature Range
Device
Package
MC44864M
T
A
= 0° to +70°C
EIAJ–20
Motorola, Inc. 1996
Rev 2
MC44864
Representative Block Diagram
B
B
B
B
B
DA3
8
DA2
DA1
V
V
CC2
33 V
4
7
5
3
1
TUN
5
17 16 15 14
7
6
Amp 4
Amp 3
Amp 2
Amp 1
B
B
B
1
7
5
3
3
Amp
In
Buffers
Bias
Test
Logic
D/A 3
6 Bit
D/A 2
6 Bit
D/A 1
6 Bit
Ref
Voltage
Latches
Latches
Latches
Latches
2
F
F
ref
out
PHO
F1
9
V
CC1
5.0 V
Decoder
DTC
Phase
Comp
Shift Register
8 Bit
F
F
ref
out
13
CA
DTB
Latches
Ref
Divider
FUN
18
19
CL
F1
62.5 kHz
SCL
SDA
2
I C Bus
Shift Register
15 Bit
Data
Receiver
1
4.0 MHz
Osc
XTAL
Gnd
AD1
AD2
20
DTF
12
Latches A
Latches B
Gnd
TDI
Preamp 1
Preamp 2
10
11
HF
1
÷
Presc
8
HF
2
Program Divider
15 Bit
Latch
Control
F
out
AVA
This device contains 3,551 active transistors.
2
MOTOROLA ANALOG IC DEVICE DATA
MC44864
ELECTRICAL CHARACTERISTICS (V
= 5.0 V, V
= 32 V, T = 25°C, unless otherwise noted.)
CC2 A
CC1
Characteristic
Pin
Min
4.5
–
Typ
5.0
50
30
1.3
0.01
1.8
–
Max
5.5
70
Unit
V
V
V
V
V
Supply Voltage Range
9
CC1
CC1
CC2
CC2
(1)(2)
Supply Current (V
= 5.0 V)
9
4
mA
V
CC1
Supply Voltage Range
Supply Current (Output Open)
25
–
35
(4)
2.5
4
mA
µA
V
Band Buffer Leakage Current when “Off” at 12 V
14 – 17
14 – 17
18, 19
18
–
1.0
Band Buffer Saturation Voltage when “On” at 15 mA
Data/Clock Current at 0 V
–
2.0
0
–10
0
µA
µA
µA
V
Clock Current at 5.0 V
–
1.0
1.0
–
Data Current at 5.0 V Acknowledge “Off”
Data Saturation Voltage at 15 mA Acknowledge “On”
Data/Clock Input Voltage Low
19
0
–
19
–
1.2
–
18, 19
18, 19
18
–
1.5
–
V
Data/Clock Input Voltage High
3.0
–
–
V
Clock Frequency Range
–
100
15
4.1
–0.5
2.5
3.0
15
–
kHz
nA
MHz
mA
mA
V
Phase Detector Current in High Impedance State
Oscillator Frequency Range
2
–15
3.5
–2.5
0.5
2.0
–15
2000
–
–
1, 2
2
4.0
–
Phase Detector High–State Source Current (@ 1.5 V)
Phase Detector Low–State Sink Current (@ 4.0 V)
Operational Amplifier Internal Reference Voltage
Operational Amplifier Input Current
DC Open Loop Gain
2
–
–
2.5
–
3
nA
V/V
MHz
Deg.
V
–
–
Gain Bandwidth Product
–
0.2
50
0.2
–
–
Phase Margin
–
–
–
V
out
Low, Sinking 50 µA
6 – 8
6 – 8
5 – 8
6 – 8
6 – 8
–
–
0.5
1.5
30
1.5
–
V
out
High, Sourcing 50 µA (V
– V
CC2 out
High)
–
V
Tuning Voltage (DC)
–
–
V
(3)
D/A Converters Step Size
0.5
–
–
LSB
LSB
mV
mV
V
D/A Converters Temperature Drift
1.0
–
DAC Offset at V
DAC Offset at V
= 2.5 V
= 25 V
–50
–700
–
50
700
33
TUN
–
–
TUN
DAC Voltages (DC)
6 – 8
–
NOTES: 1. When prescaler “Off”, typical supply current is decreased by 10 mA.
2. Band Buffers “Off”, 2.4 mA more when one buffer is on.
3. For definition of the LSB, see Figure 9 in the D/A section.
4. 2.5 mA as long as the analog outputs are not in saturation high, which means V
, V
TUN DAC
(Pins 5, 6, 7, 8) lower than V – 1.5 V. When all
CC2
outputs are in saturation high the maximum V
current is 5.0 mA.
CC2
3
MOTOROLA ANALOG IC DEVICE DATA
MC44864
HF CHARACTERISTICS (See Figure 1)
Characteristic
Pin
Min
Typ
Max
Unit
V
DC Bias
10, 11
–
1.55
–
Input Voltage Range
10–150 MHz (Prescaler “Off”)
80–1000 MHz
mVrms
10, 11
10, 11
10, 11
20
20
50
–
–
–
315
315
315
1000–1300 MHz
Figure 1. HF Sensitivity Test Circuit
2
I C Bus
12 V
Bus Controller
18, 19
+5.0 V
9
3.9 k
V
CC1
MC44864
B
7
17
In
11
10
12
1
HF Generator
HF Out Gnd
Frequency
Counter
1.0 nF
1.0 nF
22 pF
50
Ω Cable
4.0 MHz
50
Ω
Device is in test mode: B is “On”, R = 1 and R = 0 (see Bus section).
7
2
3
Sensitivity is the level of the HF generator on 50 Ω load (without MC44864 load).
Figure 2. Typical HF Input Impedance
–j
+j
0
0.5
0.5
0.5
Z
= 50 Ω
O
1.3 GHz
1
2
1
1
1.0 GHz
2
2
500 MHz
50 MHz
4
MOTOROLA ANALOG IC DEVICE DATA
MC44864
PIN FUNCTION DESCRIPTION
Pin
Symbol
Description
6, 7, 8
DA1, DA2, DA3
D/A output control voltages
9
V
Positive supply of the circuit (except DACs)
HF input from local oscillator
CC1
10, 11
HF , HF
1
2
12, 20
Gnd
CA
Ground
13
Chip Address
14, 15, 16, 17
B , B , B , B
Band buffer output can drive 15 mA
Clock input (supplied by the microprocessor via Bus)
Data input (bus)
1
3
5
7
18
19
1
SCL
SDA
XTAL
PHO
Crystal oscillator (typically 4.0 MHz)
Phase comparator output
2
3
Amp In
Negative operational amplifier input
Operational amplifier positive supply
Operational amplifier output which provides the tuning voltage
4
V
CC2
TUN
5
V
5
MOTOROLA ANALOG IC DEVICE DATA
MC44864
Figure 3. Pin Circuit Schematic
20 V
20 V
DA1
6
V
5
Amp
Out
Amp
Out
TUN
20 V
20 V
V
4
CC2
DA2
7
Amp
Out
IB
Comp
600 k
DA3
8
Amp
In
3
10 k
20 V
20 V
5.5 V
20 V
V
PHO
2
CC1
9
5.5 V
5.5 V
V
CC1
20 V
10 k
V
5.5 V
HF
1
XTAL
1
CC1
1.0 k
20 V
10
5.5 V
5.5 V
5.5 V
1.0 k
1.0 k
20 k
2.0 k
2.0 k
HF
11
Gnd
20
2
1.5 k
100
V
CC1
100 k
130 k
1.1 mA
0.4 mA
V
CC1
50
SDA
19
Gnd
12
5.0 µA
25 k
V
CC1
20 V
ACK
40 k
150 k
50 k
500
10 k
CA
13
SCL
18
20 k
15 k
20 V
20 V
100 k
B
14
B
7
1
Buffer
Buffer
17
20 V
V
2.5 k
CC1
B
15
B
5
3
Buffer
16
On/Off
Buffer
6
MOTOROLA ANALOG IC DEVICE DATA
MC44864
FUNCTIONAL DESCRIPTION
A representative block diagram and a typical system
application are shown in Figures 4 and 5. A discussion of the
features and function of the internal blocks is given below.
optimum value of the other varactor voltages. The digital
word for each voltage value is stored in a nonvolatile memory
(NVM). Hence, for each frequency point to be adjusted, three
times 6 bits of information have to be stored (plus 2 bits for
the DAC range).
Automatic Tuner Alignment
The circuit generates the tuning voltage through the PLL.
The output voltages of the D/A converters are equal to the
tuning voltage plus a positive or negative offset of up to 31
steps. During the automatic alignment one first lets the PLL
lock to the appropriate frequency and then searches for the
The information stored in the NVM reflects the
characteristic of the individual tuner. For this reason, the
NVM is preferably situated inside the tuner and is also
2
controlled by the I C Bus.
Figure 4. Block Diagram
DA3
DA2
DA1
V
TUN
39 n
180 n
1.0 n
18 k
CC2
1.0 n
1.0 n
1.0 n
Bands and
Controls Out
V
33 V
4
17 16 15 14
8
7
6
5
Amp
In
Amp 4
Amp 3
Amp 2
Amp 1
B
B
B
B
1
7
5
3
3
Buffers
Bias
10 k
1.0 n
Test
Logic
D/A 3
6 Bit
D/A 2
6 Bit
D/A 1
6 Bit
Ref
Voltage
10 k
Latches
Latches
Latches
Latches
2
F
F
ref
out
V
PHO
CC1
5.0 V
F1
9
Decoder
DTC
Phase
Comp
Shift Register
8 Bit
10 k
F
F
ref
out
CA 13
(1)
DTB
Latches
Ref
Divider
FUN
18
CL
F1
62.5 kHz
SCL
15 k
2
I C Bus
Shift Register
15 Bit
Data
Receiver
SDA
1
XTAL
4.0 MHz
Osc
19
12
AD1
AD2
(2)
20 Gnd
DTF
Latches A
Latches B
Gnd
TDI
Preamp 1
Preamp 2
10
11
HF
1
÷
Presc
8
HF
2
Program Divider
15 Bit
Latch
Control
F
out
AVA
NOTES: 1. Pin 13: Short to V
for addresses CC, CE
for addresses C8, CA (values 10 k and 15 k) for test only
Open or 1.0 nF to Gnd for addresses C4, C6
Short to Gnd for addresses C0, C2
CC
Resistors ±10%
2. The crystal may be connected to Pin 20 with no connection to external Gnd.
7
MOTOROLA ANALOG IC DEVICE DATA
MC44864
Figure 5. TV Tuner for Automatic Alignment
IF
12 V
V
UHF VHF
BIII
CC3
Band Buffers
AGC
33 V
V
V
CC2
Mixer
Filter
Filter
5.0 V
Antenna
CC1
MC44864
PLL–D/A IC
SCL
SDA
HF Input
XTAL
Clock
Data
Local
Oscillator
D–to–A
Converters
V
Amp In
Phase Cmp
TUN
DA3
DA2
DA1
NVM
Figure 6. Definition of Bytes
CA1_PLL Chip Address
1
1
1
0
0
A
A
R
A
A = 0
0
ACK
3
2
1
CO_Control Information
BA_Band Information
R
T
P
X
R
R
R
0
ACK
ACK
6
3
2
1
B
7
X
B
5
B
3
X
B
1
X
FM_Frequency Information (with MSB)
FL_Frequency Information (with LSB)
0
N
N
N
N
N
N
N
N
ACK
ACK
14
13
12
11
10
9
1
8
0
N
N
N
N
N
N
2
N
7
6
5
4
3
Chip Addresses
PLL SECTION
The chip address is programmable by Pin CA.
The PLL addresses C0, C2, C4, C6 are officially allocated
to PLL–IC’s.
Data Format and Bus Receiver
The circuit receives the information for tuning and control
2
via I C Bus. The incoming information is treated in the bus
The addresses C8, CA, CC, CE are not officially allocated.
Care has to be taken in the application that no conflict occurs
receiver. The definition of the permissible bus protocol is
shown in the four examples below:
2
with other devices on the same I C Bus when using the
Ex. 1 STA CA1 CO
Ex. 2 STA CA1 FM
Ex. 3 STA CA1 CO
Ex. 4 STA CA1 FM
BA STO
FL STO
BA FM
FL CO
addresses C8 to CE.
FL
BA
STO
STO
CA Pin (13)
A
A
A
A
0
Address Function
3
2
1
STA = Start Condition
STO = Stop Condition
–0.04 V
0.1 V
to
0
0
0
0
0
1
0
0
C0
C2
1st PLL
1st DAC
CC1
CC1
CA1 = Chip Address Byte of the PLL Section
CO = Data Byte for Control Information
BA = Band Information
FM = Data Byte for Frequency Information (MSB’s)
FL = Data Byte for Frequency Information (LSB’s)
Open or 0.2
0
0
1
1
0
1
0
0
C4
C6
2nd PLL
2nd DAC
V
to0.3V
CC1
CC1
0.42 V
to
CC1
to 1.2
1
1
0
0
0
1
0
0
C8
CA
3rd PLL
3rd DAC
CC1
0.75 V
0.9 V
1
1
1
1
0
1
0
0
CC
CE
4th PLL
4th DAC
CC1
Figure 6 shows the five bytes of information that are
needed for circuit operation: there is a chip address, two
bytes of control and band information and two bytes of
frequency information.
V
CC1
8
MOTOROLA ANALOG IC DEVICE DATA
MC44864
After the chip address, two or four data bytes may be
Buffer B may also be used to output a 62.5 kHz frequency
5
received: if three data bytes are received, the third data byte
is ignored. If five or more data bytes are received, the fifth
and following data bytes are ignored and the last
acknowledge pulse is sent at the end of the fourth data byte.
The first and the third data bytes contain a function bit F. If
the function bit F= 0, frequency information is acknowledged
and if F = 1, control/band information is acknowledged.
If the address is correct (signal AD1) the information is
loaded into latches.
A function bit in the first and third data byte is used to pass
this data either into the latches of the programmable divider
(signal DTF) or into the latches for band and control information
(signal DTB). The data transfer to the latches (signals DTF and
DTB) is initiated after the 2nd and 4th data bytes.
from an intermediate stage of the reference divider. The bits
B and B have to be “one” if the buffers are used for these
5
7
additional functions.
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider, this double latch scheme is needed to
assure correct data transfer to the counter.
The division ratio definition is given by:
N = 16384 x N + 8192 x N + … + 4 x N + 2 x N + N
Maximum Ratio 32767
14
13
2
1
0
A second string of latches is used for the data transfer into
the programmable divider to inhibit the transfer during the
preset operation (signal TDI, signal AVA is an internal
“address valid” command).
Minimum Ratio 256
where N … N
information.
are the different bits for frequency
0
14
The switching levels of clock and data (Pins 18 and 19) are
The counter reloads correctly as long as its output
frequency does not exceed 1.0 MHz.
Division ratios of < 256 are not allowed. At power–up the
counter bit N8 is preset to “1”. All other bits are undetermined.
In this way, the counter always starts with a division ratio of
256 or higher.
The data transfer between latches A and B (signal TDI) is
also initiated by any start condition on the bus.
At power–on the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N = 256 or
higher.
0.5 x V
.
CC1
The control and band information bits have the following
functions.
Bits R , R : Controls Reference Divider Division Ratio
0
1
R
R
Division Ratio
0
1
0
1
0
1
0
2048
1024
512
0
1
1
256
Bits R , R : Switches Internal Signals to the Buffer
The Prescaler
2
3
Outputs
The prescaler has a preamplifier and may be bypassed
(Bit P). The signal then passes through preamplifier 2.
The table on the following page shows the frequency
ranges which may be synthesized with and without prescaler.
R
R
Pin 17
2
3
Pin 16
0
0
1
1
0
–
–
–
BY2
1
0
1
62.5 kHz
F
–
F
The Phase Comparator
ref
–
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.
Bit B has to be “one” when Pin 16 is used to output 62.5
5
kHz. Bits B and B have to be “one” to output F and F
ref
.
5
7
BY2
The Operational Amplifier
F
is the programmable divider output frequency divided
BY2
by two.
The operational amplifier for the tuning voltage is designed
for low noise, low input bias current and high power supply
rejection. The positive input is biased internally. The
Bits R , R , T: Controls the Phase Comparator Output
2
6
Stage
operational amplifier needs 30 V supply (V
) as minimum
CC2
voltage for a guaranteed maximum tuning voltage of 28.5 V.
Figure 4 shows the usual filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
As a starting point for optimization, the component values
in Figure 4 may be used for 7.8125 kHz reference frequency
in a multiband TV tuner.
R
R
T
Output State
Normal Operation
“Off” (High Impedance)
High
2
6
0
0
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
Low
Normal Operation
“Off”
Normal Operation
“Off”
The Oscillator
The oscillator uses a 4.0 MHz crystal tied to ground in
series with a capacitor. The crystal operates in the series
resonance mode.
The crystal is driven through a 1.6 kΩ resistor on chip.
The voltage at Pin 16 “crystal”, has low amplitude and low
harmonic distortion.
The Band Buffers
The band buffers are open collector transistors and are
active “low” at Bn = 1. They are designed for 15 mA with
typical on–voltage of 1.8 V. These buffers are designed to
withstand relative high output voltage in the off–state (15 V).
B
and B buffers (Pins 16 and 17) may also be used to
The negative resistance of the oscillator at Pin 1 (XTAL) is
about 3.0 kΩ.
5
7
output internal IC signals (reference frequency and
programmable divider output frequency divided by 2) for test
purposes.
9
MOTOROLA ANALOG IC DEVICE DATA
MC44864
With Int. Prescaler
P = 0
Without Prescaler
P = 1
Input Data
Ref. Divider
Div. Ratio
Ref. Freq.
(1)
Frequency
Steps kHz
Max. Input
Freq. MHz
Frequency
Steps kHz
Max. Imput
Freq. MHz
R
R
1
Hz
0
0
0
2048
1024
512
1953.125
3906.25
7812.5
15.625
31.25
62.5
512
1.953125
3.90625
7.8125
64
1
0
1
0
1
1
1024
128
(2)
1300
(2)
1300
(3)
165
(3)
165
256
15625.0
125.0
15.625
NOTES: 1. With 4.0 MHz Crystal
2. Limit of Prescaler
3. Limit of Programmable Divider
For satellite tuner applications the circuit may be used with an external /4 prescaler and a reference divider ration of 1024 (R = 1, R = 0). In this way,
0
1
frequencies up to 4.0 GHz can be synthesized with 125 kHz resolution (4.0 MHz crystal).
The same result can be achieved with an external /32 prescaler when the internal prescaler is bypassed (P = 1).
The Reference Divider
C contain the address for the individual converter and the 6
3
bits to be converted. Bit D is the sign (log “1” for positive
The reference divider of the MC44864 is programmable
(Bits R and R ) for ratios of 2048, 1024, 512 and 256. This
5
offset, log “0” for negative offset) and the bits D to D
0
4
0
1
determine the number of steps to be made as an offset from
the tuning voltage. The bits S and S in the data byte RA
feature makes the circuit versatile.
0
1
Bit P: Controls the Prescaler
define the step size (V
) and the range of the converters
step
(see Figures 8 and 9). The range is the same for all
converters.
P
Prescaler Function
0
1
Prescaler Active
After the chip address (CA2) is acknowledged, up to four
data bytes may be received by the IC. If more than four bytes
are received, the fifth and following bytes are ignored and the
last acknowledge pulse is sent after the fourth data byte. The
data transfer to the converters (signal DTC) is initiated each
time a complete data byte is received.
Prescaler Bypassed
Prescaler Power Supply “Off”
Bits B , B , B , B : Controls the Band Buffers
1
3
5
7
B , B , B , B = 0
Buffer “Off”
Buffer “On”
1
0
3
1
5
7
73
B , B , B, B = 1
The following shows some examples of the permissible
bus protocols of the D–to–A section. The data bytes may be
sent to the IC in random order with up to four in one
sequence. The same converter may be loaded up to four
times as shown in example 6. Below are 6 examples of
permissible bus protocols.
D/A SECTION
Basic Function
The D/A section has four separate chip addresses from
the PLL section. Three D–to–A converters that have a
resolution of 6 bits (5 bits plus sign) are on chip. The analog
output voltages are dc. The converters are buffered to the
analog outputs DA1, DA2 and DA3 by operational amplifiers
with an output voltage range that is equal to the tuning
voltage range (about 0 to 30 V). The operational amplifiers
are arranged such that a positive or negative offset can be
generated from the tuning voltage.
Ex. 1 STA CA2 C1 STO
Ex. 2 STA CA2 C1 C2 STO
Ex. 3 STA CA2 C1 C2 C3 STO
Ex. 4 STA CA2 C1 C2 C3 RA
Ex. 5 STA CA2 RA C1 C2 C3
Ex. 6 STA CA2 C1 C1 C1 C1
STO
STO
STO
STA = Start Condition
STO = Stop Condition
Data Format and Bus Protocols
The D–to–A information consists of the D/A chip address
(CA2) and four data bytes. The first two bits of the data bytes
are used as the function address. Thus the bytes C , C and
CA2 = Chip Address Byte for D/A Section
C1, C2, C3 = Data Bytes for D/A Converters
RA = Data Byte for Range
1
2
Figure 7. Definition of Bytes
CA2_D/A Chip Address
C1_Converter 1
1
0
0
1
1
1
0
1
0
1
0
0
A
A
D
D
D
A = 0
0
ACK
ACK
ACK
ACK
ACK
2
1
2
2
2
D
D
D
D
D
D
D
D
D
D
D
5
5
5
4
4
4
3
3
3
1
1
1
1
0
0
0
0
C2_Converter 2
D
D
D
D
C3_Converter 3
RA_Range Selection
X
X
X
X
S
S
10
MOTOROLA ANALOG IC DEVICE DATA
MC44864
currents are then converted into voltages and added to their
respective operational amplifier nominal bias. The resulting
voltages at Pins 6, 7 and 8 are the tuning voltages (V , see
Figure 4) at Pin 5 plus any offset provided by information in
the D/A converters.
Figure 8. Output Voltage (D/A Converters)
V
= V
± V (D +2 D +4 D +8 D + 16 D )
step 0 1 2 3 4
DA
TUN
TUN
D
= 1 positive sign; D = 0 negative sign
5
5
V
V
: Tuning Voltage set by PLL
TUN
: Voltage Step (LSB) of the D/A Converters
If the data bits D to D are all “0”, the three D/A output
0
4
step
voltages on Pins 6, 7 and 8 are equal to the tuning voltage
(Pin 5) within the DAC offset voltages.
The four amplifiers have the same output characteristics
with the maximum output voltage being 1.5 V lower than
Figure 9. Range Selection of the D/A Converters
V
in the worst case. The four analog outputs are
CC2
Guaranteed
Range 31
Steps
Input Data
short–circuit protected. At power–up, the D/A outputs are
undetermined.
Typ. Step Size
V
step
S
0
S
1
The D/A converters are guaranteed to be monotonic with a
voltage step variation of ±0.5 LSB.
0
0
225 mV
125 mV
70 mV
40 mV
6.25 V
3.40 V
1.90 V
1.05 V
1
0
1
0
1
1
The D/A converters work correctly as long as the PLL loop
is active. V
is then between 0.3 V and V
– 1.5 V. If the
TUN
loop saturates, the DACs do not work.
The DAC–OFFSET is defined as the difference between
the DAC output voltage (with bits D to D = 0) and the tuning
CC2
The D/A Converters
The D/A converters convert 5 bit into analog current of
which the polarity is switched by the sixth bit. The reference
voltage of the converters is programmed by two bits (S , S
of the RA–byte) to determine the scaling factor. The analog
0
4
voltage (PLL active). The DAC operation is guaranteed from
0.3 V to V – 1.5 V. On typical samples, the DACs will
operate down to 0.2 V.
CC2
0
1
Figure 10. Definition of DAC Offset
DAC Offset
– V
(V
DAC
)
TUN
±700 mVmax
±50 mVmax
10
20
30 V
V
TUN
11
MOTOROLA ANALOG IC DEVICE DATA
MC44864
OUTLINE DIMENSIONS
M SUFFIX
PLASTIC PACKAGE
CASE 967–01
(EIAJ–20)
ISSUE O
NOTES:
1
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2
3
CONTROLLING DIMENSION: MILLIMETER.
DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
E
20
11
Q
1
4
5
TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
E
M
THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
e
A
DIM
A
1
b
c
D
E
e
MIN
–––
MAX
2.05
0.20
0.50
0.27
12.80
5.45
MIN
MAX
0.081
0.008
0.020
0.011
0.504
0.215
c
–––
0.002
0.014
0.007
0.486
0.201
A
0.05
0.35
0.18
12.35
5.10
A
b
1
1.27 BSC
0.050 BSC
M
0.10 (0.004)
0.13 (0.005)
H
7.40
0.50
1.10
0
8.20
0.85
1.50
10
0.291
0.020
0.043
0
0.323
0.033
0.059
10
E
L
L
M
E
Q
Z
0.70
–––
0.90
0.81
0.028
–––
0.035
0.032
1
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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MC44864/D
◊
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