MC68HC08AZ60FU [MOTOROLA]
Microcontroller, 8-Bit, MROM, 8.4MHz, HCMOS, PQFP64, 14 X 14 MM, 0.80 MM PITCH, 2.20 MM HEIGHT, PLASTIC, QFP-64;型号: | MC68HC08AZ60FU |
厂家: | MOTOROLA |
描述: | Microcontroller, 8-Bit, MROM, 8.4MHz, HCMOS, PQFP64, 14 X 14 MM, 0.80 MM PITCH, 2.20 MM HEIGHT, PLASTIC, QFP-64 |
文件: | 总452页 (文件大小:3298K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MC68HC08AZ60/ D
MC68HC08AZ60
MC68HC08AZ48
Ad va nc e Inform a tion
Re v 1.0
Ma rc h 20, 2000
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
List of Se c tions
List of Se c tions
List of Se c tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ta b le of Conte nts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ge ne ra l De sc rip tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
HC08AZ60 Me m ory Ma p . . . . . . . . . . . . . . . . . . . . . . . . . 23
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ROM-1 Me m ory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
ROM-2 Me m ory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
EEPROM-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
EEPROM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Ce ntra l Proc e ssor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . 65
Syste m Inte g ra tion Mod ule (SIM). . . . . . . . . . . . . . . . . . 83
Cloc k Ge ne ra tor Mod ule (CGM). . . . . . . . . . . . . . . . . 105
Ma sk Op tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Bre a k Mod ule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
© Motorola, Inc., 2000
MOTOROLA
MC68HC08AZ60 — Rev 1.0
List of Sections
3
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Go to: www.freescale.com
Freescale Semiconductor, Inc.
List of Se c tions
Com p ute r Op e ra ting Prop e rly Mod ule (COP) . . . . . . 153
Low-Volta g e Inhib it (LVI) . . . . . . . . . . . . . . . . . . . . . . . 159
Exte rna l Inte rrup t Mod ule (IRQ) . . . . . . . . . . . . . . . . . . 165
Se ria l Com m unic a tions Inte rfa c e Mod ule (SCI). . . . . 173
Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI) . . . . . . . . . . . 211
Tim e r Inte rfa c e Mod ule B (TIMB) . . . . . . . . . . . . . . . . . 243
Mod ulo Tim e r (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
I/ O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
MSCAN Controlle r (MSCAN08). . . . . . . . . . . . . . . . . . . 305
Ke yb oa rd Mod ule (KBD). . . . . . . . . . . . . . . . . . . . . . . . 355
Tim e r Inte rfa c e Mod ule A (TIMA-6) . . . . . . . . . . . . . . . 363
Ana log -to-Dig ita l Conve rte r (ADC-15) . . . . . . . . . . . . 395
Sp e c ific a tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Ap p e nd ix A: Future EEPROM Re g iste rs . . . . . . . . . . . . 421
Ap p e nd ix B: HC08AZ48 Me m ory Ma p . . . . . . . . . . . . . 425
Glossa ry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Lite ra ture Up d a te s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
MC68HC08AZ60 — Rev 1.0
4
List of Sections
MOTOROLA
For More Information On This Product,
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Freescale Semiconductor, Inc.
Ta b le of Conte nts
Ta b le of Conte nts
List of Sections
Table of Contents
General Description
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
HC08AZ60 Memory
Map
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
RAM
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
ROM-1 Memory
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
ROM-2 Memory
EEPROM-1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Future EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
MC68HC08AZ60 — Rev 1.0
MOTOROLA
Table of Contents
5
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Ta b le of Conte nts
EEPROM-2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Future EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Central Processor
Unit (CPU)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
System Integration
Module (SIM)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . .87
Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Program Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Clock Generator
Module (CGM)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . . . . . .126
Mask Options
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
MC68HC08AZ60 — Rev 1.0
6
Table of Contents
MOTOROLA
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Table of Contents
Break Module
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Monitor ROM
(MON)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Computer
Operating Properly
Module (COP)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 158
Low-Voltage Inhibit
(LVI)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
External Interrupt
Module (IRQ)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 170
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Serial
Communications
Interface
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Module (SCI)
MC68HC08AZ60 — Rev 1.0
MOTOROLA
Table of Contents
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Ta b le of Conte nts
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .193
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
Serial Peripheral
Interface Module
(SPI)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
Pin Name and Register Name Conventions . . . . . . . . . . . . . . . . . . .213
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
Timer Interface
Module B (TIMB)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
TIMB During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Modulo Timer (TIM)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
I/O Ports
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
MC68HC08AZ60 — Rev 1.0
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Table of Contents
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Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
MSCAN Controller
(MSCAN08)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . 329
Programmer’s Model of Control Registers . . . . . . . . . . . . . . . . . . . 334
Keyboard Module
(KBD)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 360
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Timer Interface
Module A (TIMA-6)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
TIMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
MC68HC08AZ60 — Rev 1.0
MOTOROLA
Table of Contents
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Ta b le of Conte nts
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
Analog-to-Digital
Converter (ADC-15)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401
Specifications
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408
Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
Appendix A: Future
EEPROM Registers
EEPROM Timebase Divider Control Registers . . . . . . . . . . . . . . . .421
EEDIVH and EEDIVL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .422
EEDIV Non-volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423
Appendix B:
HC08AZ48 Memory
Map
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428
Glossary
Literature Updates
Literature Distribution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .449
Customer Focus Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450
Microcontroller Division’s Web Site . . . . . . . . . . . . . . . . . . . . . . . . .450
MC68HC08AZ60 — Rev 1.0
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Ge ne ra l De sc rip tion
Ge ne ra l De sc rip tion
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . 16
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Analog Power Supply Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . 17
Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . . . . . . . . . 17
Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) . . . . . . . . . . . . . . . . . . 17
Port C I/O Pins (PTC5–PTC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Port D I/O Pins (PTD7–PTD0/ATD8) . . . . . . . . . . . . . . . . . . . . . . . 18
Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) . . . . . . . . . . . . . . . . . . 18
Port F I/O Pins (PTF6–PTF0/TACH2). . . . . . . . . . . . . . . . . . . . . . . 18
Port G I/O Pins (PTG2/KBD2–PTG0/KBD0). . . . . . . . . . . . . . . . . . 18
Port H I/O Pins (PTH1/KBD4–PTH0/KBD3) . . . . . . . . . . . . . . . . . . 18
CAN Transmit Pin (CANTx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CAN Receive Pin (CANRx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MC Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Introd uc tion
The MC68HC08AZ60 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
1-gen
MC68HC08AZ60 — Rev 1.0
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Ge ne ra l De sc rip tion
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
Fe a ture s
Features of the MC68HC08AZ60 include:
• High-Performance M68HC08 Architecture
• Fully Upward-Compatible Object Code with M6805, M146805,
and M68HC05 Families
• 8.4 MHz Internal Bus Frequency
• 60 Kbytes of Read-Only Memory (ROM)
• 1 Kbyte of On-Chip Electrically Erasable Programmable
Read-Only Memory with Security Option (EEPROM)
• 2 Kbyte of On-Chip RAM
• Clock Generator Module (CGM)
• Serial Peripheral Interface Module (SPI)
• Serial Communications Interface Module (SCI)
• 8-Bit, 15-Channel Analog-to-Digital Converter (ADC-15)
• 16-Bit, 6-Channel Timer Interface Module (TIMA-6)
• Periodic Interrupt Timer (TIM)
• System Protection Features
– Computer Operating Properly (COP) with Optional Reset
– Low-Voltage Detection with Optional Reset
– Illegal Opcode Detection with Optional Reset
– Illegal Address Detection with Optional Reset
• Low-Power Design (Fully Static with Stop and Wait Modes)
• Master Reset Pin and Power-On Reset
2-gen
MC68HC08AZ60 — Rev 1.0
12
General Description
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General Description
MCU Block Diagram
Features of the CPU08 include:
• Enhanced HC05 Programming Model
• Extensive Loop Control Functions
• 16 Addressing Modes (Eight More Than the HC05)
• 16-Bit Index Register and Stack Pointer
• Memory-to-Memory Data Transfers
• Fast 8 × 8 Multiply Instruction
• Fast 16/8 Divide Instruction
• Binary-Coded Decimal (BCD) Instructions
• Optimization for Controller Applications
• C Language Support
• 16-Bit, 2-Channel Timer Interface Module (TIMB)
• 5-Bit Keyboard Interrupt Module
• MSCAN Controller (Motorola Scalable CAN) implements CAN
2.0b Protocol as Defined in BOSCH Specification September
1991
MCU Bloc k Dia g ra m
Figure 1 shows the structure of the MC68HC08AZ60.
3-gen
MC68HC08AZ60 — Rev 1.0
13
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Ge ne ra l De sc rip tion
F P T
D D R F
G P T
D D R G
A P T
D D R A
B P T
C P T
D D R C
H P T
E P T
D R D E
D P T
D D R D
D D R B
D D R H
4-gen
MC68HC08AZ60 — Rev 1.0
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General Description
Pin Assignments
Pin Assig nm e nts
Figure 2 shows the MC68HC08AZ60 pin assignments.
PTC4
IRQ
PTH0/KBD3
PTD3/ATD11
PTD2/ATD10
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
RST
3
PTF0/TACH2
PTF1/TACH3
PTF2/TACH4
PTF3/TACH5
PTF4/TBCH0
CANRx
AV /V
4
SS REFL
V
5
DDAREF
PTD1/ATD9
6
PTD0/ATD8
PTB7/ATD7
7
8
PTB6/ATD6
PTB5/ATD5
PTB4/ATD4
PTB3/ATD3
PTB2/ATD2
PTB1/ATD1
PTB0/ATD0
PTA7
9
CANTx
10
11
12
13
14
15
PTF5/TBCH1
PTF6
PTE0/TxD
PTE1/RxD
PTE2/TACH0
PTE3/TACH1
16
Figure 2. MC68HC08AZ60 (64-Pin QFP)
NOTE: The following pin descriptions are just a quick reference. For a more
detailed representation, see I/O Ports on page 279.
5-gen
MC68HC08AZ60 — Rev 1.0
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Powe r Sup p ly Pins
(VDD a nd VSS)
V
DD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as shown in Figure
3. Place the C1 bypass capacitor as close to the MCU as possible. Use
a high-frequency response ceramic capacitor for C1. C2 is an optional
bulk current bypass capacitor for use in applications that require the port
pins to source high current levels.
MCU
V
V
SS
DD
C1
0.1 µF
+
C2
V
DD
NOTE: Component values shown represent typical applications.
Figure 3. Power supply bypassing
VSS is also the ground for the port output buffers and the ground return
for the serial clock in the serial peripheral interface module (SPI). See
Serial Peripheral Interface Module (SPI) on page 211.
NOTE: VSS must be grounded for proper MCU operation.
Osc illa tor Pins
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
(OSC1 a nd OSC2)
circuit. See Clock Generator Module (CGM) on page 105.
6-gen
MC68HC08AZ60 — Rev 1.0
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General Description
Pin Assignments
Exte rna l Re se t Pin
(RST)
A logic 0 on the RST pin forces the MCU to a known startup state. RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted. See
System Integration Module (SIM) on page 83 for more information.
Exte rna l Inte rrup t
Pin (IRQ)
IRQ is an asynchronous external interrupt pin. See
External Interrupt Module (IRQ) on page 165.
Ana log Powe r
Sup p ly Pin (VDDA
VDDA is the power supply pin for the analog portion of the chip. This pin
will supply the clock generator module (CGM). See
)
Clock Generator Module (CGM) on page 105.
Ana log Ground
The VSSA analog ground pin is used only for the ground connections for
the analog sections of the circuit and should be decoupled as per the
Pin (VSSA
)
V
SS digital ground pin. The analog sections consist of a clock generator
module (CGM). See Clock Generator Module (CGM) on page 105.
Exte rna l Filte r
Ca p a c itor Pin
(CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. See
Clock Generator Module (CGM) on page 105
Port A
Inp ut/ Output (I/ O)
PTA7–PTA0 are general-purpose bidirectional I/O port pins. See I/O
Ports on page 279.
Pins (PTA7–PTA0)
Port B I/ O Pins
(PTB7/ ATD7–PTB0/
ATD0)
Port B is an 8-bit special function port that shares all eight pins with the
analog-to-digital converter (ADC). See
Analog-to-Digital Converter (ADC-15) on page 395 and I/O Ports on
page 279.
Port C I/ O Pins
(PTC5–PTC0)
PTC5–PTC3 and PTC1–PTC0 are general-purpose bidirectional I/O
port pins. PTC2/MCLK is a special function port that shares its pin with
7-gen
MC68HC08AZ60 — Rev 1.0
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Ge ne ra l De sc rip tion
the system clock which has a frequency equivalent to the system clock.
See I/O Ports on page 279.
Port D I/ O Pins
(PTD7–PTD0/ ATD8)
Port D is an 8-bit special-function port that shares seven of its pins with
the analog-to-digital converter module (ADC-15), one of its pins with the
timer interface module (TIMA), and one more of its pins with the timer
interface module (TIMB). See Timer Interface Module A (TIMA-6) on
page 363, Analog-to-Digital Converter (ADC-15) on page 395 and I/O
Ports on page 279.
Port E I/ O Pins
(PTE7/ SPSCK–PTE0/
TxD)
Port E is an 8-bit special function port that shares two of its pins with the
timer interface module (TIMA), four of its pins with the serial peripheral
interface module (SPI), and two of its pins with the serial communication
interface module (SCI). See
Serial Communications Interface Module (SCI) on page 173,
Serial Peripheral Interface Module (SPI) on page 211,
Timer Interface Module A (TIMA-6) on page 363, and I/O Ports on
page 279.
Port F I/ O Pins
(PTF6–PTF0/ TACH2)
Port F is a 7-bit special function port that shares its pins with the timer
interface module (TIMB). Six of its pins are shared with the timer
interface module (TIMA-6). See Timer Interface Module A (TIMA-6) on
page 363, Modulo Timer (TIM) on page 269, and I/O Ports on page
279.
Port G I/ O Pins
(PTG2/ KBD2–PTG0
/ KBD0)
Port G is a 3-bit special function port that shares all of its pins with the
keyboard interrupt module (KBD). See Keyboard Module (KBD) on
page 355 and I/O Ports on page 279.
Port H I/ O Pins
(PTH1/ KBD4–PTH0/
KBD3)
Port H is a 2-bit special-function port that shares all of its pins with the
keyboard interrupt module (KBD). See Keyboard Module (KBD) on
page 355 and I/O Ports on page 279.
8-gen
MC68HC08AZ60 — Rev 1.0
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General Description
Pin Assignments
CAN Tra nsm it Pin
(CANTx)
This pin is the digital output from the CAN module (CANTx). See
MSCAN Controller (MSCAN08) on page 305.
CAN Re c e ive Pin
(CANRx)
This pin is the digital input to the CAN module (CANRx). See MSCAN
Controller (MSCAN08) on page 305.
Table 1. External Pins Summary
Driver
Type
Pin Name
Function
Hysteresis Reset State
PTA7–PTA0
General-Purpose I/O
Dual State
No
No
Input Hi-Z
Input Hi-Z
General-Purpose I/O
ADC Channel
PTB7/ATD7–PTB0/ATD0
Dual State
PTC5–PTC0
PTD7
General-Purpose I/O
General Purpose I/O/
Dual State
Dual State
No
No
Input Hi-Z
Input Hi-Z
General-Purpose I/O
ADC Channel/Timer
External Input Clock
PTD6/ATD14/TACLK ** ADC Channel
PTD5/ATD13 ** ADC Channel
Dual State
Dual State
No
No
No
Input Hi-Z
General-Purpose I/O
ADC Channel
Input Hi-Z
Input Hi-Z
General-Purpose I/O
ADC Channel/Timer
External Input Clock
PTD4/ATD12/TBCLK ** ADC Channel
Dual State
Dual State
PTD3/ATD11–PTD0/ATD8 **ADC
Channels
General-Purpose I/O
ADC Channel
Input Hi-Z
No
General-Purpose I/O
SPI Clock
Dual State
Open Drain
PTE7/SPSCK
PTE6/MOSI
PTE5/MISO
PTE4/SS
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Input Hi-Z
Input Hi-Z
Input Hi-Z
Input Hi-Z
Input Hi-Z
Input Hi-Z
Input Hi-Z
General-Purpose I/O
SPI Data Path
Dual State
Open Drain
General-Purpose I/O
SPI Data Path
Dual State
Open Drain
General-Purpose I/O
SPI Slave Select
Dual State
Dual State
Dual State
Dual State
General-Purpose I/O
Timer Channel 1
PTE3/TACH1
PTE2/TACH0
PTE1/RxD
General-Purpose I/O
Timer Channel 0
General-Purpose I/O
SCI Receive Data
9-gen
MC68HC08AZ60 — Rev 1.0
19
MOTOROLA
General Description
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Ge ne ra l De sc rip tion
Table 1. External Pins Summary (Continued)
Driver
Pin Name
Function
Type
Hysteresis Reset State
General-Purpose I/O
Dual State
PTE0/TxD
PTF6
No
No
Input Hi-Z
Input Hi-Z
Input Hi-Z
SCI Transmit Data
General-Purpose I/O
Dual State
Dual State
General-Purpose
PTF5/TBCH1–PTF4/TBCH0
Yes
I/O/Timer B Channel
General-Purpose I/O
Timer A Channel 5
PTF3/TACH5
PTF2/TACH4
Dual State
Dual State
Dual State
Dual State
Dual State
Dual State
Yes
Yes
Yes
Yes
Yes
Yes
Input Hi-Z
Input Hi-Z
Input Hi-Z
Input Hi-Z
Input Hi-Z
Input Hi-Z
General-Purpose I/O
Timer A Channel 4
General-Purpose I/O
Timer A Channel 3
PTF1/TACH3
General-Purpose I/O
Timer A Channel 2
PTF0/TACH2
General-Purpose I/O/
Keyboard Wakeup Pin
PTG2/KBD2–PTG0/KBD0
PTH1/KBD4 –PTH0/KBD3
General-Purpose I/O/
Keyboard Wakeup Pin
VDD
VSS
Chip Power Supply
Chip Ground
N/A
N/A
N/A
N/A
N/A
N/A
ADC Power Supply/
ADC Reference
Voltage
AVDD/VDDAREF
N/A
N/A
N/A
ADC Ground/ADC
Reference Voltage
AVSS/VREFL
VREFH
N/A
N/A
N/A
N/A
N/A
N/A
A/D Reference
Voltage
OSC1
OSC2
External Clock In
External Clock Out
PLL Loop Filter Cap
N/A
N/A
N/A
N/A
N/A
N/A
Input Hi-Z
Output
N/A
CGMXFC
External Interrupt
Request
IRQ
N/A
N/A
Input Hi-Z
RST
Reset
N/A
N/A
N/A
Yes
No
Output Low
Input Hi-Z
Output
CANRx
CANTx
CAN Serial Input
CAN Serial Output
Output
10-gen
MC68HC08AZ60 — Rev 1.0
20
General Description
MOTOROLA
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General Description
Pin Assignments
Table 2. Clock Source Summary
Module
ADC
CAN
COP
CPU
EEPROM
SPI
Clock Source
CGMXCLK or Bus Clock
CGMXCLK or CGMOUT
CGMXCLK
Bus Clock
RC OSC or Bus Clock
Bus Clock/SPSCK
CGMXCLK
SCI
TIMA-6
TIMB
TIM
Bus Clock or PTD6/ATD14/TACLK
Bus Clock or PTD4/TBCLK
Bus Clock
SIM
CGMOUT and CGMXCLK
Bus Clock
IRQ
BRK
Bus Clock
LVI
Bus Clock
CGM
OSC1 and OSC2
11-gen
MC68HC08AZ60 — Rev 1.0
21
MOTOROLA
General Description
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Ge ne ra l De sc rip tion
Ord e ring Inform a tion
This section contains instructions for ordering the MC68HC08AZ60 and
MC68HC08AZ48.
MC Ord e r
Num b e rs
Table 3. MC Order Numbers
Operating
MC Order Number
Temperature Range
MC68HC08AZ60CFU
MC68HC08AZ60VFU
MC68HC08AZ60MFU
MC68HC08AZ48CFU
MC68HC08AZ48VFU
MC68HC08AZ48MFU
–40 °C to + 85°C
–40 °C to + 105 °C
–40 °C to + 125 °C
–40 °C to + 85°C
–40 °C to + 105 °C
–40 °C to + 125 °C
12-gen
MC68HC08AZ60 — Rev 1.0
22
General Description
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HC08AZ60 Me m ory Ma p
HC08AZ60 Me m ory Ma p
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Introd uc tion
The CPU08 can address 64 Kbytes of memory space. The memory
map, shown in Figure 1, includes:
• 60 Kbytes of ROM
• 2048 Bytes of RAM
• 1024 Bytes of EEPROM with Protect Option
• 52 Bytes of User-Defined Vectors
• 224 Bytes of Monitor ROM
The following definitions apply to the memory map representation of
reserved and unimplemented locations.
•
•
Reserved — Accessing a reserved location can have
unpredictable effects on MCU operation.
Unimplemented — Accessing an unimplemented location
causes an illegal address reset if illegal address resets are
enabled.
1-mem60
MC68HC08AZ60 — Rev 1.0
23
MOTOROLA
HC08AZ60 Memory Map
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HC08AZ60 Me m ory Ma p
Figure 1. Memory Map
$0000
↓
$0000
↓
I/O REGISTERS (64 BYTES)
$003F
$0040
↓
$003F
$0040
↓
I/O REGISTERS, 16 BYTES
RAM-1, 1024 BYTES
ROM-2, 176 BYTES
$004F
$0050
↓
$004F
$0050
↓
$044F
$0450
↓
$044F
$0450
↓
$04FF
$0500
↓
$04FF
$0500
↓
CAN CONTROL AND MESSAGE
BUFFERS, 128 BYTES
$057F
$0580
↓
$057F
$0580
↓
ROM-2, 128 BYTES
EEPROM-2, 512 BYTES
EEPROM-1, 512 BYTES
RAM-2 , 1024 BYTES
ROM-2, 29,184 BYTES
ROM-1, 32,256BYTES
$05FF
$0600
↓
$05FF
$0600
↓
$07FF
$0800
↓
$07FF
$0800
↓
$09FF
$0A00
↓
$09FF
$0A00
↓
$0DFF
$0E00
↓
$0DFF
$0E00
↓
$7FFF
$8000
↓
$7FFF
$8000
↓
$FDFF
$FE00
$FE01
$FE02
$FE03
$FE04
$FDFF
$FE00
$FE01
$FE02
$FE03
$FE04
SIM BREAK STATUS REGISTER (SBSR)
SIM RESET STATUS REGISTER (SRSR)
RESERVED
SIM BREAK FLAG CONTROL REGISTER (SBFCR)
RESERVED
2-mem60
MC68HC08AZ60 — Rev 1.0
24
HC08AZ60 Memory Map
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HC08AZ60 Memory Map
Introduction
Figure 1. Memory Map (Continued)
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
RESERVED
UNIMPLEMENTED
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED)
BREAK ADDRESS REGISTER HIGH (BRKH)
BREAK ADDRESS REGISTER LOW (BRKL)
$FE0E BREAK STATUS AND CONTROL REGISTER (BSCR) $FE0E
$FE0F
$FE10
$FE11
$FE12
↓
LVI STATUS REGISTER (LVISR)
RESERVED
$FE0F
$FE10
$FE11
$FE12
↓
RESERVED
UNIMPLEMENTED (5BYTES)
$FE17
$FE18
$FE19
$FE1A
$FE1B
$FE1C
$FE1D
$FE1E
$FE1F
$FE20
↓
$FE17
$FE18
$FE19
$FE1A
$FE1B
$FE1C
$FE1D
$FE1E
$FE1F
$FE20
↓
EEPROM NON-VOLATILE REGISTER (EENVR2)
EEPROM CONTROL REGISTER (EECR2)
RESERVED
EEPROM ARRAY CONFIGURATION (EEACR2)
EEPROM NON-VOLATILE REGISTER (EENVR1)
EEPROM CONTROL REGISTER (EECR1)
RESERVED
EEPROM ARRAY CONFIGURATION (EEACR1)
MONITOR ROM (224 BYTES)
UNIMPLEMENTED (128 BYTES)
$FEFF
$FEFF
$FF00
↓
$FF00
↓
$FF7F
$FF7F
$FF80
$FF81
$FF82
↓
RESERVED
RESERVED
$FF80
$FF81
$FF82
↓
RESERVED (75 BYTES)
VECTORS (52BYTES)
$FFCB
$FFCC
↓
$FFCB
$FFCC
↓
$FFFF
$FFFF
3-mem60
MC68HC08AZ60 — Rev 1.0
25
MOTOROLA
HC08AZ60 Memory Map
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HC08AZ60 Me m ory Ma p
I/ O Se c tion
Addresses $0000–$003F, shown in Figure 2, contain most of the
control, status, and data registers. Additional I/O registers have these
addresses:
• $FE00 (SIM break status register, SBSR)
• $FE01 (SIM reset status register, SRSR)
• $FE03 (SIM break flag control register, SBFCR)
• $FE09 (configuration write-once register, CONFIG-2)
• $FE0C and $FE0D (break address registers, BRKH and BRKL)
• $FE0E (break status and control register, BRKSCR)
• $FE0F (LVI status register, LVISR)
• $FE18 (EEPROM non-volatile register, EENVR2)
• $FE19 (EEPROM control register, EECR2)
• $FE1B (EEPROM array configuration register, EEACR2)
• $FE1C (EEPROM non-volatile register, EENVR1)
• $FE1D (EEPROM control register, EECR1)
• $FE1F (EEPROM array configuration register, EEACR1)
• $FFFF (COP control register, COPCTL)
Table 1 is a list of vector locations.
4-mem60
MC68HC08AZ60 — Rev 1.0
26
HC08AZ60 Memory Map
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HC08AZ60 Memory Map
I/O Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$0000
Port A Data Register (PTA)
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
Port B Data Register (PTB)
Port C Data Register (PTC)
Port D Data Register (PTD)
PTB7
0
PTB6
0
PTB5
PTC5
PTD5
PTB4
PTC4
PTD4
PTB3
PTC3
PTD3
PTB2
PTC2
PTD2
PTB1
PTC1
PTD1
PTB0
PTC0
PTD0
PTD7
PTD6
Data Direction Register A
(DDRA)
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Data Direction Register B
(DDRB)
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
0
Data Direction Register C
(DDRC)
MCLKEN
DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Data Direction Register D
(DDRD)
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDR2 DDRD1 DDRD0
Port E Data Register (PTE)
Port F Data Register (PTF)
Port G Data Register (PTG)
Port H Data Register (PTH)
PTE7
0
PTE6
PTE5
PTE4
PTE3
PTE2
PTF2
PTE1
PTF1
PTG1
PTH1
PTE0
PTF0
PTG0
PTH0
PTF6
0
PTF5
0
PTF4
0
PTF3
0
0
0
PTG2
0
0
0
0
0
Data Direction Register E
(DDRE)
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
0
Data Direction Register F
(DDRF)
DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
0
0
0
0
0
0
0
0
0
0
Data Direction Register G
(DDRG)
DDRG2 DDRG1 DDRG0
0
Data Direction Register H
(DDRH)
DDRH1 DDRH0
SPI Control Register (SPCR)
SPRIE
R
SPMSTR CPOL
CPHA SPWOM SPE
SPTIE
= Unimplemented
R
= Reserved
Figure 2. Control, Status, and Data Registers (Sheet 1 of 6)
5-mem60
MC68HC08AZ60 — Rev 1.0
27
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HC08AZ60 Memory Map
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Addr.
Register Name
Bit 7
Read: SPRF
Write:
6
5
4
3
2
1
Bit 0
OVRF
MODF
SPTE
SPI Status and Control
Register (SPSCR)
MODFE
N
$0011
ERRIE
SPR1
SPR0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0020
$0021
$0022
SPI Data Register (SPDR)
SCI Control Register 1 (SCC1)
SCI Control Register 2 (SCC2)
SCI Control Register 3 (SCC3)
SCI Status Register 1 (SCS1)
SCI Status Register 2 (SCS2)
SCI Data Register (SCDR)
LOOPS ENSCI TXINV
M
WAKE
TE
ILTY
RE
PEN
PTY
SBK
SCTIE
R8
TCIE
SCRIE
ILIE
RWU
T8
R
R
ORIE
OR
NEIE
NF
FEIE
FE
PEIE
PE
Read: SCTE
Write:
TC
SCRF
IDLE
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
0
0
0
0
0
BKF
RPF
R7
T7
0
R6
T6
0
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SCI Baud Rate Register (SCBR)
SCP1
0
SCP0
0
SCR2
SCR1
SCR0
0
0
0
IRQF
KEYF
1
0
ACK1
0
IRQ Status and Control
Register (ISCR)
IMASK1 MODE1
IMASKK MODEK
0
0
0
Keyboard Status and Control
Register (KBSCR)
ACKK
1
PLLF
LOCK
1
0
1
0
PLL Control Register (PCTL)
PLLIE
AUTO
MUL7
PLLON
ACQ
BCS
XLD
0
0
PLL Bandwidth Control
Register (PBWC)
PLL Programming Register
(PPG)
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
Read: LVISTOP ROMSEC LVIRST LVIPWR SSREC COPRS STOP
COPD
R
Mask Option Register
(MOR)
Write:
R
R
TOIE
0
R
TSTOP
0
R
0
R
0
R
R
Read: TOF
Timer A Status and Control
Register (TASC)
PS2
PS1
PS0
Write:
Read:
Write:
0
0
TRST
Keyboard Interrupt Enable Register
(KBIE)
KBIE4
12
KBIE3
11
KBIE2
10
KBIE1
9
KBIE0
Bit 8
Read: Bit 15
Write:
14
13
Timer A Counter Register
High (TACNTH)
Figure 2. Control, Status, and Data Registers (Sheet 2 of 6)
6-mem60
MC68HC08AZ60 — Rev 1.0
28
HC08AZ60 Memory Map
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HC08AZ60 Memory Map
I/O Section
Addr.
Register Name
Bit 7
Read: Bit 7
Write:
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
Timer A Counter Register
Low (TACNTL)
$0023
Read:
Bit 15
Write:
Timer A Modulo Register
High (TAMODH)
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002C
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
Read:
Bit 7
Timer A Modulo Register
Low (TAMODL)
Write:
Read: CH0F
Timer A Channel 0 Status and
Control Register (TASC0)
CH0IE
14
MS0B
13
MS0A
12
ELS0B ELS0A TOV0 CH0MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 0 Register
High (TACH0H)
Bit 15
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 0 Register
Low (TACH0L)
Bit 7
6
5
0
4
Read: CH1F
Timer A Channel 1 Status and
Control Register (TASC1)
CH1IE
14
MS1A
12
ELS1B ELS1A TOV1 CH1MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 1 Register
High (TACH1H)
Bit 15
13
5
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 1 Register
Low (TACH1L)
Bit 7
6
4
Read: CH2F
Timer A Channel 2 Status and
Control Register (TASC2)
CH2IE
14
MS2B
13
MS2A
12
ELS2B ELS2A TOV2 CH2MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 2 Register
High (TACH2H)
Bit 15
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 2 Register
Low (TACH2L)
Bit 7
6
5
0
4
Read: CH3F
Timer A Channel 3 Status and
Control Register (TASC3)
CH3IE
14
MS3A
12
ELS3B ELS3A TOV3 CH3MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 3 Register
High (TACH3H)
Bit 15
13
5
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 3 Register
Low (TACH3L)
Bit 7
6
4
Read: CH4F
Timer A Channel 4 Status and
Control Register (TASC4)
CH4IE
14
MS4B
13
MS4A
12
ELS4B ELS4A TOV4 CH4MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 4 Register High
(TACH4H)
Bit 15
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 4 Register Low
(TACH4L)
Bit 7
6
5
4
Figure 2. Control, Status, and Data Registers (Sheet 3 of 6)
7-mem60
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29
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HC08AZ60 Me m ory Ma p
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH5F
0
Timer A Channel 5 Status and
Control Register (TASC5)
$0035
CH5IE
MS5A
ELS5B ELS5A TOV5 CH5MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 5 Register
High (TACH5H)
$0036
$0037
$0038
$0039
$003A
$0040
$0041
$0042
$0043
$0044
$0045
$0046
$0047
Bit 15
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 5 Register
Low (TACH5L)
Bit 7
Read: COCO
Analog-to-Digital Status and
Control Register (ADSCR)
AIEN
AD6
ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write:
R
Read: AD7
Write:
AD5
AD4
AD3
0
AD2
0
AD1
0
AD0
0
Analog-to-Digital Data Register
(ADR)
Read:
ADIV2
Write:
Analog-to-Digital Input Clock
Register (ADICLK)
ADIV1 ADIV0 ADICLK
0
Read: TOF
Write:
0
Timer B Status and Control
Register (TBSCR)
TOIE
TSTOP
PS2
10
PS1
9
PS0
Bit 8
TRST
12
Read: Bit 15
Write:
14
13
11
3
Timer B Counter Register High
(TBCNTH)
Read: Bit 7
Write:
6
5
4
2
1
Bit 0
Timer B Counter Register Low
(TBCNTL)
Read:
Bit 15
Write:
Timer B Modulo Register High
(TBMODH)
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
Read:
Bit 7
Timer B Modulo Register Low
(TBMODL)
Write:
Read: CH0F
Timer B CH0 Status and Control
Register (TBSC0)
CH0IE
14
MS0B
13
MS0A
12
ELS0B ELS0A TOV0 CH0MAX
Write:
Read:
Write:
Read:
Write:
0
Timer B CH0 Register High
(TBCH0H)
Bit 15
11
3
10
2
9
1
Bit 8
Bit 0
Timer B CH0 Register Low
(TBCH0L)
Bit 7
6
5
0
4
Read: CH1F
Timer B CH1 Status and Control
Register (TBSC1)
CH1IE
14
MS1A
12
ELS1B ELS1A TOV1 CH1MAX
$0048
$0049
Write:
Read:
Write:
Read:
Write:
0
Timer B CH1 Register High
(TBCH1H)
Bit 15
13
5
11
10
2
9
1
Bit 8
Bit 0
PS0
Timer B CH1 Register Low
(TBCH1L)
$004A
$004B
Bit 7
6
4
3
0
Read: TOF
Write:
0
TIM Status and Control Register
(TSC)
TOIE
TSTOP
PS2
PS1
TRST
Figure 2. Control, Status, and Data Registers (Sheet 4 of 6)
8-mem60
MC68HC08AZ60 — Rev 1.0
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HC08AZ60 Memory Map
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HC08AZ60 Memory Map
I/O Section
Addr.
Register Name
Bit 7
Read: Bit 15
Write:
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
TIM Counter Register High
(TCNTH)
$004C
Read: Bit 7
Write:
6
5
4
3
2
1
Bit 0
TIM Counter Register Low
(TCNTL)
$004D
$004E
$004F
$FE00
Read:
Bit 15
Write:
TIM Modulo Register High
(TMODH)
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
Read:
Bit 7
TIM Modulo Register Low
(TMODL)
Write:
Read:
R
SIM Break Status Register
(SBSR)
R
R
R
R
R
0
SBSW
LVI
R
0
Write:
Read: POR
Write:
PIN
COP
ILOP
ILAD
$FE01 SIM Reset Status Register (SRSR)
Read:
BCFE
Write:
SIM Break Flag Control Register
$FE03
R
R
R
14
6
R
R
R
R
R
R
R
R
R
R
R
9
R
R
(SBFCR)
Read:
R
$FE09
$FE0B
$FE0C
$FE0D
$FE0E
$FE0F
$FE11
$FE18
$FE19
$FE1A
$FE1B
RESERVED
RESERVED
Write:
Read:
R
R
R
R
R
R
Write:
Read:
Bit 15
Write:
Break Address Register High
(BRKH)
13
12
11
10
Bit 8
Read:
Bit 7
Break Address Register Low
(BRKL)
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Write:
Read:
BRKE
Write:
Break Status and Control
Register (BRKSCR)
BRKA
0
Read: LVIOUT
Write:
0
0
0
0
0
0
LVI Status Register (LVISR)
RESERVED
Read:
R
R
R
R
R
R
R
R
Write:
Read:
EEPROM Nonvolatile Register
(EENVR2)
EERA CON2
CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0
0
Write:
Read:
Write:
Read:
Write:
0
EEPROM Control
Register (EECR2)
EEBCLK
EEOFF EERAS1 EERAS0 EELAT
EEPGM
Reserved
R
R
R
R
R
R
R
R
Read: EERA CON2
Write:
CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0
EEPROM Array Control Register
(EEACR2)
Figure 2. Control, Status, and Data Registers (Sheet 5 of 6)
9-mem60
MC68HC08AZ60 — Rev 1.0
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HC08AZ60 Me m ory Ma p
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
EEPROM Nonvolatile Register
(EENVR1)
$FE1C
EERA CON2
CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0
0
0
EEPROM Control
Register (EECR1)
$FE1D
$FE1E
$FE1F
$FF80
$FF81
EEBCLK
EEOFF EERAS1 EERAS0 EELAT
EEPGM
R
Reserved
R
R
R
R
R
R
R
Read: EERA CON2
CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0
EEPROM Array Control Register
(EEACR1)
Write:
Read:
Write:
Read:
Write:
R
R
R
R
R
R
R
R
RESERVED
RESERVED
Read:
Write:
LOW BYTE OF RESET VECTOR
$FFFF COP Control Register (COPCTL)
WRITING TO $FFFF CLEARS COP COUNTER
Figure 2. Control, Status, and Data Registers (Sheet 6 of 6)
10-mem60
MC68HC08AZ60 — Rev 1.0
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HC08AZ60 Memory Map
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HC08AZ60 Memory Map
I/O Section
Table 1. Vector Addresses
Address
$FFCC
$FFCD
$FFCE
$FFCF
$FFD0
$FFD1
$FFD2
$FFD3
$FFD4
$FFD5
$FFD6
$FFD7
$FFD8
$FFD9
$FFDA
$FFDB
$FFDC
$FFDD
$FFDE
$FFDF
$FFE0
$FFE1
$FFE2
$FFE3
$FFE4
$FFE5
$FFE6
$FFE7
$FFE8
$FFE9
$FFEA
$FFEB
$FFEC
$FFED
$FFEE
$FFEF
Vector
TIMA Channel 5 Vector (High)
TIMA Channel 5 Vector (Low)
TIMA Channel 4 Vector (High)
TIMA Channel 4 Vector (Low)
ADC Vector (High)
ADC Vector (Low)
Keyboard Vector (High)
Keyboard Vector (Low)
SCI Transmit Vector (High)
SCI Transmit Vector (Low)
SCI Receive Vector (High)
SCI Receive Vector (Low)
SCI Error Vector (High)
SCI Error Vector (Low)
CAN Transmit Vector (High)
CAN Transmit Vector (Low)
CAN Receive Vector (High)
CAN Receive Vector (Low)
CAN Error Vector (High)
CAN Error Vector (Low)
CAN Wakeup Vector (High)
CAN Wakeup Vector (Low)
SPI Transmit Vector (High)
SPI Transmit Vector (Low)
SPI Receive Vector (High)
SPI Receive Vector (Low)
TIMB Overflow Vector (High)
TIMB Overflow Vector (Low)
TIMB CH1 Vector (High)
TIMB CH1 Vector (Low)
TIMB CH0 Vector (High)
TIMB CH0 Vector (Low)
TIMA Overflow Vector (High)
TIMA Overflow Vector (Low)
TIMA CH3 Vector (High)
TIMA CH3 Vector (Low)
11-mem60
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HC08AZ60 Me m ory Ma p
Table 1. Vector Addresses (Continued)
Address
$FFF0
$FFF1
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
$FFF8
$FFF9
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
Vector
TIMA CH2 Vector (High)
TIMA CH2 Vector (Low)
TIMA CH1 Vector (High)
TIMA CH1 Vector (Low)
TIMA CH0 Vector (High)
TIMA CH0 Vector (Low)
TIM Vector (High)
TIM Vector (Low)
PLL Vector (High)
PLL Vector (Low)
IRQ Vector (High)
IRQ Vector (Low)
SWI Vector (High)
SWI Vector (Low)
Reset Vector (High)
$FFFF
Reset Vector (Low)
Note that all available ROM locations not defined by the user will, by
default, be filled with the software interrupt instruction (SWI, opcode 83)
– see Central Processor Unit (CPU). Please take this into account
when defining vector addresses. It is recommended that all vector
addresses are defined.
12-mem60
MC68HC08AZ60 — Rev 1.0
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HC08AZ60 Memory Map
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RAM
RAM
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Introd uc tion
This section describes the 2048 bytes of random-access memory
(RAM).
Func tiona l De sc rip tion
Addresses $0050 through $044F and $0A00 through $0DFF are RAM
locations. The location of the stack RAM is programmable with the reset
stack pointer instruction (RSP). The 16-bit stack pointer allows the stack
RAM to be anywhere in the 64K-byte memory space.
NOTE: For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 176 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for input/output (I/O) control and user data or code. When the stack
pointer is moved from its reset location at $00FF, direct addressing
mode instructions can access all page zero RAM locations efficiently.
Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
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RAM
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RAM
NOTE: For M68HC05, M6805, and M146805 compatibility, the H register is not
stacked.
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU could overwrite
data in the RAM during a subroutine or during the interrupt stacking
operation.
2-ram
MC68HC08AZ60 — Rev 1.0
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RAM
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ROM-1 Me m ory
ROM-1 Me m ory
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
WAIT Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Introd uc tion
This section describes the operation of the embedded ROM-1 memory.
Func tiona l De sc rip tion
The ROM memory physically consists of two independent arrays of 32K
bytes with an additional 52 bytes of user vectors and two bytes of block
protection. The address ranges for the user memory and vectors are:
• $8000–$FDFF
• $FFCC–$FFFF (These locations are reserved for user-defined
interrupt and reset vectors.)
NOTE: A security feature prevents viewing of the ROM contents.1
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the ROM difficult for unauthorized users.
3-rom
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ROM-1 Me m ory
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low power
consumption standby modes.
WAIT Mod e
STOP Mod e
Putting the MCU into wait mode while the ROM is in read mode does not
affect the operation of the ROM memory directly, but there will not be any
memory activity since the CPU is inactive.
When the MCU is put into stop mode, if the ROM is in read mode, it will
be put into low power standby.
4-rom
MC68HC908AZ60 — Rev 1.0
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ROM-1 Memory
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ROM-2 Me m ory
ROM-2 Me m ory
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
WAIT Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Introd uc tion
This section describes the operation of the embedded ROM-2 memory.
Func tiona l De sc rip tion
The ROM-2 memory is an array of up to 29,488 bytes. The address
ranges for the user memory and the control register are:
• $0450–$04FF
• $0580–$05FF
• $0E00–$7FFF
NOTE: A security feature prevents viewing of the ROM contents.1
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the ROM difficult for unauthorized users.
1-rom-2
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ROM-2 Me m ory
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low power
consumption standby modes.
WAIT Mod e
STOP Mod e
Putting the MCU into wait mode while the ROM is in read mode does not
affect the operation of the ROM memory directly, but there will not be any
memory activity since the CPU is inactive.
When the MCU is put into stop mode, if the ROM is in read mode, it will
be put into low power standby.
2-rom-2
MC68HC08AZ60 — Rev 1.0
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ROM-2 Memory
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EEPROM-1
EEPROM-1
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Future EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
EEPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MCU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
MC68HC08AZ60 EEPROM Protection. . . . . . . . . . . . . . . . . . . . . . 47
EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
EEPROM Nonvolatile Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Introd uc tion
This section describes the electrically erasable programmable read-only
memory (EEPROM). The 1024 bytes available on the MC68HC08AZ60
are physically located in two 512byte arrays. This chapter details the
array covering the address range $0800 to $09FF. For information
relating to the array covering address range $0600 to $07FF see
EEPROM-2 on page 53.
1-eeprom-1
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EEPROM-1
Future EEPROM Me m ory
Design is underway to introduce an improved EEPROM module, which
will simplify programming and erase. Current read, write and erase
algorithms are fully compatible with the new EEPROM design. The new
EEPROM module requires a constant timebase through the set up of
new timebase control registers. If more information is required for code
compatibility please contact the factory. The silicon differences will be
identified by mask set. Please read Appendix A: Future EEPROM
Registers for preliminary details.
NOTE: This new silicon will not allow multiple writes before erase. EEPROM
bytes must be erased before reprogramming.
Fe a ture s
EEPROM features include:
• Byte, Block, or Bulk Erasable
• Nonvolatile Block Protection Option
• Nonvolatile MCU Configuration Bits
• On-Chip Charge Pump for Programming/Erasing
• Security Option
2-eeprom-1
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EEPROM-1
Functional Description
Func tiona l De sc rip tion
The 512 bytes of EEPROM-1 can be programmed or erased without an
external voltage supply. The EEPROM has a lifetime of 10,000
write-erase cycles. EEPROM cells are protected with a nonvolatile block
protection option. These options are stored in the EEPROM nonvolatile
register (EENVR1) and are loaded into the EEPROM array configuration
register after reset (EEACR1) or a read of EENVR1. Hardware interlocks
are provided to protect stored data corruption from accidental
programming/erasing.
EEPROM
Prog ra m m ing
The EEPROM-1 array will leave the factory in the erased state: all
addresses logic ‘1’ and bit 4 of the EENVR1 register programmed to ‘1’
such that the full array is available and unprotected.
The unprogrammed state is a logic 1. Programming changes the state
to a logic 0. Only valid EEPROM bytes in the non-protected blocks and
EENVR1 can be programmed. It is recommended that all bits should
be erased before being programmed.
Follow this procedure to program a byte of EEPROM after first ensuring
the block protect feature is not set on the address block of the byte to be
programmed:
1. Clear EERAS1 and EERAS0 and set EELAT in the EECR1. (See
note A and B.)
2. Write the desired data to any user EEPROM address.
3. Set the EEPGM bit. (See note C.)
4. Wait for a time, tEEPGM, to program the byte.
5. Clear EEPGM bit.
6. Wait for a time, tEEFPV, for the programming voltage to fall.
7. Clear EELAT bits. (See note D.)
8. Repeat steps 1 to 7 for more EEPROM programming.
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EEPROM-1
NOTES:
a. EERAS1 and EERAS0 must be cleared for programming.
Otherwise, the part will be in erase mode.
b. Setting EELAT bit configures the address and data buses to
latch data for programming the array. Only data with valid
EEPROM address will be latched. If another consecutive valid
EEPROM write occurs, this address and data will override the
previous address and data. Any attempts to read other
EEPROM data will read the latched data. If EELAT is set,
other writes to the EECR1 will only be allowed after a valid
EEPROM write.
c. To ensure proper programming sequence, the EEPGM bit
cannot be set if the EELAT bit is cleared and a non-EEPROM
write has occurred. When EEPGM is set, the onboard charge
pump generates the program voltage and applies it to the user
EEPROM array. When the EEPGM bit is cleared, the program
voltage is removed from the array and the internal charge
pump is turned off.
d. Any attempt to clear both EEPGM and EELAT bits with a
single instruction will only clear EEPGM. This is to allow time
for removal of high voltage from the EEPROM array.
4-eeprom-1
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EEPROM-1
Functional Description
EEPROM Era sing
The unprogrammed state is a logic 1. Only the valid EEPROM bytes in
the nonprotected blocks and EENVR1 can be erased.
Use this procedure to erase EEPROM after first ensuring the block
protect feature is not set on the address block of the byte to be erased:
1. Clear/set EERAS1 and EERAS0 to select byte/block/bulk erase,
and set EELAT in EECR1. (See note A.)
2. Write any data to the desired address for byte erase, to any
address in the desired block for block erase, or to any array
address for bulk erase.
3. Set the EEPGM bit. (See note B.)
4. Wait for a time, tEEPGM,/tEEBLOCK EEBULK.
/t
.
5. Clear EEPGM bit.
6. Wait for a time, tEEFPV, for the erasing voltage to fall.
7. Clear EELAT bits. (See note C.)
8. Repeat steps 1 to 7 for more EEPROM byte/block erasing.
EEBPx bit must be cleared to erase EEPROM data in the corresponding
block. If any EEBPx is set, the corresponding block can not be erased
and bulk erase mode does not apply.
NOTES:
a. Setting EELAT bit configures the address and data buses to
latch data for erasing the array. Only valid EEPROM
addresses with their data will be latched. If another
consecutive valid EEPROM write occurs, this address and
data will override the previous address and data. In block
erase mode, any EEPROM address in the block may be used
in step 2. All locations within this block will be erased. In bulk
erase mode, any EEPROM address may be used to erase the
whole EEPROM. EENVR1 is not affected with block or bulk
erase. Any attempts to read other EEPROM data will read the
latched data. If EELAT is set, other writes to the EECR1 will
only be allowed after a valid EEPROM write.
b. The EEPGM bit cannot be set if the EELAT bit is cleared and
a non-EEPROM write has occurred. This is to ensure proper
erasing sequence. Once EEPGM is set, the type of erase
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EEPROM-1
mode cannot be modified. If EEPGM is set, the onboard
charge pump generates the erase voltage and applies it to the
user EEPROM array. When the EEPGM bit is cleared, the
erase voltage is removed from the array and the internal
charge pump is turned off.
c. Any attempt to clear both EEPGM and EELAT bits with a
single instruction will only clear EEPGM. This is to allow time
for removal of high voltage from the EEPROM array.
All bits should be erased before being programmed.
EEPROM Bloc k
Prote c tion
The 512 bytes of EEPROM are divided into four 128-byte blocks. Each
of these blocks can be separately protected by EEBPx bit. Any attempt
to program or erase memory locations within the protected block will not
allow the program/erase voltage to be applied to the array. Table 1
shows the address ranges within the blocks.
Table 1. EEPROM Array Address Blocks
Block Number (EEBPx)
Address Range
$0800–$087F
$0880–$08FF
$0900–$097F
$0980–$09FF
EEBP0
EEBP1
EEBP2
EEBP3
If EEBPx bit is set, that corresponding address block is protected. These
bits are effective after a reset or a read to EENVR1 register. The block
protect configuration can be modified by erasing/programming the
corresponding bits in the EENVR1 register and then reading the
EENVR1 register.
6-eeprom-1
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EEPROM-1
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EEPROM-1
Functional Description
MCU
The EEPROM nonvolatile register (EENVR1) also contains
Config ura tion
general-purpose bits which can be used to enable/disable functions
within the MCU which, for safety reasons, need to be controlled from
nonvolatile memory. On reset, this special register loads the MCU
configuration into the volatile EEPROM array configuration register
(EEACR1). Thereafter, all reads to the EENVR1 will reload EEACR1.
The MCU configuration can be changed by programming/erasing the
EENVR1 like a normal EEPROM byte. Please note that it is the user’s
responsibility to erase and program the EENVR1 register to the
correct system requirements and verify it prior to use. The new
array configuration will take affect after a system reset or a read of the
EENVR1.
MC68HC08AZ60
EEPROM
Prote c tion
The MC68HC08AZ60 has a special protection option which prevents
program/erase access to memory locations $08F0 to $08FF. This
protect function is enabled by programming the EEPRTCT bit in the
EENVR to 0.
In addition to the disabling of the program and erase operations on
memory locations $08F0 to $08FF the enabling of the protect option has
the following effects.
• Bulk and block erase modes are disabled.
• Programming and erasing of the EENVR is disabled.
• Unsecure locations ($0800–$08EF) can be erased using the
single byte erase function as normal.
• Secured locations can be read as normal.
• Writing to a secure location no longer qualifies as a “valid
EEPROM write” as detailed in (see EEPROM Programming) Note
B and (see EEPROM Erasing) Note A.
NOTE: Once armed, the protect option is permanently enabled. As a
consequence, all functions in the EENVR will remain in the state they
were in immediately before the security was enabled.
7-eeprom-1
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EEPROM-1
EEPROM Control
Re g iste r
This read/write register controls programming/erasing of the array.
Address: $FE1D
Bit 7
EEBCLK
0
6
0
5
4
3
2
1
0
Bit 0
EEPGM
0
Read:
Write:
Reset:
EEOFF EERAS1 EERAS0 EELAT
0
0
0
0
0
0
= Unimplemented
Figure 1. EEPROM-1 Control Register (EECR1)
EEBCLK — EEPROM Bus Clock Enable
This read/write bit determines which clock will be used to drive the
internal charge pump for programming/erasing. Reset clears this bit.
1 = Bus clock drives charge pump
0 = Internal RC oscillator drives charge pump
NOTE: It is recommended that the internal RC oscillator is used to drive the
internal charge pump for applications that have a bus frequency of less
than 8 MHz.
EEOFF — EEPROM Power Down
This read/write bit disables the EEPROM module for lower power
consumption. Any attempts to access the array will give unpredictable
results. Reset clears this bit.
1 = Disable EEPROM array
0 = Enable EEPROM array
NOTE: The EEPROM requires a recovery time, tEEOFF, to stabilize after clearing
the EEOFF bit.
8-eeprom-1
MC68HC08AZ60 — Rev. 1.0
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Functional Description
EERAS1 and EERAS0 — Erase Bits
These read/write bits set the erase modes. Reset clears these bits.
Table 2. EEPROM Program/Erase Mode Select
EEBPx
EERAS1
EERAS0
MODE
Byte Program
Byte Erase
0
0
0
1
1
X
0
1
0
1
X
0
0
Block Erase
Bulk Erase
0
1
No Erase/Program
X = don’t care
EELAT — EEPROM Latch Control
This read/write bit latches the address and data buses for
programming the EEPROM array. EELAT cannot be cleared if
EEPGM is still set. Reset clears this bit.
1 = Buses configured for EEPROM programming
0 = Buses configured for normal read operation
EEPGM — EEPROM Program/Erase Enable
This read/write bit enables the internal charge pump and applies the
programming/erasing voltage to the EEPROM array if the EELAT bit
is set and a write to a valid EEPROM location has occurred. Reset
clears the EEPGM bit.
1 = EEPROM programming/erasing power switched on
0 = EEPROM programming/erasing power switched off
NOTE: Writing logic 0s to both the EELAT and EEPGM bits with a single
instruction will clear EEPGM only to allow time for the removal of high
voltage.
9-eeprom-1
MC68HC08AZ60 — Rev. 1.0
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EEPROM-1
EEPROM
The EEPROM nonvolatile register (EENVR1) is shown in Figure 2.
Nonvola tile
Re g iste r
Address: $FE1C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
EERA
CON2
CON1 EEPRTCT EEBP3
PV
EEBP2
EEBP1
EEBP0
= Unimplemented
PV = Programmed value or 1 in the erased state.
Figure 2. EEPROM-1 Nonvolatile Register (EENVR1)
EERA — EEPROM Redundant Array
This bit is reserved for future use and should always be equal to 0.
CONx — MCU Configuration Bits
These read/write bits can be used to enable/disable functions within
the MCU. Reset loads CONx from EENVR1 to EEACR1.
CON2 — Unused
CON1— Unused
NOTE: This feature is a write-once feature. Once the protection is enabled it
may not be disabled.
EEPRTCT — EEPROM Protection
This one-time programmable bit can be used to protect 16 bytes
($8F0–$8FF) from being erased or programmed.
1 = EEPROM protection disabled
0 = EEPROM protection enabled
EEBP3–EEBP0 — EEPROM Block Protection Bits
These read/write bits select blocks of EEPROM array from being
programmed or erased. Reset loads EEBP[3:0] from EENVR1 to
EEACR1.
1 = EEPROM array block is protected
0 = EEPROM array block is unprotected
10-eeprom-1
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EEPROM-1
Functional Description
EEPROM Arra y
Config ura tion
Re g iste r
The EEPROM array configration register (EEACR1) is shown in Figure
3.
Address: $FE1F
Bit 7
Read: EERA
Write:
6
5
4
3
2
1
Bit 0
CON2
CON1 EEPRTCT EEBP3
EEBP2
EEBP1
EEBP0
Reset:
EENVR
= Unimplemented
Figure 3. EEPROM-1 Array Control Register (EEACR1)
EERA — EEPROM Redundant Array
This bit is reserved for future use and should always be equal to 0.
CONx — MCU Configuration Bits
These read/write bits can be used to enable/disable functions within
the MCU. Reset loads CONx from EENVR1 to EEACR1.
CON2 — Unused
CON1— Unused
NOTE: This feature is a write-once feature. Once the protection is enabled it
may not be disabled.
EEPRTCT — EEPROM Protection
This one-time programmable bit can be used to protect 16 bytes
($8F0–$8FF) from being erased or programmed.
1 = EEPROM protection disabled
0 = EEPROM protection enabled
EEBP3–EEBP0 — EEPROM Block Protection Bits
These read/write bits select blocks of EEPROM array from being
programmed or erased. Reset loads EEBP[3:0] from EENVR1 to
EEACR1.
1 = EEPROM array block is protected
0 = EEPROM array block is unprotected
11-eeprom-1
MC68HC08AZ60 — Rev. 1.0
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Low-Powe r Mod e s
The WAIT and STOP instructions can put the MCU in low
power-consumption standby modes.
Wa it Mod e
Stop Mod e
The WAIT instruction does not affect the EEPROM. It is possible to
program the EEPROM and put the MCU in wait mode. However, if the
EEPROM is inactive, power can be reduced by setting the EEOFF bit
before executing the WAIT instruction.
The STOP instruction reduces the EEPROM power consumption to a
minimum. The STOP instruction should not be executed while the high
voltage is turned on (EEPGM = 1).
If stop mode is entered while program/erase is in progress, high voltage
will be automatically turned off. However, the EEPGM bit will remain set.
When stop mode is terminated, and if EEPGM is still set, the high voltage
will be automatically turned back on. Program/erase time will need to be
extended if program/erase is interrupted by entering stop mode.
The module requires a recovery time, tEESTOP, to stabilize after leaving
stop mode. Attempts to access the array during the recovery time will
result in unpredictable behavior.
12-eeprom-1
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EEPROM-2
EEPROM-2
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Future EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
EEPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
MCU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
MC68HC08AZ60 EEPROM Protection. . . . . . . . . . . . . . . . . . . . . . 59
EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
EEPROM Nonvolatile Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Introd uc tion
This section describes the electrically erasable programmable read-only
memory (EEPROM). The 1024 bytes available on the MC68HC08AZ60
are physically located in two 512byte arrays. This chapter details the
array covering the address range $0600 to $07FF. For information
relating to the array covering address range $0800 to $09FF see
EEPROM-1 on page 41.
1-eeprom-2
MC68HC08AZ60 — Rev 1.0
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EEPROM-2
Future EEPROM Me m ory
Design is underway to introduce an improved EEPROM module, which
will simplify programming and erase. Current read, write and erase
algorithms are fully compatible with the new EEPROM design. The new
EEPROM module requires a constant timebase through the set up of
new timebase control registers. If more information is required for code
compatibility please contact the factory. The silicon differences will be
identified by mask set. Please read Appendix A: Future EEPROM
Registers for preliminary details.
NOTE: This new silicon will not allow multiple writes before erase. EEPROM
bytes must be erased before reprogramming.
Fe a ture s
EEPROM features include:
• Byte, Block, or Bulk Erasable
• Nonvolatile Block Protection Option
• Nonvolatile MCU Configuration Bits
• On-Chip Charge Pump for Programming/Erasing
• Security Option
2-eeprom-2
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EEPROM-2
Functional Description
Func tiona l De sc rip tion
The 512 bytes of EEPROM-2 can be programmed or erased without an
external voltage supply. The EEPROM has a lifetime of 10,000
write-erase cycles. EEPROM cells are protected with a nonvolatile block
protection option. These options are stored in the EEPROM nonvolatile
register (EENVR2) and are loaded into the EEPROM array configuration
register after reset (EEACR2) or a read of EENVR2. Hardware interlocks
are provided to protect stored data corruption from accidental
programming/erasing.
EEPROM
Prog ra m m ing
The EEPROM-2 array will leave the factory in the erased state: all
addresses logic ‘1’ and bit 4 of the EENVR2 register programmed to ‘1’
such that the full array is available and unprotected.
The unprogrammed state is a logic 1. Programming changes the state
to a logic 0. Only valid EEPROM bytes in the non-protected blocks and
EENVR2 can be programmed. It is recommended that all bits should
be erased before being programmed.
Follow this procedure to program a byte of EEPROM after first ensuring
the block protect feature is not set on the address block of the byte to be
programmed:
1. Clear EERAS1 and EERAS0 and set EELAT in the EECR2. (See
note A and B.)
2. Write the desired data to any user EEPROM address.
3. Set the EEPGM bit. (See note C.)
4. Wait for a time, tEEPGM, to program the byte.
5. Clear EEPGM bit.
6. Wait for a time, tEEFPV, for the programming voltage to fall.
7. Clear EELAT bits. (See note D.)
8. Repeat steps 1 to 7 for more EEPROM programming.
3-eeprom-2
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EEPROM-2
NOTES:
a. EERAS1 and EERAS0 must be cleared for programming.
Otherwise, the part will be in erase mode.
b. Setting EELAT bit configures the address and data buses to
latch data for programming the array. Only data with valid
EEPROM address will be latched. If another consecutive valid
EEPROM write occurs, this address and data will override the
previous address and data. Any attempts to read other
EEPROM data will read the latched data. If EELAT is set,
other writes to the EECR2 will only be allowed after a valid
EEPROM write.
c. To ensure proper programming sequence, the EEPGM bit
cannot be set if the EELAT bit is cleared and a non-EEPROM
write has occurred. When EEPGM is set, the onboard charge
pump generates the program voltage and applies it to the user
EEPROM array. When the EEPGM bit is cleared, the program
voltage is removed from the array and the internal charge
pump is turned off.
d. Any attempt to clear both EEPGM and EELAT bits with a
single instruction will only clear EEPGM. This is to allow time
for removal of high voltage from the EEPROM array.
4-eeprom-2
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EEPROM-2
Functional Description
EEPROM Era sing
The unprogrammed state is a logic 1. Only the valid EEPROM bytes in
the nonprotected blocks and EENVR2 can be erased.
Use this procedure to erase EEPROM after first ensuring the block
protect feature is not set on the address block of the byte to be erased:
1. Clear/set EERAS1 and EERAS0 to select byte/block/bulk erase,
and set EELAT in EECR2. (See note A.)
2. Write any data to the desired address for byte erase, to any
address in the desired block for block erase, or to any array
address for bulk erase.
3. Set the EEPGM bit. (See note B.)
4. Wait for a time, tEEPGM,/tEEBLOCK EEBULK.
/t
.
5. Clear EEPGM bit.
6. Wait for a time, tEEFPV, for the erasing voltage to fall.
7. Clear EELAT bits. (See note C.)
8. Repeat steps 1 to 7 for more EEPROM byte/block erasing.
EEBPx bit must be cleared to erase EEPROM data in the corresponding
block. If any EEBPx is set, the corresponding block can not be erased
and bulk erase mode does not apply.
NOTES:
a. Setting EELAT bit configures the address and data buses to
latch data for erasing the array. Only valid EEPROM
addresses with their data will be latched. If another
consecutive valid EEPROM write occurs, this address and
data will override the previous address and data. In block
erase mode, any EEPROM address in the block may be used
in step 2. All locations within this block will be erased. In bulk
erase mode, any EEPROM address may be used to erase the
whole EEPROM. EENVR2 is not affected with block or bulk
erase. Any attempts to read other EEPROM data will read the
latched data. If EELAT is set, other writes to the EECR2 will
only be allowed after a valid EEPROM write.
b. The EEPGM bit cannot be set if the EELAT bit is cleared and
a non-EEPROM write has occurred. This is to ensure proper
erasing sequence. Once EEPGM is set, the type of erase
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EEPROM-2
mode cannot be modified. If EEPGM is set, the onboard
charge pump generates the erase voltage and applies it to the
user EEPROM array. When the EEPGM bit is cleared, the
erase voltage is removed from the array and the internal
charge pump is turned off.
c. Any attempt to clear both EEPGM and EELAT bits with a
single instruction will only clear EEPGM. This is to allow time
for removal of high voltage from the EEPROM array.
All bits should be erased before being programmed.
EEPROM Bloc k
Prote c tion
The 512 bytes of EEPROM are divided into four 128-byte blocks. Each
of these blocks can be separately protected by EEBPx bit. Any attempt
to program or erase memory locations within the protected block will not
allow the program/erase voltage to be applied to the array. Table 1
shows the address ranges within the blocks.
Table 1. EEPROM Array Address Blocks
Block Number (EEBPx)
Address Range
$0600–$067F
$0680–$06FF
$0700–$077F
$0780–$07FF
EEBP0
EEBP1
EEBP2
EEBP3
If EEBPx bit is set, that corresponding address block is protected. These
bits are effective after a reset or a read to EENVR2 register. The block
protect configuration can be modified by erasing/programming the
corresponding bits in the EENVR2 register and then reading the
EENVR2 register.
6-eeprom-2
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EEPROM-2
Functional Description
MCU
The EEPROM nonvolatile register (EENVR2) also contains
Config ura tion
general-purpose bits which can be used to enable/disable functions
within the MCU which, for safety reasons, need to be controlled from
nonvolatile memory. On reset, this special register loads the MCU
configuration into the volatile EEPROM array configuration register
(EEACR2). Thereafter, all reads to the EENVR2 will reload EEACR2.
The MCU configuration can be changed by programming/erasing the
EENVR2 like a normal EEPROM byte. Please note that it is the user’s
responsibility to erase and program the EENVR2 register to the
correct system requirements and verify it prior to use. The new
array configuration will take affect after a system reset or a read of the
EENVR2.
MC68HC08AZ60
EEPROM
Prote c tion
The MC68HC08AZ60 has a special protection option which prevents
program/erase access to memory locations $08F0 to $08FF. This
protect function is enabled by programming the EEPRTCT bit in the
EENVR to 0.
In addition to the disabling of the program and erase operations on
memory locations $08F0 to $08FF the enabling of the protect option has
the following effects.
• Bulk and block erase modes are disabled.
• Programming and erasing of the EENVR is disabled.
• Unsecure locations ($0800–$08EF) can be erased using the
single byte erase function as normal.
• Secured locations can be read as normal.
• Writing to a secure location no longer qualifies as a “valid
EEPROM write” as detailed in (see EEPROM Programming) Note
B and (see EEPROM Erasing) Note A.
NOTE: Once armed, the protect option is permanently enabled. As a
consequence, all functions in the EENVR will remain in the state they
were in immediately before the security was enabled.
7-eeprom-2
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EEPROM Control
Re g iste r
This read/write register controls programming/erasing of the array.
Address: $FE19
Bit 7
EEBCLK
0
6
0
5
4
3
2
1
0
Bit 0
EEPGM
0
Read:
Write:
Reset:
EEOFF EERAS1 EERAS0 EELAT
0
0
0
0
0
0
= Unimplemented
Figure 1. EEPROM-2 Control Register (EECR2)
EEBCLK — EEPROM Bus Clock Enable
This read/write bit determines which clock will be used to drive the
internal charge pump for programming/erasing. Reset clears this bit.
1 = Bus clock drives charge pump
0 = Internal RC oscillator drives charge pump
NOTE: It is recommended that the internal RC oscillator is used to drive the
internal charge pump for applications that have a bus frequency of less
than 8 MHz.
EEOFF — EEPROM Power Down
This read/write bit disables the EEPROM module for lower power
consumption. Any attempts to access the array will give unpredictable
results. Reset clears this bit.
1 = Disable EEPROM array
0 = Enable EEPROM array
NOTE: The EEPROM requires a recovery time, tEEOFF, to stabilize after clearing
the EEOFF bit.
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Functional Description
EERAS1 and EERAS0 — Erase Bits
These read/write bits set the erase modes. Reset clears these bits.
Table 2. EEPROM Program/Erase Mode Select
EEBPx
EERAS1
EERAS0
MODE
Byte Program
Byte Erase
0
0
0
1
1
X
0
1
0
1
X
0
0
Block Erase
Bulk Erase
0
1
No Erase/Program
X = don’t care
EELAT — EEPROM Latch Control
This read/write bit latches the address and data buses for
programming the EEPROM array. EELAT cannot be cleared if
EEPGM is still set. Reset clears this bit.
1 = Buses configured for EEPROM programming
0 = Buses configured for normal read operation
EEPGM — EEPROM Program/Erase Enable
This read/write bit enables the internal charge pump and applies the
programming/erasing voltage to the EEPROM array if the EELAT bit
is set and a write to a valid EEPROM location has occurred. Reset
clears the EEPGM bit.
1 = EEPROM programming/erasing power switched on
0 = EEPROM programming/erasing power switched off
NOTE: Writing logic 0s to both the EELAT and EEPGM bits with a single
instruction will clear EEPGM only to allow time for the removal of high
voltage.
9-eeprom-2
MC68HC08AZ60 — Rev 1.0
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EEPROM
The EEPROM nonvolatile register (EENVR2) is shown in Figure 2.
Nonvola tile
Re g iste r
Address: $FE18
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
EERA
CON2
CON1 EEPRTCT EEBP3
PV
EEBP2
EEBP1
EEBP0
= Unimplemented
PV = Programmed value or 1 in the erased state.
Figure 2. EEPROM-2 Nonvolatile Register (EENVR2)
EERA — EEPROM Redundant Array
This bit is reserved for future use and should always be equal to 0.
CONx — MCU Configuration Bits
These read/write bits can be used to enable/disable functions within
the MCU. Reset loads CONx from EENVR2 to EEACR2.
CON2 — Unused
CON1— Unused
NOTE: This feature is a write-once feature. Once the protection is enabled it
may not be disabled.
EEPRTCT — EEPROM Protection
This one-time programmable bit can be used to protect 16 bytes
($8F0–$8FF) from being erased or programmed.
1 = EEPROM protection disabled
0 = EEPROM protection enabled
EEBP3–EEBP0 — EEPROM Block Protection Bits
These read/write bits select blocks of EEPROM array from being
programmed or erased. Reset loads EEBP[3:0] from EENVR2 to
EEACR2.
1 = EEPROM array block is protected
0 = EEPROM array block is unprotected
10-eeprom-2
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EEPROM-2
Functional Description
EEPROM Arra y
Config ura tion
Re g iste r
The EEPROM array configration register (EEACR2) is shown in Figure
3.
Address: $FE1B
Bit 7
Read: EERA
Write:
6
5
4
3
2
1
Bit 0
CON2
CON1 EEPRTCT EEBP3
EEBP2
EEBP1
EEBP0
Reset:
EENVR
= Unimplemented
Figure 3. EEPROM-2 Array Control Register (EEACR2)
EERA — EEPROM Redundant Array
This bit is reserved for future use and should always be equal to 0.
CONx — MCU Configuration Bits
These read/write bits can be used to enable/disable functions within
the MCU. Reset loads CONx from EENVR2 to EEACR2.
CON2 — Unused
CON1— Unused
NOTE: This feature is a write-once feature. Once the protection is enabled it
may not be disabled.
EEPRTCT — EEPROM Protection
This one-time programmable bit can be used to protect 16 bytes
($8F0–$8FF) from being erased or programmed.
1 = EEPROM protection disabled
0 = EEPROM protection enabled
EEBP3–EEBP0 — EEPROM Block Protection Bits
These read/write bits select blocks of EEPROM array from being
programmed or erased. Reset loads EEBP[3:0] from EENVR2 to
EEACR2.
1 = EEPROM array block is protected
0 = EEPROM array block is unprotected
11-eeprom-2
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Low-Powe r Mod e s
The WAIT and STOP instructions can put the MCU in low
power-consumption standby modes.
Wa it Mod e
Stop Mod e
The WAIT instruction does not affect the EEPROM. It is possible to
program the EEPROM and put the MCU in wait mode. However, if the
EEPROM is inactive, power can be reduced by setting the EEOFF bit
before executing the WAIT instruction.
The STOP instruction reduces the EEPROM power consumption to a
minimum. The STOP instruction should not be executed while the high
voltage is turned on (EEPGM = 1).
If stop mode is entered while program/erase is in progress, high voltage
will be automatically turned off. However, the EEPGM bit will remain set.
When stop mode is terminated, and if EEPGM is still set, the high voltage
will be automatically turned back on. Program/erase time will need to be
extended if program/erase is interrupted by entering stop mode.
The module requires a recovery time, tEESTOP, to stabilize after leaving
stop mode. Attempts to access the array during the recovery time will
result in unpredictable behavior.
12-eeprom-2
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Ce ntra l Proc e ssor Unit (CPU)
Ce ntra l Proc e ssor Unit (CPU)
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Index register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Stack pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Program counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Arithmetic/logic unit (ALU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
WAIT mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Introd uc tion
This section describes the central processor unit (CPU8). The M68HC08
CPU is an enhanced and fully object-code-compatible version of the
M68HC05 CPU. The CPU08 Reference Manual (Motorola document
number CPU08RM/AD) contains a description of the CPU instruction
set, addressing modes, and architecture.
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Ce ntra l Proc e ssor Unit (CPU)
Fe a ture s
Features of the CPU include the following:
• Full upward, object-code compatibility with M68HC05 family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with X-register manipulation instructions
• 8.4MHz CPU internal bus frequency
• 64K byte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Low-power STOP and WAIT Modes
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Central Processor Unit (CPU)
CPU registers
CPU re g iste rs
Figure 1 shows the five CPU registers. CPU registers are not part of the
memory map.
7
0
0
0
0
0
ACCUMULATOR (A)
15
15
15
H
X
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
7
V
1
1 H
I
N Z C CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 1. CPU registers
Ac c um ula tor (A)
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
A
Unaffected by reset
Figure 2. Accumulator (A)
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Ce ntra l Proc e ssor Unit (CPU)
Ind e x re g iste r
(H:X)
The 16-bit index register allows indexed addressing of a 64K byte
memory space. H is the upper byte of the index register and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
Bit
Bit
0
15 14 13 12 11 10
9
0
8
0
7
6
5
4
3
2
1
Read:
Write:
Reset:
H:X
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X = Indeterminate
Figure 3. Index register (H:X)
The index register can also be used as a temporary data storage
location.
Sta c k p ointe r (SP)
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Bit
Bit
0
15 14 13 12 11 10
9
8
7
6
5
1
4
1
3
1
2
1
1
1
Read:
Write:
Reset:
SP
0
0
0
0
0
0
0
0
1
1
1
Figure4. Stack pointer (SP)
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CPU registers
NOTE: The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct
address (page zero) space. For correct operation, the stack pointer must
point only to RAM locations.
Prog ra m c ounte r
(PC)
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
Bit
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
PC
Loaded with vector from $FFFE and $FFFF
Figure 5. Program counter (PC)
Cond ition c od e
re g iste r (CCR)
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to ‘1’. The following paragraphs describe the
functions of the condition code register.
Bit 7
V
6
1
1
5
1
1
4
3
I
2
1
Z
X
Bit 0
C
Read:
Write:
Reset:
CCR
H
X
N
X
X
1
X
X = Indeterminate
Figure 6. Condition code register (CCR)
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V — Overflow flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-carry flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an ADD or ADC operation. The
half-carry flag is required for binary-coded decimal (BCD) arithmetic
operations. The DAA instruction uses the states of the H and C flags
to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE: To maintain M6805 compatibility, the upper byte of the index register (H)
is not stacked automatically. If the interrupt service routine modifies H,
then the user must stack and unstack H using the PSHH and PULH
instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return from interrupt (RTI) instruction pulls the CPU registers from the
stack and restores the interrupt mask from the stack. After any reset, the
interrupt mask is set and can only be cleared by the clear interrupt mask
software instruction (CLI).
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CPU registers
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/borrow flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions - such as bit test and
branch, shift, and rotate - also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
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Arithm e tic / log ic unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Motorola document number
CPU08RM/AD) for a description of the instructions and addressing
modes and more detail about CPU architecture.
Low-p owe r m od e s
The WAIT and STOP instructions put the MCU in low--power
consumption standby modes.
WAIT m od e
The WAIT instruction:
• clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from WAIT mode by interrupt, the I
bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
STOP m od e
The STOP instruction:
• clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from STOP mode by
external interrupt, the I bit remains clear. After exit by reset, the I
bit is set.
• Disables the CPU clock
After exiting STOP mode, the CPU clock begins running after the
oscillator stabilization delay.
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CPU during break interrupts
CPU d uring b re a k inte rrup ts
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. See Break Module on page 135. The program
counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor mode).
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
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Ce ntra l Proc e ssor Unit (CPU)
Instruc tion Se t Sum m a ry
Table 1 provides a summary of the M68HC08 instruction set.
Table 1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
ADC #opr
IMM
DIR
EXT
IX2
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
2
3
4
4
3
2
4
5
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
A ← (A) + (M) + (C)
↕ ↕ – ↕ ↕ ↕
IX1
IX
SP1
SP2
F9
ADC opr,SP
ADC opr,SP
9EE9 ff
9ED9 ee ff
ADD #opr
ADD opr
IMM
DIR
EXT
IX2
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
2
3
4
4
3
2
4
5
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
Add without Carry
A ← (A) + (M)
↕ ↕ – ↕ ↕ ↕
IX1
IX
SP1
SP2
FB
9EEB ff
9EDB ee ff
AIS #opr
AIX #opr
Add Immediate Value (Signed) to SP
Add Immediate Value (Signed) to H:X
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
–
–
–
–
–
–
–
–
–
–
– IMM
– IMM
A7 ii
AF ii
2
2
AND #opr
AND opr
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
2
3
4
4
3
2
4
5
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
Logical AND
A ← (A) & (M)
0
–
–
–
↕ ↕ –
F4
9EE4 ff
9ED4 ee ff
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
DIR
INH
INH
IX1
IX
38 dd
48
58
68 ff
78
9E68 ff
4
1
1
4
3
5
Arithmetic Shift Left
(Same as LSL)
↕ –
↕ –
↕ ↕ ↕
↕ ↕ ↕
C
0
b7
b7
b0
b0
SP1
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
DIR
INH
INH
IX1
IX
37 dd
47
4
1
1
4
3
5
57
C
Arithmetic Shift Right
–
–
67 ff
77
SP1
9E67 ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
– REL
24 rr
3
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Instruction Set Summary
Table 1. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
V H I N Z C
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
4
4
4
4
4
4
4
4
BCLR n, opr
Clear Bit n in M
Mn ← 0
–
–
–
–
–
–
BCS rel
BEQ rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (Z) = 1
–
–
–
–
–
–
–
–
–
–
– REL
– REL
25 rr
27 rr
3
3
Branch if Greater Than or Equal To
(Signed Operands)
BGE opr
BGT opr
PC ← (PC) + 2 + rel ? (N V) = 0
–
–
–
–
–
–
–
–
–
–
– REL
– REL
90 rr
92 rr
3
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 + rel ? (Z) | (N
V) = 0
3
3
BHCC rel
BHCS rel
BHI rel
Branch if Half Carry Bit Clear
Branch if Half Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? (H) = 0
PC ← (PC) + 2 + rel ? (H) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
28 rr
29 rr
22 rr
3
3
3
Branch if Higher or Same
(Same as BCC)
BHS rel
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
– REL
24 rr
BIH rel
BIL rel
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
–
–
–
–
–
–
–
–
–
–
– REL
– REL
2F rr
2E rr
3
3
BIT #opr
BIT opr
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
B5 dd
C5 hh ll
D5 ee ff
E5 ff
2
3
4
4
3
2
4
5
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test
(A) & (M)
0
–
–
↕ ↕ –
F5
SP1
SP2
9EE5 ff
9ED5 ee ff
Branch if Less Than or Equal To
(Signed Operands)
BLE opr
PC ← (PC) + 2 + rel ? (Z) | (N
V) = 1
–
–
–
–
–
– REL
93 rr
3
BLO rel
BLS rel
BLT opr
BMC rel
BMI rel
BMS rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
– REL
– REL
– REL
25 rr
23 rr
91 rr
2C rr
2B rr
2D rr
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
Branch if Less Than (Signed Operands)
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? (N
V) =1
PC ← (PC) + 2 + rel ? (I) = 0
PC ← (PC) + 2 + rel ? (N) = 1
PC ← (PC) + 2 + rel ? (I) = 1
Branch if Interrupt Mask Set
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Table 1. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
V H I N Z C
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? (Z) = 0
PC ← (PC) + 2 + rel ? (N) = 0
PC ← (PC) + 2 + rel
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
26 rr
2A rr
20 rr
3
3
3
BPL rel
BRA rel
Branch if Plus
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n,opr,rel Branch if Bit n in M Clear
PC ← (PC) + 3 + rel ? (Mn) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
↕
BRN rel
Branch Never
PC ← (PC) + 2
– REL
21 rr
3
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n,opr,rel Branch if Bit n in M Set
PC ← (PC) + 3 + rel ? (Mn) = 1
↕
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
4
4
4
4
4
4
4
4
BSET n,opr
BSR rel
Set Bit n in M
Mn ← 1
–
–
–
–
–
–
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
Branch to Subroutine
–
–
–
–
–
–
–
–
–
–
– REL
AD rr
4
PC ← (PC) + rel
CBEQ opr,rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
31 dd rr
41 ii rr
51 ii rr
61 ff rr
71 rr
5
4
4
5
4
6
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
IMM
IMM
Compare and Branch if Equal
–
IX1+
IX+
CBEQ opr,SP,rel
SP1
9E61 ff rr
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
–
–
–
–
–
0
–
–
–
–
0 INH
– INH
98
9A
1
2
Clear Interrupt Mask
CLR opr
CLRA
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
3F dd
4F
3
1
1
1
3
2
4
CLRX
INH
5F
CLRH
Clear
0
–
–
0
1
– INH
IX1
IX
SP1
8C
CLR opr,X
CLR ,X
6F ff
7F
CLR opr,SP
9E6F ff
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Instruction Set Summary
Table 1. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
V H I N Z C
CMP #opr
IMM
DIR
EXT
IX2
A1 ii
B1 dd
C1 hh ll
D1 ee ff
E1 ff
2
3
4
4
3
2
4
5
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
Compare A with M
(A) – (M)
↕ –
–
↕ ↕ ↕
IX1
IX
SP1
SP2
F1
CMP opr,SP
CMP opr,SP
9EE1 ff
9ED1 ee ff
COM opr
COMA
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
33 dd
43
4
1
1
4
3
5
COMX
53
Complement (One’s Complement)
Compare H:X with M
0
–
–
–
↕ ↕ 1
COM opr,X
COM ,X
COM opr,SP
63 ff
73
9E63 ff
SP1
CPHX #opr
CPHX opr
IMM
DIR
65 ii ii+1
75 dd
3
4
(H:X) – (M:M + 1)
↕ –
↕ –
↕ ↕ ↕
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
B3 dd
C3 hh ll
D3 ee ff
E3 ff
2
3
4
4
3
2
4
5
Compare X with M
(X) – (M)
–
↕ ↕ ↕
F3
SP1
SP2
9EE3 ff
9ED3 ee ff
DAA
Decimal Adjust A
(A)
U
–
–
–
–
–
↕ ↕ ↕ INH
72
2
10
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
5
3
3
5
4
6
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DIR
INH
– INH
IX1
IX
3B dd rr
4B rr
Decrement and Branch if Not Zero
–
–
5B rr
6B ff rr
7B rr
SP1
9E6B ff rr
DEC opr
DECA
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
SP1
3A dd
4A
4
1
1
4
3
5
DECX
5A
Decrement
Divide
↕ –
–
–
↕ ↕ –
DEC opr,X
DEC ,X
DEC opr,SP
6A ff
7A
9E6A ff
A ← (H:A)/(X)
H ← Remainder
DIV
–
0
–
–
–
↕ ↕ INH
52
7
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
2
3
4
4
3
2
4
5
Exclusive OR M with A
A ← (A
M)
–
↕ ↕ –
F8
SP1
SP2
9EE8 ff
9ED8 ee ff
13-cpu
MC68HC08AZ60 — Rev 1.0
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Ce ntra l Proc e ssor Unit (CPU)
Table 1. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
V H I N Z C
INC opr
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C dd
4C
4
1
1
4
3
5
INCA
INCX
5C
Increment
Jump
↕ –
–
↕ ↕ –
INC opr,X
INC ,X
6C ff
7C
9E6C ff
INC opr,SP
SP1
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT
– IX2
IX1
IX
BC dd
CC hh ll
DC ee ff
EC ff
2
3
4
3
2
PC ← Jump Address
–
–
–
–
–
–
–
–
–
–
FC
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT
– IX2
IX1
BD dd
CD hh ll
DD ee ff
ED ff
4
5
6
5
4
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
Jump to Subroutine
IX
FD
LDA #opr
LDA opr
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A6 ii
B6 dd
C6 hh ll
D6 ee ff
E6 ff
2
3
4
4
3
2
4
5
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
Load A from M
Load H:X from M
Load X from M
A ← (M)
H:X ← (M:M + 1)
X ← (M)
0
0
0
–
–
–
–
–
–
↕ ↕ –
↕ ↕ –
↕ ↕ –
F6
9EE6 ff
9ED6 ee ff
LDHX #opr
LDHX opr
IMM
DIR
45 ii jj
55 dd
3
4
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
IMM
DIR
EXT
IX2
IX1
IX
AE ii
BE dd
CE hh ll
DE ee ff
EE ff
FE
9EEE ff
9EDE ee ff
2
3
4
4
3
2
4
5
SP1
SP2
LSL opr
LSLA
DIR
INH
INH
IX1
IX
38 dd
48
4
1
1
4
3
5
LSLX
Logical Shift Left
(Same as ASL)
58
C
0
↕ –
↕ –
–
–
↕ ↕ ↕
LSL opr,X
LSL ,X
LSL opr,SP
68 ff
78
9E68 ff
b7
b0
SP1
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
DIR
INH
INH
IX1
IX
34 dd
44
54
64 ff
74
9E64 ff
4
1
1
4
3
5
0
C
Logical Shift Right
0 ↕ ↕
b7
b0
SP1
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
DD
4E dd dd
5E dd
5
4
4
4
(M)
← (M)
Source
Destination
DIX+
IMD
IX+D
Move
0
–
–
0
–
–
↕ ↕ –
6E ii dd
7E dd
H:X ← (H:X) + 1 (IX+D, DIX+)
X:A ← (X) × (A)
MUL
Unsigned multiply
–
–
0 INH
42
5
14-cpu
MC68HC08AZ60 — Rev 1.0
78
Central Processor Unit (CPU)
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Central Processor Unit (CPU)
Instruction Set Summary
Table 1. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
V H I N Z C
NEG opr
DIR
INH
INH
IX1
IX
30 dd
40
4
1
1
4
3
5
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
NEGA
NEGX
50
Negate (Two’s Complement)
↕ –
–
↕ ↕ ↕
NEG opr,X
NEG ,X
60 ff
70
9E60 ff
NEG opr,SP
SP1
NOP
NSA
No Operation
None
–
–
–
–
–
–
–
–
–
–
– INH
– INH
9D
62
1
3
Nibble Swap A
A ← (A[3:0]:A[7:4])
ORA #opr
ORA opr
IMM
DIR
EXT
IX2
AA ii
BA dd
CA hh ll
DA ee ff
EA ff
2
3
4
4
3
2
4
5
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Inclusive OR A and M
A ← (A) | (M)
0
–
–
↕ ↕ –
IX1
IX
FA
SP1
SP2
9EEA ff
9EDA ee ff
PSHA
PSHH
PSHX
PULA
PULH
PULX
Push A onto Stack
Push H onto Stack
Push X onto Stack
Pull A from Stack
Pull H from Stack
Pull X from Stack
Push (A); SP ← (SP) – 1
Push (H); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
SP ← (SP + 1); Pull (A)
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
– INH
– INH
– INH
87
8B
89
86
8A
88
2
2
2
2
2
2
ROL opr
ROLA
DIR
INH
INH
39 dd
49
4
1
1
4
3
5
ROLX
59
C
Rotate Left through Carry
Rotate Right through Carry
↕ –
↕ –
–
↕ ↕ ↕
↕ ↕ ↕
ROL opr,X
ROL ,X
ROL opr,SP
IX1
IX
69 ff
79
9E69 ff
b7
b0
SP1
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
DIR
INH
INH
IX1
IX
36 dd
46
56
66 ff
76
9E66 ff
4
1
1
4
3
5
C
–
–
b7
b0
SP1
RSP
RTI
Reset Stack Pointer
Return from Interrupt
SP ← $FF
–
–
–
–
– INH
9C
80
1
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕ ↕ ↕ ↕ ↕ ↕ INH
7
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
RTS
Return from Subroutine
–
–
–
–
–
– INH
81
4
15-cpu
MC68HC08AZ60 — Rev 1.0
79
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Central Processor Unit (CPU)
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Ce ntra l Proc e ssor Unit (CPU)
Table 1. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
V H I N Z C
SBC #opr
IMM
DIR
EXT
IX2
A2 ii
B2 dd
C2 hh ll
D2 ee ff
E2 ff
2
3
4
4
3
2
4
5
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract with Carry
A ← (A) – (M) – (C)
↕ –
–
↕ ↕ ↕
IX1
IX
SP1
SP2
F2
SBC opr,SP
SBC opr,SP
9EE2 ff
9ED2 ee ff
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
–
–
–
–
–
1
–
–
–
–
1 INH
– INH
99
9B
1
2
Set Interrupt Mask
STA opr
DIR
EXT
IX2
B7 dd
C7 hh ll
D7 ee ff
E7 ff
3
4
4
3
2
4
5
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
M ← (A)
0
–
–
↕ ↕ – IX1
IX
SP1
SP2
F7
9EE7 ff
9ED7 ee ff
STHX opr
Store H:X in M
(M:M + 1) ← (H:X)
0
–
–
–
–
0
↕ ↕ – DIR
35 dd
8E
4
1
STOP
Enable IRQ Pin; Stop Oscillator
I ← 0; Stop Oscillator
–
–
– INH
STX opr
DIR
EXT
IX2
BF dd
CF hh ll
DF ee ff
EF ff
3
4
4
3
2
4
5
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M
M ← (X)
0
–
–
–
↕ ↕ – IX1
IX
SP1
SP2
FF
9EEF ff
9EDF ee ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
IMM
DIR
EXT
A0 ii
B0 dd
C0 hh ll
D0 ee ff
E0 ff
2
3
4
4
3
2
4
5
IX2
↕ ↕ ↕
IX1
Subtract
A ← (A) – (M)
↕ –
IX
SP1
SP2
F0
9EE0 ff
9ED0 ee ff
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
Software Interrupt
–
–
1
–
–
– INH
83
9
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
TAX
TPA
Transfer A to CCR
Transfer A to X
CCR ← (A)
X ← (A)
↕ ↕ ↕ ↕ ↕ ↕ INH
84
97
85
2
1
1
–
–
–
–
–
–
–
–
–
–
– INH
– INH
Transfer CCR to A
A ← (CCR)
16-cpu
MC68HC08AZ60 — Rev 1.0
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Central Processor Unit (CPU)
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Central Processor Unit (CPU)
Opcode Map
Table 1. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
V H I N Z C
TST opr
DIR
INH
INH
IX1
IX
3D dd
4D
3
1
1
3
2
4
TSTA
TSTX
5D
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0
–
–
↕ ↕ –
TST opr,X
TST ,X
6D ff
7D
9E6D ff
TST opr,SP
SP1
TSX
Transfer SP to H:X
Transfer X to A
H:X ← (SP) + 1
A ← (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
95
9F
94
2
1
2
TXA
TXS
Transfer H:X to SP
(SP) ← (H:X) – 1
A Accumulatorn
Any bit
C Carry/borrow bitopr
CCRCondition code registerPC
Operand (one or two bytes)
Program counter
ddDirect address of operandPCH
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Stack pointer
dd rrDirect address of operand and relative offset of branch instructionPCL
DDDirect to direct addressing modeREL
DIRDirect addressing moderel
DIX+Direct to indexed with post increment addressing moderr
ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingSP1
EXTExtended addressing modeSP2
ff Offset byte in indexed, 8-bit offset addressingSP
H Half-carry bitU
Undefined
H Index register high byteV
Overflow bit
hh llHigh and low bytes of operand address in extended addressingX
I Interrupt maskZ
Index register low byte
Zero bit
ii Immediate operand byte&
Logical AND
IMDImmediate source to direct destination addressing mode|
IMMImmediate addressing mode
INHInherent addressing mode( )
Logical OR
Logical EXCLUSIVE OR
Contents of
IXIndexed, no offset addressing mode–( )
IX+Indexed, no offset, post increment addressing mode#
IX+DIndexed with post increment to direct addressing mode«
IX1Indexed, 8-bit offset addressing mode←
IX1+Indexed, 8-bit offset, post increment addressing mode?
IX2Indexed, 16-bit offset addressing mode:
MMemory location↕
Negation (two’s complement)
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
N Negative bit—
Not affected
Op c od e Ma p
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MC68HC08AZ60 — Rev 1.0
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Central Processor Unit (CPU)
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Ce ntra l Proc e ssor Unit (CPU)
18-cpu
MC68HC08AZ60 — Rev 1.0
82
Central Processor Unit (CPU)
MOTOROLA
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Syste m Inte g ra tion Mod ule (SIM)
Syste m Inte g ra tion Mod ule (SIM)
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . 87
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . 88
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . 88
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Active Resets from Internal Sources. . . . . . . . . . . . . . . . . . . . . . . . 89
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . 91
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 92
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SIM Counter During Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . 93
SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . . . . . . . 93
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Program Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . 98
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 103
1-sim
MC68HC08AZ60 — Rev 1.0
MOTOROLA
System Integration Module (SIM)
83
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Syste m Inte g ra tion Mod ule (SIM)
Introd uc tion
This section describes the system integration module (SIM), which
supports up to 32 external and/or internal interrupts. Together with the
central processor unit (CPU), the SIM controls all MCU activities. A block
diagram of the SIM is shown in Figure 1. Figure 2 is a summary of the
SIM input/output (I/O) registers. The SIM is a system state controller that
coordinates CPU and exception timing. The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and
computer operating properly (COP) timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
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System Integration Module (SIM)
Introduction
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO CGM)
SIM
COUNTER
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
÷ 2
CLOCK
CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
MASTER
RESET
CONTROL
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
SIM RESET STATUS REGISTER
COP (FROM COP MODULE)
RESET
INTERRUPT SOURCES
CPU INTERFACE
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 1. SIM Block Diagram
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Syste m Inte g ra tion Mod ule (SIM)
Register Name
Bit 7
6
R
5
R
4
R
3
R
2
R
0
1
SBSW
LVI
Bit 0
SIM Break Status Register (SBSR)
R
R
0
SIM Reset Status Register (SRSR) POR
PIN
R
COP
R
ILOP
R
ILAD
R
SIM Break Flag Control Register (SBFCR) BCFE
R
R
R
R
=Reserved
Figure 2. SIM I/O Register Summary
Table 1. I/O Register Address Summary
Register
Address
SBSR
$FE00
SRSR
$FE01
SBFCR
$FE03
Table 2 shows the internal signal names used in this section.
Table 2. Signal Name Conventions
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
Description
Buffered Version of OSC1 from Clock Generator Module
(CGM)
PLL Output
PLL-Based or OSC1-Based Clock Output from CGM Module
(Bus Clock = CGMOUT Divided by Two)
IAB
IDB
Internal Address Bus
Internal Data Bus
PORRST
IRST
Signal from the Power-On Reset Module to the SIM
Internal Reset Signal
R/W
Read/Write Signal
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System Integration Module (SIM)
SIM Bus Clock Control and Generation
SIM Bus Cloc k Control a nd Ge ne ra tion
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 3. This clock can come
from either an external oscillator or from the on-chip PLL. (See
Clock Generator Module (CGM) on page 105).
Bus Tim ing
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. (See Clock Generator Module (CGM) on page 105).
Cloc k Sta rtup from
POR or LVI Re se t
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after 4096 CGMXCLK cycles. The
RST pin is driven low by the SIM during this entire period. The bus clocks
start upon completion of the timeout.
CGMXCLK
OSC1
SIM COUNTER
CLOCK
SELECT
CIRCUIT
A
B
CGMOUT
BUS CLOCK
GENERATORS
÷ 2
÷ 2
CGMVCLK
S*
*When S = 1,
CGMOUT = B
BCS
SIM
PLL
PTC3
MONITOR MODE
USER MODE
CGM
Figure 3. CGM Clock Signals
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Syste m Inte g ra tion Mod ule (SIM)
Cloc ks in Stop
Mod e a nd Wa it
Mod e
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles. See Stop Mode on page
100.
In wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
Re se t a nd Syste m Initia liza tion
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see SIM Counter on page 93),
but an external reset does not. Each of the resets sets a corresponding
bit in the SIM reset status register (SRSR) (see SIM Registers on page
101).
Exte rna l Pin Re se t
Pulling the asynchronous RST pin low halts all processing. The PIN bit
of the SIM reset status register (SRSR) is set as long as RST is held low
for a minimum of 67 CGMXCLK cycles, assuming that neither the POR
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System Integration Module (SIM)
Reset and System Initialization
nor the LVI was the source of the reset. See Table 3 for details. Figure
4 shows the relative timing.
Table 3. PIN Bit Set Timing
Reset Type
POR/LVI
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
CGMOUT
RST
IAB
VECT H VECT L
PC
Figure 4. External Reset Timing
Ac tive Re se ts from
Inte rna l Sourc e s
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles (see Figure
5). An internal reset can be caused by an illegal address, illegal opcode,
COP timeout, LVI, or POR (see Figure 6). Note that for LVI or POR
resets, the SIM cycles through 4096 CGMXCLK cycles during which the
SIM forces the RST pin low. The internal reset signal then follows the
sequence from the falling edge of RST shown in Figure 5.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
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Syste m Inte g ra tion Mod ule (SIM)
IRST
RST
RSTPULLED LOW BY MCU
32 CYCLES
32 CYCLES
CGMXCLK
IAB
VECTOR HIGH
Figure 5. Internal Reset Timing
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
INTERNAL RESET
POR
Figure 6. Sources of Internal Reset
Po we r-On Re se t
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Another sixty-four CGMXCLK cycles later, the
CPU and memories are released from reset to allow the reset vector
sequence to occur.
At power-on, the following events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables CGMOUT.
• Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
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System Integration Module (SIM)
Reset and System Initialization
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
CGMXCLK
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 7. POR Recovery
Com p ute r
Op e ra ting
Pro p e rly (COP)
Re se t
The overflow of the COP counter causes an internal reset and sets the
COP bit in the SIM reset status register (SRSR) if the COPD bit in the
CONFIG-1 register is at logic zero.
See Computer Operating Properly Module (COP) on page 153.
Ille g a l Op c o d e
Re se t
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the MOR register is logic zero, the SIM
treats the STOP instruction as an illegal opcode and causes an illegal
opcode reset.
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Syste m Inte g ra tion Mod ule (SIM)
Ille g a l Ad d re ss
Re se t
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset.
Extra care should be exercised if code running in these parts is
eventually shrunk into a smaller ROM size. Code errors may result
in illegal addresses being accessed. Devices with smaller ROM
sizes may behave in a different manner in this instance. Is is the
user’s responsibility to check their code for illegal addresses.
Also note that some HC08 devices generate illegal address resets
with data fetches under certain circumstances. User’s should
always check relevant data books and always check their code for
illegal addresses.
Lo w-Vo lta g e
Inhib it (LVI) Re se t
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the VDD voltage falls to the VLVII voltage. The LVI bit in the SIM reset
status register (SRSR) is set and a chip reset is asserted if the LVIPWRD
and LVIRSTD bits in the CONFIG-1 register are at logic zero. The RST
pin will be held low until the SIM counts 4096 CGMXCLK cycles after
V
DD rises above VLVIR. Another sixty-four CGMXCLK cycles later, the
CPU is released from reset to allow the reset vector sequence to occur.
See Low-Voltage Inhibit (LVI) on page 159.
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System Integration Module (SIM)
SIM Counter
SIM Counte r
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM
counter overflow supplies the clock for the COP module. The SIM
counter is 12 bits long and is clocked by the falling edge of CGMXCLK.
SIM Counte r
During Powe r-On
Re se t
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the clock generation module (CGM) to drive the
bus clock state machine.
SIM Counte r
During Stop Mod e
Re c ove ry
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic one, then the stop recovery is
reduced from the normal delay of 4096 CGMXCLK cycles down to 32
CGMXCLK cycles. This is ideal for applications using canned oscillators
that do not require long start-up times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC
cleared.
SIM Counte r a nd
Re se t Sta te s
External reset has no effect on the SIM counter. See Stop Mode on
page 100 for details. The SIM counter is free-running after all reset
states. See Active Resets from Internal Sources on page 89 for
counter control and internal reset recovery sequences.
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Syste m Inte g ra tion Mod ule (SIM)
Prog ra m Exc e p tion Control
Normal, sequential program execution can be changed in three different
ways:
• Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
Inte rrup ts
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 8 shows interrupt entry timing. Figure
10 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared), see Figure
9.
MODULE
INTERRUPT
I BIT
IAB
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4
VECT H
VECT L START ADDR
IDB
R/W
DUMMY
PC – 1[7:0] PC–1[15:8]
X
A
CCR
V DATA H V DATA L OPCODE
Figure 8. Interrupt Entry
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System Integration Module (SIM)
Program Exception Control
FROM RESET
YES
BREAK INTERRUPT?
NO
YES
I BIT SET?
NO
YES
IRQ
INTERRUPT?
NO
STACK CPU REGISTERS.
SET I BIT.
(AS MANY INTERRUPTS
AS EXIST ON CHIP)
LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT
INSTRUCTION.
YES
YES
SWI
INSTRUCTION?
NO
RTI
UNSTACK CPU REGISTERS.
EXECUTE INSTRUCTION.
INSTRUCTION?
NO
Figure 9. Interrupt Processing
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Syste m Inte g ra tion Mod ule (SIM)
MODULE
INTERRUPT
I BIT
IAB
IDB
SP – 4
SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
CCR
A
X
PC –1 [7:0] PC–1[15:8] OPCODE OPERAND
R/W
Figure 10. Interrupt Recovery
Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing
of a hardware interrupt begins after completion of the current
instruction. When the current instruction is complete, the SIM checks
all pending hardware interrupts. If interrupts are not masked (I bit
clear in the condition code register), and if the corresponding interrupt
enable bit is set, the SIM proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first. Figure 11
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service
routine, the pending interrupt is serviced before the LDA instruction is
executed.
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE: To maintain compatibility with the M68HC05, M6805 and M146805
Families the H register is not pushed on the stack during interrupt entry.
If the interrupt service routine modifies the H register or uses the indexed
addressing mode, software should save the H register and then restore
it prior to exiting the routine.
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System Integration Module (SIM)
Program Exception Control
CLI
BACKGROUND
ROUTINE
LDA #$FF
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 11. Interrupt Recognition Example
SWI Instruction
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE: A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
Re se t
All reset sources always have higher priority than interrupts and cannot
be arbitrated.
Bre a k Inte rrup ts
The break module can stop normal program flow at a
software-programmable break point by asserting its break interrupt
output. See Break Module on page 135. The SIM puts the CPU into the
break state by forcing it to the SWI vector location. Refer to the break
interrupt subsection of each module to see how each module is affected
by the break state.
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Syste m Inte g ra tion Mod ule (SIM)
Sta tus Fla g
Prote c tion in Bre a k
Mod e
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a two-step clearing mechanism — for example, a read
of one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the
flag as normal.
Low-Powe r Mod e s
Executing the WAIT or STOP instruction puts the MCU in a low power-
consumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described
below. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
Wa it Mod e
In wait mode, the CPU clocks are inactive while one set of peripheral
clocks continue to run. Figure 12 shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module
is active or inactive in wait mode. Some modules can be programmed to
be active in wait mode.
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM
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System Integration Module (SIM)
Low-Power Modes
break status register (SBSR). If the COP disable bit, COPD, in the
configuration register is logic 0, then the computer operating properly
module (COP) is enabled and remains active in wait mode.
IAB
IDB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 12. Wait Mode Entry Timing
IAB
IDB
$6E0B
$A6
$6E0C
$00FF
$00FE
$00FD
$00FC
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 13. Wait Recovery from Interrupt or Break
32
Cycles
32
Cycles
IAB
$6E0B
$A6
RSTVCTH RSTVCTL
IDB $A6
RST
$A6
CGMXCLK
Figure 14. Wait Recovery from Internal Reset
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Syste m Inte g ra tion Mod ule (SIM)
Stop Mod e
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and
CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop
recovery time is selectable using the SSREC bit in the mask option
register (MOR). If SSREC is set, stop recovery is reduced from the
normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for
applications using canned oscillators that do not require long startup
times from stop mode.
NOTE: External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 15 shows stop mode entry timing.
CPUSTOP
IAB
IDB
STOP ADDR
STOP ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 15. Stop Mode Entry Timing
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System Integration Module (SIM)
SIM Registers
STOP RECOVERY PERIOD
CGMXCLK
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP –1
SP –2
SP –3
Figure 16. Stop Mode Recovery from Interrupt or Break
SIM Re g iste rs
The SIM has three memory mapped registers.
SIM Bre a k Sta tus
Re g iste r
The SIM break status register contains a flag to indicate that a break
caused an exit from stop or wait mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
SBSW
See Note
0
Bit 0
R
Read:
Write:
Reset:
R
R
R
R
R
R
R
= Reserved
NOTE: Writing a logic 0 clears SBSW
Figure 17. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
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following code is an example of this. Writing zero to the SBSW bit
clears it.
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the
; break service routine software.
HIBYTE EQU
LOBYTE EQU
5
6
;
If not SBSW, do RTI
BRCLR SBSW,SBSR, RETURN ; See if wait mode or stop mode was exited
; by break.
TST
BNE
DEC
DEC
LOBYTE,SP
DOLO
; If RETURNLO is not zero,
; then just decrement low byte.
; Else deal with high byte, too.
; Point to WAIT/STOP opcode.
; Restore H register.
HIBYTE,SP
LOBYTE,SP
DOLO
RETURN PULH
RTI
SIM Re se t Sta tus
Re g iste r
This register contains six flags that show the source of the last reset. The
status register will automatically clear after reading it. A power-on reset
sets the POR bit and clears all other bits in the register.
Address: $FE01
Bit 7
POR
6
5
4
3
2
0
1
Bit 0
0
Read:
Write:
POR:
PIN
COP
ILOP
ILAD
LVI
1
0
0
0
0
0
0
0
= Unimplemented
Figure 18. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
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SIM Registers
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset was caused by the LVI circuit
0 = POR or read of SRSR
SIM Bre a k Fla g
Control Re g iste r
The SIM break control register contains a bit that enables software to
clear status bits while the MCU is in a break state.
Address: $FE03
Bit 7
6
5
4
3
2
1
R
0
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
0
R
=Reserved
Figure 19. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
21-sim
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Cloc k Ge ne ra tor Mod ule (CGM)
Cloc k Ge ne ra tor Mod ule (CGM)
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Phase-Locked Loop Circuit (PLL). . . . . . . . . . . . . . . . . . . . . . . . . 109
Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . . . 111
Manual and Automatic PLL Bandwidth Modes. . . . . . . . . . . . . 111
Programming the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Special Programming Exceptions. . . . . . . . . . . . . . . . . . . . . . . 115
Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . . . . . . . 117
Crystal Amplifier Output Pin (OSC2). . . . . . . . . . . . . . . . . . . . . . . 117
External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . 117
Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . 118
Crystal Output Frequency Signal (CGMXCLK). . . . . . . . . . . . . . . 118
CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . 118
CGM CPU Interrupt (CGMINT). . . . . . . . . . . . . . . . . . . . . . . . . . . 118
CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
PLL Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
PLL Bandwidth Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . 121
PLL Programming Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . . . . . . 126
Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 126
1-cgm
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Parametric Influences on Reaction Time . . . . . . . . . . . . . . . . . . .128
Choosing a Filter Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Introd uc tion
The CGM generates the crystal clock signal, CGMXCLK, which operates
at the frequency of the crystal. The CGM also generates the base clock
signal, CGMOUT, from which the system clocks are derived. CGMOUT
is based on either the crystal clock divided by two or the phase-locked
loop (PLL) clock, CGMVCLK, divided by two. The PLL is a frequency
generator designed for use with 1-MHz to 8-MHz crystals or ceramic
resonators. The PLL can generate an 8-MHz bus frequency without
using a 32-MHz crystal.
Fe a ture s
Features of the CGM include:
• Phase-Locked Loop with Output Frequency in Integer Multiples of
the Crystal Reference
• Programmable Hardware Voltage-Controlled Oscillator (VCO) for
Low-Jitter Operation
• Automatic Bandwidth Control Mode for Low-Jitter Operation
• Automatic Frequency Lock Detector
• CPU Interrupt on Entry or Exit from Locked Condition
2-cgm
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Clock Generator Module (CGM)
Functional Description
Func tiona l De sc rip tion
The CGM consists of three major submodules:
• Crystal oscillator circuit — The crystal oscillator circuit generates
the constant crystal frequency clock, CGMXCLK.
• Phase-locked loop (PLL) — The PLL generates the
programmable VCO frequency clock CGMVCLK.
• Base clock selector circuit — This software-controlled circuit
selects either CGMXCLK divided by two or the VCO clock,
CGMVCLK, divided by two as the base clock, CGMOUT. The
system clocks are derived from CGMOUT.
Figure 1 shows the structure of the CGM.
Crysta l Osc illa tor
Circ uit
The crystal oscillator circuit consists of an inverting amplifier and an
external crystal. The OSC1 pin is the input to the amplifier and the OSC2
pin is the output. The SIMOSCEN signal enables the crystal oscillator
circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and
runs at a rate equal to the crystal frequency. CGMXCLK is then buffered
to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing
for operation. The duty cycle of CGMXCLK is not guaranteed to be 50%
and depends on external factors, including the crystal and related
external components.
An externally generated clock also can feed the OSC1 pin of the crystal
oscillator circuit. Connect the external clock to the OSC1 pin and let the
OSC2 pin float.
3-cgm
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CGMXCLK
CGMOUT
OSC1
CLOCK
SELECT
CIRCUIT
A
B
÷ 2
S*
*When S = 1,
CGMOUT = B
CGMRDV
CGMRCLK
BCS
PTC3
V
CGMXFC
V
SS
DDA
MONITOR MODE
VRS7–VRS4
USER MODE
VOLTAGE
CONTROLLED
OSCILLATOR
PHASE
DETECTOR
LOOP
FILTER
PLL ANALOG
CGMINT
LOCK
DETECTOR
BANDWIDTH
CONTROL
INTERRUPT
CONTROL
LOCK
AUTO
ACQ
PLLIE
PLLF
MUL7–MUL4
CGMVDV
CGMVCLK
FREQUENCY
DIVIDER
Figure 1. CGM Block Diagram
4-cgm
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Clock Generator Module (CGM)
Functional Description
Register Name
Bit 7
PLLIE
0
6
5
PLLON
1
4
BCS
0
3
2
1
Bit 0
Read:
PLLF
1
1
1
1
PLL Control Register (PCTL) Write:
Reset:
0
LOCK
0
1
0
0
1
0
0
1
0
0
1
0
0
Read:
AUTO
0
ACQ
0
XLD
0
PLL Bandwidth Control Register
Write:
(PBWC)
Reset:
Read:
PLL Programming Register (PPG) Write:
Reset:
MUL7
0
MUL6
1
MUL5
1
MUL4
0
VRS7
0
VRS6
1
VRS5
1
VRS4
0
= Unimplemented
Figure 2. I/O Register Summary
Table 1. I/O Register Address Summary
Register
Address
PCTL
PBWC
$001D
PPG
$001C
$001E
Pha se -Loc ke d
Loop Circ uit (PLL)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
Circ uits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
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Cloc k Ge ne ra tor Mod ule (CGM)
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, fVRS
.
Modulating the voltage on the CGMXFC pin changes the frequency
within this range. By design, fVRS is equal to the nominal center-of-range
frequency, fNOM, (4.9152 MHz) times a linear factor L or (L)fNOM
.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, fRCLK, and is fed to the PLL through a
buffer. The buffer output is the final reference clock, CGMRDV, running
at a frequency fRDV = fRCLK
.
The VCO’s output clock, CGMVCLK, running at a frequency fVCLK, is fed
back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor, N. The divider’s output is the VCO
feedback clock, CGMVDV, running at a frequency fVDV = fVCLK/N. See
Programming the PLL for more information.
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the dc voltage on the external capacitor connected to
CGMXFC based on the width and direction of the correction pulse. The
filter can make fast or slow corrections depending on its mode, as
described in Acquisition and Tracking Modes on page 111. The value
of the external capacitor and the reference frequency determines the
speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, fRDV. The circuit determines the mode of the PLL and the lock
condition based on this comparison.
6-cgm
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Clock Generator Module (CGM)
Functional Description
Ac q uisitio n a nd
Tra c king Mo d e s
The PLL filter is manually or automatically configurable into one of two
operating modes:
• Acquisition mode — In acquisition mode, the filter can make large
frequency corrections to the VCO. This mode is used at PLL
startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in
acquisition mode, the ACQ bit is clear in the PLL bandwidth control
register. See PLL Bandwidth Control Register on page 121.
• Tracking mode — In tracking mode, the filter makes only small
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. See Base Clock Selector Circuit on page 115. The PLL
is automatically in tracking mode when it’s not in acquisition mode
or when the ACQ bit is set.
Ma nua l a nd
Auto m a tic PLL
Ba nd wid th Mo d e s
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. See PLL Bandwidth Control Register on page 121. If PLL
CPU interrupt requests are enabled, the software can wait for a PLL
CPU interrupt request and then check the LOCK bit. If CPU interrupts
are disabled, software can poll the LOCK bit continuously (during PLL
startup, usually) or at periodic intervals. In either case, when the LOCK
bit is set, the VCO clock is safe to use as the source for the base clock.
See Base Clock Selector Circuit on page 115. If the VCO is selected
as the source for the base clock and the LOCK bit is clear, the PLL has
suffered a severe noise hit and the software must take appropriate
action, depending on the application. See Interrupts on page 125.
These conditions apply when the PLL is in automatic bandwidth control
mode:
7-cgm
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• The ACQ bit (See PLL Bandwidth Control Register.) is a read-only
indicator of the mode of the filter. See Acquisition and Tracking
Modes on page 111.
• The ACQ bit is set when the VCO frequency is within a certain
tolerance, ∆trk, and is cleared when the VCO frequency is out of a
certain tolerance, ∆unt. See Electrical Specifications on page
408.
• The LOCK bit is a read-only indicator of the locked state of the
PLL.
• The LOCK bit is set when the VCO frequency is within a certain
tolerance, ∆Lock, and is cleared when the VCO frequency is out of
a certain tolerance, ∆unl. See Electrical Specifications on page
408.
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. See PLL Control
Register on page 119.
The PLL also can operate in manual mode (AUTO = 0). Manual mode is
used by systems that do not require an indicator of the lock condition for
proper operation. Such systems typically operate well below fbusmax and
require fast startup. The following conditions apply when in manual
mode:
• ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
• Before entering tracking mode (ACQ = 1), software must wait a
given time, tacq (see Electrical Specifications on page 408), after
turning on the PLL by setting PLLON in the PLL control register
(PCTL).
• Software must wait a given time, tal, after entering tracking mode
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
8-cgm
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Clock Generator Module (CGM)
Functional Description
Pro g ra m m ing the
PLL
Use this 9-step procedure to program the PLL. The table below lists the
variables used and their meaning.
Table 2. Variable Definitions
Variable
fBUSDES
fVCLKDES
fRCLK
Definition
Desired Bus Clock Frequency
Desired VCO Clock Frequency
Chosen Reference Crystal Frequency
Calculated VCO Clock Frequency
Calculated Bus Clock Frequency
Nominal VCO Center Frequency
Shifted VCO Center Frequency
fVCLK
fBUS
fNOM
fVRS
1. Choose the desired bus frequency, fBUSDES
.
Example: fBUSDES = 8 MHz
2. Calculate the desired VCO frequency, fVCLKDES
fVCLKDES = 4 × fBUSDES
.
Example: fVCLKDES = 4 × 8 MHz = 32 MHz
3. Using a reference frequency, fRCLK, equal to the crystal frequency,
calculate the VCO frequency multiplier, N. Round the result to the
nearest integer.
fVCLKDES
N = ----------------------
f
RCLK
32 MHz
Example: N = -------------------- = 8
4 MHz
4. Calculate the VCO frequency, fVCLK
.
fVCLK = N × fRCLK
Example: fVCLK = 8 × 4 MHz = 32 MHz
5. Calculate the bus frequency, fBUS, and compare fBUS with
fBUSDES
.
9-cgm
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fVCLK
fBUS = -------------
4
32 MHz
Example: fBUS= -------------------- = 8 MHz
4
6. If the calculated fbus is not within the tolerance limits of your
application, select another fBUSDES or another fRCLK
.
7. Using the value 4.9152 MHz for fNOM, calculate the VCO linear
range multiplier, L. The linear range multiplier controls the
frequency range of the PLL.
fVCLK
L = round -----------
-
fNOM
32 MHz
-------------------------------
4.9152 MHz
Example: L =
= 7
8. Calculate the VCO center-of-range frequency, fVRS. The
center-of-range frequency is the midpoint between the minimum
and maximum frequencies attainable by the PLL.
fVRS = L × fNOM
Example: fVRS = 7 × 4.9152 MHz = 34.4 MHz
fNOM
----------------
NOTE: For proper operation,fVRS – fVCLK
≤
.
2
Exceeding the recommended maximum bus frequency or VCO
frequency can crash the MCU.
9. Program the PLL registers accordingly:
a. In the upper four bits of the PLL programming register (PPG),
program the binary equivalent of N.
b. In the lower four bits of the PLL programming register (PPG),
program the binary equivalent of L.
10-cgm
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Clock Generator Module (CGM)
Functional Description
Sp e c ia l
Pro g ra m m ing
Exc e p tio ns
The programming method described in Programming the PLL on page
113, does not account for two possible exceptions. A value of 0 for N or
L is meaningless when used in the equations given. To account for these
exceptions:
• A 0 value for N is interpreted the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the
source for the base clock. See Base Clock Selector Circuit on
page 115.
Ba se Cloc k
Se le c tor Circ uit
This circuit is used to select either the crystal clock, CGMXCLK, or the
VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The
two input clocks go through a transition control circuit that waits up to
three CGMXCLK cycles and three CGMVCLK cycles to change from
one clock source to the other. During this time, CGMOUT is held in
stasis. The output of the transition control circuit is then divided by two
to correct the duty cycle. Therefore, the bus clock frequency, which is
one-half of the base clock frequency, is one-fourth the frequency of the
selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source
if the PLL is not turned on. The PLL cannot be turned off if the VCO clock
is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the VCO clock. The VCO clock also cannot
be selected as the base clock source if the factor L is programmed to a
0. This value would set up a condition inconsistent with the operation of
the PLL, so that the PLL would be disabled and the crystal clock would
be forced as the source of the base clock.
CGM Exte rna l
Conne c tions
In its typical configuration, the CGM requires seven external
components. Five of these are for the crystal oscillator and two are for
the PLL.
The crystal oscillator is normally connected in a Pierce oscillator
configuration, as shown in Figure 3. Figure 3 shows only the logical
11-cgm
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representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
• Crystal, X1
• Fixed capacitor, C1
• Tuning capacitor, C2 (can also be a fixed capacitor)
• Feedback resistor, RB
• Series resistor, RS (optional)
The series resistor (RS) may not be required for all ranges of operation,
especially with high-frequency crystals. Refer to the crystal
manufacturer’s data for more information.
Figure 3 also shows the external components for the PLL:
• Bypass capacitor, CBYP
• Filter capacitor, CF
Routing should be done with great care to minimize signal cross talk and
noise. (See Acquisition/Lock Time Specifications on page 126 for
routing information and more information on the filter capacitor’s value
and its effects on PLL performance).
12-cgm
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Clock Generator Module (CGM)
I/O Signals
SIMOSCEN
CGMXCLK
V
DD
*
R
C
S
F
C
R
BYP
B
X
1
C
C
2
1
*R can be 0 (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data.
S
Figure 3. CGM External Connections
I/ O Sig na ls
The following paragraphs describe the CGM input/output (I/O) signals.
The OSC1 pin is an input to the crystal oscillator amplifier.
Crysta l Am p lifie r
Inp ut Pin (OSC1)
Crysta l Am p lifie r
Outp ut Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
Exte rna l Filte r
Ca p a c itor Pin
(CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase
corrections. A small external capacitor is connected to this pin.
NOTE: To prevent noise problems, CF should be placed as close to the
CGMXFC pin as possible with minimum routing distances and no routing
of other signals across the CF connection.
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Ana log Powe r Pin
(VDDA
VDDA is a power pin used by the analog portions of the PLL. Connect the
VDDA pin to the same voltage potential as the VDD pin.
)
NOTE: Route VDDA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
Osc illa tor Ena b le
The SIMOSCEN signal enables the oscillator and PLL.
Sig na l (SIMOSCEN)
Crysta l Outp ut
Fre q ue nc y Sig na l
(CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (fxclk) and comes directly from the crystal oscillator circuit.
Figure 3 shows only the logical relation of CGMXCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
CGM Ba se Cloc k
Outp ut (CGMOUT)
CGMOUT is the clock output of the CGM. This signal is used to generate
the MCU clocks. CGMOUT is a 50% duty cycle clock running at twice
the bus frequency. CGMOUT is software programmable to be either the
oscillator output, CGMXCLK, divided by two or the VCO clock,
CGMVCLK, divided by two.
CGM CPU Inte rrup t
(CGMINT)
CGMINT is the CPU interrupt signal generated by the PLL lock detector.
14-cgm
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Clock Generator Module (CGM)
CGM Registers
CGM Re g iste rs
Three registers control and monitor operation of the CGM:
• PLL control register (PCTL)
• PLL bandwidth control register (PBWC)
• PLL programming register (PPG)
PLL Control
Re g iste r
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, and the base clock selector bit.
Address: $001C
Bit 7
PLLIE
0
6
5
PLLON
1
4
BCS
0
3
1
2
1
1
1
Bit 0
1
Read:
Write:
Reset:
PLLF
0
1
1
1
1
= Unimplemented
Figure 4. PLL Control Register (PCTL)
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate a CPU interrupt
request when the LOCK bit toggles, setting the PLL flag, PLLF. When
the AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
1 = PLL CPU interrupt requests enabled
0 = PLL CPU interrupt requests disabled
15-cgm
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PLLF — PLL Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates a CPU interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE: Do not inadvertently clear the PLLF bit. Be aware that any read or
read-modify-write operation on the PLL control register clears the PLLF
bit.
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). See Base Clock Selector Circuit
on page 115. Reset sets this bit so that the loop can stabilize as the
MCU is powering up.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output,
CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM
output, CGMOUT. CGMOUT frequency is one-half the frequency of
the selected clock. BCS cannot be set while the PLLON bit is clear.
After toggling BCS, it may take up to three CGMXCLK and three
CGMVCLK cycles to complete the transition from one source clock to
the other. During the transition, CGMOUT is held in stasis. See Base
Clock Selector Circuit on page 115. Reset and the STOP instruction
clear the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
NOTE: PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
16-cgm
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CGM Registers
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. See Base Clock Selector Circuit on page 115.
PCTL3–PCTL0 — Unimplemented
These bits provide no function and always read as logic 1s.
PLL Ba nd wid th
The PLL bandwidth control register:
Control Re g iste r
• Selects automatic or manual (software-controlled) bandwidth
control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking
mode
Address: $001D
Bit 7
AUTO
0
6
5
ACQ
0
4
XLD
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
LOCK
0
0
0
0
0
= Unimplemented
Figure 5. PLL Bandwidth Control Register (PBWC)
17-cgm
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Cloc k Ge ne ra tor Mod ule (CGM)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), clear the
ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
logic 0 and has no meaning. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ — Acquisition Mode Bit
When the AUTO bit is set, ACQ is a read-only bit that indicates
whether the PLL is in acquisition mode or tracking mode. When the
AUTO bit is clear, ACQ is a read/write bit that controls whether the
PLL is in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written
value from manual operation is stored in a temporary location and is
recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
XLD — Crystal Loss Detect Bit
When the VCO output, CGMVCLK, is driving CGMOUT, this
read/write bit can indicate whether the crystal reference frequency is
active or not.
1 = Crystal reference not active
0 = Crystal reference active
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Clock Generator Module (CGM)
CGM Registers
To check the status of the crystal reference, do the following:
1. Write a logic 1 to XLD.
2. Wait N × 4 cycles. N is the VCO frequency multiplier.
3. Read XLD.
The crystal loss detect function works only when the BCS bit is set,
selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD
always reads as logic 0.
Bits 3–0 — Reserved for Test
These bits enable test functions not available in user mode. To ensure
software portability from development systems to user applications,
software should write 0s to bits 3–0 when writing to PBWC.
PLL Prog ra m m ing
Re g iste r
The PLL programming register contains the programming information
for the modulo feedback divider and the programming information for the
hardware configuration of the VCO.
Address: $001E
Bit 7
MUL7
0
6
MUL6
1
5
MUL5
1
4
MUL4
0
3
VRS7
0
2
VRS6
1
1
VRS5
1
Bit 0
VRS4
0
Read:
Write:
Reset:
Figure 6. PLL Programming Register (PPG)
MUL7–MUL4 — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. (See Circuits on page 109 and
Programming the PLL on page 113). A value of $0 in the multiplier
select bits configures the modulo feedback divider the same as a
value of $1. Reset initializes these bits to $6 to give a default multiply
value of 6.
19-cgm
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Table 3. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
VCO Frequency Multiplier (N)
0000
0001
0010
0011
1
1
2
3
1101
1110
1111
13
14
15
NOTE: The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
VRS7–VRS4 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency,
fVRS. (See Circuits on page 109, Programming the PLL on page
113, and PLL Control Register on page 119.) VRS7–VRS4 cannot
be written when the PLLON bit in the PLL control register (PCTL) is
set. See Special Programming Exceptions on page 115. A value of
$0 in the VCO range select bits disables the PLL and clears the BCS
bit in the PCTL. (See Base Clock Selector Circuit on page 115 and
Special Programming Exceptions on page 115 for more
information.) Reset initializes the bits to $6 to give a default range
multiply value of 6.
NOTE: The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
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Clock Generator Module (CGM)
Interrupts
Inte rrup ts
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupt requests from the PLL. PLLF, the interrupt flag in the
PCTL, becomes set whether CPU interrupt requests are enabled or not.
When the AUTO bit is clear, CPU interrupt requests from the PLL are
disabled and PLLF reads as logic 0.
Software should read the LOCK bit after a PLL CPU interrupt request to
see if the request was due to an entry into lock or an exit from lock. When
the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be
selected as the CGMOUT source by setting BCS in the PCTL. When the
PLL exits lock, the VCO clock frequency is corrupt, and appropriate
precautions should be taken. If the application is not frequency sensitive,
CPU interrupt requests should be disabled to prevent PLL interrupt
service routines from impeding software performance or from exceeding
stack limitations.
NOTE: Software can select the CGMVCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low
power-consumption standby modes.
Wa it Mod e
The CGM remains active in wait mode. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and
PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
21-cgm
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Stop Mod e
The STOP instruction disables the CGM and holds low all CGM outputs
(CGMXCLK, CGMOUT, and CGMINT).
If CGMOUT is being driven by CGMVCLK and a STOP instruction is
executed; the PLL will clear the BCS bit in the PLL control register,
causing CGMOUT to be driven by CGMXCLK. When the MCU recovers
from STOP, the crystal clock divided by two drives CGMOUT and BCS
remains clear.
CGM During Bre a k Inte rrup ts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. See Break Module on page
135.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
the PLL control register during the break state without affecting the PLLF
bit.
Ac q uisition/ Loc k Tim e Sp e c ific a tions
The acquisition and lock times of the PLL are, in many applications, the
most critical PLL design parameters. Proper design and use of the PLL
ensures the highest stability and lowest acquisition/lock times.
Ac q uisition/ Loc k
Tim e De finitions
Typical control systems refer to the acquisition time or lock time as the
reaction time, within specified tolerances, of the system to a step input.
In a PLL, the step input occurs when the PLL is turned on or when it
suffers a noise hit. The tolerance is usually specified as a percent of the
step input or when the output settles to the desired value plus or minus
22-cgm
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Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
a percent of the frequency change. Therefore, the reaction time is
constant in this definition, regardless of the size of the step input. For
example, consider a system with a 5% acquisition time tolerance. If a
command instructs the system to change from 0 Hz to 1 MHz, the
acquisition time is the time taken for the frequency to reach
1 MHz ±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is
operating at 1 MHz and suffers a –100 kHz noise hit, the acquisition time
is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5%
of the 100-kHz step input.
Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.
The discrepancy in these definitions makes it difficult to specify an
acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are:
• Acquisition time, tacq, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance, ∆trk.
Acquisition time is based on an initial frequency error,
(fdes – forig)/fdes, of not more than ±100%. In automatic bandwidth
control mode (see Manual and Automatic PLL Bandwidth
Modes on page 111), acquisition time expires when the ACQ bit
becomes set in the PLL bandwidth control register (PBWC).
• Lock time, tLock, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the lock mode entry tolerance, ∆Lock. Lock
time is based on an initial frequency error, (fdes – forig)/fdes, of not
more than ±100%. In automatic bandwidth control mode, lock time
expires when the LOCK bit becomes set in the PLL bandwidth
control register (PBWC). (See Manual and Automatic PLL
Bandwidth Modes on page 111).
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Cloc k Ge ne ra tor Mod ule (CGM)
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or longer in many cases.
Pa ra m e tric
Influe nc e s on
Re a c tion Tim e
Acquisition and lock times are designed to be as short as possible while
still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL
is the reference frequency, fRDV. This frequency is the input to the phase
detector and controls how often the PLL makes corrections. For stability,
the corrections must be small compared to the desired frequency, so
several corrections are required to reduce the frequency error.
Therefore, the slower the reference the longer it takes to make these
corrections. This parameter is also under user control via the choice of
crystal frequency fXCLK
.
Another critical parameter is the external filter capacitor. The PLL
modifies the voltage on the VCO by adding or subtracting charge from
this capacitor. Therefore, the rate at which the voltage changes for a
given frequency error (thus a change in charge) is proportional to the
capacitor size. The size of the capacitor also is related to the stability of
the PLL. If the capacitor is too small, the PLL cannot make small enough
adjustments to the voltage and the system cannot lock. If the capacitor
is too large, the PLL may not be able to adjust the voltage in a
reasonable time. See Choosing a Filter Capacitor on page 129.
Also important is the operating voltage potential applied to VDDA. The
power supply potential alters the characteristics of the PLL. A fixed value
is best. Variable supplies, such as batteries, are acceptable if they vary
within a known range at very slow speeds. Noise on the power supply is
not acceptable, because it causes small frequency errors which
continually change the acquisition time of the PLL.
Temperature and processing also can affect acquisition time because
the electrical characteristics of the PLL change. The part operates as
specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of
the PLL. These factors include noise injected into the PLL through the
24-cgm
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Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
filter capacitor, filter capacitor leakage, stray impedances on the circuit
board, and even humidity or circuit board contamination.
Choosing a Filte r
Ca p a c itor
As described in Parametric Influences on Reaction Time on page
128, the external filter capacitor, CF, is critical to the stability and reaction
time of the PLL. The PLL is also dependent on reference frequency and
supply voltage. The value of the capacitor must, therefore, be chosen
with supply potential and reference frequency in mind. For proper
operation, the external filter capacitor must be chosen according to this
equation:
VDDA
CF = Cfact ------------
frdv
For acceptable values of Cfact, (see Electrical Specifications on page
408). For the value of VDDA, choose the voltage potential at which the
MCU is operating. If the power supply is variable, choose a value near
the middle of the range of possible supply values.
This equation does not always yield a commonly available capacitor
size, so round to the nearest available size. If the value is between two
different sizes, choose the higher value for better stability. Choosing the
lower size may seem attractive for acquisition time improvement, but the
PLL may become unstable. Also, always choose a capacitor with a tight
tolerance (±20% or better) and low dissipation.
Re a c tion Tim e
Ca lc ula tion
The actual acquisition and lock times can be calculated using the
equations below. These equations yield nominal values under the
following conditions:
• Correct selection of filter capacitor, CF (see Choosing a Filter
Capacitor on page 129).
• Room temperature operation
• Negligible external leakage on CGMXFC
• Negligible noise
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Cloc k Ge ne ra tor Mod ule (CGM)
The K factor in the equations is derived from internal PLL parameters.
acq is the K factor when the PLL is configured in acquisition mode, and
K
Ktrk is the K factor when the PLL is configured in tracking mode. (See
Acquisition and Tracking Modes on page 111).
VDDA
tacq = ----------- ------------
fRDV KACQ
8
VDDA
4
tal =
----------- -----------
fRDV KTRK
tLock = tACQ + tAL
Note the inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See Manual
and Automatic PLL Bandwidth Modes on page 111). A certain
number of clock cycles, nACQ, is required to ascertain that the PLL is
within the tracking mode entry tolerance, ∆TRK, before exiting acquisition
mode. A certain number of clock cycles, nTRK, is required to ascertain
that the PLL is within the lock mode entry tolerance, ∆Lock. Therefore, the
acquisition time, tACQ, is an integer multiple of nACQ RDV
acquisition to lock time, tAL, is an integer multiple of nTRK RDV
/f
, and the
/f . Also,
since the average frequency over the entire measurement period must
be within the specified tolerance, the total time usually is longer than
tLock as calculated above.
In manual mode, it is usually necessary to wait considerably longer than
tLock before selecting the PLL clock (see Base Clock Selector Circuit
on page 115), because the factors described in Parametric Influences
on Reaction Time on page 128, may slow the lock time considerably.
26-cgm
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Ma sk Op tions
Ma sk Op tions
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Introd uc tion
This section describes use of mask options by custom-masked ROMs
and the mask option register in the MC68HC08AZ60.
Func tiona l De sc rip tion
The mask options are hard-wired connections, specified at the same
time as the ROM code, which allow the user to customise the MCU. The
options control the enable or disable ability of the following functions:
• ROM security1
• Resets caused by the LVI module
• Power to the LVI module
• Stop mode recovery time (32 CGMXCLK cycles or 4096
CGMXCLK cycles)
• COP timeout period (218 – 24 CGMXCLK cycles or 213 – 24
CGMXCLK cycles)
1. No security feature is absolutely secure. However, Motoroola’s strategy is to make reading or
copying the ROM data dificult for unauthorized users.
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Ma sk Op tions
• Stop instruction
• Computer operating properly module (COP)
The mask option register ($001F) is used in the initialization of various
options. For free compatibility with the emulator OTP
(MC68HC908AZ60), a write to $001F in the MC68HC08AZ60 has no
effect on MCU operation.
Ma sk Op tion Re g iste r
Bit 7
6
5
4
3
2
1
STOP
R
Bit 0
COPD
R
Read: LVISTOP ROMSEC LVIRST LVIPWR SSREC COPRS
Write:
R
R
R
R
R
R
R
Reset:
Unaffected by Reset
=Reserved
Figure 1. Configuration Register (CONFIG-1)
LVISTOP — LVI Stop Mode Enable Bit
LVISTOP enables the LVI module in stop mode. (See
Low-Voltage Inhibit (LVI) on page 159).
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
ROMSEC — ROM Security Bit
ROMSEC enables the RM security feature. Setting the ROMSEC bit
prevents reading of the ROM contents Acccess to the ROM is denied
to unauthorized users of customer-specified software.
1 = ROM security enabled
0 = ROM security disabled
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. (See
Low-Voltage Inhibit (LVI) on page 159).
1 = LVI module resets enabled
0 = LVI module resets disabled
2-mops
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Mask Options
Mask Option Register
LVIPWR — LVI Power Enable Bit
LVIPWR enables the LVI module. (See Low-Voltage Inhibit (LVI) on
page 159).
1 = LVI module power enabled
0 = LVI module power disabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay. (See
Stop Mode on page 126).
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE: If using an external crystal oscillator, do not set the SSREC bit.
COPL — COP Long Timeout
COPL enables the shorter COP timeout period. (See
Computer Operating Properly Module (COP) on page 153).
1 = COP timeout period is 213 – 24 CGMXCLK cycles
0 = COP timeout period is 218 – 24 CGMXCLK cycles
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See
Computer Operating Properly Module (COP) on page 153).
1 = COP module disabled
0 = COP module enabled
Extra care should be exercised when selecting mask option
registers since other HC08 family parts may have different register
options. If in doubt, check with your local field applications
representative.
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Ma sk Op tions
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Bre a k Mod ule
Bre a k Mod ule
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . 137
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . 139
Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Introd uc tion
The break module can generate a break interrupt that stops normal
program flow at a defined address to enter a background program.
Fe a ture s
• Accessible I/O Registers during Break Interrupts
• CPU-Generated Break Interrupts
• Software-Generated Break Interrupts
• COP Disabling during Break Interrupts
1-brk
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Bre a k Mod ule
Func tiona l De sc rip tion
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal to the
CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU
instruction. The program counter vectors to $FFFC and $FFFD ($FEFC
and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
• Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 1 shows the structure of the break module.
IAB[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB[15:0]
CONTROL
BREAK
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB[7:0]
Figure 1. Break Module Block Diagram
2-brk
MC68HC08AZ60 — Rev 1.0
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Break Module
Functional Description
Register Name
Bit 7
Bit 15
0
6
14
0
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
Bit 0
Bit 8
0
Read:
Write:
Reset:
Break Address Register High
(BRKH)
Read:
Write:
Reset:
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Break Address Register Low
(BRKL)
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
0
0
0
BRKE
0
BRKA
0
Break Status and Control Register
(BSCR)
0
= Unimplemented
R = Reserved
Figure 2. I/O Register Summary
Table 1. I/O Register Address Summary
Register
Address
BRKH
$FE0C
BRKL
BSCR
$FE0E
$FE0D
Fla g Prote c tion
During Bre a k
Inte rrup ts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state.
CPU During Bre a k
Inte rrup ts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
3-brk
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Bre a k Mod ule
TIM During Bre a k
Inte rrup ts
A break interrupt stops the timer counter.
COP During Bre a k
Inte rrup ts
The COP is disabled during a break interrupt when VHi is present on the
RST pin.
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low power-consump-
tion standby modes.
Wa it Mod e
If enabled, the break module is active in wait mode. The SIM break
stop/wait bit (SBSW) in the SIM break status register indicates whether
wait was exited by a break interrupt. If so, the user can modify the return
address on the stack by subtracting one from it. (See
System Integration Module (SIM) on page 83).
Stop Mod e
The break module is inactive in stop mode. The STOP instruction does
not affect break module register states. A break interrupt will cause an
exit from stop mode and sets the SBSW bit in the SIM break status
register.
4-brk
MC68HC08AZ60 — Rev 1.0
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Break Module
Break Module Registers
Bre a k Mod ule Re g iste rs
These registers control and monitor operation of the break module:
• Break address register high (BRKH)
• Break address register low (BRKL)
• Break status and control register (BSCR)
Bre a k Sta tus a nd
Control Re g iste r
The break status and control register contains break module enable and
status bits.
Address: $FE0E
Bit 7
BRKE
0
6
BRKA
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 3. Break Status and Control Register (BSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches.
Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
BRKA — Break Active Bit
This read/write status and control bit is set when a break address
match occurs. Writing a logic 1 to BRKA generates a break interrupt.
Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = (When read) Break address match
0 = (When read) No break address match
5-brk
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Bre a k Mod ule
Bre a k Ad d re ss
Re g iste rs
The break address registers contain the high and low bytes of the
desired breakpoint address. Reset clears the break address registers.
Register: BRKH
Address: $FE0C
Bit 7
BRKL
$FE0D
6
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
1
0
Bit 0
Bit 8
0
Read:
Bit 15
Write:
14
0
Reset:
Read:
Write:
Reset:
0
Bit 7
0
6
5
4
3
2
Bit 0
0
0
0
0
0
0
Figure 4. Break Address Registers (BRKH and BRKL)
6-brk
MC68HC08AZ60 — Rev 1.0
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Monitor ROM (MON)
Monitor ROM (MON)
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Echoing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Introd uc tion
This section describes the monitor ROM (MON). The monitor ROM
allows complete testing of the MCU through a single-wire interface with
a host computer.
1-mon
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Monitor ROM (MON)
Fe a ture s
Features of the monitor ROM include:
• Normal User-Mode Pin Functionality
• One Pin Dedicated to Serial Communication between Monitor
ROM and Host Computer
• Standard Mark/Space Non-Return-to-Zero (NRZ) Communication
with Host Computer
• Up to 28.8 kBaud Communication with Host Computer
• Execution of Code in RAM.
Func tiona l De sc rip tion
Monitor ROM receives and executes commands from a host computer.
Figure 1 shows a sample circuit used to enter monitor mode and
communicate with a host computer via a standard RS-232 interface.
While simple monitor commands can access any memory address, the
MC68HC08AZ60 has a ROM security feature to prevent external
viewing of the contents of ROM. Proper procedures must be followed to
verify ROM content. Access to the ROM is denied to unauthorized users
of customer specified software (see Security on page 151).
In monitor mode, the MCU can execute host-computer code in RAM
while all MCU pins except PTA0 retain normal operating mode functions.
All communication between the host computer and the MCU is through
the PTA0 pin. A level-shifting and multiplexing interface is required
between PTA0 and the host computer. PTA0 is used in a wired-OR
configuration and requires a pullup resistor.
2-mon
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Monitor ROM (MON)
Functional Description
V
DD
68HC08
10 kΩ
RST
0.1 µF
V
HI
10 Ω
IRQ
V
DDA
VDDA/VDDAREF
CGMXFC
0.1 µF
1
20
MC145407
+
+
+
+
10 µF
10 µF
10 µF
10 µF
OSC1
OSC2
3
4
18
17
X1
20 pF
10 MΩ
4.9152 MHz
V
DD
20 pF
2
19
V
SSA
V
SS
DB-25
2
5
6
16
15
3
7
V
DD
V
DD
0.1 µF
V
DD
V
DD
1
2
6
4
14
3
MC74HC125
10 kΩ
PTA0
PTC3
5
V
DD
V
DD
10 kΩ
7
10 kΩ
PTC0
PTC1
A
(SEE
NOTE.)
B
NOTE: Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4
Position B — Bus clock = CGMXCLK ÷ 2
Figure 1. Monitor Mode Circuit
3-mon
MC68HC08AZ60 — Rev 1.0
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Monitor ROM (MON)
Ente ring Monitor
Mod e
Table 1 shows the pin conditions for entering monitor mode.
Table 1. Mode Selection
Bus
Frequency
Mode
CGMOUT
CGMXCLK
CGMVCLK
CGMOUT
--------------------------
2
(1)
(1)
VHI
1
1
0
0
1
1
1
0
Monitor
Monitor
----------------------------- or -----------------------------
2
2
CGMOUT
--------------------------
2
VHI
CGMXCLK
1. For VHI, 5.0 Volt DC Electrical Characteristics on page 410, and
Maximum Ratings on page 408.
Enter monitor mode by either
• Executing a software interrupt instruction (SWI) or
• Applying a logic 0 and then a logic 1 to the RST pin.
Once out of reset, the MCU waits for the host to send eight security bytes
(see Security on page 151). After the security bytes, the MCU sends a
break signal (10 consecutive logic 0s) to the host computer, indicating
that it is ready to receive a command.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt.
The alternate vectors are in the $FE page instead of the $FF page and
allow code execution from the internal monitor firmware instead of user
code. The COP module is disabled in monitor mode as long as VHI (see
5.0 Volt DC Electrical Characteristics on page 410), is applied to
either the IRQ pin or the RESET pin. (See
System Integration Module (SIM) on page 83 for more information on
modes of operation).
NOTE: Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The CGMOUT frequency is
equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
4-mon
MC68HC08AZ60 — Rev 1.0
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Monitor ROM (MON)
Functional Description
Table 2 is a summary of the differences between user mode and monitor
mode.
Table 2. Mode Differences
Functions
Modes
Reset
Vector Vector Vector Vector Vector Vector
High Low High Low High Low
Reset
Break
Break
SWI
SWI
COP
User
Enabled
$FFFE $FFFF $FFFC $FFFD $FFFC $FFFD
Monitor Disabled(1) $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD
1. If the high voltage (VHI) is removed from the IRQ/VPP pin while in monitor mode, the SIM
asserts its COP enable output. The COP is a mask option enabled or disabled by the
COPD bit in the configuration register. See 5.0 Volt DC Electrical Character-
istics on page 410.
Da ta Form a t
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. (See Figure 2 and Figure 3.)
The data transmit and receive rate can be anywhere from 4800 baud to
28.8 kBaud. Transmit and receive baud rates must be identical.
NEXT
START
BIT
START
BIT
STOP
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Figure 2. Monitor Data Format
NEXT
START
BIT
START
$A5
STOP
BIT 0
BIT 1
BIT 2
BIT 2
BIT 3
BIT3
BIT 4
BIT4
BIT 5
BIT5
BIT 6
BIT6
BIT 7
BIT7
BIT
BIT
STOP
BIT
START
BIT
NEXT
START
BIT
BREAK
BIT 0
BIT 1
Figure 3. Sample Monitor Waveforms
5-mon
MC68HC08AZ60 — Rev 1.0
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Monitor ROM (MON)
Ec hoing
As shown in Figure 4, the monitor ROM immediately echoes each
received byte back to the PTA0 pin for error checking.
Any result of a command appears after the echo of the last byte of the
command.
SENT TO
MONITOR
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
ECHO
RESULT
Figure 4. Read Transaction
Bre a k Sig na l
A start bit followed by nine low bits is a break signal. (See Figure 5).
When the monitor receives a break signal, it drives the PTA0 pin high for
the duration of two bits before echoing the break signal.
MISSING STOP BIT
TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 5. Break Transaction
6-mon
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Monitor ROM (MON)
Functional Description
Com m a nd s
The monitor ROM uses these commands:
• READ, read memory
• WRITE, write memory
• IREAD, indexed read
• IWRITE, indexed write
• READSP, read stack pointer
• RUN, run user program
A sequence of IREAD or IWRITE commands can access a block of
memory sequentially over the full 64-Kbyte memory map.
Table 3. READ (Read Memory) Command
Description
Operand
Read byte from memory
Specifies 2-byte address in high byte:low byte order
Returns contents of specified address
$4A
Data Returned
Opcode
Command Sequence
SENT TO
MONITOR
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
ECHO
RESULT
7-mon
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Monitor ROM (MON)
Table 4. WRITE (Write Memory) Command
Description
Operand
Write byte to memory
Specifies 2-byte address in high byte:low byte order; low byte followed by data byte
Data Returned
Opcode
None
$49
Command Sequence
SENT TO
MONITOR
WRITE
ECHO
WRITE
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
DATA
Table 5. IREAD (Indexed Read) Command
Description
Operand
Read next 2 bytes in memory from last address accessed
Specifies 2-byte address in high byte:low byte order
Returns contents of next two addresses
$1A
Data Returned
Opcode
Command Sequence
SENT TO
MONITOR
IREAD
IREAD
DATA
DATA
RESULT
ECHO
8-mon
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Monitor ROM (MON)
Functional Description
Table 6. IWRITE (Indexed Write) Command
Description
Operand
Write to last address accessed + 1
Specifies single data byte
Data Returned
Opcode
None
$19
Command Sequence
SENT TO
MONITOR
IWRITE
IWRITE
DATA
DATA
ECHO
Table 7. READSP (Read Stack Pointer) Command
Description
Operand
Reads stack pointer
None
Data Returned
Opcode
Returns stack pointer in high byte:low byte order
$0C
Command Sequence
SENT TO
MONITOR
READSP
READSP
SP HIGH
SP LOW
RESULT
ECHO
9-mon
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Monitor ROM (MON)
Table 8. RUN (Run User Program) Command
Description
Operand
Executes RTI instruction
None
None
$28
Data Returned
Opcode
Command Sequence
SENT TO
MONITOR
RUN
RUN
ECHO
Ba ud Ra te
The part features a monitor mode which is optimised to operate with
either a 4.1952MHz crystal clock source (or multiples of 4.1952MHz) or
a 4MHz crystal (or multiples of 4MHz). This supports designs which use
the MSCAN module, which is generally clocked from a 4MHz, 8MHz or
16MHz crystal. The table below outlines the available baud rates for a
range of crystals and how they can match to a PC baud rate.
Table 9
Baud rate
Closest PC baud PC
Error %
Clock freq
32kHz
PTC3=0
PTC3=1
28.98
PTC3=0
57.6
PTC3=1
28.8
PTC3=0 PTC3=1
57.97
1811.59
3623.19
7246.37
7597.83
8904.35
14492.72
0.64
0.64
0.64
0.64
1.08
0.49
0.64
0.64
0.63
0.64
0.64
0.64
1.08
0.50
0.64
0.64
1MHz
905.80
1800
900
2MHz
1811.59
3623.19
3798.91
4452.17
7246.37
3600
1800
3600
3840
4430
7200
14400
4MHz
7200
4.194MHz
4.9152MHz
8MHz
7680
8861
14400
28800
16MHz
28985.51 14492.75
Care should be taken when setting the baud rate since incorrect
baud rate setting can result in communications failure.
10-mon
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Monitor ROM (MON)
Functional Description
Se c urity
A security feature discourages unauthorized reading of ROM locations
while in monitor mode. The host can bypass the security feature at
monitor mode entry by sending eight security bytes that match the bytes
at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain
user-defined data.
NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons, enter
data at locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for
the host to send the eight security bytes on pin PA0.
V
DD
4096 + 32 CGMXCLK CYCLES
24 CGMXCLK CYCLES
RST
PA7
256 CGMXCLK CYCLES (ONE BIT TIME)
FROM HOST
FROM MCU
PA0
1
1
4
1
4
2
1
NOTE: 1 = Echo delay (2 bit times)
2 = Data return delay (2 bit times)
4 = Wait 1 bit time before sending next byte.
Figure 6. Monitor Mode Entry Timing
If the received bytes match those at locations $FFF6–$FFFD, the host
bypasses the security feature and can read all ROM locations and
execute code from ROM. Security remains bypassed until a power-on
reset occurs. After the host bypasses security, any reset other than a
power-on reset requires the host to send another eight bytes. If the reset
was not a power-on reset, the security remains bypassed regardless of
the data that the host sends.
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Monitor ROM (MON)
If the received bytes do not match the data at locations $FFF6–$FFFD,
the host fails to bypass the security feature. The MCU remains in monitor
mode, but reading ROM locations returns undefined data, and trying to
execute code from ROM causes an illegal address reset. After the host
fails to bypass security, any reset other than a power-on reset causes an
endless loop of illegal address resets.
After receiving the eight security bytes from the host, the MCU transmits
a break character signalling that it is ready to receive a command.
NOTE: The MCU does not transmit a break character until after the host sends
the eight security bytes.
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Com p ute r Op e ra ting Prop e rly Mod ule (COP)
Com p ute r Op e ra ting Prop e rly Mod ule (COP)
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
STOP Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
COPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
COPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 158
Introd uc tion
The COP module contains a free-running counter that generates a reset
if allowed to overflow. The COP module helps software recover from
runaway code. Prevent a COP reset by periodically clearing the COP
counter.
1-cop
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Com p ute r Op e ra ting Prop e rly Mod ule (COP)
Func tiona l De sc rip tion
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler. If not cleared by software, the COP counter overflows and
generates an asynchronous reset after 213 – 24 or 218 – 24 CGMXCLK
cycles, depending on the state of the COP long timeout bit, COPL, in the
CONFIG-1. When COPL = 1, a 4.9152-MHz crystal gives a COP timeout
period of 53.3 ms. Writing any value to location $FFFF before an
overflow occurs prevents a COP reset by clearing the COP counter and
stages 4–12 of the SIM counter.
NOTE: Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the reset status register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ pin is
held at VHi. During the break state, VHi on the RST pin disables the COP.
NOTE: Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
2-cop
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Computer Operating Properly Module (COP)
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Computer Operating Properly Module (COP)
I/O Signals
I/ O Sig na ls
The following paragraphs describe the signals shown in Figure 1.
12-BIT COP PRESCALER
CGMXCLK
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
RESET
RESET STATUS
REGISTER
6-BIT COP COUNTER
COPD FROM MOR
RESET
CLEAR COP
COUNTER
COPCTL WRITE
COPRS FROM MOR
Figure 1. COP Block Diagram
CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.
STOP Instruc tion
The STOP instruction clears the COP prescaler.
3-cop
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Com p ute r Op e ra ting Prop e rly Mod ule (COP)
COPCTL Write
Writing any value to the COP control register (COPCTL) (see COP
Control Register on page 157), clears the COP counter and clears
stages 12 through 4 of the COP prescaler. Reading the COP control
register returns the reset vector.
Powe r-On Re se t
The power-on reset (POR) circuit clears the COP prescaler 4096
CGMXCLK cycles after power-up.
Inte rna l Re se t
An internal reset clears the COP prescaler and the COP counter.
Re se t Ve c tor Fe tc h
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the COP prescaler.
COPD
COPL
The COPD signal reflects the state of the COP disable bit (COPD) in the
MOR register. (See Mask Options on page 131).
The COPL signal reflects the state of the COP rate select bit. COPRS in
the mask option register. (See Mask Options on page 131).
4-cop
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Computer Operating Properly Module (COP)
COP Control Register
COP Control Re g iste r
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Low Byte of Reset Vector
Clear COP Counter
Unaffected by Reset
Figure 2. COP Control Register (COPCTL)
Inte rrup ts
The COP does not generate CPU interrupt requests.
Monitor Mod e
The COP is disabled in monitor mode when VHi is present on the IRQ
pin or on the RST pin.
5-cop
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Com p ute r Op e ra ting Prop e rly Mod ule (COP)
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low power-consump-
tion standby modes.
Wa it Mod e
Stop Mod e
The COP remains active in wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter in a CPU interrupt routine.
Stop mode turns off the CGMXCLK input to the COP and clears the COP
prescaler. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
The STOP bit in the mask option register (MOR) enables the STOP
instruction. To prevent inadvertently turning off the COP with a STOP
instruction, disable the STOP instruction by clearing the STOP bit.
COP Mod ule During Bre a k Inte rrup ts
The COP is disabled during a break interrupt when VHi is present on the
RST pin.
6-cop
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Low-Volta g e Inhib it (LVI)
Low-Volta g e Inhib it (LVI)
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Polled LVI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
False Reset Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
LVI Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
1-lvi
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Low-Volta g e Inhib it (LVI)
Introd uc tion
This section describes the low-voltage inhibit module, which monitors
the voltage on the VDD pin and can force a reset when the VDD voltage
falls to the LVI trip voltage.
Fe a ture s
Features of the LVI module include:
• Programmable LVI Reset
• Programmable Power Consumption
• Digital Filtering of VDD Pin Level
NOTE: If a low voltage interrupt (LVI) occurs during programming of EEPROM
memory, then adequate programming time may may not have been
allowed to ensure the integrity and retention of the data. It is the
responsibility of the user to ensure that in the event of an LVI any
addresses being programmed receive specification programming
conditions.
Func tiona l De sc rip tion
Figure 1 shows the structure of the LVI module. The LVI is enabled out
of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWR, enables the LVI to monitor VDD
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate
a reset when VDD falls below a voltage, LVITRIPF, and remains at or
below that level for nine or more consecutive CPU cycles.
Note that short VDD spikes may not trip the LVI. It is the user’s
responsibility to ensure a clean VDD signal within the specified
operating voltage range if normal microcontroller operation is to be
guaranteed.
2-lvi
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Low-Voltage Inhibit (LVI)
Functional Description
LVISTOP, enables the LVI module during stop mode. This will ensure
when the STOP instruction is implemented, the LVI will continue to
monitor the voltage level on VDD. LVIPWR, LVISTOP, and LVIRST are
in the MOR register. (See Mask Options on page 131).
Once an LVI reset occurs, the MCU remains in reset until VDD rises
above a voltage, LVITRIPR. VDD must be above LVITRIPR for only one
CPU cycle to bring the MCU out of reset. (See Forced Reset Operation
on page 162). The output of the comparator controls the state of the
LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
V
DD
LVIPWR
FROM MOR
FROM MOR
LVIRST
CPU CLOCK
V
V
DD > LVITRIP = 0
DD
LVI RESET
LOW V
DD
DIGITAL FILTER
DETECTOR
V
DD < LVITRIP = 1
Stop Mode
Filter Bypass
ANLGTRIP
LVIOUT
LVISTOP
FROM MOR
Figure 1. LVI Module Block Diagram
3-lvi
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Low-Volta g e Inhib it (LVI)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$FE0F
LVI Status Register (LVISR) LVIOUT
= Unimplemented
Figure 2. LVI I/O Register Summary
Polle d LVI
Op e ra tion
In applications that can operate at VDD levels below the LVITRIPF level,
software can monitor VDD by polling the LVIOUT bit. In the mask option
register, the LVIPWR bit must be at logic 1 to enable the LVI module, and
the LVIRST bit must be at logic 0 to disable LVI resets.
Forc e d Re se t
Op e ra tion
In applications that require VDD to remain above the LVITRIPF level,
enabling LVI resets allows the LVI module to reset the MCU when VDD
falls to the LVITRIPF level and remains at or below that level for nine or
more consecutive CPU cycles. In the mask option register, the LVIPWR
and LVIRST bits must be at logic 1 to enable the LVI module and to
enable LVI resets.
Fa lse Re se t
Prote c tion
The VDD pin level is digitally filtered to reduce false resets due to power
supply noise. In order for the LVI module to reset the MCU,VDD must
remain at or below the LVITRIPF level for nine or more consecutive CPU
cycles. VDD must be above LVITRIPR for only one CPU cycle to bring the
MCU out of reset.
4-lvi
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Low-Voltage Inhibit (LVI)
LVI Status Register
LVI Sta tus Re g iste r
The LVI status register flags VDD voltages below the LVITRIPF level.
Address: $FE0F
Bit 7
Read: LVIOUT
Write:
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 3. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the
LVITRIPF voltage for 32 to 40 CGMXCLK cycles. (See Table 1). Reset
clears the LVIOUT bit.
Table 1. LVIOUT Bit Indication
VDD
LVIOUT
For Number of
At Level:
CGMXCLK Cycles:
V
> LVI
Any
0
0
DD
TRIPR
V
V
V
< LVI
< 32 CGMXCLK Cycles
DD
DD
DD
TRIPF
Between 32 and 40
CGMXCLK Cycles
< LVI
< LVI
0 or 1
TRIPF
> 40 CGMXCLK Cycles
Any
1
TRIPF
LVI
TRIPF
< V
< LVI
Previous Value
DD
TRIPR
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Low-Volta g e Inhib it (LVI)
LVI Inte rrup ts
Low-Powe r Mod e s
Wa it Mod e
The LVI module does not generate interrupt requests.
The WAIT and STOP instructions put the MCU in low
power-consumption standby modes.
With the LVIPWR bit in the mask option register programmed to logic 1,
the LVI module is active after a WAIT instruction.
With the LVIRST bit in the mask option register programmed to logic 1,
the LVI module can generate a reset and bring the MCU out of wait
mode.
Stop Mod e
With the LVISTOP and LVIPWR bits in the mask option register
programmed to a logic 1, the LVI module will be active after a STOP
instruction. Because CPU clocks are disabled during stop mode, the LVI
trip must bypass the digital filter to generate a reset and bring the MCU
out of stop.
With the LVIPWR bit in the mask option register programmed to logic 1
and the LVISTOP bit at a logic 0, the LVI module will be inactive after a
STOP instruction.
Note that the LVI feature is intended to provide the safe shutdown
of the microcontroller and thus protection of related circuitry prior
to any application VDD voltage collapsing completely to an unsafe
level. Is is not intended that users operate the microcontroller at
lower than the specified operating voltage, VDD
6-lvi
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Exte rna l Inte rrup t Mod ule (IRQ)
Exte rna l Inte rrup t Mod ule (IRQ)
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
IRQ Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . 170
IRQ Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Introd uc tion
Fe a ture s
This section describes the nonmaskable external interrupt (IRQ) input.
Features include:
• Dedicated External Interrupt Pin (IRQ)
• Hysteresis Buffer
• Programmable Edge-Only or Edge- and Level-Interrupt Sensitivity
• Automatic Interrupt Acknowledge
1-irq
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Exte rna l Inte rrup t Mod ule (IRQ)
Func tiona l De sc rip tion
A logic 0 applied to the external interrupt pin can latch a CPU interrupt
request. Figure 1 shows the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An
interrupt latch remains set until one of the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the latch that caused the vector
fetch.
• Software clear — Software can clear an interrupt latch by writing
to the appropriate acknowledge bit in the interrupt status and
control register (ISCR). Writing a logic 1 to the ACK1 bit clears the
IRQ latch.
• Reset — A reset automatically clears both interrupt latches.
ACK1
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
V
DD
IRQF
CLR
D
Q
SYNCHRO-
NIZER
IRQ
INTERRUPT
REQUEST
CK
IRQ
IRQ
LATCH
IMASK1
MODE1
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
Figure 1. IRQ Block Diagram
2-irq
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External Interrupt Module (IRQ)
Functional Description
Table 1. IRQ I/O Register Summary
Addr.
Register Name
Bit 7
6
0
5
0
4
0
3
IRQF
R
2
0
1
Bit 0
Read:
Write:
0
$001A IRQ Status/Control Register (ISCR)
IMASK1 MODE1
R
R
R
R
ACK1
R
=Reserved
The external interrupt pin is falling-edge triggered and is software-
configurable to be both falling-edge and low-level triggered. The MODE1
bit in the ISCR controls the triggering sensitivity of the IRQ pin.
When an interrupt pin is edge-triggered only, the interrupt latch remains
set until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt latch remains set until both of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE1 control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK1 bit in the ISCR masks all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the corresponding IMASK bit is clear.
NOTE: The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
(See Figure 2).
3-irq
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Exte rna l Inte rrup t Mod ule (IRQ)
FROM RESET
YES
I BIT SET?
NO
YES
INTERRUPT?
NO
STACK CPU REGISTERS.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
YES
YES
NO
RTI
UNSTACK CPU REGISTERS.
EXECUTE INSTRUCTION.
INSTRUCTION?
NO
Figure 2. IRQ Interrupt Flowchart
4-irq
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External Interrupt Module (IRQ)
IRQ Pin
IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch.
A vector fetch, software clear, or reset clears the IRQ latch.
If the MODE1 bit is set, the IRQ pin is both falling-edge sensitive and
low-level sensitive. With MODE1 set, both of the following actions must
occur to clear the IRQ latch:
• Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK1 bit in the interrupt status and control register (ISCR).
The ACK1 bit is useful in applications that poll the IRQ pin and
require software to clear the IRQ latch. Writing to the ACK1 bit can
also prevent spurious interrupts due to noise. Setting ACK1 does
not affect subsequent transitions on the IRQ pin. A falling edge on
IRQ/VPP that occurs after writing to the ACK1 bit latches another
interrupt request. If the IRQ mask bit, IMASK1, is clear, the CPU
loads the program counter with the vector address at locations
$FFFA and $FFFB.
• Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic
0, the IRQ latch remains set.
The vector fetch or software clear and the return of the IRQ pin to logic 1
can occur in any order. The interrupt request remains pending as long
as the IRQ pin is at logic 0. A reset will clear the latch and the MODE1
control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE1 bit is clear, the IRQ pin is falling-edge sensitive only. With
MODE1 clear, a vector fetch or software clear immediately clears the
IRQ latch.
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Exte rna l Inte rrup t Mod ule (IRQ)
The IRQF bit in the ISCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK1 bit, which makes
it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
IRQ Mod ule During Bre a k Inte rrup ts
The system integration module (SIM) controls whether the IRQ interrupt
latch can be cleared during the break state. The BCFE bit in the SIM
break flag control register (SBFCR) enables software to clear the latches
during the break state. (See SIM Break Flag Control Register on page
103
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK1 bit in the
IRQ status and control register during the break state has no effect on
the IRQ latch.
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External Interrupt Module (IRQ)
IRQ Status and Control Register
IRQ Sta tus a nd Control Re g iste r
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. The ISCR has these functions:
• Shows the state of the IRQ interrupt flag
• Clears the IRQ interrupt latch
• Masks IRQ interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin
Address: $001A
Bit 7
0
6
5
0
4
0
3
IRQF
R
2
0
1
Bit 0
Read:
Write:
Reset:
0
IMASK1 MODE1
R
R
R
0
R
0
ACK1
0
0
0
0
0
0
R
=Reserved
Figure 3. IRQ Status and Control Register (ISCR)
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK1 — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK1
always reads as logic 0. Reset clears ACK1.
IMASK1 — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests.
Reset clears IMASK1.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
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Exte rna l Inte rrup t Mod ule (IRQ)
MODE1 — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
Reset clears MODE1.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
8-irq
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Se ria l Com m unic a tions Inte rfa c e Mod ule (SCI)
Se ria l Com m unic a tions Inte rfa c e Mod ule (SCI)
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . 182
Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 193
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
PTE0/SCTxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
PTE1/SCRxD (Receive Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
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SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Introd uc tion
The SCI allows asynchronous communications with peripheral devices
and other MCUs.
Fe a ture s
The SCI module’s features include:
• Full Duplex Operation
• Standard Mark/Space Non-Return-to-Zero (NRZ) Format
• 32 Programmable Baud Rates
• Programmable 8-Bit or 9-Bit Character Length
• Separately Enabled Transmitter and Receiver
• Separate Receiver and Transmitter CPU Interrupt Requests
• Programmable Transmitter Output Polarity
• Two Receiver Wakeup Methods:
– Idle Line Wakeup
– Address Mark Wakeup
• Interrupt-Driven Operation with Eight Interrupt Flags:
– Transmitter Empty
– Transmission Complete
– Receiver Full
– Idle Receiver Input
– Receiver Overrun
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Serial Communications Interface Module (SCI)
Pin Name Conventions
– Noise Error
– Framing Error
– Parity Error
• Receiver Framing Error Detection
• Hardware Parity Checking
• 1/16 Bit-Time Noise Detection
Pin Na m e Conve ntions
The generic names of the SCI input/output (I/O) pins are:
• RxD (receive data)
• TxD (transmit data)
SCI I/O lines are implemented by sharing parallel I/O port pins. The full
name of an SCI input or output reflects the name of the shared port pin.
Table 1 shows the full names and the generic names of the SCI I/O
pins.The generic pin names appear in the text of this section.
Table 1. Pin Name Conventions
Generic Pin Names
Full Pin Names
RxD
TxD
PTE1/SCRxD
PTE0/SCTxD
Func tiona l De sc rip tion
Figure 1 shows the structure of the SCI module. The SCI allows
full-duplex, asynchronous, NRZ serial communication between the MCU
and remote devices, including other MCUs. The transmitter and receiver
of the SCI operate independently, although they use the same baud rate
generator. During normal operation, the CPU monitors the status of the
SCI, writes the data to be transmitted, and processes received data.
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Se ria l Com m unic a tions Inte rfa c e Mod ule (SCI)
INTERNAL BUS
SCI DATA
REGISTER
SCI DATA
REGISTER
RECEIVE
SHIFT REGISTER
TRANSMIT
SHIFT REGISTER
RxD
TxD
TXINV
SCTIE
R8
T8
TCIE
SCRIE
ILIE
TE
SCTE
TC
RE
RWU
SBK
SCRF
IDLE
OR
NF
FE
PE
ORIE
NEIE
FEIE
PEIE
LOOPS
ENSCI
LOOPS
RECEIVE
CONTROL
FLAG
CONTROL
TRANSMIT
CONTROL
WAKEUP
CONTROL
M
BKF
RPF
ENSCI
WAKE
ILTY
PEN
PTY
PRE-
BAUD RATE
÷ 4
CGMXCLK
SCALER GENERATOR
DATA SELECTION
CONTROL
÷ 16
Figure 1. SCI Module Block Diagram
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Functional Description
Register Name
Bit 7
LOOPS
0
6
ENSCI
0
5
4
M
0
3
WAKE
0
2
ILTY
0
1
PEN
0
Bit 0
PTY
0
Read:
TXINV
SCI Control Register 1 (SCC1) Write:
Reset:
Read:
0
SCRIE
0
SCTIE
TCIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
SCI Control Register 2 (SCC2) Write:
Reset:
0
0
Read:
SCI Control Register 3 (SCC3) Write:
Reset:
R8
T8
R
R
ORIE
NEIE
FEIE
PEIE
U
U
0
0
0
0
0
0
Read: SCTE
SCI Status Register 1 (SCS1) Write:
Reset:
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
Read:
BKF
RPF
SCI Status Register 2 (SCS2) Write:
Reset:
0
0
0
0
0
0
0
0
Read:
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SCI Data Register (SCDR) Write:
Reset:
Unaffected by Reset
Read:
SCI Baud Rate Register (SCBR) Write:
Reset:
SCP1
0
SCP0
0
R
0
SCR2
0
SCR1
0
SCR0
0
0
0
= Unimplemented
U = Unaffected
R = Reserved
Figure 2. SCI I/O Register Summary
Table 2. SCI I/O Register Address Summary
Register
Address
SCC1
$0013
SCC2
$0014
SCC3
$0015
SCS1
$0016
SCS2
$0017
SCDR
$0018
SCBR
$0019
Da ta Form a t
The SCI uses the standard non-return-to-zero mark/space data format
illustrated in Figure 3.
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8-BIT DATA FORMAT
(BIT M IN SCC1 CLEAR)
PARITY
OR DATA
BIT
NEXT
START
BIT
START
BIT
STOP
BIT
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
9-BIT DATA FORMAT
(BIT M IN SCC1 SET)
PARITY
OR DATA
BIT
NEXT
START
BIT
START
BIT
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 STOP
BIT
Figure 3. SCI Data Formats
Tra nsm itte r
Figure 4 shows the structure of the SCI transmitter.
Cha ra c te r Le ng th
The transmitter can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCC1) determines character length.
When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is
the ninth bit (bit 8).
Cha ra c te r
Tra nsm issio n
During an SCI transmission, the transmit shift register shifts a character
out to the TxD pin. The SCI data register (SCDR) is the write-only buffer
between the internal data bus and the transmit shift register. To initiate
an SCI transmission:
1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI)
in SCI control register 1 (SCC1).
2. Enable the transmitter by writing a logic 1 to the transmitter enable
bit (TE) in SCI control register 2 (SCC2).
3. Clear the SCI transmitter empty bit (SCTE) by first reading SCI
status register 1 (SCS1) and then writing to the SCDR.
4. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically
loads the transmit shift register with a preamble of logic 1s. After the
preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes
into the most significant bit position.
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Functional Description
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the
SCDR transfers a byte to the transmit shift register. The SCTE bit
indicates that the SCDR can accept new data from the internal data bus.
If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the
SCTE bit generates a transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the TxD
pin goes to the idle condition, logic 1. If at any time software clears the
ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver
relinquish control of the port E pins.
INTERNAL BUS
PRE-
BAUD
÷ 4
÷ 16
SCI DATA REGISTER
SCALER DIVIDER
SCP1
SCP0
SCR1
SCR2
SCR0
11-BIT
TRANSMIT
SHIFT REGISTER
H
8
7
6
5
4
3
2
1
0
L
TxD
TXINV
M
PEN
PTY
PARITY
GENERATION
T8
TRANSMITTER
CONTROL LOGIC
SCTE
SCTIE
SBK
SCTE
LOOPS
ENSCI
TE
SCTIE
TC
TC
TCIE
TCIE
Figure 4. SCI Transmitter
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Se ria l Com m unic a tions Inte rfa c e Mod ule (SCI)
Register Name
Bit 7
LOOPS
0
6
ENSCI
0
5
4
M
0
3
WAKE
0
2
ILTY
0
1
PEN
0
Bit 0
PTY
0
Read:
TXINV
SCI Control Register 1 (SCC1) Write:
Reset:
0
SCRIE
0
Read:
SCTIE
TCIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
SCI Control Register 2 (SCC2) Write:
Reset:
0
0
Read:
SCI Control Register 3 (SCC3) Write:
Reset:
R8
T8
R
R
ORIE
NEIE
FEIE
PEIE
U
U
0
0
0
0
0
0
Read: SCTE
SCI Status Register 1 (SCS1) Write:
Reset:
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
Read:
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SCI Data Register (SCDR) Write:
Reset:
Unaffected by Reset
Read:
SCI Baud Rate Register (SCBR) Write:
Reset:
SCP1
0
SCP0
0
R
0
SCR2
0
SCR1
0
SCR0
0
0
0
= Unimplemented
U = Unaffected
R = Reserved
Figure 5. SCI Transmitter I/O Register Summary
Table 3. SCI Transmitter I/O Address Summary
Register
SCC1
SCC2
$0014
SCC3
$0015
SCS1
$0016
SCDR
$0018
SCBR
$0019
Address $0013
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Functional Description
Bre a k C ha ra c te rs
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit
shift register with a break character. A break character contains all logic
0s and has no start, stop, or parity bit. Break character length depends
on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic
continuously loads break characters into the transmit shift register. After
software clears the SBK bit, the shift register finishes transmitting the
last break character and then transmits at least one logic 1. The
automatic logic 1 at the end of a break character guarantees the
recognition of the start bit of the next character.
The SCI recognizes a break character when a start bit is followed by
eight or nine logic 0 data bits and a logic 0 where the stop bit should be.
Receiving a break character has the following effects on SCI registers:
• Sets the framing error bit (FE) in SCS1
• Sets the SCI receiver full bit (SCRF) in SCS1
• Clears the SCI data register (SCDR)
• Clears the R8 bit in SCC3
• Sets the break flag bit (BKF) in SCS2
• May set the overrun (OR), noise flag (NF), parity error (PE), or
reception in progress flag (RPF) bits
Id le C ha ra c te rs
An idle character contains all logic 1s and has no start, stop, or parity bit.
Idle character length depends on the M bit in SCC1. The preamble is a
synchronizing idle character that begins every transmission.
If the TE bit is cleared during a transmission, the TxD pin becomes idle
after completion of the transmission in progress. Clearing and then
setting the TE bit during a transmission queues an idle character to be
sent after the character currently being transmitted.
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NOTE: When queueing an idle character, return the TE bit to logic 1 before the
stop bit of the current character shifts out to the TxD pin. Setting TE after
the stop bit appears on TxD causes data previously written to the SCDR
to be lost.
A good time to toggle the TE bit for a queued idle character is when the
SCTE bit becomes set and just before writing the next byte to the SCDR.
Inve rsio n o f
Tra nsm itte d
Outp ut
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)
reverses the polarity of transmitted data. All transmitted values, including
idle, break, start, and stop bits, are inverted when TXINV is at logic 1.
(See SCI Control Register 1.)
Tra nsm itte r
Inte rrup ts
The following conditions can generate CPU interrupt requests from the
SCI transmitter:
• SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates
that the SCDR has transferred a character to the transmit shift
register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2
enables the SCTE bit to generate transmitter CPU interrupt
requests.
• Transmission complete (TC) — The TC bit in SCS1 indicates that
the transmit shift register and the SCDR are empty and that no
break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to
generate transmitter CPU interrupt requests.
Re c e ive r
Figure 6 shows the structure of the SCI receiver.
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Functional Description
INTERNAL BUS
SCR1
SCR2
SCR0
SCP1
SCP0
SCI DATA REGISTER
PRE-
BAUD
÷ 4
÷ 16
SCALER DIVIDER
11-BIT
RECEIVE SHIFT REGISTER
CGMXCLK
DATA
RECOVERY
H
8
7
6
5
4
3
2
1
0
L
RxD
ALL ZEROS
BKF
RPF
M
RWU
SCRF
IDLE
WAKE
ILTY
WAKEUP
LOGIC
PEN
PTY
R8
PARITY
CHECKING
IDLE
ILIE
ILIE
SCRF
SCRIE
SCRIE
OR
OR
ORIE
ORIE
NF
NF
NEIE
NEIE
FE
FE
FEIE
FEIE
PE
PE
PEIE
PEIE
Figure 6. SCI Receiver Block Diagram
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Se ria l Com m unic a tions Inte rfa c e Mod ule (SCI)
Register Name
Bit 7
LOOPS
0
6
ENSCI
0
5
4
M
0
3
WAKE
0
2
ILTY
0
1
PEN
0
Bit 0
PTY
0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
TXINV
SCI Control Register 1 (SCC1)
0
SCRIE
0
SCTIE
TCIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
SCI Control Register 2 (SCC2)
SCI Control Register 3 (SCC3)
SCI Status Register 1 (SCS1)
SCI Status Register 2 (SCS2)
SCI Data Register (SCDR)
0
0
R8
T8
R
R
ORIE
NEIE
FEIE
PEIE
U
U
0
0
0
0
0
0
Read: SCTE
Write:
TC
SCRF
IDLE
OR
NF
FE
PE
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
1
1
0
0
0
0
0
0
BKF
RPF
0
0
0
0
0
0
0
0
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
Unaffected by Reset
SCP1
0
SCP0
0
R
0
SCR2
0
SCR1
0
SCR0
0
SCI Baud Rate Register (SCBR) Write:
Reset:
0
0
= Unimplemented
U = Unaffected
R
= Reserved
Figure 7. SCI I/O Receiver Register Summary
Table 4. SCI Receiver I/O Address Summary
Register SCC1
Address $0013
SCC2
$0014
SCC3
$0015
SCS1
$0016
SCS2
$0017
SCDR
$0018
SCBR
$0019
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Functional Description
Cha ra c te r Le ng th
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCC1) determines character length.
When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the
ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth
bit (bit 7).
Cha ra c te r
Re c e p tio n
During an SCI reception, the receive shift register shifts characters in
from the RxD pin. The SCI data register (SCDR) is the read-only buffer
between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character transfers to the SCDR. The SCI receiver full bit,
SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the
received byte can be read. If the SCI receive interrupt enable bit, SCRIE,
in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt
request.
Da ta Sa m p ling
The receiver samples the RxD pin at the RT clock rate. The RT clock is
an internal signal with a frequency 16 times the baud rate. To adjust for
baud rate mismatch, the RT clock is resynchronized at the following
times (see Figure 8):
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
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Se ria l Com m unic a tions Inte rfa c e Mod ule (SCI)
START BIT
LSB
RxD
START BIT
QUALIFICATION
START BIT
DATA
SAMPLES
VERIFICATION SAMPLING
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
Figure 8. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes
samples at RT3, RT5, and RT7. Table 5 summarizes the results of the
start bit verification samples.
Table 5. Start Bit Verification
RT3, RT5, and RT7 Samples
Start Bit Verification
Noise Flag
000
001
010
011
100
101
110
111
Yes
Yes
Yes
No
0
1
1
0
1
0
0
0
Yes
No
No
No
If start bit verification is not successful, the RT clock is reset and a new
search for a start bit begins.
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Functional Description
To determine the value of a data bit and to detect noise, recovery logic
takes samples at RT8, RT9, and RT10. Table 6 summarizes the results
of the data bit samples.
Table 6. Data Bit Recovery
RT8, RT9, and RT10 Samples
Data Bit Determination
Noise Flag
000
001
010
011
100
101
110
111
0
0
0
1
0
1
1
1
0
1
1
1
1
1
1
0
NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If
any or all of the RT8, RT9, and RT10 start bit samples are logic 1s
following a successful start bit verification, the noise flag (NF) is set and
the receiver assumes that the bit is a start bit.
To verify a stop bit and to detect noise, recovery logic takes samples at
RT8, RT9, and RT10. Table 7 summarizes the results of the stop bit
samples.
Table 7. Stop Bit Recovery
RT8, RT9, and RT10 Samples
Framing Error Flag
Noise Flag
000
001
010
011
100
101
110
111
1
1
1
0
1
0
0
0
0
1
1
1
1
1
1
0
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Fra m ing Erro rs
If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming character, it sets the framing error bit, FE, in
SCS1. A break character also sets the FE bit because a break character
has no stop bit. The FE bit is set at the same time that the SCRF bit is
set.
Ba ud Ra te
To le ra nc e
A transmitting device may be operating at a baud rate below or above
the receiver baud rate. Accumulated bit time misalignment can cause
one of the three stop bit data samples to fall outside the actual stop bit.
Then a noise error occurs. If more than one of the samples is outside the
stop bit, a framing error occurs. In most applications, the baud rate
tolerance is much more than the degree of misalignment that is likely to
occur.
As the receiver samples an incoming character, it resynchronizes the RT
clock on any valid falling edge within the character. Resynchronization
within characters corrects misalignments between transmitter bit times
and receiver bit times.
Slow Data Tolerance
Figure 9 shows how much a slow received character can be
misaligned without causing a noise error or a framing error. The slow
stop bit begins at RT8 instead of RT1 but arrives in time for the stop
bit data samples at RT8, RT9, and RT10.
MSB
STOP
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 9. Slow Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
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Functional Description
With the misaligned character shown in Figure 9, the receiver counts
154 RT cycles at the point when the count of the transmitting device
is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 8-bit character with no errors is
154 – 147
× 100 = 4.54%
-------------------------
154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 9, the receiver counts
170 RT cycles at the point when the count of the transmitting device
is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 9-bit character with no errors is
170 – 163
× 100 = 4.12%
-------------------------
170
Fast Data Tolerance
Figure 10 shows how much a fast received character can be
misaligned without causing a noise error or a framing error. The fast
stop bit ends at RT10 instead of RT16 but is still there for the stop bit
data samples at RT8, RT9, and RT10.
STOP
IDLE OR NEXT CHARACTER
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 10. Fast Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
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Se ria l Com m unic a tions Inte rfa c e Mod ule (SCI)
With the misaligned character shown in Figure 10, the receiver
counts 154 RT cycles at the point when the count of the transmitting
device is 10 bit times × 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a fast 8-bit character with no errors is
154 – 160
× 100 = 3.90%.
-------------------------
154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 10, the receiver
counts 170 RT cycles at the point when the count of the transmitting
device is 11 bit times × 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a fast 9-bit character with no errors is
170 – 176
× 100 = 3.53%.
-------------------------
170
Re c e ive r Wa ke up
So that the MCU can ignore transmissions intended only for other
receivers in multiple-receiver systems, the receiver can be put into a
standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the
receiver into a standby state during which receiver interrupts are
disabled.
Depending on the state of the WAKE bit in SCC1, either of two
conditions on the RxD pin can bring the receiver out of the standby state:
• Address mark — An address mark is a logic 1 in the most
significant bit position of a received character. When the WAKE bit
is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI
receiver full bit, SCRF. Software can then compare the character
containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and
processes the characters that follow. If they are not the same,
software can set the RWU bit and put the receiver back into the
standby state.
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Functional Description
• Idle input line condition — When the WAKE bit is clear, an idle
character on the RxD pin wakes the receiver from the standby
state by clearing the RWU bit. The idle character that wakes the
receiver does not set the receiver idle bit, IDLE, or the SCI receiver
full bit, SCRF. The idle line type bit, ILTY, determines whether the
receiver begins counting logic 1s as idle character bits after the
start bit or after the stop bit.
NOTE: With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.
Re c e ive r Inte rrup ts
The following sources can generate CPU interrupt requests from the SCI
receiver:
• SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that
the receive shift register has transferred a character to the SCDR.
SCRF can generate a receiver CPU interrupt request. Setting the
SCI receive interrupt enable bit, SCRIE, in SCC2 enables the
SCRF bit to generate receiver CPU interrupts.
• Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11
consecutive logic 1s shifted in from the RxD pin. The idle line
interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate
CPU interrupt requests.
Erro r Inte rrup ts
The following receiver error flags in SCS1 can generate CPU interrupt
requests:
• Receiver overrun (OR) — The OR bit indicates that the receive
shift register shifted in a new character before the previous
character was read from the SCDR. The previous character
remains in the SCDR, and the new character is lost. The overrun
interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI
error CPU interrupt requests.
• Noise flag (NF) — The NF bit is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, in SCC3 enables
NF to generate SCI error CPU interrupt requests.
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• Framing error (FE) — The FE bit in SCS1 is set when a logic 0
occurs where the receiver expects a stop bit. The framing error
interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI
error CPU interrupt requests.
• Parity error (PE) — The PE bit in SCS1 is set when the SCI
detects a parity error in incoming data. The parity error interrupt
enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU
interrupt requests.
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low
power-consumption standby modes.
Wa it Mod e
The SCI module remains active in wait mode. Any enabled CPU
interrupt request from the SCI module can bring the MCU out of wait
mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.
Stop Mod e
The SCI module is inactive in stop mode. The STOP instruction does not
affect SCI register states. SCI module operation resumes after the MCU
exits stop mode.
Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.
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SCI During Break Module Interrupts
SCI During Bre a k Mod ule Inte rrup ts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. (See Break Module on page
135).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
I/ O Sig na ls
Port E shares two of its pins with the SCI module. The two SCI I/O pins
are:
• PTE0/SCTxD — Transmit data
• PTE1/SCRxD — Receive data
PTE0/ SCTxD
(Tra nsm it Da ta )
The PTE0/SCTxD pin is the serial data output from the SCI transmitter.
The SCI shares the PTE0/SCTxD pin with port E. When the SCI is
enabled, the PTE0/SCTxD pin is an output regardless of the state of the
DDRE2 bit in data direction register E (DDRE).
PTE1/ SCRxD
(Re c e ive Da ta )
The PTE1/SCRxD pin is the serial data input to the SCI receiver. The
SCI shares the PTE1/SCRxD pin with port E. When the SCI is enabled,
the PTE1/SCRxD pin is an input regardless of the state of the DDRE1
bit in data direction register E (DDRE).
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Se ria l Com m unic a tions Inte rfa c e Mod ule (SCI)
I/ O Re g iste rs
The following I/O registers control and monitor SCI operation:
• SCI control register 1 (SCC1)
• SCI control register 2 (SCC2)
• SCI control register 3 (SCC3)
• SCI status register 1 (SCS1)
• SCI status register 2 (SCS2)
• SCI data register (SCDR)
• SCI baud rate register (SCBR)
SCI Control
Re g iste r 1
SCI control register 1:
• Enables loop mode operation
• Enables the SCI
• Controls output polarity
• Controls character length
• Controls SCI wakeup method
• Controls idle character detection
• Enables parity function
• Controls parity type
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I/O Registers
Address: $0013
Bit 7
6
ENSCI
0
5
TXINV
0
4
M
0
3
WAKE
0
2
ILLTY
0
1
Bit 0
Read:
LOOPS
Write:
PEN
0
PTY
0
Reset:
0
Figure 11. SCI Control Register 1 (SCC1)
LOOPS — Loop Mode Select Bit
This read/write bit enables loop mode operation. In loop mode the
RxD pin is disconnected from the SCI, and the transmitter output goes
into the receiver input. Both the transmitter and the receiver must be
enabled to use loop mode. Reset clears the LOOPS bit.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI — Enable SCI Bit
This read/write bit enables the SCI and the SCI baud rate generator.
Clearing ENSCI sets the SCTE and TC bits in SCI status register 1
and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = SCI enabled
0 = SCI disabled
TXINV — Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data. Reset
clears the TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE: Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
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Se ria l Com m unic a tions Inte rfa c e Mod ule (SCI)
M — Mode (Character Length) Bit
This read/write bit determines whether SCI characters are eight or
nine bits long. (See Table 8).The ninth bit can serve as an extra stop
bit, as a receiver wakeup signal, or as a parity bit. Reset clears the M
bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Condition Bit
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit position of a received
character or an idle condition on the RxD pin. Reset clears the WAKE
bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY — Idle Line Type Bit
This read/write bit determines when the SCI starts counting logic 1s
as idle character bits. The counting begins either after the start bit or
after the stop bit. If the count begins after the start bit, then a string of
logic 1s preceding the stop bit may cause false recognition of an idle
character. Beginning the count after the stop bit avoids false idle
character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
PEN — Parity Enable Bit
This read/write bit enables the SCI parity function. (See Table 8).
When enabled, the parity function inserts a parity bit in the most
significant bit position. (See Table 7). Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
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I/O Registers
PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks
for odd parity or even parity. (See Table 8). Reset clears the PTY bit.
1 = Odd parity
0 = Even parity
NOTE: Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 8. Character Format Selection
Control Bits
PEN:PTY
Character Format
Start
Bits
Data
Bits
Stop
Parity
Character
Length
M
Bits
0
1
0
0
1
1
0X
0X
10
11
10
11
1
1
1
1
1
1
8
9
7
7
8
8
None
None
Even
Odd
1
1
1
1
1
1
10 Bits
11 Bits
10 Bits
10 Bits
11 Bits
11 Bits
Even
Odd
SCI Control
Re g iste r 2
SCI control register 2:
• Enables the following CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt
requests
– Enables the TC bit to generate transmitter CPU interrupt
requests
– Enables the SCRF bit to generate receiver CPU interrupt
requests
– Enables the IDLE bit to generate receiver CPU interrupt
requests
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• Enables the transmitter
• Enables the receiver
• Enables SCI wakeup
• Transmits SCI break characters
Address: $0014
Bit 7
6
TCIE
0
5
SCRIE
0
4
ILIE
0
3
TE
0
2
RE
0
1
RWU
0
Bit 0
SBK
0
Read:
Write:
Reset:
SCTIE
0
Figure 12. SCI Control Register 2 (SCC2)
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter
CPU interrupt requests. Setting the SCTIE bit in SCC3 enables the
SCTE bit to generate CPU interrupt requests. Reset clears the SCTIE
bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU
interrupt requests. Reset clears the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
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I/O Registers
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver
CPU interrupt requests. Setting the SCRIE bit in SCC3 enables the
SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE
bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU
interrupt requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
TxD pin. If software clears the TE bit, the transmitter completes any
transmission in progress before the TxD returns to the idle condition
(logic 1). Clearing and then setting TE during a transmission queues
an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
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RE — Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver but does not affect receiver interrupt flag bits.
Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
NOTE: Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RWU — Receiver Wakeup Bit
This read/write bit puts the receiver in a standby state during which
receiver interrupts are disabled. The WAKE bit in SCC1 determines
whether an idle input or an address mark brings the receiver out of the
standby state and clears the RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting and then clearing this read/write bit transmits a break
character followed by a logic 1. The logic 1 after the break character
guarantees recognition of a valid start bit. If SBK remains set, the
transmitter continuously transmits break characters with no logic 1s
between them. Reset clears the SBK bit.
1 = Transmit break characters
0 = No break characters being transmitted
NOTE: Do not toggle the SBK bit immediately after setting the SCTE bit.
Toggling SBK before the preamble begins causes the SCI to send a
break character instead of a preamble.
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I/O Registers
SCI Control
Re g iste r 3
SCI control register 3:
• Stores the ninth SCI data bit received and the ninth SCI data bit to
be transmitted.
• Enables the following interrupts:
– Receiver overrun interrupts
– Noise error interrupts
– Framing error interrupts
– Parity error interrupts
Address: $0015
Bit 7
R8
6
T8
U
5
R
0
4
3
2
NEIE
0
1
FEIE
0
Bit 0
PEIE
0
Read:
Write:
Reset:
R
ORIE
U
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 13. SCI Control Register 3 (SCC3)
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth
bit (bit 8) of the received character. R8 is received at the same time
that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth
bit (bit 7). Reset has no effect on the R8 bit.
T8 — Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write
ninth bit (bit 8) of the transmitted character. T8 is loaded into the
transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
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ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the noise error bit, NE. Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
FEIE — Receiver Framing Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the framing error bit, FE. Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI receiver CPU interrupt requests
generated by the parity error bit, PE. Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
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I/O Registers
SCI Sta tus Register 1
SCI status register 1 contains flags to signal the following conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
• Parity error
Address: $0016
Bit 7
Read: SCTE
Write:
6
5
4
3
2
1
Bit 0
PE
TC
SCRF
IDLE
OR
NF
FE
Reset:
1
1
0
0
0
0
0
0
= Unimplemented
Figure 14. SCI Status Register 1 (SCS1)
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal
operation, clear the SCTE bit by reading SCS1 with SCTE set and
then writing to SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
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TC — Transmission Complete Bit
This read-only bit is set when the SCTE bit is set, and no data,
preamble, or break character is being transmitted. TC generates an
SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also
set. TC is cleared automatically when data, preamble, or break is
queued and ready to be sent. There may be up to 1.5 transmitter
clocks of latency between queueing data, preamble, and break and
the transmission actually starting. Reset sets the TC bit.
1 = No transmission in progress
0 = Transmission in progress
SCRF — SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. SCRF can generate an SCI
receiver CPU interrupt request. When the SCRIE bit in SCC2 is set
the SCRF generates a CPU interrupt request. In normal operation,
clear the SCRF bit by reading SCS1 with SCRF set and then reading
the SCDR. Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an SCI error CPU
interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit
by reading SCS1 with IDLE set and then reading the SCDR. After the
receiver is enabled, it must receive a valid character that sets the
SCRF bit before an idle condition can set the IDLE bit. Also, after the
IDLE bit has been cleared, a valid character must again set the SCRF
bit before an idle condition can set the IDLE bit. Reset clears the IDLE
bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the
SCDR before the receive shift register receives the next character.
The OR bit generates an SCI error CPU interrupt request if the ORIE
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I/O Registers
bit in SCC3 is also set. The data in the shift register is lost, but the data
already in the SCDR is not affected. Clear the OR bit by reading SCS1
with OR set and then reading the SCDR. Reset clears the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Software latency may allow an overrun to occur between reads of SCS1
and SCDR in the flag-clearing sequence. Figure 15 shows the normal
flag-clearing sequence and an example of an overrun caused by a
delayed flag-clearing sequence. The delayed read of SCDR does not
clear the OR bit because OR was not set when SCS1 was read. Byte 2
caused the overrun and is lost. The next flag-clearing sequence reads
byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is
important to know which byte is lost due to an overrun, the flag-clearing
routine can check the OR bit in a second read of SCS1 after reading the
data register.
NORMAL FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCDR
BYTE 2
READ SCDR
BYTE 3
DELAYED FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 1
READ SCDR
BYTE 3
Figure 15. Flag Clearing Sequence
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Se ria l Com m unic a tions Inte rfa c e Mod ule (SCI)
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the
RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in
SCC3 is also set. Clear the NF bit by reading SCS1 and then reading
the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the
stop bit. FE generates an SCI error CPU interrupt request if the FEIE
bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
SCI Sta tus
Register 2
SCI status register 2 contains flags to signal the following conditions:
• Break character detected
• Incoming data
Address: $0017
Bit 7
6
5
4
0
3
0
2
0
1
Bit 0
RPF
Read:
Write:
Reset:
BKF
0
0
0
0
0
= Unimplemented
Figure 16. SCI Status Register 2 (SCS2)
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Serial Communications Interface Module (SCI)
I/O Registers
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break
character on the RxD pin. In SCS1, the FE and SCRF bits are also
set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared.
BKF does not generate a CPU interrupt request. Clear BKF by
reading SCS2 with BKF set and then reading the SCDR. Once
cleared, BKF can become set again only after logic 1s again appear
on the RxD pin followed by another break character. Reset clears the
BKF bit.
1 = Break character detected
0 = No break character detected
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the
RT1 time period of the start bit search. RPF does not generate an
interrupt request. RPF is reset after the receiver detects false start bits
(usually from noise or a baud rate mismatch), or when the receiver
detects an idle character. Polling RPF before disabling the SCI
module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress
SCI Da ta Re g iste r
The SCI data register is the buffer between the internal data bus and the
receive and transmit shift registers. Reset has no effect on data in the
SCI data register.
Address: $0018
Bit 7
R7
6
5
4
3
2
1
Bit 0
R0
Read:
Write:
Reset:
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
T7
T0
Unaffected by Reset
Figure 17. SCI Data Register (SCDR)
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Se ria l Com m unic a tions Inte rfa c e Mod ule (SCI)
R7/T7:R0/T0 — Receive/Transmit Data Bits
Reading address $0018 accesses the read-only received data bits,
R7:R0. Writing to address $0018 writes the data to be transmitted,
T7:T0. Reset has no effect on the SCI data register.
NOTE: Do not use read-modify-write instructions on the SCI data register.
SCI Ba ud Ra te
Re g iste r
The baud rate register selects the baud rate for both the receiver and the
transmitter.
Address: $0019
Bit 7
0
6
5
SCP1
0
4
3
2
SCR2
0
1
SCR1
0
Bit 0
SCR0
0
Read:
Write:
Reset:
SCP0
R
0
0
0
= Unimplemented
R
= Reserved
Figure 18. SCI Baud Rate Register (SCBR)
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown
in Table 9. Reset clears SCP1 and SCP0.
Table 9. SCI Baud Rate Prescaling
SCP[1:0]
Prescaler Divisor (PD)
00
01
10
11
1
3
4
13
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Serial Communications Interface Module (SCI)
I/O Registers
SCR2 – SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate divisor as shown in
Table 10. Reset clears SCR2–SCR0.
Table 10. SCI Baud Rate Selection
SCR[2:1:0]
000
Baud Rate Divisor (BD)
1
2
001
010
4
011
8
100
16
32
64
128
101
110
111
Use the following formula to calculate the SCI baud rate:
fCrystal
Baud rate = ------------------------------------
64 × PD × BD
where:
f
Crystal = crystal frequency
PD = prescaler divisor
BD = baud rate divisor
Table 11 shows the SCI baud rates that can be generated with a
4.9152-MHz crystal.
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Se ria l Com m unic a tions Inte rfa c e Mod ule (SCI)
Table 11. SCI Baud Rate Selection Examples
Prescaler
Divisor
(PD)
Baud Rate
Divisor
(BD)
Baud Rate
= 4.9152 MHz)
SCP[1:0]
SCR[2:1:0]
(f
Crystal
00
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
1
1
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
1
2
76,800
38,400
19,200
9600
4800
2400
1200
600
1
4
1
8
1
16
32
64
128
1
1
1
1
3
25,600
12,800
6400
3200
1600
800
3
2
3
4
3
8
3
16
32
64
128
1
3
3
400
3
200
4
19,200
9600
4800
2400
1200
600
4
2
4
4
4
8
4
16
32
64
128
1
4
4
300
4
150
13
13
13
13
13
13
13
13
5908
2954
1477
739
2
4
8
16
32
64
128
369
185
92
46
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Pin Name and Register Name Conventions . . . . . . . . . . . . . . . . . . . 213
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Transmission Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . . . . . . . 218
Transmission Format When CPHA = 0. . . . . . . . . . . . . . . . . . . . . 219
Transmission Format When CPHA = 1. . . . . . . . . . . . . . . . . . . . . 220
Transmission Initiation Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Overflow Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Mode Fault Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
VSS (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
SPI Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . 238
SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
Introd uc tion
This section describes the serial peripheral interface (SPI) module,
which allows full-duplex, synchronous, serial communications with
peripheral devices.
Fe a ture s
Features of the SPI module include:
• Full-Duplex Operation
• Master and Slave Modes
• Double-Buffered Operation with Separate Transmit and Receive
Registers
• Four Master Mode Frequencies (Maximum = Bus Frequency ÷ 2)
• Maximum Slave Mode Frequency = Bus Frequency
• Serial Clock with Programmable Polarity and Phase
• Two Separately Enabled Interrupts with CPU Service:
– SPRF (SPI Receiver Full)
– SPTE (SPI Transmitter Empty)
• Mode Fault Error Flag with CPU Interrupt Capability
• Overflow Error Flag with CPU Interrupt Capability
• Programmable Wired-OR Mode
• I2C (Inter-Integrated Circuit) Compatibility
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Serial Peripheral Interface Module (SPI)
Pin Name and Register Name Conventions
Pin Na m e a nd Re g iste r Na m e Conve ntions
The generic names of the SPI input/output (I/O) pins are:
• SS (slave select)
• SPSCK (SPI serial clock)
• MOSI (master out slave in)
• MISO (master in slave out)
The SPI shares four I/O pins with a parallel I/O port. The full name of an
SPI pin reflects the name of the shared port pin. Table 1 shows the full
names of the SPI I/O pins. The generic pin names appear in the text that
follows.
Table 1. Pin Name Conventions
SPI Generic Pin Name
Full SPI Pin Name
MISO
MOSI
SS
SPSCK
PTE5/MISO PTE6/MOSI PTE4/SS PTE7/SPSCK
The generic names of the SPI I/O registers are:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
Table 2 shows the names and the addresses of the SPI I/O registers.
Table 2. I/O Register Addresses
Register Name
SPI Control Register (SPCR)
SPI Status and Control Register (SPSCR)
SPI Data Register (SPDR)
Address
$0010
$0011
$0012
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
Func tiona l De sc rip tion
Table 3 summarizes the SPI I/O registers and Figure 1 shows the
structure of the SPI module.
Table 3. SPI I/O Register Summary
Addr
Register Name
R/W Bit 7
6
R
0
5
4
3
2
1
Bit 0
SPTIE
0
Read:
SPRIE
Write:
SPI Control Register
$0010
SPMSTR CPOL
CPHA SPWOM SPE
(SPCR)
Reset:
0
1
0
1
0
0
Read: SPRF
OVRF MODF
SPTE
SPI Status and Control Register
(SPSCR)
$0011
$0012
ERRIE
0
MODFEN SPR1
SPR0
0
Write:
R
0
R
0
R
0
R
1
Reset:
0
0
Read:
Write:
Reset:
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SPI Data Register
(SPDR)
Unaffected by Reset
R
=Reserved
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Serial Peripheral Interface Module (SPI)
Functional Description
INTERNAL BUS
TRANSMIT DATA REGISTER
SHIFT REGISTER
BUS CLOCK
MISO
MOSI
7
6
5
4
3
2
1
0
÷ 2
÷ 8
÷ 32
CLOCK
DIVIDER
RECEIVE DATA REGISTER
PIN
CONTROL
LOGIC
÷ 128
CLOCK
SPSCK
SS
SPMSTR
SPE
SELECT
M
CLOCK
LOGIC
S
SPR1
SPR0
SPMSTR
CPHA
CPOL
SPWOM
TRANSMITTER CPU INTERRUPT REQUEST
RECEIVER/ERROR CPU INTERRUPT REQUEST
MODFEN
ERRIE
SPTIE
SPI
CONTROL
SPRIE
SPE
SPRF
SPTE
OVRF
MODF
Figure 1. SPI Module Block Diagram
The SPI module allows full-duplex, synchronous, serial communication
between the MCU and peripheral devices, including other MCUs.
Software can poll the SPI status flags or SPI operation can be interrupt
driven. All SPI interrupts can be serviced by the CPU.
The following paragraphs describe the operation of the SPI module.
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
Ma ste r Mod e
The SPI operates in master mode when the SPI master bit, SPMSTR
(SPCR $0010), is set.
NOTE: Configure the SPI modules as master and slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave
SPI before disabling the master SPI. See SPI Control Register on page
236.
Only a master SPI module can initiate transmissions. Software begins
the transmission from a master SPI module by writing to the SPI data
register. If the shift register is empty, the byte immediately transfers to
the shift register, setting the SPI transmitter empty bit, SPTE (SPSCR
$0011). The byte begins shifting out on the MOSI pin under the control
of the serial clock. (See Table 4).
The SPR1 and SPR0 bits control the baud rate generator and determine
the speed of the shift register. (See SPI Status and Control Register
on page 238). Through the SPSCK pin, the baud rate generator of the
master also controls the shift register of the slave peripheral.
MASTER MCU
SLAVE MCU
MISO
MOSI
MISO
MOSI
SHIFT REGISTER
SHIFT REGISTER
SPSCK
SS
SPSCK
SS
BAUD RATE
GENERATOR
V
DD
Figure 2. Full-Duplex Master-Slave Connections
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Serial Peripheral Interface Module (SPI)
Functional Description
As the byte shifts out on the MOSI pin of the master, another byte shifts
in from the slave on the master’s MISO pin. The transmission ends when
the receiver full bit, SPRF (SPSCR), becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data
register. In normal operation, SPRF signals the end of a transmission.
Software clears SPRF by reading the SPI status and control register and
then reading the SPI data register. Writing to the SPI data register clears
the SPTIE bit.
Sla ve Mod e
The SPI operates in slave mode when the SPMSTR bit (SPCR, $0010)
is clear. In slave mode the SPSCK pin is the input for the serial clock
from the master MCU. Before a data transmission occurs, the SS pin of
the slave MCU must be at logic 0. SS must remain low until the
transmission is complete. (See Mode Fault Error on page 225).
In a slave SPI module, data enters the shift register under the control of
the serial clock from the master SPI module. After a byte enters the shift
register of a slave SPI, it is transferred to the receive data register, and
the SPRF bit (SPSCR) is set. To prevent an overflow condition, slave
software then must read the SPI data register before another byte enters
the shift register.
The maximum frequency of the SPSCK for an SPI configured as a slave
is the bus clock speed, which is twice as fast as the fastest master
SPSCK clock that can be generated. The frequency of the SPSCK for an
SPI configured as a slave does not have to correspond to any SPI baud
rate. The baud rate only controls the speed of the SPSCK generated by
an SPI configured as a master. Therefore, the frequency of the SPSCK
for an SPI configured as a slave can be any frequency less than or equal
to the bus speed.
When the master SPI starts a transmission, the data in the slave shift
register begins shifting out on the MISO pin. The slave can load its shift
register with a new byte for the next transmission by writing to its transmit
data register. The slave must write to its transmit data register at least
one bus cycle before the master starts the next transmission. Otherwise
the byte already in the slave shift register shifts out on the MISO pin.
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
Data written to the slave shift register during a a transmission remains in
a buffer until the end of the transmission.
When the clock phase bit (CPHA) is set, the first edge of SPSCK starts
a transmission. When CPHA is clear, the falling edge of SS starts a
transmission. (See Transmission Formats on page 218).
If the write to the data register is late, the SPI transmits the data already
in the shift register from the previous transmission.
NOTE: To prevent SPSCK from appearing as a clock edge, SPSCK must be in
the proper idle state before the slave is enabled.
Tra nsm ission Form a ts
During an SPI transmission, data is simultaneously transmitted (shifted
out serially) and received (shifted in serially). A serial clock line
synchronizes shifting and sampling on the two serial data lines. A slave
select line allows individual selection of a slave SPI device; slave
devices that are not selected do not interfere with SPI bus activities. On
a master SPI device, the slave select line can be used optionally to
indicate a multiple-master bus contention.
Cloc k Pha se a nd
Pola rity Controls
Software can select any of four combinations of serial clock (SCK) phase
and polarity using two bits in the SPI control register (SPCR). The clock
polarity is specified by the CPOL control bit, which selects an active high
or low clock and has no significant effect on the transmission format.
The clock phase (CPHA) control bit (SPCR) selects one of two
fundamentally different transmission formats. The clock phase and
polarity should be identical for the master SPI device and the
communicating slave device. In some cases, the phase and polarity are
changed between transmissions to allow a master device to
communicate with peripheral slaves having different requirements.
NOTE: Before writing to the CPOL bit or the CPHA bit (SPCR), disable the SPI
by clearing the SPI enable bit (SPE).
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Serial Peripheral Interface Module (SPI)
Transmission Formats
Tra nsm ission
Form a t Whe n
CPHA = 0
Figure 3 shows an SPI transmission in which CPHA (SPCR) is logic 0.
The figure should not be used as a replacement for data sheet
parametric information. Two waveforms are shown for SCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted
as a master or slave timing diagram since the serial clock (SCK), master
in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the
output from the slave, and the MOSI signal is the output from the master.
The SS line is the slave select input to the slave. The slave SPI drives
its MISO output only when its slave select input (SS) is at logic 0, so that
only the selected slave drives to the master. The SS pin of the master is
not shown but is assumed to be inactive. The SS pin of the master must
be high or must be reconfigured as general-purpose I/O not affecting the
SPI (see Mode Fault Error on page 225). When CPHA = 0, the first
SPSCK edge is the MSB capture strobe. Therefore, the slave must
begin driving its data before the first SPSCK edge, and a falling edge on
the SS pin is used to start the transmission. The SS pin must be toggled
high and then low again between each byte transmitted.
SCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
SCK CPOL = 0
SCK CPOL = 1
MOSI
MSB
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
BIT 1
BIT 1
LSB
LSB
FROM MASTER
MISO
FROM SLAVE
MSB
SS TO SLAVE
CAPTURE STROBE
Figure 3. Transmission Format (CPHA = 0)
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
Tra nsm ission
Form a t Whe n
CPHA = 1
Figure 4 shows an SPI transmission in which CPHA (SPCR) is logic 1.
The figure should not be used as a replacement for data sheet
parametric information. Two waveforms are shown for SCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted
as a master or slave timing diagram since the serial clock (SCK), master
in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the
output from the slave, and the MOSI signal is the output from the master.
The SS line is the slave select input to the slave. The slave SPI drives
its MISO output only when its slave select input (SS) is at logic 0, so that
only the selected slave drives to the master. The SS pin of the master is
not shown but is assumed to be inactive. The SS pin of the master must
be high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See Mode Fault Error on page 225). When CPHA = 1, the master
begins driving its MOSI pin on the first SPSCK edge. Therefore, the
slave uses the first SPSCK edge as a start transmission signal. The SS
pin can remain low between transmissions. This format may be
preferable in systems having only one master and only one slave driving
the MISO data line.
SCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
SCK CPOL = 0
SCK CPOL =1
MOSI
FROM MASTER
MSB
MSB
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
BIT 1
BIT 1
LSB
MISO
FROM SLAVE
LSB
SS TO SLAVE
CAPTURE STROBE
Figure 4. Transmission Format (CPHA = 1)
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Serial Peripheral Interface Module (SPI)
Transmission Formats
Tra nsm ission
Initia tion La te nc y
When the SPI is configured as a master (SPMSTR = 1), transmissions
are started by a software write to the SPDR ($0012). CPHA has no effect
on the delay to the start of the transmission, but it does affect the initial
state of the SCK signal. When CPHA = 0, the SCK signal remains
inactive for the first half of the first SCK cycle. When CPHA = 1, the first
SCK cycle begins with an edge on the SCK line from its inactive to its
active level. The SPI clock rate (selected by SPR1–SPR0) affects the
delay from the write to SPDR and the start of the SPI transmission. (See
Figure 5). The internal SPI clock in the master is a free-running
derivative of the internal MCU clock. It is only enabled when both the
SPE and SPMSTR bits (SPCR) are set to conserve power. SCK edges
occur half way through the low time of the internal MCU clock. Since the
SPI clock is free-running, it is uncertain where the write to the SPDR will
occur relative to the slower SCK. This uncertainty causes the variation
in the initiation delay shown in Figure 5. This delay will be no longer than
a single SPI bit time. That is, the maximum delay between the write to
SPDR and the start of the SPI transmission is two MCU bus cycles for
DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and
128 MCU bus cycles for DIV128.
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
WRITE
TO SPDR
INITIATION DELAY
MSB
BUS
CLOCK
MOSI
BIT 6
BIT 5
SCK
CPHA = 1
SCK
CPHA = 0
SCK CYCLE
NUMBER
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
WRITE
TO SPDR
BUS
CLOCK
SCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
EARLIEST LATEST
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SCK = INTERNAL CLOCK ÷ 8;
8 POSSIBLE START POINTS
LATEST
LATEST
LATEST
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
Figure 5. Transmission Start Delay (Master)
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Serial Peripheral Interface Module (SPI)
Error Conditions
Error Cond itions
Two flags signal SPI error conditions:
1. Overflow (OVRFin SPSCR) — Failing to read the SPI data register
before the next byte enters the shift register sets the OVRF bit.
The new byte does not transfer to the receive data register, and
the unread byte still can be read by accessing the SPI data
register. OVRF is in the SPI status and control register.
2. Mode fault error (MODF in SPSCR) — The MODF bit indicates
that the voltage on the slave select pin (SS) is inconsistent with the
mode of the SPI. MODF is in the SPI status and control register.
Ove rflow Error
The overflow flag (OVRF in SPSCR) becomes set if the SPI receive data
register still has unread data from a previous transmission when the
capture strobe of bit 1 of the next transmission occurs. (See Figure 3
and Figure 4.) If an overflow occurs, the data being received is not
transferred to the receive data register so that the unread data can still
be read. Therefore, an overflow error always indicates the loss of data.
OVRF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE in SPSCR) is also set. MODF and OVRF can
generate a receiver/error CPU interrupt request. (See Figure 8). It is not
possible to enable only MODF or OVRF to generate a receiver/error
CPU interrupt request. However, leaving MODFEN low prevents MODF
from being set.
If an end-of-block transmission interrupt was meant to pull the MCU out
of wait, having an overflow condition without overflow interrupts enabled
causes the MCU to hang in wait mode. If the OVRF is enabled to
generate an interrupt, it can pull the MCU out of wait mode instead.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not,
watch for an overflow condition. Figure 6 shows how it is possible to
miss an overflow.
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
BYTE 1
BYTE 2
4
BYTE 3
6
BYTE 4
8
1
SPRF
OVRF
2
5
READ SPSCR
READ SPDR
3
7
1
2
BYTE 1 SETS SPRF BIT.
5
CPU READS SPSCRW WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
6
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
3
4
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
BYTE 2 SETS SPRF BIT.
8
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS SET. BYTE 4 IS LOST.
Figure 6. Missed Read of Overflow Condition
The first part of Figure 6 shows how to read the SPSCR and SPDR to
clear the SPRF without problems. However, as illustrated by the second
transmission example, the OVRF flag can be set in between the time
that SPSCR and SPDR are read.
In this case, an overflow can be easily missed. Since no more SPRF
interrupts can be generated until this OVRF is serviced, it will not be
obvious that bytes are being lost as more transmissions are completed.
To prevent this, either enable the OVRF interrupt or do another read of
the SPSCR after the read of the SPDR. This ensures that the OVRF was
not set before the SPRF was cleared and that future transmissions will
complete with an SPRF interrupt. Figure 7 illustrates this process.
Generally, to avoid this second SPSCR read, enable the OVRF to the
CPU by setting the ERRIE bit (SPSCR).
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Serial Peripheral Interface Module (SPI)
Error Conditions
BYTE 1
1
BYTE 2
5
BYTE 3
7
BYTE 4
11
SPI RECEIVE
COMPLETE
SPRF
OVRF
2
4
6
9
12
14
READ SPSCR
READ SPDR
3
8
10
13
1
2
8
9
BYTE 1 SETS SPRF BIT.
CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
3
4
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
10
CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
11
12
13
BYTE 4 SETS SPRF BIT.
CPU READS SPSCR.
5
6
BYTE 2 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
14
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
Figure 7. Clearing SPRF When OVRF Interrupt Is Not Enabled
Mod e Fa ult Error
For the MODF flag (in SPSCR) to be set, the mode fault error enable bit
(MODFEN in SPSCR) must be set. Clearing the MODFEN bit does not
clear the MODF flag but does prevent MODF from being set again after
MODF is cleared.
MODF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE in SPSCR) is also set. The SPRF, MODF,
and OVRF interrupts share the same CPU interrupt vector. MODF and
OVRF can generate a receiver/error CPU interrupt request. (See Figure
8). It is not possible to enable only MODF or OVRF to generate a
receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
In a master SPI with the mode fault enable bit (MODFEN) set, the mode
fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master
SPI causes the following events to occur:
• If ERRIE = 1, the SPI generates an SPI receiver/error CPU
interrupt request.
• The SPE bit is cleared.
• The SPTE bit is set.
• The SPI state counter is cleared.
• The data direction register of the shared I/O port regains control of
port drivers.
NOTE: To prevent bus contention with another master SPI after a mode fault
error, clear all data direction register (DDR) bits associated with the SPI
shared port pins.
NOTE: Setting the MODF flag (SPSCR) does not clear the SPMSTR bit.
Reading SPMSTR when MODF = 1 will indicate a MODE fault error
occurred in either master mode or slave mode.
When configured as a slave (SPMSTR = 0), the MODF flag is set if SS
goes high during a transmission. When CPHA = 0, a transmission begins
when SS goes low and ends once the incoming SPSCK returns to its idle
level after the shift of the eighth data bit. When CPHA = 1, the
transmission begins when the SPSCK leaves its idle level and SS is
already low. The transmission continues until the SPSCK returns to its
IDLE level after the shift of the last data bit. (See Transmission
Formats on page 218).
NOTE: When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0)
and later unselected (SS is at logic 1) even if no SPSCK is sent to that
slave. This happens because SS at logic 0 indicates the start of the
transmission (MISO driven out with the value of MSB) for CPHA = 0.
When CPHA = 1, a slave can be selected and then later unselected with
no transmission occurring. Therefore, MODF does not occur since a
transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI
receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
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Serial Peripheral Interface Module (SPI)
Interrupts
bit does not clear the SPE bit or reset the SPI in any way. Software can
abort the SPI transmission by toggling the SPE bit of the slave.
NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK
clocks, even if a transmission has begun.
To clear the MODF flag, read the SPSCR and then write to the SPCR
register. This entire clearing procedure must occur with no MODF
condition existing or else the flag will not be cleared.
Inte rrup ts
Four SPI status flags can be enabled to generate CPU interrupt
requests:
Table 4. SPI Interrupts
Flag
Request
SPTE (Transmitter Empty) SPI Transmitter CPU Interrupt Request (SPTIE = 1)
SPRF (Receiver Full)
OVRF (Overflow)
SPI Receiver CPU Interrupt Request (SPRIE = 1)
SPI Receiver/Error Interrupt Request
(SPRIE = 1, ERRIE = 1)
SPI Receiver/Error Interrupt Request
(SPRIE = 1, ERRIE = 1, MODFEN = 1)
MODF (Mode Fault)
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests.
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt, provided that the SPI is enabled
(SPE = 1).
The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF flags to generate a receiver/error CPU interrupt request.
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF flag is enabled to generate
receiver/error CPU interrupt requests.
SPTE
SPTIE
SPE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
SPRIE
SPRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
ERRIE
MODF
OVRF
Figure 8. SPI Interrupt Request Generation
Two sources in the SPI status and control register can generate CPU
interrupt requests:
1. SPI receiver full bit (SPRF) — The SPRF bit becomes set every
time a byte transfers from the shift register to the receive data
register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF can generate an SPI receiver/error CPU interrupt request.
2. SPI transmitter empty (SPTE) — The SPTE bit becomes set every
time a byte transfers from the transmit data register to the shift
register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE can generate an SPTE CPU interrupt request.
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Serial Peripheral Interface Module (SPI)
Queuing Transmission Data
Que uing Tra nsm ission Da ta
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE in SPSCR) indicates
when the transmit data buffer is ready to accept new data. Write to the
SPI data register only when the SPTE bit is high. Figure 9 shows the
timing associated with doing back-to-back transmissions with the SPI
(SPSCK has CPHA:CPOL = 1:0).
1
3
8
WRITE TO SPDR
SPTE
5
10
2
SPSCK (CPHA:CPOL = 1:0)
MOSI
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT
6
5
4
3
2
1
6
5
4
3
2
1
6
5
4
BYTE 1
BYTE 2
BYTE 3
4
9
SPRF
READ SPSCR
READ SPDR
6
11
7
12
1
2
3
4
CPU WRITES BYTE 1 TO SPDR, CLEARING
SPTE BIT.
7
8
CPU READS SPDR, CLEARING SPRF BIT.
CPU WRITES BYTE 3 TO SPDR, QUEUEING
BYTE 3 AND CLEARING SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
9
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING
BYTE 2 AND CLEARING SPTE BIT.
10
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
11
12
CPU READS SPSCR WITH SPRF BIT SET.
CPU READS SPDR, CLEARING SPRF BIT.
5
6
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU READS SPSCR WITH SPRF BIT SET.
Figure 9. SPRF/SPTE CPU Interrupt Timing
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
For a slave, the transmit data buffer allows back-to-back transmissions
to occur without the slave having to time the write of its data between the
transmissions. Also, if no new data is written to the data buffer, the last
value contained in the shift register will be the next data word
transmitted.
Re se tting the SPI
Any system reset completely resets the SPI. Partial reset occurs
whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the
following occurs:
• The SPTE flag is set.
• Any transmission currently in progress is aborted.
• The shift register is cleared.
• The SPI state counter is cleared, making it ready for a new
complete transmission.
• All the SPI port logic is defaulted back to being general-purpose
I/O.
The following additional items are reset only by a system reset:
• All control bits in the SPCR register
• All control bits in the SPSCR register (MODFEN, ERRIE, SPR1,
and SPR0)
• The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE
between transmissions without having to reset all control bits when SPE
is set back to high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still
service these interrupts after the SPI has been disabled. The user can
disable the SPI by writing 0 to the SPE bit. The SPI also can be disabled
by a mode fault occurring in an SPI that was configured as a master with
the MODFEN bit set.
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Serial Peripheral Interface Module (SPI)
Low-Power Modes
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
Wa it Mod e
The SPI module remains active after the execution of a WAIT instruction.
In wait mode, the SPI module registers are not accessible by the CPU.
Any enabled CPU interrupt request from the SPI module can bring the
MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF
bit to generate CPU interrupt requests by setting the error interrupt
enable bit (ERRIE). (See Interrupts on page 227).
Stop Mod e
The SPI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect register conditions. SPI operation
resumes after the MCU exits stop mode. If stop mode is exited by reset,
any transfer in progress is aborted and the SPI is reset.
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
SPI During Bre a k Inte rrup ts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR, $FE03) enables software to
clear status bits during the break state. (See SIM Break Flag Control
Register on page 103).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit
cleared, a write to the data register in break mode will not initiate a
transmission nor will this data be transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared
has no effect.
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Serial Peripheral Interface Module (SPI)
I/O Signals
I/ O Sig na ls
The SPI module has four I/O pins and shares three of them with a
parallel I/O port.
• MISO — Data received
• MOSI — Data transmitted
• SPSCK — Serial clock
• SS — Slave select
• VSS — Clock ground
The SPI has limited inter-integrated circuit (I2C) capability (requiring
software support) as a master in a single-master environment. To
communicate with I2C peripherals, MOSI becomes an open-drain output
when the SPWOM bit in the SPI control register is set. In I2C
communication, the MOSI and MISO pins are connected to a
bidirectional pin from the I2C peripheral and through a pullup resistor
to VDD.
MISO (Ma ste r
In/ Sla ve Out)
MISO is one of the two SPI module pins that transmit serial data. In full
duplex operation, the MISO pin of the master SPI module is connected
to the MISO pin of the slave SPI module. The master SPI simultaneously
receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is
configured as a slave. The SPI is configured as a slave when its
SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a
multiple-slave system, a logic 1 on the SS pin puts the MISO pin in a
high-impedance state.
When enabled, the SPI controls data direction of the MISO pin
regardless of the state of the data direction register of the shared I/O
port.
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
MOSI (Ma ste r
Out/ Sla ve In)
MOSI is one of the two SPI module pins that transmit serial data. In full
duplex operation, the MOSI pin of the master SPI module is connected
to the MOSI pin of the slave SPI module. The master SPI simultaneously
transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin
regardless of the state of the data direction register of the shared I/O
port.
SPSCK (Se ria l
Cloc k)
The serial clock synchronizes data transmission between master and
slave devices. In a master MCU, the SPSCK pin is the clock output. In a
slave MCU, the SPSCK pin is the clock input. In full duplex operation,
the master and slave MCUs exchange a byte of data in eight serial clock
cycles.
When enabled, the SPI controls data direction of the SPSCK pin
regardless of the state of the data direction register of the shared I/O
port.
SS (Sla ve Se le c t)
The SS pin has various functions depending on the current state of the
SPI. For an SPI configured as a slave, the SS is used to select a slave.
For CPHA = 0, the SS is used to define the start of a transmission. (See
Transmission Formats.) Since it is used to indicate the start of a
transmission, the SS must be toggled high and low between each byte
transmitted for the CPHA = 0 format. However, it can remain low
throughout the transmission for the CPHA = 1 format. See Figure 10.
MISO/MOSI
MASTER SS
BYTE 1
BYTE 2
BYTE 3
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Figure 10. CPHA/SS Timing
When an SPI is configured as a slave, the SS pin is always configured
as an input. It cannot be used as a general-purpose I/O regardless of the
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Serial Peripheral Interface Module (SPI)
I/O Signals
state of the MODFEN control bit. However, the MODFEN bit can still
prevent the state of the SS from creating a MODF error. (See SPI Status
and Control Register on page 238).
NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK
clocks, even if a transmission already has begun.
When an SPI is configured as a master, the SS input can be used in
conjunction with the MODF flag to prevent multiple masters from driving
MOSI and SPSCK. (See Mode Fault Error on page 225). For the state
of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK
register must be set. If the MODFEN bit is low for an SPI master, the SS
pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. With MODFEN high, it is an
input-only pin to the SPI regardless of the state of the data direction
register of the shared I/O port.
The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the data register. (See Table 5).
Table 5. SPI Configuration
SPE SPMSTR MODFEN SPI Configuration
State of SS Logic
General-Purpose I/O;
SS Ignored by SPI
0
1
1
1
X
0
1
1
X
X
0
Not Enabled
Slave
Input-Only to SPI
General-Purpose I/O;
SS Ignored by SPI
Master without MODF
Master with MODF
1
Input-Only to SPI
X = don’t care
VSS (Cloc k
Ground )
VSS is the ground return for the serial clock pin, SPSCK, and the ground
for the port output buffers. To reduce the ground return path loop and
minimize radio frequency (RF) emissions, connect the ground pin of the
slave to the VSS pin.
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
I/ O Re g iste rs
Three registers control and monitor SPI operation:
• SPI control register (SPCR $0010)
• SPI status and control register (SPSCR $0011)
• SPI data register (SPDR $0012)
SPI Control
Re g iste r
The SPI control register:
• Enables SPI module interrupt requests
• Selects CPU interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
• Enables the SPI module
Address: $0010
Bit 7
6
5
4
3
2
1
SPE
0
Bit 0
SPTIE
0
Read:
Write:
Reset:
SPRIE
R
SPMSTR CPOL
CPHA SPWOM
0
0
1
0
1
0
R
=Reserved
Figure 11. SPI Control Register (SPCR)
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
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Serial Peripheral Interface Module (SPI)
I/O Registers
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin
between transmissions. (See Figure 3 and Figure 4.) To transmit
data between SPI modules, the SPI modules must have identical
CPOL bits. Reset clears the CPOL bit.
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial
clock and SPI data. (See Figure 3 and Figure 4.) To transmit data
between SPI modules, the SPI modules must have identical CPHA
bits. When CPHA = 0, the SS pin of the slave SPI module must be set
to logic 1 between bytes. (See Figure 10). Reset sets the CPHA bit.
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle
state and begin driving the MISO pin with the MSB of its data. Once
the transmission begins, no new data is allowed into the shift register
from the data register. Therefore, the slave data register must be
loaded with the desired transmit data before the falling edge of SS.
Any data written after the falling edge is stored in the data register and
transferred to the shift register at the current transmission.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the
beginning of the transmission. The same applies when SS is high for
a slave. The MISO pin is held in a high-impedance state, and the
incoming SPSCK is ignored. In certain cases, it may also cause the
MODF flag to be set. (See Mode Fault Error on page 225). A logic 1
on the SS pin does not in any way affect the state of the SPI state
machine.
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
SPWOM — SPI Wired-OR Mode Bit
This read/write bit disables the pullup devices on pins SPSCK, MOSI,
and MISO so that those pins become open-drain outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
SPE — SPI Enable Bit
This read/write bit enables the SPI module. Clearing SPE causes a
partial reset of the SPI (see Resetting the SPI on page 230). Reset
clears the SPE bit.
1 = SPI module enabled
0 = SPI module disabled
SPTIE — SPI Transmit Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
SPI Sta tus a nd
Control Re g iste r
The SPI status and control register contains flags to signal the following
conditions:
• Receive data register full
• Failure to clear SPRF bit before next byte is received (overflow
error)
• Inconsistent logic level on SS pin (mode fault error)
• Transmit data register empty
The SPI status and control register also contains bits that perform these
functions:
• Enable error interrupts
• Enable mode fault error detection
• Select master SPI baud rate
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Serial Peripheral Interface Module (SPI)
I/O Registers
Address: $0011
Bit 7
6
5
OVRF
R
4
MODF
R
3
SPTE
R
2
1
Bit 0
Read: SPRF
ERRIE
MODFEN SPR1
SPR0
0
Write:
R
0
Reset:
0
0
0
1
0
0
R
=Reserved
Figure 12. SPI Status and Control Register (SPSCR)
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from
the shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the
SPI status and control register with SPRF set and then reading the
SPI data register. Any read of the SPI data register clears the SPRF
bit.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error Interrupt Enable Bit
This read-only bit enables the MODF and OVRF flags to generate
CPU interrupt requests. Reset clears the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte
in the receive data register before the next byte enters the shift
register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the
OVRF bit by reading the SPI status and control register with OVRF set
and then reading the SPI data register. Reset clears the OVRF flag.
1 = Overflow
0 = No overflow
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
MODF — Mode Fault Bit
This clearable, read-only flag is set in a slave SPI if the SS pin goes
high during a transmission. In a master SPI, the MODF flag is set if
the SS pin goes low at any time. Clear the MODF bit by reading the
SPI status and control register with MODF set and then writing to the
SPI data register. Reset clears the MODF bit.
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
SPTE — SPI Transmitter Empty Bit
This clearable, read-only flag is set each time the transmit data
register transfers a byte into the shift register. SPTE generates an
SPTE CPU interrupt request if the SPTIE bit in the SPI control register
is set also.
NOTE: Do not write to the SPI data register unless the SPTE bit is high.
For an idle master or idle slave that has no data loaded into its
transmit buffer, the SPTE will be set again within two bus cycles since
the transmit buffer empties into the shift register. This allows the user
to queue up a 16-bit value to send. For an already active slave, the
load of the shift register cannot occur until the transmission is
completed. This implies that a back-to-back write to the transmit data
register is not possible. The SPTE indicates when the next write can
occur.
Reset sets the SPTE bit.
1 = Transmit data register empty
0 = Transmit data register not empty
MODFEN — Mode Fault Enable Bit
This read/write bit, when set to 1, allows the MODF flag to be set. If
the MODF flag is set, clearing the MODFEN does not clear the MODF
flag. If the SPI is enabled as a master and the MODFEN bit is low,
then the SS pin is available as a general-purpose I/O.
If the MODFEN bit is set, then this pin is not available as a general
purpose I/O. When the SPI is enabled as a slave, the SS pin is not
available as a general-purpose I/O regardless of the value of
MODFEN. (See SS (Slave Select) on page 234).
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Serial Peripheral Interface Module (SPI)
I/O Registers
If the MODFEN bit is low, the level of the SS pin does not affect the
operation of an enabled SPI configured as a master. For an enabled
SPI configured as a slave, having MODFEN low only prevents the
MODF flag from being set. It does not affect any other part of SPI
operation. (See Mode Fault Error on page 225).
SPR1 and SPR0 — SPI Baud Rate Select Bits
In master mode, these read/write bits select one of four baud rates as
shown in Table 6. SPR1 and SPR0 have no effect in slave mode.
Reset clears SPR1 and SPR0.
Table 6. SPI Master Baud Rate Selection
SPR1:SPR0
Baud Rate Divisor (BD)
00
01
10
11
2
8
32
128
Use this formula to calculate the SPI baud rate:
CGMOUT
Baud rate = --------------------------
2 × BD
where:
CGMOUT = base clock output of the clock generator module (CGM),
see Clock Generator Module (CGM) on page 105.
BD = baud rate divisor
SPI Da ta Re g iste r
The SPI data register is the read/write buffer for the receive data register
and the transmit data register. Writing to the SPI data register writes data
into the transmit data register. Reading the SPI data register reads data
from the receive data register. The transmit data and receive data
registers are separate buffers that can contain different values. See
Figure 1
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Se ria l Pe rip he ra l Inte rfa c e Mod ule (SPI)
Address: $0012
Bit 7
6
5
4
3
2
1
Bit 0
R0
Read:
Write:
Reset:
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
T0
Indeterminate after Reset
Figure 13. SPI Data Register (SPDR)
R7–R0/T7–T0 — Receive/Transmit Data Bits
NOTE: Do not use read-modify-write instructions on the SPI data register since
the buffer read is not the same as the buffer written.
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Tim e r Inte rfa c e Mod ule B (TIMB)
Tim e r Inte rfa c e Mod ule B (TIMB)
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
TIMB Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . 251
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . 252
PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
TIMB During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
TIMB Clock Pin (PTD4/TBLCK) . . . . . . . . . . . . . . . . . . . . . . . . . . 257
TIMB Channel I/O Pins (PTF5/TBCH1–PTF4/TBCH0). . . . . . . . . 257
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
TIMB Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . 258
TIMB Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
TIMB Counter Modulo Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 261
TIMB Channel Status and Control Registers . . . . . . . . . . . . . . . . 262
TIMB Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
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Tim e r Inte rfa c e Mod ule B (TIMB)
Introd uc tion
This section describes the timer interface module (TIMB). The TIMB is a
2-channel timer that provides a timing reference with input capture,
output compare, and pulse width modulation functions. Figure 1 is a
block diagram of the TIMB.
Fe a ture s
Features of the TIMB include:
• Two Input Capture/Output Compare Channels
– Rising-Edge, Falling-Edge, or Any-Edge Input Capture Trigger
– Set, Clear, or Toggle Output Compare Action
• Buffered and Unbuffered Pulse Width Modulation (PWM) Signal
Generation
• Programmable TIMB Clock Input
– 7-Frequency Internal Bus Clock Prescaler Selection
– External TIMB Clock Input (4-MHz Maximum Frequency)
• Free-Running or Modulo Up-Count Operation
• Toggle Any Channel Pin on Overflow
• TIMB Counter Stop and Reset Bits
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Timer Interface Module B (TIMB)
Features
TCLK
PTD4/TBLCK
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
TRST
PS2
PS1
PS0
16-BIT COUNTER
INTER-
RUPT
LOGIC
TOF
TOIE
16-BIT COMPARATOR
TMODH:TMODL
ELS0B
ELS0A
ELS1A
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
TOV0
CH0MAX
PTF4
LOGIC
PTF4/TBCH0
CH0F
MS0B
INTER-
RUPT
LOGIC
16-BIT LATCH
CH0IE
MS0A
ELS1B
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
TOV1
CH1MAX
PTF5
LOGIC
PTF5/TBCH1
CH1F
INTER-
RUPT
LOGIC
16-BIT LATCH
CH1IE
MS1A
Figure 1. TIMB Block Diagram
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Tim e r Inte rfa c e Mod ule B (TIMB)
Addr.
$0040
$0041
$0042
Register Name
Bit 7
6
5
4
3
0
2
PS2
10
2
1
PS1
9
Bit 0
PS0
TIMB Status/Control Register (TBSC) TOF
TIMB Counter Register High (TBCNTH) Bit 15
TIMB Counter Register Low (TBCNTL) Bit 7
TOIE TSTOP TRST
14
6
13
5
12
4
11
3
Bit 8
Bit 0
Bit 8
Bit 0
1
$0043 TIMB Counter Modulo Reg. High (TBMODH) Bit 15
$0044 TIMB Counter Modulo Reg. Low (TBMODL) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
$0045 TIMB Ch. 0 Status/Control Register (TBSC0) CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
$0046
$0047
TIMB Ch. 0 Register High (TBCH0H) Bit 15
TIMB Ch. 0 Register Low (TBCH0L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
$0048 TIMB Ch. 1 Status/Control Register (TBSC1) CH1F CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
$0049
$004A
TIMB Ch. 1 Register High (TBCH1H) Bit 15
TIMB Ch. 1 Register Low (TBCH1L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
R
=Reserved
Figure 2. TIMB I/O Register Summary
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Timer Interface Module B (TIMB)
Functional Description
Func tiona l De sc rip tion
Figure 1 shows the TIMB structure. The central component of the TIMB
is the 16-bit TIMB counter that can operate as a free-running counter or
a modulo up-counter. The TIMB counter provides the timing reference
for the input capture and output compare functions. The TIMB counter
modulo registers, TBMODH–TBMODL, control the modulo value of the
TIMB counter. Software can read the TIMB counter value at any time
without affecting the counting sequence.
The two TIMB channels are programmable independently as input
capture or output compare channels.
TIMB Counte r
Pre sc a le r
The TIMB clock source can be one of the seven prescaler outputs or the
TIMB clock pin, PTD4/TBLCK. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS[2:0], in
the TIMB status and control register select the TIMB clock source.
Inp ut Ca p ture
An input capture function has three basic parts: edge select logic, an
input capture latch, and a 16-bit counter. Two 8-bit registers, which make
up the 16-bit input capture register, are used to latch the value of the
free-running counter after the corresponding input capture edge detector
senses a defined transition. The polarity of the active edge is
programmable. The level transition which triggers the counter transfer is
defined by the corresponding input edge bits (ELSxB and ELSxA in
TBSC0 through TBSC1 control registers with x referring to the active
channel number). When an active edge occurs on the pin of an input
capture channel, the TIMB latches the contents of the TIMB counter into
the TIMB channel registers, TCHxH–TCHxL. Input captures can
generate TIMB CPU interrupt requests. Software can determine that an
input capture event has occurred by enabling input capture interrupts or
by polling the status flag bit.
The result obtained by an input capture will be two more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization.
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Tim e r Inte rfa c e Mod ule B (TIMB)
The free-running counter contents are transferred to the TIMB channel
status and control register (TBCHxH–TBCHxL, see TIMB Channel
Registers on page 266) on each proper signal transition regardless of
whether the TIMB channel flag (CH0F–CH1F in TBSC0–TBSC1
registers) is set or clear. When the status flag is set, a CPU interrupt is
generated if enabled. The value of the count latched or “captured” is the
time of the event. Because this value is stored in the input capture
register 2 bus cycles after the actual event occurs, user software can
respond to this event at a later time and determine the actual time of the
event. However, this must be done prior to another input capture on the
same pin; otherwise, the previous time value will be lost.
By recording the times for successive edges on an incoming signal,
software can determine the period and/or pulse width of the signal. To
measure a period, two successive edges of the same polarity are
captured. To measure a pulse width, two alternate polarity edges are
captured. Software should track the overflows at the 16-bit module
counter to extend its range.
Another use for the input capture function is to establish a time
reference. In this case, an input capture function is used in conjunction
with an output compare function. For example, to activate an output
signal a specified number of clock cycles after detecting an input event
(edge), use the input capture function to record the time at which the
edge occurred. A number corresponding to the desired delay is added to
this captured value and stored to an output compare register (see TIMB
Channel Registers on page 266). Because both input captures and
output compares are referenced to the same 16-bit modulo counter, the
delay can be controlled to the resolution of the counter independent of
software latencies.
Reset does not affect the contents of the input capture channel register
(TBCHxH–TBCHxL).
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Timer Interface Module B (TIMB)
Functional Description
Outp ut Com p a re
With the output compare function, the TIMB can generate a periodic
pulse with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIMB can set, clear, or toggle the channel pin. Output compares can
generate TIMB CPU interrupt requests.
Unb uffe re d
Outp ut Co m p a re
Any output compare channel can generate unbuffered output compare
pulses as described in Output Compare on page 249. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIMB channel registers.
An unsynchronized write to the TIMB channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIMB overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIMB may
pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
• When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
• When changing to a larger output compare value, enable channel
x TIMB overflow interrupts and write the new value in the TIMB
overflow interrupt routine. The TIMB overflow interrupt occurs at
the end of the current counter overflow period. Writing a larger
value in an output compare interrupt routine (at the end of the
current pulse) could cause two output compares to occur in the
same counter overflow period.
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Tim e r Inte rfa c e Mod ule B (TIMB)
Buffe re d Outp ut
Co m p a re
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the PTF5/TBCH1 pin. The TIMB
channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMB channel 0 status and control register
(TBSC0) links channel 0 and channel 1. The output compare value in the
TIMB channel 0 registers initially controls the output on the
PTE2/TACH0 pin. Writing to the TIMB channel 1 registers enables the
TIMB channel 1 registers to synchronously control the output after the
TIMB overflows. At each subsequent overflow, the TIMB channel
registers (0 or 1) that control the output are the ones written to last. TSC0
controls and monitors the buffered output compare function, and TIMB
channel 1 status and control register (TBSC1) is unused. While the
MS0B bit is set, the channel 1 pin, PTF4/TBCH0, is available as a
general-purpose I/O pin.
NOTE: Channels 2 and 3 and channels 4 and 5 can be linked to operate as
specified above.
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output
compares.
Pulse Wid th
By using the toggle-on-overflow feature with an output compare channel,
Mod ula tion (PWM)
the TIMB can generate a PWM signal. The value in the TIMB counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIMB counter
modulo registers. The time between overflows is the period of the PWM
signal.
As Figure 3 shows, the output compare value in the TIMB channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIMB to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIMB to set the pin if the state of the PWM
pulse is logic 0.
8-timb
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Timer Interface Module B (TIMB)
Functional Description
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 3. PWM Period and Pulse Width
The value in the TIMB counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIMB counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000 (see TIMB Status and Control Register).
The value in the TIMB channel registers determines the pulse width of
the PWM output. The pulse width of an 8-bit PWM signal is variable in
256 increments. Writing $0080 (128) to the TIMB channel registers
produces a duty cycle of 128/256 or 50%.
Unb uffe re d PWM
Sig na l Ge ne ra tio n
Any output compare channel can generate unbuffered PWM pulses as
described in Pulse Width Modulation (PWM) on page 250. The pulses
are unbuffered because changing the pulse width requires writing the
new pulse width value over the value currently in the TIMB channel
registers.
An unsynchronized write to the TIMB channel registers to change a
pulse width value could cause incorrect operation for up to two PWM
periods. For example, writing a new value before the counter reaches
the old value but after the counter reaches the new value prevents any
compare during that PWM period. Also, using a TIMB overflow interrupt
routine to write a new, smaller pulse width value may cause the compare
to be missed. The TIMB may pass the new value before it is written to
the TIMB channel registers.
9-timb
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Tim e r Inte rfa c e Mod ule B (TIMB)
Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
• When changing to a longer pulse width, enable channel x TIMB
overflow interrupts and write the new value in the TIMB overflow
interrupt routine. The TIMB overflow interrupt occurs at the end of
the current PWM period. Writing a larger value in an output
compare interrupt routine (at the end of the current pulse) could
cause two output compares to occur in the same PWM period.
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
Buffe re d PWM
Sig na l Ge ne ra tio n
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the PTF4/TBCH0 pin. The TIMB channel registers of
the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIMB channel 0 status and control register
(TBSC0) links channel 0 and channel 1. The TIMB channel 0 registers
initially control the pulse width on the PTF4/TBCH0 pin. Writing to the
TIMB channel 1 registers enables the TIMB channel 1 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMB channel registers (0 or
1) that control the pulse width are the ones written to last. TBSC0
controls and monitors the buffered PWM function, and TIMB channel 1
status and control register (TBSC1) is unused. While the MS0B bit is set,
the channel 1 pin, PTF5/TBCH1, is available as a general-purpose I/O
pin.
10-timb
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Timer Interface Module B (TIMB)
Functional Description
NOTE: In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
PWM Initia liza tio n
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
1. In the TIMB status and control register (TBSC):
a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP.
b. Reset the TIMB counter by setting the TIMB reset bit, TRST.
2. In the TIMB counter modulo registers (TBMODH–TBMODL), write
the value for the required PWM period.
3. In the TIMB channel x registers (TBCHxH–TBCHxL), write the
value for the required pulse width.
4. In TIMB channel x status and control register (TBSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the mode
select bits, MSxB–MSxA. (See Table 2).
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB–ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See Table 2.)
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIMB status control register (TBSC), clear the TIMB stop bit,
TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMB channel 0 registers (TBCH0H–TBCH0L)
initially control the buffered PWM output. TIMB status control register 0
11-timb
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Tim e r Inte rfa c e Mod ule B (TIMB)
(TBSC0) controls and monitors the PWM signal from the linked
channels. MS0B takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on
TIMB overflows. Subsequent output compares try to force the output to
a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. (See TIMB Channel
Status and Control Registers on page 262.)
Inte rrup ts
The following TIMB sources can generate interrupt requests:
• TIMB overflow flag (TOF) — The TOF bit is set when the TIMB
counter value rolls over to $0000 after matching the value in the
TIMB counter modulo registers. The TIMB overflow interrupt
enable bit, TOIE, enables TIMB overflow CPU interrupt requests.
TOF and TOIE are in the TIMB status and control register.
• TIMB channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIMB CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
12-timb
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Timer Interface Module B (TIMB)
Low-Power Modes
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
Wa it Mod e
The TIMB remains active after the execution of a WAIT instruction. In
wait mode, the TIMB registers are not accessible by the CPU. Any
enabled CPU interrupt request from the TIMB can bring the MCU out of
wait mode.
If TIMB functions are not required during wait mode, reduce power
consumption by stopping the TIMB before executing the WAIT
instruction.
Stop Mod e
The TIMB is inactive after the execution of a STOP instruction. The
STOP instruction does not affect register conditions or the state of the
TIMB counter. TIMB operation resumes when the MCU exits stop mode.
13-timb
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Tim e r Inte rfa c e Mod ule B (TIMB)
TIMB During Bre a k Inte rrup ts
A break interrupt stops the TIMB counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See SIM Break Flag Control
Register on page 103).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
14-timb
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Timer Interface Module B (TIMB)
I/O Signals
I/ O Sig na ls
Port D shares one of its pins with the TIMB. Port F shares two of its pins
with the TIMB. PTD4/TBLCK is an external clock input to the TIMB
prescaler. The two TIMB channel I/O pins are PTF4/TBCH0 and
PTF5/TBCH1.
TIMB Cloc k Pin
(PTD4/ TBLCK)
PTD4/TBLCK is an external clock input that can be the clock source for
the TIMB counter instead of the prescaled internal bus clock. Select the
PTD4/TBLCK input by writing logic 1s to the three prescaler select bits,
PS[2:0]. (See TIMB Status and Control Register.) The minimum TCLK
pulse width, TCLKLMIN or TCLKHMIN, is:
1
------------------------------------- + t SU
bus frequency
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD4/TBLCK is available as a general-purpose I/O pin or ADC channel
when not used as the TIMB clock input. When the PTD6/TACLK pin is
the TIMB clock input, it is an input regardless of the state of the DDRD6
bit in data direction register D.
TIMB Cha nne l I/ O
Pins
(PTF5/ TBCH1–PTF4/
TBCH0)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTF4/TBCH0 and PTF5/TBCH1
can be configured as buffered output compare or buffered PWM pins.
15-timb
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Tim e r Inte rfa c e Mod ule B (TIMB)
I/ O Re g iste rs
These I/O registers control and monitor TIMB operation:
• TIMB status and control register (TBSC)
• TIMB control registers (TBCNTH–TBCNTL)
• TIMB counter modulo registers (TBMODH–TBMODL)
• TIMB channel status and control registers (TBSC0 and TBSC1)
• TIMB channel registers (TBCH0H–TBCH0L, TBCH1H–TBCH1L)
TIMB Sta tus a nd
Control Re g iste r
The TIMB status and control register:
• Enables TIMB overflow interrupts
• Flags TIMB overflows
• Stops the TIMB counter
• Resets the TIMB counter
• Prescales the TIMB counter clock
Address: $0040
Bit 7
TOF
0
6
5
TSTOP
1
4
0
3
0
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
Write:
Reset:
TOIE
TRST
0
R
0
0
0
R
=Reserved
Figure 4. TIMB Status and Control Register (TBSC)
TOF — TIMB Overflow Flag Bit
This read/write flag is set when the TIMB counter resets to $0000 after
reaching the modulo value programmed in the TIMB counter modulo
registers. Clear TOF by reading the TIMB status and control register
when TOF is set and then writing a logic 0 to TOF. If another TIMB
overflow occurs before the clearing sequence is complete, then
16-timb
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Timer Interface Module B (TIMB)
I/O Registers
writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset
clears the TOF bit. Writing a logic 1 to TOF has no effect.
1 = TIMB counter has reached modulo value
0 = TIMB counter has not reached modulo value
TOIE — TIMB Overflow Interrupt Enable Bit
This read/write bit enables TIMB overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIMB overflow interrupts enabled
0 = TIMB overflow interrupts disabled
TSTOP — TIMB Stop Bit
This read/write bit stops the TIMB counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMB
counter until software clears the TSTOP bit.
1 = TIMB counter stopped
0 = TIMB counter active
NOTE: Do not set the TSTOP bit before entering wait mode if the TIMB is
required to exit wait mode. Also, when the TSTOP bit is set and the timer
is configured for input capture operation, input captures are inhibited
until TSTOP is cleared.
TRST — TIMB Reset Bit
Setting this write-only bit resets the TIMB counter and the TIMB
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIMB counter is reset and always reads as logic 0. Reset clears
the TRST bit.
1 = Prescaler and TIMB counter cleared
0 = No effect
NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIMB
counter at a value of $0000.
17-timb
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Tim e r Inte rfa c e Mod ule B (TIMB)
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTD4/TBLCK pin or one of the
seven prescaler outputs as the input to the TIMB counter as Table 1
shows. Reset clears the PS[2:0] bits.
Table 1. Prescaler Selection
PS[2:0]
000
001
010
011
TIMB Clock Source
Internal Bus Clock ÷1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
PTD4/TBLCK
100
101
110
111
TIMB Counte r
Re g iste rs
The two read-only TIMB counter registers contain the high and low bytes
of the value in the TIMB counter. Reading the high byte (TBCNTH)
latches the contents of the low byte (TBCNTL) into a buffer. Subsequent
reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL
is read. Reset clears the TIMB counter registers. Setting the TIMB reset
bit (TRST) also clears the TIMB counter registers.
NOTE: If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL
by reading TBCNTL before exiting the break interrupt. Otherwise,
TBCNTL retains the value latched during the break.
Register Name and Address TBCNTH — $0041
Bit 7
6
BIT 14
R
5
BIT 13
R
4
BIT 12
R
3
BIT 11
R
2
BIT 10
R
1
BIT 9
R
Bit 0
BIT 8
R
Read: BIT 15
Write:
R
0
Reset:
0
0
0
0
0
0
0
Figure 5. TIMB Counter Registers (TBCNTH and TBCNTL)
18-timb
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Timer Interface Module B (TIMB)
I/O Registers
Register Name and Address TBCNTL — $0042
Bit 7
6
BIT 6
R
5
BIT 5
R
4
BIT 4
R
3
BIT 3
R
2
BIT 2
R
1
Bit 0
Read: BIT 7
BIT 1
R
BIT 0
R
Write:
R
0
Reset:
0
0
0
0
0
0
0
R
R =Reserved
Figure 5. TIMB Counter Registers (TBCNTH and TBCNTL)
TIMB Counte r
Mod ulo Re giste rs
The read/write TIMB modulo registers contain the modulo value for the
TIMB counter. When the TIMB counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIMB counter resumes
counting from $0000 at the next clock. Writing to the high byte (TMODH)
inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is
written. Reset sets the TIMB counter modulo registers.
Register Name and Address TBMODH — $0043
Bit 7
BIT 15
1
6
BIT 14
1
5
BIT 13
1
4
BIT 12
1
3
BIT 11
1
2
BIT 10
1
1
BIT 9
1
Bit 0
BIT 8
1
Read:
Write:
Reset:
Register Name and Address TBMODL — $0044
Bit 7
BIT 7
1
6
BIT 6
1
5
BIT 5
1
4
BIT 4
1
3
BIT 3
1
2
BIT 2
1
1
BIT 1
1
Bit 0
BIT 0
1
Read:
Write:
Reset:
Figure 6. TIMB Counter Modulo Registers (TMODH and TMODL)
NOTE: Reset the TIMB counter before writing to the TIMB counter modulo
registers.
19-timb
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Tim e r Inte rfa c e Mod ule B (TIMB)
TIMB Cha nne l
Sta tus a nd Control
Re g iste rs
Each of the TIMB channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input
capture trigger
• Selects output toggling on TIMB overflow
• Selects 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Register Name and Address TBSC0 — $0045
Bit 7
6
CH0IE
0
5
MS0B
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Read: CH0F
Write:
0
0
Reset:
Register Name and Address TBSC1 — $0048
Bit 7
6
5
0
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Read: CH1F
CH1IE
Write:
0
0
R
0
Reset:
0
R
R =Reserved
Figure 7. TIMB Channel Status
and Control Registers (TBSC0–TBSC1)
20-timb
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Timer Interface Module B (TIMB)
I/O Registers
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIMB
counter registers matches the value in the TIMB channel x registers.
When CHxIE = 0, clear CHxF by reading TIMB channel x status and
control register with CHxF set, and then writing a logic 0 to CHxF. If
another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMB CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIMB channel 0.
Setting MS0B disables the channel 1 status and control register and
reverts TBCH1 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
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Tim e r Inte rfa c e Mod ule B (TIMB)
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation. (See Table
2).
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin once PWM, input capture, or output compare
operation is enabled. (See Table 2). Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE: Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIMB status and control register
(TBSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port E or port F, and pin PTEx/TBCHx or pin PTFx/TBCHx is
available as a general-purpose I/O pin. However, channel x is at a
state determined by these bits and becomes transparent to the
respective pin when PWM, input capture, or output compare mode is
enabled. Table 2 shows how ELSxB and ELSxA work. Reset clears
the ELSxB and ELSxA bits.
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Timer Interface Module B (TIMB)
I/O Registers
Table 2. Mode, Edge, and Level Selection
MSxB:MSxA ELSxB:ELSxA
Mode
Configuration
Pin under Port Control;
Initialize Timer
Output Level High
X0
X1
00
00
Output
Preset
Pin under Port Control;
Initialize Timer
Output Level Low
00
00
00
01
01
01
1X
1X
01
10
11
01
10
11
01
10
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Toggle Output on Compare
Input
Capture
Output
Compare Clear Output on Compare
or PWM
Set Output on Compare
Buffered
Output
Compare
orBuffered
PWM
Toggle Output on Compare
Clear Output on Compare
1X
11
Set Output on Compare
NOTE: Before enabling a TIMB channel register for input capture operation,
make sure that the PTFx/TBCHx pin is stable for at least two bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIMB counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIMB counter overflow.
0 = Channel x pin does not toggle on TIMB counter overflow.
NOTE: When TOVx is set, a TIMB counter overflow takes precedence over a
channel x output compare if both occur at the same time.
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Tim e r Inte rfa c e Mod ule B (TIMB)
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 0, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 8 shows, the CHxMAX bit takes effect in the cycle after it is set
or cleared. The output stays at the 100% duty cycle level until the
cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTEx/TCHx
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 8. CHxMAX Latency
TIMB Cha nne l
Re g iste rs
These read/write registers contain the captured TIMB counter value of
the input capture function or the output compare value of the output
compare function. The state of the TIMB channel registers after reset is
unknown.
In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the
TIMB channel x registers (TBCHxH) inhibits input captures until the low
byte (TBCHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0), writing to the high byte of
the TIMB channel x registers (TBCHxH) inhibits output compares and
the CHxF bit until the low byte (TBCHxL) is written.
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Timer Interface Module B (TIMB)
I/O Registers
Register Name and Address TBCH0H — $0046
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Indeterminate after Reset
Register Name and Address TBCH0L — $0047
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Register Name and Address TBCH1H — $0049
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after Reset
Register Name and Address TBCH1L — $004A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Figure 9. TIMB Channel Registers
(TBCH0H/L–TBCH1H/L)
MC68HC08AZ60 — Rev 1.0
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Tim e r Inte rfa c e Mod ule B (TIMB)
MC68HC08AZ60 — Rev 1.0
268
Timer Interface Module B (TIMB)
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Mod ulo Tim e r (TIM)
Mod ulo Tim e r (TIM)
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
TIM Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . 274
TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
TIM Counter Modulo Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Introd uc tion
This section describes the modulo timer which is a periodic interrupt
timer whose counter is clocked internally via software programmable
options. Figure 1 is a block diagram of the TIM.
1-tim
MC68HC08AZ60 — Rev 1.0
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Modulo Timer (TIM)
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Mod ulo Tim e r (TIM)
Fe a ture s
Features of the TIM include:
• Programmable TIM Clock Input
• Free-Running or Modulo Up-Count Operation
• TIM Counter Stop and Reset Bits
Func tiona l De sc rip tion
Figure 1 shows the structure of the TIM. The central component of the
TIM is the 16-bit TIM counter that can operate as a free-running counter
or a modulo up-counter. The counter provides the timing reference for
the interrupt. The TIM counter modulo registers, TMODH–TMODL,
control the modulo value of the counter. Software can read the counter
value at any time without affecting the counting sequence.
2-tim
MC68HC08AZ60 — Rev 1.0
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Modulo Timer (TIM)
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Modulo Timer (TIM)
Functional Description
PRESCALER SELECT
PRESCALER
INTERNAL
BUS CLOCK
CSTOP
CRST
PS2
PS1
PS0
16-BIT COUNTER
INTER-
RUPT
LOGIC
TOF
TOIE
16-BIT COMPARATOR
TIMTMODH:TIMTMODL
Figure 1. TIM Block Diagram
Register Name
Bit 7
TOF
0
6
5
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
0
TOIE
TSTOP
PS2
PS1
PS0
TIM Status and Control Register
(TSC)
TRST
0
0
0
1
0
0
0
9
0
Read: Bit 15
Write:
14
13
12
11
10
Bit 8
TIM Counter Register High
(TCNTH)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 7
Bit 0
TIM Counter Register Low
(TCNTL)
0
Bit 15
1
0
14
1
0
13
1
0
12
1
0
11
1
0
10
1
0
9
1
1
1
0
Bit 8
1
TIM Counter Modulo Register High
(TMODH)
Bit 7
1
6
5
4
3
2
Bit 0
1
TIM Counter Modulo Register Low
(TMODL)
1
1
1
1
1
=Unimplemented
Figure 2. TIM I/O Register Summary
Table 1. TIM I/O Register Address Summary
Register
TSC
TCNTH TCNTL TMODH TMODL
$004C $004D $004E $004F
Address $004B
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Mod ulo Tim e r (TIM)
TIM Counte r Pre sc a le r
The clock source can be one of the seven prescaler outputs. The
prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the status and control register select the
TIM clock source.
The value in the TIM counter modulo registers and the selected
prescaler output determines the frequency of the periodic interrupt. The
TIM overflow flag (TOF) is set when the TIM counter value rolls over to
$0000 after matching the value in the TIM counter modulo registers. The
TIM interrupt enable bit, TOIE, enables TIM overflow CPU interrupt
requests. TOF and TOIE are in the TIM status and control register.
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low power-consump-
tion standby modes.
Wa it Mod e
The TIM remains active after the execution of a WAIT instruction. In wait
mode the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
Stop Mod e
The TIM is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the TIM
counter. TIM operation resumes when the MCU exits stop mode after an
external interrupt.
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MC68HC08AZ60 — Rev 1.0
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Modulo Timer (TIM)
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Modulo Timer (TIM)
TIM During Break Interrupts
TIM During Bre a k Inte rrup ts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See SIM Break Flag Control
Register on page 103).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
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Mod ulo Tim e r (TIM)
I/ O Re g iste rs
The following I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM counter registers (TCNTH–TCNTL)
• TIM counter modulo registers (TMODH–TMODL)
TIM Sta tus a nd
The TIM status and control register:
Control Re g iste r
• Enables TIM interrupt
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
Address: $004B
Bit 7
TOF
0
6
TOIE
0
5
TSTOP
1
4
0
3
0
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
Write:
Reset:
TRST
0
0
0
= Unimplemented
Figure 3. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter resets to $0000 after
reaching the modulo value programmed in the TIM counter modulo
registers. Clear TOF by reading the TIM status and control register
when TOF is set and then writing a logic 0 to TOF. If another TIM
overflow occurs before the clearing sequence is complete, then
writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset
clears the TOF bit. Writing a logic 1 to TOF has no effect.
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Modulo Timer (TIM)
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Modulo Timer (TIM)
I/O Registers
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM
counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIM counter is reset and always reads as logic zero. Reset clears
the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIM counter
at a value of $0000.
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Mod ulo Tim e r (TIM)
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the
input to the TIM counter as Table 2 shows. Reset clears the PS[2:0]
bits.
Table 2. Prescaler Selection
PS[2:0]
000
001
010
TIM Clock Source
Internal Bus Clock ÷1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
Internal Bus Clock ÷ 64
011
100
101
110
111
TIM Counte r
Re g iste rs
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address: $004C
Bit 7
Read: Bit 15
Write:
6
5
4
3
2
1
9
Bit 0
Bit 8
14
13
12
11
10
Reset:
0
0
0
0
0
0
0
0
Figure 4. TIM Counter Registers (TCNTH–TCNTL)
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Modulo Timer (TIM)
I/O Registers
Address: $004D
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit 8
Read: Bit 15
Write:
14
13
12
11
10
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 4. TIM Counter Registers (TCNTH–TCNTL)
TIM Counte r
Mod ulo Re giste rs
The read/write TIM modulo registers contain the modulo value for the
TIM counter. When the TIM counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next clock. Writing to the high byte (TMODH) inhibits
the TOF bit and overflow interrupts until the low byte (TMODL) is written.
Reset sets the TIM counter modulo registers.
Address: $004E:$004F
Bit 7
Bit 15
1
6
14
1
5
13
1
4
12
1
3
11
1
2
10
1
1
9
1
Bit 0
Bit 8
1
Read:
Write:
Reset:
Address: $004E:$004F
Bit 7
6
6
1
5
5
1
4
4
1
3
3
1
2
2
1
1
1
1
Bit 0
Bit 0
1
Read:
Bit 7
Write:
Reset:
1
Figure 5. TIM Counter Modulo Registers (TMODH–TMODL)
NOTE: Reset the TIM counter before writing to the TIM counter modulo registers.
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Mod ulo Tim e r (TIM)
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I/ O Ports
I/ O Ports
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Port A Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Port B Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Port C Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Port D Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Port E Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Port G Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Data Direction Register G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Port H Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Data Direction Register H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
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I/ O Ports
Introd uc tion
Fifty bidirectional input/output (I/O) form seven parallel ports. All I/O pins
are programmable as inputs or outputs.
NOTE: Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
PTA0
PTB0
PTC0
PTD0
Port A Data Register (PTA) PTA7
Port B Data Register (PTB) PTB7
PTA6
PTB6
0
PTA5
PTB5
PTC5
PTD5
PTA4
PTB4
PTC4
PTD4
PTA3
PTB3
PTC3
PTD3
PTA2
PTB2
PTC2
PTD2
PTA1
PTB1
PTC1
PTD1
Port C Data Register (PTC)
0
Port D Data Register (PTD) PTD7
PTD6
Data Direction Register A (DDRA) DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Data Direction Register B (DDRB) DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Data Direction Register C (DDRC) MCLKEN
0
DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Data Direction Register D (DDRD) DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Port E Data Register (PTE) PTE7
PTE6
PTF6
0
PTE5
PTF5
0
PTE4
PTF4
0
PTE3
PTF3
0
PTE2
PTF2
PTG2
0
PTE1
PTF1
PTG1
PTH1
PTE0
PTF0
PTG0
PTH0
Port F Data Register (PTF)
Port G Data Register (PTG)
Port H Data Register (PTH)
0
0
0
0
0
0
0
Data Direction Register E (DDRE) DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
Data Direction Register F (DDRF)
Data Direction Register G (DDRG)
Data Direction Register H (DDRH)
0
0
0
DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
0
0
0
0
0
0
0
0
DDRG2 DDRG1 DDRG0
0
DDRH1‘ DDRH0
Figure 1. CAN Protocol I/O Port Register Summary
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I/O Ports
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I/O Ports
Port A
Port A
Port A is an 8-bit general-purpose bidirectional I/O port.
Port A Da ta
Re g iste r
The port A data register contains a data latch for each of the eight
port A pins.
Address: $0000
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Unaffected by Reset
Figure 2. Port A Data Register (PTA)
PTA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
Da ta Dire c tion
Re g iste r A
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for
the corresponding port A pin; a logic 0 disables the output buffer.
Address: $0004
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
0
0
0
0
0
0
0
0
Figure 3. Data Direction Register A (DDRA)
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I/ O Ports
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
DDRAx
RESET
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)
Figure 4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 1 summarizes the
operation of the port A pins.
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I/O Ports
Port B
Table 1. Port A Pin Functions
Accesses
Accesses to PTA
DDRA
Bit
PTA
Bit
I/O Pin
Mode
to DDRA
Read/Write
DDRA[7:0]
DDRA[7:0]
Read
Pin
Write
0
X
X
Input, Hi-Z
Output
PTA[7:0](1)
PTA[7:0]
1
PTA[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Port B
Port B is an 8-bit special function port that shares all of its pins with the
analog-to-digital converter.
Port B Da ta
Re g iste r
The port B data register contains a data latch for each of the eight port
B pins.
Address: $0001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Unaffected by Reset
ATD4 ATD3
Alternate
Functions:
ATD7
ATD6
ATD5
ATD2
ATD1
ATD0
Figure 5. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
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ATD[7:0] — ADC Channels
PTB7/ATD7–PTB0/ATD0 are eight of the analog-to-digital converter
channels. The ADC channel select bits, CH[4:0], determine whether
the PTB7/ATD7–PTB0/ATD0 pins are ADC channels or
general-purpose I/O pins. If an ADC channel is selected and a read of
this corresponding bit in the port B data register occurs, the data will
be 0 if the data direction for this bit is programmed as an input.
Otherwise, the data will reflect the value in the data latch. (See
Analog-to-Digital Converter (ADC-15) on page 395). Data direction
register B (DDRB) does not affect the data direction of port B pins that
are being used by the ADC. However, the DDRB bits always
determine whether reading port B returns to the states of the latches
or logic 0.
Da ta Dire c tion
Re g iste r B
Data direction register B determines whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for
the corresponding port B pin; a logic 0 disables the output buffer.
Address: $0005
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
0
0
0
0
0
0
0
0
Figure 6. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 7 shows the port B I/O logic.
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Port B
READ DDRB ($0005)
WRITE DDRB ($0005)
DDRBx
RESET
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
Figure 7. Port B I/O Circuit
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx
data latch. When bit DDRBx is a logic 0, reading address $0001 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 2 summarizes the
operation of the port B pins.
Table 2. Port B Pin Functions
Accesses
Accesses to PTB
DDRB
Bit
PTB
Bit
I/O Pin
Mode
to DDRB
Read/Write
DDRB[7:0]
DDRB[7:0]
Read
Pin
Write
0
X
X
Input, Hi-Z
Output
PTB[7:0](1)
PTB[7:0]
1
PTB[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
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Port C
Port C is an 6-bit general-purpose bidirectional I/O port.
Port C Da ta
Re g iste r
The port C data register contains a data latch for each of the six port C
pins.
Address: $0002
Bit 7
0
6
0
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
R
R
Unaffected by Reset
R
=Reserved
Alternate
Functions:
MCLK
Figure 8. Port C Data Register (PTC)
PTC[5:0] — Port C Data Bits
These read/write bits are software-programmable. Data direction of
each port C pin is under the control of the corresponding bit in data
direction register C. Reset has no effect on port C data (5:0).
MCLK — T12 System Clock Bit
The system clock is driven out of PTC2 when enabled by MCLKEN bit
in PTCDDR7.
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Port C
Da ta Dire c tion
Re g iste r C
Data direction register C determines whether each port C pin is an input
or an output. Writing a logic 1 to a DDRC bit enables the output buffer
for the corresponding port C pin; a logic 0 disables the output buffer.
Address: $0006
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
0
MCLKEN
DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
R
0
0
0
0
0
0
0
0
R
=Reserved
Figure 9. Data Direction Register C (DDRC)
MCLKEN — MCLK Enable Bit
This read/write bit enables MCLK to be an output signal on PTC2. If
MCLK is enabled, DDRC2 has no effect. Reset clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
DDRC[5:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE: Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 10 shows the port C I/O logic.
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READ DDRC ($0006)
WRITE DDRC ($0006)
DDRCx
RESET
WRITE PTC ($0002)
PTCx
PTCx
READ PTC ($0002)
Figure 10. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx
data latch. When bit DDRCx is a logic 0, reading address $0002 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 3 summarizes the
operation of the port C pins.
Table 3. Port C Pin Functions
Accesses
Accesses to PTC
Bit
PTC
Bit
I/O Pin
Mode
to DDRC
Read/Write
DDRC[2]
Value
Read
Pin
Write
PTC2
0
2
2
Input, Hi-Z
Output
1
DDRC[2]
0
—
0
X
X
Input, Hi-Z
Output
DDRC[5:0]
DDRC[5:0]
Pin
PTC[5:0](1)
PTC[5:0]
1
PTC[5:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
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Port D
Port D
Port D is an 8-bit general-purpose I/O port.
Port D Da ta
Re g iste r
Port D is a 8-bit special function port that shares seven of its pins with
the analog to digital converter and two with the timer interface
modules.
Address: $0003
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Unaffected by Reset
Alternate
Functions:
ATD14/
TACLK
ATD12/
ATD11
TBCLK
R
ATD13
ATD10
ATD9
ATD8
Figure 11. Port D Data Register (PTD)
PTD[7:0] — Port D Data Bits
PTD[7:0] are read/write, software programmable bits. Data direction
of PTD[7:0] pins are under the control of the corresponding bit in data
direction register D.
ATD[14:8] — ADC Channel Status Bits
PTD6/ATD14/TACLK–PTD0/ATD8 are seven of the 15 analog-to-
digital converter channels. The ADC channel select bits, CH[4:0],
determine whether the PTD6/ATD14/TACLK–PTD0/ATD8 pins are
ADC channels or general-purpose I/O pins. If an ADC channel is
selected and a read of this corresponding bit in the port B data register
occurs, the data will be 0 if the data direction for this bit is
programmed as an input. Otherwise, the data will reflect the value in
the data latch. (See Analog-to-Digital Converter (ADC-15) on page
395).
Data direction register D (DDRD) does not affect the data direction of
port D pins that are being used by the TIMA or TIMB. However, the
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DDRD bits always determine whether reading port D returns the states
of the latches or logic 0.
TACLK/TBCLK — Timer Clock Input Bit
The PTD6/TACLK pin is the external clock input for the TIMA. The
PTD4/TBLCK pin is the external clock input for the TIMB. The
prescaler select bits, PS[2:0], select PTD6/TACLK or PTD4/TBLCK
as the TIM clock input. (See TIMA Channel Status and Control
Registers on page 384 and TIMB Channel Status and Control
Registers on page 262). When not selected as the TIM clock,
PTD6/TACLKand PTD4/TBLCKare available for general-purpose I/O.
While TACLK/TBCLK are selected corresponding DDRD bits have no
effect.
Da ta Dire c tion
Re g iste r D
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic 0 disables the output buffer.
Address: $0007
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
0
0
0
0
0
0
0
0
Figure 12. Data Direction Register D (DDRD)
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 13 shows the port D I/O logic.
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Port D
READ DDRD ($0007)
WRITE DDRD ($0007)
DDRDx
RESET
WRITE PTD ($0003)
PTDx
PTDx
READ PTD ($0003)
Figure 13. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic 0, reading address $0003 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 4 summarizes the
operation of the port D pins.
Table 4. Port D Pin Functions
Accesses to
Accesses to PTD
DDRD PTD
I/O Pin
Mode
DDRD
Bit
Bit
Read/Write
DDRD[7:0]
DDRD[7:0]
Read
Pin
Write
PTD[7:0](1)
0
1
X
X
Input, Hi-Z
Output
PTD[7:0]
PTD[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
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Port E
Port E is an 8-bit special function port that shares two of its pins with the
timer interface module (TIMA), two of its pins with the serial
communications interface module (SCI), and four of its pins with the
serial peripheral interface module (SPI).
Port E Da ta
Re g iste r
The port E data register contains a data latch for each of the eight port
E pins.
Address: $0008
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTE7
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
Unaffected by Reset
SS TACH1
Alternate
Function:
SPSCK
MOSI
MISO
TACH0
RxD
TxD
Figure 14. Port E Data Register (PTE)
PTE[7:0] — Port E Data Bits
PTE[7:0] are read/write, software programmable bits. Data direction
of each port E pin is under the control of the corresponding bit in data
direction register E.
SPSCK — SPI Serial Clock Bit
The PTE7/SPSCK pin is the serial clock input of an SPI slave module
and serial clock output of an SPI master module. When the SPE bit is
clear, the PTE7/SPSCK pin is available for general-purpose I/O. (See
SPI Control Register on page 236).
MOSI — Master Out/Slave In Bit
The PTE6/MOSI pin is the master out/slave in terminal of the SPI
module. When the SPE bit is clear, the PTE6/MOSI pin is available for
general-purpose I/O.
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Port E
MISO — Master In/Slave Out Bit
The PTE5/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTE5/MISO pin is available for general-purpose
I/O. (See SPI Control Register on page 236).
SS — Slave Select Bit
The PTE4/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set and
MODFEN bit is low, the PTE4/SS pin is available for general-purpose
I/O. (See SS (Slave Select) on page 234). When the SPI is enabled
as a slave, the DDRF0 bit in data direction register E (DDRE) has no
effect on the PTE4/SS pin.
NOTE: Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SPI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 5).
TACH[1:0] — Timer Channel I/O Bits
The PTE3/TACH1–PTE2/TACH0 pins are the TIM input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0
pins are timer channel I/O pins or general-purpose I/O pins. (See
TIMA Channel Status and Control Registers on page 384).
NOTE: Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the TIM. However, the DDRE bits
always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 5).
RxD — SCI Receive Data Input Bit
The PTE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and
the PTE1/RxD pin is available for general-purpose I/O. (See SCI
Control Register 1 on page 194).
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TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O. (See SCI
Control Register 1 on page 194).
NOTE: Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SCI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 5).
Da ta Dire c tion
Re g iste r E
Data direction register E determines whether each port E pin is an input
or an output. Writing a logic 1 to a DDRE bit enables the output buffer for
the corresponding port E pin; a logic 0 disables the output buffer.
Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
0
0
0
0
0
0
0
0
Figure 15. Data Direction Register E (DDRE)
DDRE[7:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE[7:0], configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE: Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 16 shows the port E I/O logic.
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Port E
READ DDRE ($000C)
WRITE DDRE ($000C)
DDREx
RESET
WRITE PTE ($0008)
PTEx
PTEx
READ PTE ($0008)
Figure 16. Port E I/O Circuit
When bit DDREx is a logic 1, reading address $0008 reads the PTEx
data latch. When bit DDREx is a logic 0, reading address $0008 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 5 summarizes the
operation of the port E pins.
Table 5. Port E Pin Functions
Accesses
Accesses to PTE
DDRE
Bit
PTE
Bit
I/O Pin
Mode
to DDRE
Read/Write
DDRE[7:0]
DDRE[7:0]
Read
Pin
Write
0
X
X
Input, Hi-Z
Output
PTE[7:0](1)
PTE[7:0]
1
PTE[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
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Port F
Port F is a 7-bit special function port that shares four of its pins with the
timer interface module (TIMA-6) and two of its pins with the timer
interface module (TIMB).
Port F Da ta
Re g iste r
The port F data register contains a data latch for each of the seven port
F pins.
Address: $0009
Bit 7
0
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTF6
PTF5
PTF4
PTF3
PTF2
PTF1
PTF0
R
Unaffected by Reset
TBCH0 TACH5
Alternate
Function:
TBCH1
TACH4
TACH3
TACH2
R
=Reserved
Figure 17. Port F Data Register (PTF)
PTF[6:0] — Port F Data Bits
These read/write bits are software programmable. Data direction of
each port F pin is under the control of the corresponding bit in data
direction register F. Reset has no effect on PTF[6:0].
TACH[5:2] — Timer A Channel I/O Bits
The PTF3–PTF0/TACH2 pins are the TIM input capture/output
compare pins. The edge/level select bits, ELSxB:ELSxA, determine
whether the PTF3–PTF0/TACH2 pins are timer channel I/O pins or
general-purpose I/O pins. (See TIMA Status and Control Register
on page 380).
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Port F
TBCH[1:0] — Timer B Channel I/O Bits
The PTF5/TBCH1–PTF4/TBCH0 pins are the TIMB input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTF5/TBCH1–PTF4/TBCH0
pins are timer channel I/O pins or general-purpose I/O pins. (See TIM
Status and Control Register on page 274).
NOTE: Data direction register F (DDRF) does not affect the data direction of port
F pins that are being used by the TIM. However, the DDRF bits always
determine whether reading port F returns the states of the latches or the
states of the pins. (See Table 6).
Da ta Dire c tion
Re g iste r F
Data direction register F determines whether each port F pin is an input
or an output. Writing a logic 1 to a DDRF bit enables the output buffer for
the corresponding port F pin; a logic 0 disables the output buffer.
Address: $000D
Bit 7
0
6
5
DDRF5
0
4
DDRF4
0
3
DDRF3
0
2
DDRF2
0
1
DDRF1
0
Bit 0
DDRF0
0
Read:
Write:
Reset:
DDRF6
R
0
0
R
=Reserved
Figure 18. Data Direction Register F (DDRF)
DDRF[6:0] — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears
DDRF[6:0], configuring all port F pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE: Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 19 shows the port F I/O logic.
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READ DDRF ($000D)
WRITE DDRF ($000D)
DDRFx
RESET
WRITE PTF ($0009)
PTFx
PTFx
READ PTF ($0009)
Figure 19. Port F I/O Circuit
When bit DDRFx is a logic 1, reading address $0009 reads the PTFx
data latch. When bit DDRFx is a logic 0, reading address $0009 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 6 summarizes the
operation of the port F pins.
Table 6. Port F Pin Functions
Accesses
Accesses to PTF
DDRF
Bit
PTF
Bit
I/O Pin
Mode
to DDRF
Read/Write
DDRF[6:0]
DDRF[6:0]
Read
Pin
Write
0
X
X
Input, Hi-Z
Output
PTF[6:0](1)
PTF[6:0]
1
PTF[6:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
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Port G
Port G
Port G is a 3-bit special function port that shares all of its pins with the
keyboard interrupt module (KBD).
Port G Da ta
Re g iste r
The port G data register contains a data latch for each of the three port
G pins.
Address: $000A
Bit 7
0
6
0
5
0
4
0
3
0
2
1
Bit 0
Read:
Write:
Reset:
PTG2
PTG1
PTG0
R
R
R
R
R
Unaffected by Reset
Alternate
Function:
KBD2
KBD1
KBD0
R
=Reserved
Figure 20. Port G Data Register (PTG)
PTG[2:0] — Port G Data Bits
These read/write bits are software programmable. Data direction of
each port G pin is under the control of the corresponding bit in data
direction register G. Reset has no effect on PTG[2:0].
KBD[2:0] — Keyboard Wakeup pins
The keyboard interrupt enable bits, KBIE[2:0], in the keyboard
interrupt control register, enable the port G pins as external interrupt
pins (See Keyboard Module (KBD) on page 355). Enabling an
external interrupt pin will override the corresponding DDRGx.
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Da ta Dire c tion
Re g iste r G
Data direction register G determines whether each port G pin is an input
or an output. Writing a logic 1 to a DDRG bit enables the output buffer
for the corresponding port G pin; a logic 0 disables the output buffer.
Address: $000E
Bit 7
0
6
5
0
4
0
3
0
2
1
Bit 0
Read:
Write:
Reset:
0
DDRG2 DDRG1 DDRG0
R
R
R
0
R
0
R
0
0
0
0
0
0
R
=Reserved
Figure 21. Data Direction Register G (DDRG)
DDRG[2:0] — Data Direction Register G Bits
These read/write bits control port G data direction. Reset clears
DDRG[2:0], configuring all port G pins as inputs.
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
NOTE: Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
Figure 22 shows the port G I/O logic.
READ DDRG ($000E)
WRITE DDRG ($000E)
DDRGx
RESET
WRITE PTG ($000A)
PTGx
PTGx
READ PTG ($000A)
Figure 22. Port G I/O Circuit
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Port H
When bit DDRGx is a logic 1, reading address $000A reads the PTGx
data latch. When bit DDRGx is a logic 0, reading address $000A reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 7 summarizes the
operation of the port G pins.
Table 7. Port G Pin Functions
Accesses
Accesses to PTG
DDRG
Bit
PTG
Bit
I/O Pin
Mode
to DDRG
Read/Write
DDRG[2:0]
DDRG[2:0]
Read
Pin
Write
0
X
X
Input, Hi-Z
Output
PTG[2:0](1)
PTG[2:0]
1
PTG[2:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Port H
Port H is a 2-bit special function port that shares all of its pins with the
keyboard interrupt module (KBD).
Port H Da ta
Re g iste r
The port H data register contains a data latch for each of the two port H
pins.
Address: $000B
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
Bit 0
Read:
Write:
Reset:
PTH1
PTH0
R
R
R
R
R
R
Unaffected by Reset
Alternate
Function:
KBD4
KBD3
R
=Reserved
Figure 23. Port H Data Register (PTH)
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PTH[1:0] — Port H Data Bits
These read/write bits are software programmable. Data direction of
each port H pin is under the control of the corresponding bit in data
direction register H. Reset has no effect on PTH[1:0].
KBD[4:3] — Keyboard Wake-up pins
The keyboard interrupt enable bits, KBIE[4:3], in the keyboard
interrupt control register, enable the port H pins as external interrupt
pins (See Keyboard Module (KBD) on page 355).
Da ta Dire c tion
Re g iste r H
Data direction register H determines whether each port H pin is an input
or an output. Writing a logic 1 to a DDRH bit enables the output buffer
for the corresponding port H pin; a logic 0 disables the output buffer.
Address: $000F
Bit 7
0
6
5
0
4
0
3
0
2
0
1
Bit 0
Read:
Write:
Reset:
0
DDRH1 DDRH0
R
R
R
0
R
0
R
0
R
0
0
0
0
0
R
=Reserved
Figure 24. Data Direction Register H (DDRH)
DDRH[1:0] — Data Direction Register H Bits
These read/write bits control port H data direction. Reset clears
DDRG[1:0], configuring all port H pins as inputs.
1 = Corresponding port H pin configured as output
0 = Corresponding port H pin configured as input
NOTE: Avoid glitches on port H pins by writing to the port H data register before
changing data direction register H bits from 0 to 1.
Figure 25 shows the port H I/O logic.
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Port H
READ DDRH ($000F)
WRITE DDRH ($000F)
DDRHx
RESET
WRITE PTH ($000B)
PTHx
PTHx
READ PTH ($000B)
Figure 25. Port H I/O Circuit
When bit DDRHx is a logic 1, reading address $000B reads the PTHx
data latch. When bit DDRHx is a logic 0, reading address $000B reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 8 summarizes the
operation of the port H pins.
Table 8. Port H Pin Functions
Accesses
Accesses to PTH
DDRH
Bit
PTH
Bit
I/O Pin
Mode
to DDRH
Read/Write
DDRH[1:0]
DDRH[1:0]
Read
Pin
Write
0
X
X
Input, Hi-Z
Output
PTH[1:0](1)
PTH[1:0]
1
PTH[1:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
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MSCAN Controlle r (MSCAN08)
MSCAN Controlle r (MSCAN08)
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Background. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Receive Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Transmit Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Protocol Violation Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Low Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
MSCAN08 Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
MSCAN08 Soft Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
MSCAN08 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
CPU Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Programmable Wakeup Function . . . . . . . . . . . . . . . . . . . . . . . . . 324
Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . 329
Message Buffer Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Identifier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Data Length Register (DLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Data Segment Registers (DSRn) . . . . . . . . . . . . . . . . . . . . . . . . . 333
Transmit Buffer Priority Registers. . . . . . . . . . . . . . . . . . . . . . . . . 334
Programmer’s Model of Control Registers . . . . . . . . . . . . . . . . . . . . 334
MSCAN08 Module Control Register 0 . . . . . . . . . . . . . . . . . . . . . 337
MSCAN08 Module Control Register 1 . . . . . . . . . . . . . . . . . . . . . 338
MSCAN08 Bus Timing Register 0. . . . . . . . . . . . . . . . . . . . . . . . . 340
MSCAN08 Bus Timing Register 1. . . . . . . . . . . . . . . . . . . . . . . . . 341
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MSCAN Controlle r (MSCAN08)
MSCAN08 Receiver Flag Register (CRFLG) . . . . . . . . . . . . . . . .342
MSCAN08 Receiver Interrupt Enable Register. . . . . . . . . . . . . . .345
MSCAN08 Transmitter Flag Register . . . . . . . . . . . . . . . . . . . . . .346
MSCAN08 Transmitter Control Register. . . . . . . . . . . . . . . . . . . .348
MSCAN08 Identifier Acceptance Control Register . . . . . . . . . . . .349
MSCAN08 Receive Error Counter . . . . . . . . . . . . . . . . . . . . . . . .350
MSCAN08 Transmit Error Counter . . . . . . . . . . . . . . . . . . . . . . . .350
MSCAN08 Identifier Acceptance Registers . . . . . . . . . . . . . . . . .351
MSCAN08 Identifier Mask Registers (CIDMR0-3) . . . . . . . . . . . .352
Introd uc tion
The MSCAN08 is the specific implementation of the Motorola scalable
controller area network (MSCAN) concept targeted for the Motorola
M68HC08 Microcontroller Family.
The module is a communication controller implementing the CAN 2.0
A/B protocol as defined in the BOSCH specification dated September
1991.
The CAN protocol was primarily, but not exclusively, designed to be
used as a vehicle serial data bus, meeting the specific requirements of
this field: real-time processing, reliable operation in the electromagnetic
interference (EMI) environment of a vehicle, cost-effectiveness and
required bandwidth.
MSCAN08 utilizes an advanced buffer arrangement, resulting in a
predictable real-time behavior, and simplifies the application software.
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MSCAN Controller (MSCAN08)
Features
Fe a ture s
Basic features of the MSCAN08 are:
• Modular Architecture
• Implementation of the CAN Protocol — Version 2.0A/B
– Standard and Extended Data Frames.
– 0–8 Bytes Data Length.
– Programmable Bit Rate up to 1 Mbps Depending on the Actual
Bit Timing and the Clock Jitter of the PLL
• Support for Remote Frames
• Double-Buffered Receive Storage Scheme
• Triple-Buffered Transmit Storage Scheme with Internal
Priorisation Using a “Local Priority” Concept
• Flexible Maskable Identifier Filter Supports Alternatively One Full
Size Extended Identifier Filter or Two 16-Bit Filters or Four 8-Bit
Filters
• Programmable Wakeup Functionality with Integrated Low-Pass
Filter
• Programmable Loop-Back Mode Supports Self-Test Operation
• Separate Signalling and Interrupt Capabilities for All CAN
Receiver and Transmitter Error States (Warning, Error Passive,
Bus Off)
• Programmable MSCAN08 Clock Source Either CPU Bus Clock or
Crystal Oscillator Output
• Programmable Link to On-Chip Timer Interface Module (TIMB) for
Time-Stamping and Network Synchronization
• Low-Power Sleep Mode
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MSCAN Controlle r (MSCAN08)
Exte rna l Pins
The MSCAN08 uses two external pins, one input (RxCAN) and one
output (TxCAN). The TxCAN output pin represents the logic level on the
CAN: 0 is for a dominant state, and 1 is for a recessive state.
A typical CAN system with MSCAN08 is shown in Figure 1.
CAN STATION 1
CAN NODE 1
MCU
CAN NODE 2
CAN NODE N
CAN CONTROLLER
(MSCAN08)
TXCAN
RXCAN
TRANSCEIVER
CAN_L
CAN_H
C A N BUS
Figure 1. The CAN System
Each CAN station is connected physically to the CAN bus lines through
a transceiver chip. The transceiver is capable of driving the large current
needed for the CAN and has current protection against defected CAN or
defected stations.
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MSCAN Controller (MSCAN08)
Message Storage
Me ssa g e Stora g e
MSCAN08 facilitates a sophisticated message storage system which
addresses the requirements of a broad range of network applications.
Ba c kg round
Modern application layer software is built under two fundamental
assumptions:
1. Any CAN node is able to send out a stream of scheduled
messages without releasing the bus between two messages.
Such nodes will arbitrate for the bus right after sending the
previous message and will only release the bus in case of lost
arbitration.
2. The internal message queue within any CAN node is organized as
such that the highest priority message will be sent out first if more
than one message is ready to be sent.
Above behavior cannot be achieved with a single transmit buffer. That
buffer must be reloaded right after the previous message has been sent.
This loading process lasts a definite amount of time and has to be
completed within the inter-frame sequence (IFS) to be able to send an
uninterrupted stream of messages. Even if this is feasible for limited
CAN bus speeds, it requires that the CPU reacts with short latencies to
the transmit interrupt.
A double buffer scheme would de-couple the re-loading of the transmit
buffers from the actual message being sent and as such reduces the
reactiveness requirements on the CPU. Problems may arise if the
sending of a message would be finished just while the CPU re-loads the
second buffer. In that case, no buffer would then be ready for
transmission and the bus would be released.
At least three transmit buffers are required to meet the first of the above
requirements under all circumstances. The MSCAN08 has three
transmit buffers.
The second requirement calls for some sort of internal priorisation which
the MSCAN08 implements with the “local priority” concept described in
Receive Structures on page 310.
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MSCAN Controlle r (MSCAN08)
Re c e ive Struc ture s
The received messages are stored in a 2-stage input first in first out
(FIFO). The two message buffers are mapped using a Ping Pong
arrangement into a single memory area (see Figure 2). While the
background receive buffer (RxBG) is exclusively associated to the
MSCAN08, the foreground receive buffer (RxFG) is addressable by the
CPU08. This scheme simplifies the handler software, because only one
address area is applicable for the receive process.
Both buffers have a size of 13 bytes to store the CAN control bits, the
identifier (standard or extended), and the data content (for details, see
Programmer’s Model of Message Storage on page 329).
The receiver full flag (RXF) in the MSCAN08 receiver flag register
(CRFLG) (see MSCAN08 Receiver Flag Register (CRFLG) on page
342), signals the status of the foreground receive buffer. When the buffer
contains a correctly received message with matching identifier, this flag
is set.
On reception, each message is checked to see if it passes the filter (for
details see Identifier Acceptance Filter on page 314) and in parallel is
written into RxBG. The MSCAN08 copies the content of RxBG into
RxFG1, sets the RXF flag, and generates a receive interrupt to the
CPU2. The user’s receive handler has to read the received message
from RxFG and to reset the RXF flag to acknowledge the interrupt and
to release the foreground buffer. A new message which can follow
immediately after the IFS field of the CAN frame, is received into RxBG.
The overwriting of the background buffer is independent of the identifier
filter function.
When the MSCAN08 module is transmitting, the MSCAN08 receives its
own messages into the background receive buffer, RxBG. It does NOT
overwrite RxFG, generate a receive interrupt or acknowledge its own
messages on the CAN bus. The exception to this rule is in loop-back
mode (see MSCAN08 Module Control Register 1 on page 338), where
the MSCAN08 treats its own messages exactly like all other incoming
messages. The MSCAN08 receives its own transmitted messages in the
1. Only if the RXF flag is not set.
2. The receive interrupt will occur only if not masked. A polling scheme can be applied on RXF
also.
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MSCAN Controller (MSCAN08)
Message Storage
event that it loses arbitration. If arbitration is lost, the MSCAN08 must be
prepared to become receiver.
An overrun condition occurs when both the foreground and the
background receive message buffers are filled with correctly received
messages with accepted identifiers and another message is correctly
received from the bus with an accepted identifier. The latter message will
be discarded and an error interrupt with overrun indication will be
generated if enabled. The MSCAN08 is still able to transmit messages
with both receive message buffers filled, but all incoming messages are
discarded.
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CPU08 Ibus
MSCAN08
RxBG
RxFG
RXF
TXE
Tx0
Tx1
Tx2
PRIO
TXE
PRIO
TXE
PRIO
Figure 2. User Model for Message Buffer Organization
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Message Storage
Tra nsm it Struc ture s
The MSCAN08 has a triple transmit buffer scheme to allow multiple
messages to be set up in advance and to achieve an optimized real-time
performance. The three buffers are arranged as shown in Figure 2.
All three buffers have a 13-byte data structure similar to the outline of the
receive buffers (see Programmer’s Model of Message Storage on
page 329). An additional transmit buffer priority register (TBPR) contains
an 8-bit “local priority” field (PRIO) (see Transmit Buffer Priority
Registers on page 334).
To transmit a message, the CPU08 has to identify an available transmit
buffer which is indicated by a set transmit buffer empty (TXE) flag in the
MSCAN08 transmitter flag register (CTFLG) (see MSCAN08
Transmitter Flag Register on page 346).
The CPU08 then stores the identifier, the control bits and the data
content into one of the transmit buffers. Finally, the buffer has to be
flagged ready for transmission by clearing the TXE flag.
The MSCAN08 then will schedule the message for transmission and will
signal the successful transmission of the buffer by setting the TXE flag.
A transmit interrupt is generated1 when TXE is set and can be used to
drive the application software to re-load the buffer.
In case more than one buffer is scheduled for transmission when the
CAN bus becomes available for arbitration, the MSCAN08 uses the local
priority setting of the three buffers for prioritzation. For this purpose,
every transmit buffer has an 8-bit local priority field (PRIO). The
application software sets this field when the message is set up. The local
priority reflects the priority of this particular message relative to the set
of messages being emitted from this node. The lowest binary value of
the PRIO field is defined as the highest priority.
1. The transmit interrupt will occur only if not masked. A polling scheme can be applied on TXE
also.
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The internal scheduling process takes place whenever the MSCAN08
arbitrates for the bus. This is also the case after the occurrence of a
transmission error.
When a high priority message is scheduled by the application software,
it may become necessary to abort a lower priority message being set up
in one of the three transmit buffers. As messages that are already under
transmission cannot be aborted, the user has to request the abort by
setting the corresponding abort request flag (ABTRQ) in the
transmission control register (CTCR). The MSCAN08 will then grant the
request, if possible, by setting the corresponding abort request
acknowledge (ABTAK) and the TXE flag in order to release the buffer
and by generating a transmit interrupt. The transmit interrupt handler
software can tell from the setting of the ABTAK flag whether the
message was actually aborted (ABTAK = 1) or sent (ABTAK = 0).
Id e ntifie r Ac c e p ta nc e Filte r
The Identifier Acceptance Registers (CIDAR0-3) define the acceptance
patterns of the standard or extended identifier (ID10-ID0 or ID28-ID0).
Any of these bits can be marked ‘don’t care’ in the Identifier Mask
Registers (CIDMR0-3).
A filter hit is indicated to the application on software by a set RXF
(Receive Buffer Full Flag, see MSCAN08 Receiver Flag Register
(CRFLG) on page 342) and two bits in the Identifier Acceptance Control
Register (see MSCAN08 Identifier Acceptance Control Register on
page 349). These Identifier Hit Flags (IDHIT1-0) clearly identify the filter
section that caused the acceptance. They simplify the application
software’s task to identify the cause of the receiver interrupt. In case that
more than one hit occurs (two or more filters match) the lower hit has
priority.
A very flexible programmable generic identifier acceptance filter has
been introduced to reduce the CPU interrupt loading. The filter is
programmable to operate in four different modes:
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Identifier Acceptance Filter
• Single identifier acceptance filter, each to be applied to a) the full
29 bits of the extended identifier and to the following bits of the
CAN frame: RTR, IDE, SRR or b) the 11 bits of the standard
identifier plus the RTR and IDE bits of CAN 2.0A/B messages.
This mode implements a single filter for a full length CAN 2.0B
compliant extended identifier. Figure 3 shows how the 32-bit filter
bank (CIDAR0-3, CIDMR0-3) produces a filter 0 hit.
• Two identifier acceptance filters, each to be applied to a) the 14
most significant bits of the extended identifier plus the SRR and
the IDE bits of CAN2.0B messages, or b) the 11 bits of the
identifier plus the RTR and IDE bits of CAN 2.0A/B messages.
Figure 4 shows how the 32-bit filter bank (CIDAR0-3, CIDMR0-3)
produces filter 0 and 1 hits.
• Four identifier acceptance filters, each to be applied to the first
eight bits of the identifier. This mode implements four independent
filters for the first eight bits of a CAN 2.0A/B compliant standard
identifier. Figure 5 shows how the 32-bit filter bank (CIDAR0-3,
CIDMR0-3) produces filter 0 to 3 hits.
• Closed filter. No CAN message will be copied into the foreground
buffer RxFG, and the RXF flag will never be set.
ID28
ID10
IDR0
IDR0
ID21 ID20
ID3 ID2
IDR1
ID15 ID14
IDR2
ID7 ID6
IDR3
RTR
IDR1 IDE
AM7
AC7
CIDMR0
CIDAR0
AM0 AM7
AC0 AC7
CIDMR1
CIDAR1
AM0 AM7
AC0 AC7
CIDMR2
CIDAR2
AM0 AM7
AC0 AC7
CIDMR3
CIDAR3
AM0
AC0
ID Accepted (Filter 0 Hit)
Figure 3. Single 32-Bit Maskable Identifier Acceptance Filter
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ID28
ID10
IDR0
IDR0
ID21 ID20
ID3 ID2
IDR1
ID15 ID14
IDR2
ID7 ID6
IDR3
RTR
IDR1 IDE
AM7
AC7
CIDMR0
CIDAR0
AM0 AM7
AC0 AC7
CIDMR1
CIDAR1
AM0
AC0
ID ACCEPTED (FILTER 0 HIT)
AM7
AC7
CIDMR2
AM0 AM7
AC0 AC7
CIDMR3
AM0
AC0
CIDAR2
CIDAR3
ID ACCEPTED (FILTER 1 HIT)
Figure 4. Dual 16-Bit Maskable Acceptance Filters
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MSCAN Controller (MSCAN08)
Identifier Acceptance Filter
.
ID28
ID10
IDR0
IDR0
ID21 ID20
ID3 ID2
IDR1
IDR1
ID15 ID14
IDE
IDR2
ID7 ID6
IDR3
RTR
AM7
AC7
CIDMR0
CIDAR0
AM0
AC0
ID ACCEPTED (FILTER 0 HIT)
AM7
AC7
CIDMR1
CIDAR1
AM0
AC0
ID ACCEPTED (FILTER 1 HIT)
AM7
AC7
CIDMR2
CIDAR2
AM0
AC0
ID ACCEPTED (FILTER 2 HIT)
AM7
AC7
CIDMR3
CIDAR3
AM0
AC0
ID ACCEPTED (FILTER 3 HIT)
Figure 5. Quadruple 8-Bit Maskable Acceptance Filters
13-mscan
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MSCAN Controlle r (MSCAN08)
Inte rrup ts
The MSCAN08 supports four interrupt vectors mapped onto eleven
different interrupt sources, any of which can be individually masked (for
details see MSCAN08 Receiver Flag Register (CRFLG) on page 342,
to MSCAN08 Transmitter Control Register on page 348).
•
Transmit Interrupt: At least one of the three transmit buffers is
empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXE flags of the empty message buffers are
set.
•
Receive Interrupt: A message has been received successfully and
loaded into the foreground receive buffer. This interrupt will be
emitted immediately after receiving the EOF symbol. The RXF flag
is set.
•
•
Wakeup Interrupt: An activity on the CAN bus occurred during
MSCAN08 internal sleep mode.
Error Interrupt: An overrun, error, or warning condition occurred.
The receiver flag register (CRFLG) will indicate one of the
following conditions:
– Overrun: An overrun condition as described in Receive
Structures on page 310, has occurred.
– Receiver Warning: The receive error counter has reached the
CPU Warning limit of 96.
– Transmitter Warning: The transmit error counter has reached
the CPU Warning limit of 96.
– Receiver Error Passive: The receive error counter has
exceeded the error passive limit of 127 and MSCAN08 has
gone to error passive state.
– Transmitter Error Passive: The transmit error counter has
exceeded the error passive limit of 127 and MSCAN08 has
gone to error passive state.
– Bus Off: The transmit error counter has exceeded 255 and
MSCAN08 has gone to bus off state.
14-mscan
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MSCAN Controller (MSCAN08)
Interrupts
Inte rrup t
Ac knowle d g e
Interrupts are directly associated with one or more status flags in either
the MSCAN08 receiver flag register (CRFLG) or the MSCAN08
transmitter flag register (CTFLG). Interrupts are pending as long as one
of the corresponding flags is set. The flags in the above registers must
be reset within the interrupt handler in order to handshake the interrupt.
The flags are reset through writing a ‘1’ to the corresponding bit position.
A flag cannot be cleared if the respective condition still prevails.
NOTE: Bit manipulation instructions (BSET) shall not be used to clear interrupt
flags.
Inte rrup t Ve c tors
The MSCAN08 supports four interrupt vectors as shown in Table 1. The
vector addresses and the relative interrupt priority are dependent on the
chip integration and to be defined.
Table 1. MSCAN08 Interrupt Vector Addresses
Local
Mask
Global
Mask
Function
Source
Wakeup
WUPIF
RWRNIF
TWRNIF
RERRIF
TERRIF
BOFFIF
OVRIF
RXF
WUPIE
RWRNIE
TWRNIE
RERRIE
TERRIE
BOFFIE
OVRIE
Error
Interrupts
I Bit
Receive
Transmit
RXFIE
TXE0
TXEIE0
TXEIE1
TXEIE2
TXE1
TXE2
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MSCAN Controlle r (MSCAN08)
Protoc ol Viola tion Prote c tion
The MSCAN08 will protect the user from accidentally violating the CAN
protocol through programming errors. The protection logic implements
the following features:
• The receive and transmit error counters cannot be written or
otherwise manipulated.
• All registers which control the configuration of the MSCAN08 can
not be modified while the MSCAN08 is on-line. The SFTRES bit in
the MSCAN08 module control register (see MSCAN08 Module
Control Register 0 on page 337) serves as a lock to protect the
following registers:
– MSCAN08 module control register 1 (CMCR1)
– MSCAN08 bus timing register 0 and 1 (CBTR0 and CBTR1)
– MSCAN08 identifier acceptance control register (CIDAC)
– MSCAN08 identifier acceptance registers (CIDAR0–3)
– MSCAN08 identifier mask registers (CIDMR0–3)
• The TxCAN pin is forced to recessive when the MSCAN08 is in
any of the Low Power Modes.
Low Powe r Mod e s
In addition to normal mode, the MSCAN08 has three modes with
reduced power consumption: Sleep, Soft Reset and Power Down
modes. In Sleep and Soft Reset mode, power consumption is reduced
by stopping all clocks except those to access the registers. In Power
Down mode, all clocks are stopped and no power is consumed.
The WAIT and STOP instructions put the MCU in low power consuption
stand-by modes. Table 2 summarizes the combinations of MSCAN08
and CPU modes. A particular combination of modes is entered for the
given settings of the bits SLPAK and SFTRES. For all modes, an
MSCAN wake-up interrupt can occur only if SLPAK=WUPIE=1. While
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MSCAN Controller (MSCAN08)
Low Power Modes
the CPU is in WAIT mode, the MSCAN08 is operated as in Normal
mode.
Table 2. MSCAN08 vs CPU operating modes
CPU Mode
MSCAN
Mode
STOP
WAIT or RUN
SLPAK = X(1)
SFTRES = X
Power Down
Sleep
SLPAK = 1
SFTRES = 0
SLPAK = 0
SFTRES = 1
Soft Reset
Normal
SLPAK = 0
SFTRES = 0
1. ‘X’ means don’t care.
MSCAN08 Sle e p
Mod e
The CPU can request the MSCAN08 to enter the low-power mode by
asserting the SLPRQ bit in the module configuration register (see Figure
6). The time when the MSCAN08 enters Sleep mode depends on its
activity:
• if it is transmitting, it continues to transmit untl there is no more
message to be transmitted, and then goes into Sleep mode
• if it is receiving, it waits for the end of this message and then goes
into Sleep mode
• if it is neither transmitting or receiving, it will immediately go into
Sleep mode
NOTE: The application software must avoid setting up a transmission (by
clearing or more TXE flags) and immediately request Sleep mode (by
setting SLPRQ). It then depends on the exact sequesnce of operations
whether MSCAN08 starts transmitting or goes into Sleep mode directly.
During Sleep mode, the SLPAK flag is set. The application software
should use SLPAK as a handshake indication for the request (SLPRQ)
to go into Sleep mode. When in Sleep mode, the MSCAN08 stops its
internal clocks. However, clocks to allow register accesses still run. If the
17-mscan
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MSCAN Controlle r (MSCAN08)
MSCAN08 is in buss-off state, it stops counting the 128*11 consecutive
recessive bits due to the stopped clocks. The TxCAN pin stays in
recessive state. If RXF=1, the message can be read and RXF can be
cleared. Copying of RxGB into RxFG doesn’t take place while in Sleep
mode. It is possible to access the transmit buffers and to clear the TXE
flags. No message abort takes place while in Sleep mode.
The MSCAN08 leaves Sleep mode (wake-up) when:
• bus activity occurs or
• the MCU clears the SLPRQ bit or
• the MCU sets the SFTRES bit
MSCAN08 Running
SLPRQ = 0
SLPAK = 0
MCU
MCU
or MSCAN08
MSCAN08 Sleeping
Sleep Request
SLPRQ = 1
SLPAK = 1
SLPRQ = 1
SLPAK = 0
MSCAN08
Figure 6. Sleep Request/Acknowledge Cycle
NOTE: The MCU cannot clear the SLPRQ bit before the MSCAN08 is in Sleep
mode (SLPAK=1).
After wake-up, the MSCAN08 waits for 11 consecutive recessive bits to
synchronize to the bus. As a consequence, if the MSCAN08 is woken-up
by a CAN frame, this frame is not received. The receive message buffers
(RxFG and RxBG) contain messages if they were received before Sleep
mode was entered. All pending actions are executed upon wake-up:
18-mscan
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MSCAN Controller (MSCAN08)
Low Power Modes
copying of RxBG into RxFG, message aborts and message
transmissions. If the MSCAN08 is still in bus-off state after Sleep mode
was left, it continues counting the 128*11 consecutive recessive bits.
MSCAN08 Soft
Re se t Mod e
In Soft Reset mode, the MSCAN08 is stopped. Registers can still be
accessed. This mode is used to initialize the module configuration, bit
timing and the CAN message filter. See MSCAN08 Module Control
Register 0 on page 337 for a complete description of the Soft Reset
mode.
When setting the SFTRES bit, the MSCAN08 immediately stops all
ongoing transmissions and receptions, potentially causing CAN protocol
violations.
NOTE: The user is responsible to take care that the MSCAN08 is not active
when Soft Reset mode is entered. The recommended procedure is to
bring the MSCAN08 into Sleep mode before the SFTRES bit is set.
MSCAN08 Powe r
The MSCAN08 is in Power Down mode when the CPU is in Stop mode.
Down Mod e
When entering the Power Down mode, the MSCAN08 imediately stops
all ongoing transmissions and receptions, potentially causing CAN
protocol violations.
NOTE: The user is responsible to take care that the MSCAN08 is not active
when Power Down mode is enterd. The recommended procedure is to
bring the MSCAN08 into Sleep mode before the SOP instruction is
executed.
To protect the CAN bus system from fatal consequences of violations to
the above rule, the MSCAN08 drives the TxCAN pin into recessive state.
In Power Down mode, no registers can be accessed.
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MSCAN Controlle r (MSCAN08)
CPU Wa it Mod e
The MSCAN08 module remains active during CPU wait mode. The
MSCAN08 will stay synchronized to the CAN bus and generates
transmit, receive, and error interrupts to the CPU, if enabled. Any such
interrupt will bring the MCU out of wait mode.
Prog ra m m a b le
Wa ke up Func tion
The MSCAN08 can be programmed to apply a low-pass filter function to
the RxCAN input line while in internal sleep mode (see information on
control bit WUPM in MSCAN08 Module Control Register 1 on page
338). This feature can be used to protect the MSCAN08 from wake-up
due to short glitches on the CAN bus lines. Such glitches can result from
electromagnetic inference within noisy environments.
Tim e r Link
The MSCAN08 will generate a timer signal whenever a valid frame has
been received. Because the CAN specification defines a frame to be
valid if no errors occurred before the EOF field has been transmitted
successfully, the timer signal will be generated right after the EOF. A
pulse of one bit time is generated. As the MSCAN08 receiver engine
also receives the frames being sent by itself, a timer signal also will be
generated after a successful transmission.
The previously described timer signal can be routed into the on-chip
timer interface module (TIM).This signal is connected to the timer n
channel m input1 under the control of the timer link enable (TLNKEN) bit
in the CMCR0.
After timer n has been programmed to capture rising edge events, it can
be used under software control to generate 16-bit time stamps which can
be stored with the received message.
1. The timer channel being used for the timer link is integration dependent.
20-mscan
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MSCAN Controller (MSCAN08)
Clock System
Cloc k Syste m
Figure 7 shows the structure of the MSCAN08 clock generation circuitry
and its interaction with the clock generation module (CGM). With this
flexible clocking scheme the MSCAN08 is able to handle CAN bus rates
ranging from 10 kbps up to 1 Mbps.
CGMXCLK
OSC
÷ 2
CGMOUT
(TO SIM)
BCS
PLL
÷ 2
CGM
MSCAN08
(2 * BUS FREQ.)
÷ 2
MSCANCLK
PRESCALER
(1 .. 64)
CLKSRC
Figure 7. Clocking Scheme
The clock source bit (CLKSRC) in the MSCAN08 module control register
(CMCR1) (see MSCAN08 Module Control Register 0 on page 337)
defines whether the MSCAN08 is connected to the output of the crystal
oscillator or to the PLL output.
The clock source has to be chosen such that the tight oscillator tolerance
requirements (up to 0.4%) of the CAN protocol are met.
21-mscan
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MSCAN Controlle r (MSCAN08)
NOTE: If the system clock is generated from a PLL, it is recommended to select
the crystal clock source rather than the system clock source due to jitter
considerations, especially at faster CAN bus rates.
A programmable prescaler is used to generate out of the MSCAN08
clock the time quanta (Tq) clock. A time quantum is the atomic unit of
time handled by the MSCAN08.
fMSCANCLK
fTq =
Presc value
A bit time is subdivided into three segments1(see Figure 8).
• SYNC_SEG: This segment has a fixed length of one time
quantum. Signal edges are expected to happen within this section.
• Time segment 1: This segment includes the PROP_SEG and the
PHASE_SEG1 of the CAN standard. It can be programmed by
setting the parameter TSEG1 to consist of 4 to 16 time quanta.
• Time segment 2: This segment represents PHASE_SEG2 of the
CAN standard. It can be programmed by setting the TSEG2
parameter to be 2 to 8 time quanta long.
fTq
Bit rate=
No. of time quanta
The synchronization jump width (SJW) can be programmed in a range
of 1 to 4 time quanta by setting the SJW parameter.
The above parameters can be set by programming the bus timing
registers, CBTR0–CBTR1, see MSCAN08 Bus Timing Register 0 on
page 340 and MSCAN08 Bus Timing Register 1 on page 341).
1. For further explanation of the underlying concepts please refer to ISO/DIS 11 519-1, Section
10.3.
22-mscan
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Clock System
NOTE: It is the user’s responsibility to make sure that the bit timing settings are
in compliance with the CAN standard,
Table 8 gives an overview on the CAN conforming segment settings and
the related parameter values.
NRZ SIGNAL
SYNC
TIME SEG. 2
(PHASE_SEG2)
TIME SEGMENT 1
(PROP_SEG + PHASE_SEG1)
_SEG
1
4 ... 16
2 ... 8
8... 25 TIME QUANTA
= 1 BIT TIME
SAMPLE POINT
(SINGLE OR TRIPLE SAMPLING)
Figure 8. Segments within the Bit Time
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MSCAN Controlle r (MSCAN08)
Table 3. Time segment syntax
System expects transitions to occur on the bus
SYNC_SEG
during this period.
A node in transmit mode will transfer a new
value to the CAN bus at this point.
Transmit point
A node in receive mode will sample the bus at
this point. If the three samples per bit option is
selected then this point marks the position of
the third sample.
Sample point
Table 4. CAN Standard Compliant Bit Time Segment Settings
Time
Segment 1
Time
Segment 2
Synchron.
Jump Width
TSEG1
TSEG2
SJW
5 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
9 .. 16
4 .. 9
3 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
2
3
4
5
6
7
8
1
2
3
4
5
6
7
1 .. 2
1 .. 3
1 .. 4
1 .. 4
1 .. 4
1 .. 4
1 .. 4
0 .. 1
0 .. 2
0 .. 3
0 .. 3
0 .. 3
0 .. 3
0 .. 3
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MSCAN Controller (MSCAN08)
Memory Map
Me m ory Ma p
The MSCAN08 occupies 128 bytes in the CPU08 memory space. The
absolute mapping is implementation dependent with the base address
being a multiple of 128.
$xx00
$xx08
$xx09
$xx0D
$xx0E
$xx0F
$xx10
$xx17
$xx18
$xx3F
$xx40
$xx4F
$xx50
$xx5F
$xx60
$xx6F
$xx70
$xx7F
CONTROL REGISTERS
9 BYTES
RESERVED
5 BYTES
ERROR COUNTERS
2 BYTES
IDENTIFIER FILTER
8 BYTES
RESERVED
40 BYTES
RECEIVE BUFFER
TRANSMIT BUFFER 0
TRANSMIT BUFFER 1
TRANSMIT BUFFER 2
Figure 9. MSCAN08 Memory Map
Prog ra m m e r’s Mod e l of Me ssa g e Stora g e
This section details the organization of the receive and transmit
message buffers and the associated control registers. For reasons of
programmer interface simplification, the receive and transmit message
buffers have the same outline. Each message buffer allocates 16 bytes
in the memory map containing a 13-byte data structure. An additional
transmit buffer priority register (TBPR) is defined for the transmit buffers.
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Addr
Register Name
$05b0
$05b1
$05b2
$05b3
$05b4
$05b5
$05b6
$05b7
$05b8
$05b9
$05bA
$05bB
$05bC
IDENTIFIER REGISTER 0
IDENTIFIER REGISTER 1
IDENTIFIER REGISTER 2
IDENTIFIER REGISTER 3
DATA SEGMENT REGISTER 0
DATA SEGMENT REGISTER 1
DATA SEGMENT REGISTER 2
DATA SEGMENT REGISTER 3
DATA SEGMENT REGISTER 4
DATA SEGMENT REGISTER 5
DATA SEGMENT REGISTER 6
DATA SEGMENT REGISTER 7
DATA LENGTH REGISTER
TRANSMIT BUFFER PRIORITY
REGISTER(1)
$05bD
$05bE
$05bF
UNUSED
UNUSED
1. Not applicable for receive buffers
Figure 10. Message Buffer Organization
Me ssa g e Buffe r
Outline
Figure 11 shows the common 13-byte data structure of receive and
transmit buffers for extended identifiers. The mapping of standard
identifiers into the IDR registers is shown in Figure 12. All bits of the
13-byte data structure are undefined out of reset.
NOTE: The foreground receive buffer can be read anytime but cannot be
written. The transmit buffers can be read or written anytime.
Id e ntifie r Re g iste rs
The identifiers consist of either 11 bits (ID10–ID0) for the standard, or 29
bits (ID28–ID0) for the extended format. ID10/28 is the most significant
bit and is transmitted first on the bus during the arbitration procedure.
The priority of an identifier is defined to be highest for the smallest binary
number.
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Programmer’s Model of Message Storage
SRR — Substitute Remote Request
This fixed recessive bit is used only in extended format. It must be set
to 1 by the user for transmission buffers and will be stored as received
on the CAN bus for receive buffers.
Addr
Register
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$05b0
IDR0
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
$05b1
$05b2
$05b3
$05b4
$05b5
$05b6
$05b7
$05b8
$05b9
$05bA
$05bB
$05bC
IDR1
IDR2
ID20
ID14
ID6
ID19
ID13
ID5
ID18
ID12
ID4
SRR (=1) IDE (=1)
ID17
ID9
ID16
ID8
ID15
ID7
ID11
ID3
ID10
ID2
IDR3
ID1
ID0
RTR
DB0
DB0
DB0
DB0
DB0
DB0
DB0
DB0
DLC0
DSR0
DSR1
DSR2
DSR3
DSR4
DSR5
DSR6
DSR7
DLR
DB7
DB7
DB7
DB7
DB7
DB7
DB7
DB7
DB6
DB6
DB6
DB6
DB6
DB6
DB6
DB6
DB5
DB5
DB5
DB5
DB5
DB5
DB5
DB5
DB4
DB4
DB4
DB4
DB4
DB4
DB4
DB4
DB3
DB3
DB3
DB3
DB3
DB3
DB3
DB3
DLC3
DB2
DB2
DB2
DB2
DB2
DB2
DB2
DB2
DLC2
DB1
DB1
DB1
DB1
DB1
DB1
DB1
DB1
DLC1
= Unimplemented
Figure 11. Receive/Transmit Message Buffer Extended Identifier (IDRn)
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Addr
Register
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$05b0
IDR0
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
$05b1
$05b2
$05b3
IDR1
IDR2
IDR3
ID2
ID1
ID0
RTR
IDE(=0)
= Unimplemented
Figure 12. Standard Identifier Mapping
IDE — ID Extended
This flag indicates whether the extended or standard identifier format
is applied in this buffer. In case of a receive buffer, the flag is set as
being received and indicates to the CPU how to process the buffer
identifier registers. In case of a transmit buffer, the flag indicates to the
MSCAN08 what type of identifier to send.
1 = Extended format, 29 bits
0 = Standard format, 11 bits
RTR — Remote Transmission Request
This flag reflects the status of the remote transmission request bit in
the CAN frame. In case of a receive buffer, it indicates the status of
the received frame and supports the transmission of an answering
frame in software. In case of a transmit buffer, this flag defines the
setting of the RTR bit to be sent.
1 = Remote frame
0 = Data frame
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MSCAN Controller (MSCAN08)
Programmer’s Model of Message Storage
Da ta Le ng th
This register keeps the data length field of the CAN frame.
Re g iste r (DLR)
DLC3–DLC0 — Data Length Code Bits
The data length code contains the number of bytes (data byte count)
of the respective message. At transmission of a remote frame, the
data length code is transmitted as programmed while the number of
transmitted bytes is always 0. The data byte count ranges from 0 to 8
for a data frame. Table 5 shows the effect of setting the DLC bits.
Table 5. Data Length Codes
Data Length Code
Data
Byte
DLC0 Count
DLC3
DLC2
DLC1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
8
Da ta Se g m e nt
Re g iste rs (DSRn)
The eight data segment registers contain the data to be transmitted or
received. The number of bytes to be transmitted or being received is
determined by the data length code in the corresponding DLR.
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Tra nsm it Buffe r
Priority Re g iste rs
Address: $05bD
Bit 7
6
PRIO6
u
5
PRIO5
u
4
PRIO4
u
3
PRIO3
u
2
PRIO2
u
1
PRIO1
u
Bit 0
PRIO0
u
Read:
PRIO7
Write:
Reset:
u
Figure 13. Transmit Buffer Priority Register (TBPR)
PRIO7–PRIO0 — Local Priority
This field defines the local priority of the associated message buffer.
The local priority is used for the internal priorization process of the
MSCAN08 and is defined to be highest for the smallest binary
number. The MSCAN08 implements the following internal priorization
mechanism:
• All transmission buffers with a cleared TXE flag participate in the
priorization right before the SOF is sent.
• The transmission buffer with the lowest local priority field wins the
priorization.
• In case more than one buffer has the same lowest priority, the
message buffer with the lower index number wins.
Prog ra m m e r’s Mod e l of Control Re g iste rs
The programmer’s model has been laid out for maximum simplicity and
efficiency. Figure 14 gives an overview on the control register block of
the MSCAN08.
30-mscan
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MSCAN Controller (MSCAN08)
Programmer’s Model of Control Registers
Addr
Register
Bit 7
6
5
4
3
TLNKEN
0
2
1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
0
0
SYNCH
SLPAK
$0500
CMCR0
SLPRQ
SFTRES
0
0
0
0
$0501
$0502
$0503
$0504
$0505
$0506
$0507
$0508
$0509
CMCR1
CBTR0
CBTR1
CRFLG
CRIER
CTFLG
CTCR
LOOPB
BRP2
WUPM CLKSRC
SJW1
SAMP
WUPIF
SJW0
BRP5
BRP4
BRP3
BRP1
BRP0
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
RWRNIF TWRNIF RERRIF
RWRNIE TWRNIE RERRIE
TERRIF
BOFFIF
BOFFIE
TXE2
OVRIF
OVRIE
TXE1
RXF
RXFIE
TXE0
WUPIE
0
TERRIE
0
ABTAK2
ABTAK1
ABTAK0
0
0
0
0
ABTRQ2 ABTRQ1 ABTRQ0
0
TXEIE2
0
TXEIE1
IDHIT1
TXEIE0
IDHIT0
CIDAC
Reserved
IDAM1
IDAM0
R
R
R
R
R
R
R
R
= Unimplemented
R
= Reserved
Figure 14. MSCAN08 Control Register Structure
31-mscan
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MSCAN Controlle r (MSCAN08)
Addr
Register
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$050E
CRXERR
RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
$050F
$0513
$0513
$0513
$0513
$0517
$0517
$0517
$0517
CTXERR
CIDAR0
CIDAR1
CIDAR2
CIDAR3
CIDMR0
CIDMR1
CIDMR2
CIDMR3
AC7
AC7
AC7
AC7
AM7
AM7
AM7
AM7
AC6
AC6
AC6
AC6
AM6
AM6
AM6
AM6
AC5
AC5
AC5
AC5
AM5
AM5
AM5
AM5
AC4
AC4
AC4
AC4
AM4
AM4
AM4
AM4
AC3
AC3
AC3
AC3
AM3
AM3
AM3
AM3
AC2
AC2
AC2
AC2
AM2
AM2
AM2
AM2
AC1
AC1
AC1
AC1
AM1
AM1
AM1
AM1
AC0
AC0
AC0
AC0
AM0
AM0
AM0
AM0
Figure 14. MSCAN08 Control Register Structure (Continued)
32-mscan
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MSCAN Controller (MSCAN08)
Programmer’s Model of Control Registers
MSCAN08 Mod ule
Control Re g iste r 0
Address: $0500
Bit 7
6
0
5
0
4
3
TLNKEN
0
2
1
Bit 0
Read:
Write:
Reset:
0
SYNCH
SLPAK
SLPRQ SFTRES
0
0
0
0
0
0
1
= Unimplemented
Figure 15. Module Control Register 0 (CMCR0)
SYNCH — Synchronized Status
This bit indicates whether the MSCAN08 is synchronized to the CAN
bus and as such can participate in the communication process.
1 = MSCAN08 synchronized to the CAN bus
0 = MSCAN08 not synchronized to the CAN bus
TLNKEN — Timer Enable
This flag is used to establish a link between the MSCAN08 and the
on-chip timer (see Timer Link on page 324).
1 = The MSCAN08 timer signal output is connected to the timer
input.
0 = The port is connected to the timer input.
SLPAK — Sleep Mode Acknowledge
This flag indicates whether the MSCAN08 is in module internal sleep
mode. It shall be used as a handshake for the sleep mode request
(see MSCAN08 Sleep Mode on page 321). If the MSCAN08 detects
bus activity while in Sleep mode, it clears the flag.
1 = Sleep – MSCAN08 in internal sleep mode
0 = Wakeup – MSCAN08 is not in Sleep mode
33-mscan
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MSCAN Controlle r (MSCAN08)
SLPRQ — Sleep Request, Go to Internal Sleep Mode
This flag requests the MSCAN08 to go into an internal power-saving
mode (see MSCAN08 Sleep Mode on page 321).
1 = Sleep — The MSCAN08 will go into internal sleep mode.
0 = Wakeup — The MSCAN08 will function normally.
SFTRES — Soft Reset
When this bit is set by the CPU, the MSCAN08 immediately enters the
soft reset state. Any ongoing transmission or reception is aborted and
synchronization to the bus is lost.
The following registers enter and stay in their hard reset state:
CMCR0, CRFLG, CRIER, CTFLG, and CTCR.
The registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0–3, and
CIDMR0–3 can only be written by the CPU when the MSCAN08 is in
soft reset state. The values of the error counters are not affected by
soft reset.
When this bit is cleared by the CPU, the MSCAN08 tries to
synchronize to the CAN bus. If the MSCAN08 is not in bus-off state,
it will be synchronized after 11 recessive bits on the bus; if the
MSCAN08 is in bus-off state, it continues to wait for 128 occurrences
of 11 recessive bits.
Clearing SFTRES and writing to other bits in CMCR0 must be in
separate instructions.
1 = MSCAN08 in soft reset state
0 = Normal operation
MSCAN08 Mod ule
Control Re g iste r 1
Address: $0501
Bit 7
0
6
0
5
0
4
0
3
0
2
LOOPB
0
1
Bit 0
Read:
Write:
Reset:
WUPM CLKSRC
0
0
0
0
0
0
0
= Unimplemented
Figure 16. Module Control Register (CMCR1)
34-mscan
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MSCAN Controller (MSCAN08)
Programmer’s Model of Control Registers
LOOPB — Loop Back Self-Test Mode
When this bit is set, the MSCAN08 performs an internal loop back
which can be used for self-test operation: the bit stream output of the
transmitter is fed back to the receiver internally. The RxCAN input pin
is ignored and the TxCAN output goes to the recessive state (logic
‘1’). The MSCAN08 behaves as it does normally when transmitting
and treats its own transmitted message as a message received from
a remote node. In this state the MSCAN08 ignores the bit sent during
the ACK slot of the CAN frame Acknowledge field to insure proper
reception of its own message. Both transmit and receive interrupt are
generated.
1 = Activate loop back self-test mode
0 = Normal operation
WUPM — Wakeup Mode
This flag defines whether the integrated low-pass filter is applied to
protect the MSCAN08 from spurious wakeups (see Programmable
Wakeup Function on page 324).
1 = MSCAN08 will wake up the CPU only in cases of a dominant
pulse on the bus which has a length of at least twup
.
0 = MSCAN08 will wake up the CPU after any recessive to
dominant edge on the CAN bus.
CLKSRC — Clock Source
This flag defines which clock source the MSCAN08 module is driven
from (see Clock System on page 325).
1 = The MSCAN08 clock source is CGMOUT (see Figure 7).
0 = The MSCAN08 clock source is CGMXCLK/2 (see Figure 7).
NOTE: The CMCR1 register can be written only if the SFTRES bit in the
MSCAN08 module control register is set
35-mscan
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MSCAN Controlle r (MSCAN08)
MSCAN08 Bus
Address: $0502
Bit 7
Tim ing Re g iste r 0
6
SJW0
0
5
BRP5
0
4
BRP4
0
3
BRP3
0
2
BRP2
0
1
BRP1
0
Bit 0
BRP0
0
Read:
SJW1
Write:
Reset:
0
Figure 17. Bus Timing Register 0 (CBTR0)
SJW1 and SJW0 — Synchronization Jump Width
The synchronization jump width (SJW) defines the maximum number
of time quanta (Tq) clock cycles by which a bit may be shortened, or
lengthened, to achieve resynchronization on data transitions on the
bus (see Table 6).
Table 6. Synchronization Jump Width
SJW1
SJW0
Synchronization Jump Width
1 Tq cycle
0
0
1
1
0
1
0
1
2 Tq cycle
3 Tq cycle
4 Tq cycle
BRP5–BRP0 — Baud Rate Prescaler
These bits determine the time quanta (Tq) clock, which is used to build
up the individual bit timing, according toTable 7.
Table 7. Baud Rate Prescaler
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
Prescaler Value (P)
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
1
1
:
0
1
0
1
:
1
2
3
4
:
:
:
:
:
:
:
:
1
1
1
1
1
1
64
NOTE: The CBTR0 register can be written only if the SFTRES bit in the
MSCAN08 module control register is set.
36-mscan
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MSCAN Controller (MSCAN08)
Programmer’s Model of Control Registers
MSCAN08 Bus
Address: $0503
Bit 7
Tim ing Re g iste r 1
6
5
4
3
2
1
Bit 0
Read:
SAMP
Write:
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Reset:
0
0
0
0
0
0
0
0
Figure 18. Bus Timing Register 1 (CBTR1)
SAMP — Sampling
This bit determines the number of serial bus samples to be taken per
bit time. If set, three samples per bit are taken, the regular one
(sample point) and two preceding samples, using a majority rule. For
higher bit rates, SAMP should be cleared, which means that only one
sample will be taken per bit.
1 = Three samples per bit1
0 = One sample per bit
TSEG22–TSEG10 — Time Segment
Time segments within the bit time fix the number of clock cycles per
bit time and the location of the sample point.
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are
programmable as shown in Table 9.
Table 8. Time Segment Values
Time
Segment 1
Time
Segment 2
TSEG13 TSEG12 TSEG11 TSEG10
TSEG22 TSEG21 TSEG20
0
0
0
0
0
0
0
0
1
0
1
0
1 Tq Cycle(1)
2 Tq Cycles(1)
3Tq Cycles(1)
0
0
.
0
0
.
0
1
.
1 Tq Cycle(1)
2 Tq Cycles
.
0
.
0
.
1
.
1
.
4 Tq Cycles
.
.
.
.
1
1
1
8Tq Cycles
.
.
.
.
.
.
1
1
1
1
16 Tq Cycles
1. This setting is not valid. Please refer to Table 4 for valid settings.
1. In this case PHASE_SEG1 must be at least 2 time quanta.
37-mscan
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MSCAN Controlle r (MSCAN08)
The bit time is determined by the oscillator frequency, the baud rate
prescaler, and the number of time quanta (Tq) clock cycles per bit as
shown in Table 9).
Pres value
Bit time=
• number of Time Quanta
fMSCANCLK
NOTE: The CBTR1 register can only be written if the SFTRES bit in the
MSCAN08 module control register is set.
MSCAN08
All bits of this register are read and clear only. A flag can be cleared by
Re c e ive r Fla g
Re g iste r (CRFLG)
writing a 1 to the corresponding bit position. A flag can be cleared only
when the condition which caused the setting is valid no more. Writing a
0 has no effect on the flag setting. Every flag has an associated interrupt
enable flag in the CRIER register. A hard or soft reset will clear the
register.
Address: $0504
Bit 7
6
5
4
3
2
1
OVRIF
0
Bit 0
RXF
0
Read:
Write:
Reset:
WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF
0
0
0
0
0
0
Figure 19. Receiver Flag Register (CRFLG)
WUPIF — Wakeup Interrupt Flag
If the MSCAN08 detects bus activity while in Sleep mode, it sets the
WUPIF flag. If not masked, a wake-up interrupt is pending while this
flag is set.
1 = MSCAN08 has detected activity on the bus and requested
wake-up.
0 = No wake-up interrupt has occurred.
38-mscan
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MSCAN Controller (MSCAN08)
Programmer’s Model of Control Registers
RWRNIF — Receiver Warning Interrupt Flag
This flag is set when the MSCAN08 goes into warning status due to
the receive error counter (REC) exceeding 96 and neither one of the
Error Interrupt flags or the Bus-off Interrupt flag is set1. If not masked,
an error interrupt is pending while this flag is set.
1 = MSCAN08 has gone into receiver warning status.
0 = No receiver warning status hasbeen reached.
TWRNIF — Transmitter Warning Interrupt Flag
This flag is set when the MSCAN08 goes into warning status due to
the transmit error counter (TEC) exceeding 96 and neither one of the
error interrupt flags or the bus-off interrupt flag is set2. If not masked,
an error interrupt is pending while this flag is set.
1 = MSCAN08 has gone into transmitter warning status.
0 = No transmitter warning status has been reached.
RERRIF — Receiver Error Passive Interrupt Flag
This flag is set when the MSCAN08 goes into error passive status due
to the receive error counter exceeding 127 and the bus-off interrupt
flag is not set3. If not masked, an Error interrupt is pending while this
flag is set.
1 = MSCAN08 has gone into receiver error passive status.
0 = No receiver error passive atatus has been reached.
TERRIF — Transmitter Error Passive Interrupt Flag
This flag is set when the MSCAN08 goes into error passive status due
to the Transmit Error counter exceeding 127 and the Bus-off interrupt
flag is not set4. If not masked, an Error interrupt is pending while this
flag is set.
1 = MSCAN08 went into transmit error passive status.
0 = No transmit error passive atatus has been reached.
1. Condition to set the flaf: RWRNIF = (96 ð REC) & RERRIF & TERRIF & BOFFIF
2. Condition to set the flaf: TWRNIF = (96 ð TEC) & RERRIF & TERRIF & BOFFIF
3. Condition to set the flaf: RERRIF = (127 ð REC ð 255) & BOFFIF
4. Condition to set the flaf: TERRIF = (128 ð TEC ð 255) & BOFFIF
39-mscan
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MSCAN Controlle r (MSCAN08)
BOFFIF — Bus-Off Interrupt Flag
This flag is set when the MSCAN08 goes into bus-off status, due to
the transmit error counter exceeding 255. It cannot be cleared before
the MSCAN08 has monitored 128 times 11 consecutive ‘recessive’
bits on the bus. If not masked, an Error interrupt is pending while this
flag is set.
1 = MSCAN08has gone into bus-off status.
0 = No bus-off status has bee reached.
OVRIF — Overrun Interrupt Flag
This flag is set when a data overrun condition occurs. If not masked,
an error interrupt is pending while this flag is set.
1 = A data overrun has been detected since last clearing the flag.
0 = No data overrun has occurred.
RXF — Receive Buffer Full
The RXF flag is set by the MSCAN08 when a new message is
available in the foreground receive buffer. This flag indicates whether
the buffer is loaded with a correctly received message. After the CPU
has read that message from the receive buffer the RXF flag must be
cleared to release the buffer. A set RXF flag prohibits the exchange
of the background receive buffer into the foreground buffer. If not
masked, a receive interrupt is pending while this flag is set.
1 = The receive buffer is full. A new message is available.
0 = The receive buffer is released (not full).
NOTE: To ensure data integrity, no registers of the receive buffer shall be read
while the RXF flag is cleared.
NOTE: The CRFLG register is held in the reset state when the SFTRES bit in
CMCR0 is set.
40-mscan
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MSCAN Controller (MSCAN08)
Programmer’s Model of Control Registers
MSCAN08
Re c e ive r Inte rrup t
Ena b le Re g iste r
Address: $0505
Bit 7
6
5
4
3
2
1
OVRIE
0
Bit 0
RXFIE
0
Read:
WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE
Write:
Reset:
0
0
0
0
0
0
Figure 20. Receiver Interrupt Enable Register (CRIER)
WUPIE — Wakeup Interrupt Enable
1 = A wakeup event will result in a wakeup interrupt.
0 = No interrupt will be generated from this event.
RWRNIE — Receiver Warning Interrupt Enable
1 = A receiver warning status event will result in an error interrupt.
0 = No interrupt is generated from this event.
TWRNIE — Transmitter Warning Interrupt Enable
1 = A transmitter warning status event will result in an error
interrupt.
0 = No interrupt is generated from this event.
RERRIE — Receiver Error Passive Interrupt Enable
1 = A receiver error passive status event will result in an error
interrupt.
0 = No interrupt is generated from this event.
TERRIE — Transmitter Error Passive Interrupt Enable
1 = A transmitter error passive status event will result in an error
interrupt.
0 = No interrupt is generated from this event.
BOFFIE — Bus-Off Interrupt Enable
1 = A bus-off event will result in an error interrupt.
0 = No interrupt is generated from this event.
OVRIE — Overrun Interrupt Enable
1 = An overrun event will result in an error interrupt.
0 = No interrupt is generated from this event.
41-mscan
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MSCAN Controlle r (MSCAN08)
RXFIE — Receiver Full Interrupt Enable
1 = A receive buffer full (successful message reception) event will
result in a receive interrupt.
0 = No interrupt will be generated from this event.
NOTE: The CRIER register is held in the reset state when the SFTRES bit in
CMCR0 is set.
MSCAN08
The Abort Acknowledge flags are read only. The Transmitter Buffer
Tra nsm itte r Fla g
Re g iste r
Empty flags are read and clear only. A flag can be cleared by writing a 1
to the corresponding bit position. Writing a 0 has no effect on the flag
setting. The Transmitter Buffer Empty flags each have an associated
interrupt enablebit in the CTCR register. A hard or soft reset will resets
the register.
Address: $0506
Bit 7
5
6
5
4
3
0
2
TXE2
1
1
TXE1
1
Bit 0
TXE0
1
Read:
Write:
Reset:
0
ABTAK2 ABTAK1 ABTAK0
0
0
0
0
0
= Unimplemented
Figure 21. Transmitter Flag Register (CTFLG)
ABTAK2–ABTAK0 — Abort Acknowledge
This flag acknowledges that a message has been aborted due to a
pending abort request from the CPU. After a particular message
buffer has been flagged empty, this flag can be used by the
application software to identify whether the message has been
aborted successfully or has been sent. The ABTAKx flag is cleared
implicitly whenever the corresponding TXE flag is cleared.
1 = The message has been aborted.
0 = The message has not been aborted, thus has been sent out.
42-mscan
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Programmer’s Model of Control Registers
TXE2–TXE0 — Transmitter Empty
This flag indicates that the associated transmit message buffer is
empty, thus not scheduled for transmission. The CPU must
handshake (clear) the flag after a message has been set up in the
transmit buffer and is due for transmission. The MSCAN08 sets the
flag after the message has been sent successfully. The flag is also set
by the MSCAN08 when the transmission request was successfully
aborted due to a pending abort request (see Transmit Buffer
Priority Registers on page 334). If not masked, a receive interrupt is
pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx flag
(ABTAK, see above). When a TXEx flag is set, the corresponding
ABTRQx bit (ABTRQ, see MSCAN08 Transmitter Control Register
on page 348) is cleared.
1 = The associated message buffer is empty (not scheduled).
0 = The associated message buffer is full (loaded with a message
due for transmission).
NOTE: To ensure data integrity, no registers of the transmit buffers should be
written to while the associated TXE flag is cleared.
NOTE: The CTFLG register is held in the reset state when the SFTRES bit in
CMCR0 is set.
43-mscan
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MSCAN Controlle r (MSCAN08)
MSCAN08
Tra nsm itte rControl
Re g iste r
Address: $0507
Bit 7
6
5
4
3
0
2
1
Bit 0
Read:
Write:
Reset:
0
ABTRQ2 ABTRQ1 ABTRQ0
TXEIE2 TXEIE1 TXEIE0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 22. Transmitter Control Register (CTCR)
ABTRQ2–ABTRQ0 — Abort Request
The CPU sets an ABTRQx bit to request that an already scheduled
message buffer (TXE = 0) be aborted. The MSCAN08 will grant the
request if the message has not already started transmission, or if the
transmission is not successful (lost srbitration or error). When a
message is aborted the associated TXE and the abort acknowledge
flag (ABTAK) (see MSCAN08 Transmitter Flag Register on page
346) will be set and an TXE interrupt is generated if enabled. The
CPU cannot reset ABTRQx. ABTRQx is cleared implicitly whenever
the associated TXE flag is set.
1 = Abort request pending
0 = No abort request
NOTE: The software must not clear one or more of the TXE flags in CTFLG and
simultaneaously set the respective ABTRQ bit(s).
TXEIE2–TXEIE0 — Transmitter Empty Interrupt Enable
1 = A transmitter empty (transmit buffer available for transmission)
event results in a transmitter empty interrupt.
0 = No interrupt is generated from this event.
NOTE: The CTCR register is held in the reset state when the SFTRES bit in
CMCR0 is set.
44-mscan
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MSCAN Controller (MSCAN08)
Programmer’s Model of Control Registers
MSCAN08
Address: $0508
Bit 7
Id e ntifie r
Ac c e p ta nc e
Control Re g iste r
6
0
5
IDAM1
0
4
IDAM0
0
3
0
2
0
1
Bit 0
Read:
Write:
Reset:
0
IDHIT1
IDHIT0
0
0
0
0
0
0
= Unimplemented
Figure 23. Identifier Acceptance Control Register (CIDAC)
IDAM1–IDAM0— Identifier Acceptance Mode
The CPU sets these flags to define the identifier acceptance filter
organization (see Identifier Acceptance Filter on page 314). Table 9
summarizes the different settings. In “filter closed” mode no messages
will be accepted so that the foreground buffer will never be reloaded.
Table 9. Identifier Acceptance Mode Settings
IDAM1
IDAM0
Identifier Acceptance Mode
Single 32-Bit Acceptance Filter
Two 16-Bit Acceptance Filter
Four 8-Bit Acceptance Filters
Filter Closed
0
0
1
1
0
1
0
1
IDHIT1–IDHIT0— Identifier Acceptance Hit Indicator
The MSCAN08 sets these flags to indicate an identifier acceptance hit
(see Identifier Acceptance Filter on page 314). Table 9 summarizes
the different settings.
Table 10. Identifier Acceptance Hit Indication
IDHIT1
IDHIT0
Identifier Acceptance Hit
Filter 0 Hit
0
0
1
1
0
1
0
1
Filter 1 Hit
Filter 2 Hit
Filter 3 Hit
45-mscan
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MSCAN Controlle r (MSCAN08)
The IDHIT indicators are always related to the message in the
foreground buffer. When a message gets copied from the background to
the foreground buffer, the indicators are updated as well.
NOTE: The CIDAC register can be written only if the SFTRES bit in the CMCR0
is set.
MSCAN08 Re c e ive
Error Counte r
Address: $050E
Bit 7
6
5
4
3
2
1
Bit 0
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 24. Receiver Error Counter (CRXERR)
This register reflects the status of the MSCAN08 receive error counter.
The register is read only.
MSCAN08 Tra nsm it
Error Counte r
Address: $050F
Bit 7
6
5
4
3
2
1
Bit 0
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 25. Transmit Error Counter (CTXERR)
This register reflects the status of the MSCAN08 transmit error counter.
The register is read only.
NOTE: Both error counters may only be read when in Sleep or Soft Reset mode.
46-mscan
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MSCAN Controller (MSCAN08)
Programmer’s Model of Control Registers
MSCAN08
Id e ntifie r
Ac c e p ta nc e
Re g iste rs
On reception each message is written into the background receive
buffer. The CPU is only signalled to read the message, however, if it
passes the criteria in the identifier acceptance and identifier mask
registers (accepted); otherwise, the message will be overwritten by the
next message (dropped).
The acceptance registers of the MSCAN08 are applied on the IDR0 to
IDR3 registers of incoming messages in a bit by bit manner.
For extended identifiers, all four acceptance and mask registers are
applied. For standard identifiers only the first two (CIDMR0/1 and
CIDAR0/1) are applied.
CIDAR0
Address: $0510
Bit 7
6
5
4
3
2
1
Bit 0
AC0
Read:
Write:
Reset:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
Unaffected by Reset
CIDAR1 Address: $050511
Bit 7
6
5
4
3
2
1
Bit 0
AC0
Read:
Write:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
Reset:
Unaffected by Reset
CIDAR2
Address: $0512
Bit 7
6
5
4
3
2
1
Bit 0
AC0
Read:
Write:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
Reset:
Unaffected by Reset
CIDAR3
Address: $0513
Bit 7
6
5
4
3
2
1
Bit 0
AC0
Read:
Write:
Reset:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
Unaffected by Reset
Figure 26. Identifier Acceptance Registers (CIDAR0–CIDAR3)
47-mscan
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MSCAN Controlle r (MSCAN08)
AC7–AC0 — Acceptance Code Bits
AC7–AC0 comprise a user-defined sequence of bits with which the
corresponding bits of the related identifier register (IDRn) of the
receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
NOTE: The CIDAR0–3 registers can be written only if the SFTRES bit in
CMCR0 is set
MSCAN08
The identifier mask registers specify which of the corresponding bits in
Id e ntifie r Ma sk
Re g iste rs
(CIDMR0-3)
the identifier acceptance register are relevant for acceptance filtering.
For standatd identifiers it is required to program thelast three bits
(AM2-AM0) in the mask register CIDMR1 to ‘don’t care’.
CIDMRO
Address: $0514
Bit 7
6
5
4
3
2
1
Bit 0
AM0
Read:
Write:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
Reset:
Unaffected by Reset
CIDMR1
Address: $0515
Bit 7
6
5
4
3
2
1
Bit 0
AM0
Read:
Write:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
Reset:
Unaffected by Reset
CIDMR2
Address: $0516
Bit 7
6
5
4
3
2
1
Bit 0
AM0
Read:
Write:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
Reset:
Unaffected by Reset
CIDMR3
Address: $0517
Bit 7
6
5
4
3
2
1
Bit 0
AM0
Read:
Write:
Reset:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
Unaffected by Reset
Figure 27. Identifier Mask Registers (CIDMR0–CIDMR3)
48-mscan
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MSCAN Controller (MSCAN08)
Programmer’s Model of Control Registers
AM7–AM0 — Acceptance Mask Bits
If a particular bit in this register is cleared, this indicates that the
corresponding bit in the identifier acceptance register must be the
same as its identifier bit before a match will be detected. The
message will be accepted if all such bits match. If a bit is set, it
indicates that the state of the corresponding bit in the identifier
acceptance register will not affect whether or not the message is
accepted.
1 = Ignore corresponding acceptance code register bit.
0 = Match corresponding acceptance code register and identifier
bits.
NOTE: The CIDMR0-3 registers can be written only if the SFTRES bit in the
CMCR0 is set
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MSCAN Controlle r (MSCAN08)
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Ke yb oa rd Mod ule (KBD)
Ke yb oa rd Mod ule (KBD)
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . 360
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Keyboard Status and Control Register . . . . . . . . . . . . . . . . . . . . . 361
Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . 362
Introd uc tion
The keyboard interrupt module (KBD) provides five independently
maskable external interrupt pins.
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Ke yb oa rd Mod ule (KBD)
Fe a ture s
KBD features include:
• Five Keyboard Interrupt Pins with Separate Keyboard Interrupt
Enable Bits and One Keyboard Interrupt Mask
• Hysteresis Buffers
• Programmable Edge-Only or Edge- and Level- Interrupt Sensitivity
• Automatic Interrupt Acknowledge
• Exit from Low-Power Modes
Func tiona l De sc rip tion
Writing to the KBIE4–KBIE0 bits in the keyboard interrupt enable register
independently enables or disables each port G or port H pin as a
keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its
internal pullup device. A logic 0 applied to an enabled keyboard interrupt
pin latches a keyboard interrupt request.
A keyboard interrupt is latched when one or more keyboard pins goes
low after all were high. The MODEK bit in the keyboard status and
control register controls the triggering mode of the keyboard interrupt.
• If the keyboard interrupt is edge-sensitive only, a falling edge on a
keyboard pin does not latch an interrupt request if another
keyboard pin is already low. To prevent losing an interrupt request
on one pin because another pin is still low, software can disable
the latter pin while it is low.
• If the keyboard interrupt is falling edge- and low level-sensitive, an
interrupt request is present as long as any keyboard pin is low.
2-kbd
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Keyboard Module (KBD)
Functional Description
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Ke yb oa rd Mod ule (KBD)
If the MODEK bit is set, the keyboard interrupt pins are both falling edge-
and low level-sensitive, and both of the following actions must occur to
clear a keyboard interrupt request:
• Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the interrupt request.
Software may generate the interrupt acknowledge signal by
writing a logic 1 to the ACKK bit in the keyboard status and control
register (KBSCR). The ACKK bit is useful in applications that poll
the keyboard interrupt pins and require software to clear the
keyboard interrupt request. Writing to the ACKK bit prior to leaving
an interrupt service routine also can prevent spurious interrupts
due to noise. Setting ACKK does not affect subsequent transitions
on the keyboard interrupt pins. A falling edge that occurs after
writing to the ACKK bit latches another interrupt request. If the
keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the
program counter with the vector address at locations $FFDE and
$FFDF.
• Return of all enabled keyboard interrupt pins to logic 1. As long as
any enabled keyboard interrupt pin is at logic 0, the keyboard
interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard
interrupt pins to logic 1 may occur in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling
edge-sensitive only. With MODEK clear, a vector fetch or software clear
immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing
the interrupt request even if a keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register
can be used to see if a pending interrupt exists. The KEYF bit is not
affected by the keyboard interrupt mask bit (IMASKK) which makes it
useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data
direction register to configure the pin as an input and read the data
register.
4-kbd
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Keyboard Module (KBD)
Keyboard Initialization
NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction
register. However, the data direction register bit must be a logic 0 for
software to read the pin.
Ke yb oa rd Initia liza tion
When a keyboard interrupt pin is enabled, it takes time for the internal
pullup to reach a logic 1. Therefore, a false interrupt can occur as soon
as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the
keyboard status and control register
2. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register
3. Write to the ACKK bit in the keyboard status and control register
to clear any false interrupts
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged
immediately after enabling the pin. An interrupt signal on an edge- and
level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate
DDRG bits in data direction register G.
2. Configure the keyboard pins as outputs by setting the appropriate
DDRH bits in data direction register H.
3. Write logic 1s to the appropriate port G and port H data register
bits.
4. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
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Ke yb oa rd Mod ule (KBD)
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in
low-power-consumption standby modes.
Wa it Mod e
Stop Mod e
The keyboard module remains active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.
The keyboard module remains active in stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of stop mode.
Ke yb oa rd Mod ule During Bre a k Inte rrup ts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. See Break Module on page
135.
To allow software to clear the KEYF bit during a break interrupt, write a
logic 1 to the BCFE bit. If KEYF is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the KEYF bit during the break state, write a logic 0 to the
BCFE bit. With BCFE at logic 0, writing to the keyboard acknowledge bit
(ACKK) in the keyboard status and control register during the break state
has no effect. See Keyboard Status and Control Register on page
361.
6-kbd
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Keyboard Module (KBD)
I/O Registers
I/ O Re g iste rs
The following registers control and monitor operation of the keyboard
module:
• Keyboard status and control register (KBSCR)
• Keyboard interrupt enable register (KBIER)
Ke yb oa rd Sta tus
a nd Control
Re g iste r
The keyboard status and control register:
• Flags keyboard interrupt requests
• Acknowledges keyboard interrupt requests
• Masks keyboard interrupt requests
• Controls keyboard interrupt triggering sensitivity
Address: $001A
Bit 7
0
6
0
5
0
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
KEYF
0
ACKK
0
IMASKK MODEK
0
0
0
0
0
0
0
= Unimplemented
Figure 3. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as logic 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending. Reset
clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
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Ke yb oa rd Mod ule (KBD)
ACKK — Keyboard Acknowledge Bit
Writing a logic 1 to this write-only bit clears the keyboard interrupt
request. ACKK always reads as logic 0. Reset clears ACKK.
IMASKK — Keyboard Interrupt Mask Bit
Writing a logic 1 to this read/write bit prevents the output of the
keyboard interrupt mask from generating interrupt requests. Reset
clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard
interrupt pins. Reset clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
Ke yb oa rd
Inte rrup t Ena b le
Re g iste r
The keyboard interrupt enable register enables or disables each port G
and each port H pin to operate as a keyboard interrupt pin.
Address: $001B
Bit 7
0
6
0
5
0
4
KBIE4
0
3
KBIE3
0
2
KBIE2
0
1
KBIE1
0
Bit 0
KBIE0
0
Read:
Write:
Reset:
0
0
0
= Unimplemented
Figure 4. Keyboard Interrupt Enable Register (KBIER)
KBIE4–KBIE0 — Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard
interrupt pin to latch interrupt requests. Reset clears the keyboard
interrupt enable register.
1 = PDx pin enabled as keyboard interrupt pin
0 = PDx pin not enabled as keyboard interrupt pin
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Tim e r Inte rfa c e Mod ule A (TIMA-6)
Tim e r Inte rfa c e Mod ule A (TIMA-6)
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
TIMA Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . 372
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . 373
PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
TIMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
TIMA Clock Pin (PTD6/ATD14/ TCLK) . . . . . . . . . . . . . . . . . . . . . 379
TIMA Channel I/O Pins (PTF3–PTF0/TACH2 and
PTE3/TACH1–PTE2/TACH0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
TIMA Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . 380
TIMA Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
TIMA Counter Modulo Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 383
TIMA Channel Status and Control Registers . . . . . . . . . . . . . . . . 384
TIMA Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
1-tima-6
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Tim e r Inte rfa c e Mod ule A (TIMA-6)
Introd uc tion
This section describes the timer interface module (TIMA). The TIMA is a
6-channel timer that provides a timing reference with input capture,
output compare, and pulse-width-modulation functions. Figure 1 is a
block diagram of the TIMA.
Fe a ture s
Features of the TIMA include:
• Six Input Capture/Output Compare Channels
– Rising-Edge, Falling-Edge, or Any-Edge Input Capture Trigger
– Set, Clear, or Toggle Output Compare Action
• Buffered and Unbuffered Pulse Width Modulation (PWM) Signal
Generation
• Programmable TIMA Clock Input
– 7-Frequency Internal Bus Clock Prescaler Selection
– External TIMA Clock Input (4-MHz Maximum Frequency)
• Free-Running or Modulo Up-Count Operation
• Toggle Any Channel Pin on Overflow
• TIMA Counter Stop and Reset Bits
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Timer Interface Module A (TIMA-6)
Features
TCLK
PTD6/TACLK
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
TRST
PS2
PS1
PS0
16-BIT COUNTER
INTER-
RUPT
LOGIC
TOF
TOIE
16-BIT COMPARATOR
TMODH:TMODL
ELS0B
ELS0A
ELS1A
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
TOV0
CH0MAX
PTE2
LOGIC
PTE2/TACH0
CH0F
MS0B
INTER-
RUPT
LOGIC
16-BIT LATCH
CH0IE
MS0A
ELS1B
ELS2B
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
TOV1
CH1MAX
PTE3
LOGIC
PTE3/TACH1
CH1F
INTER-
RUPT
LOGIC
16-BIT LATCH
CH1IE
MS1A
ELS2A
CHANNEL 2
16-BIT COMPARATOR
TCH2H:TCH2L
TOV2
CH2MAX
PTF0
PTF0/TACH2
PTF1/TACH3
LOGIC
CH2F
MS2B
INTER-
RUPT
LOGIC
16-BIT LATCH
CH2IE
MS2A
ELS3B
ELS4B
ELS3A
CHANNEL 3
16-BIT COMPARATOR
TCH3H:TCH3L
TOV3
CH3MAX
PTF1
LOGIC
CH3F
INTER-
RUPT
16-BIT LATCH
LOGIC
CH3IE
MS3A
ELS4A
CHANNEL 4
16-BIT COMPARATOR
TCH4H:TCH4L
TOV4
CH5MAX
PTF2
LOGIC
PTF2
PTF3
CH4F
MS4B
INTER-
RUPT
LOGIC
16-BIT LATCH
CH4IE
MS4A
ELS5B
ELS5A
CHANNEL 5
16-BIT COMPARATOR
TCH5H:TCH5L
TOV5
CH5MAX
PTF3
LOGIC
CH5F
INTER-
RUPT
LOGIC
16-BIT LATCH
CH5IE
MS5A
Figure 1. TIMA Block Diagram
3-tima-6
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Tim e r Inte rfa c e Mod ule A (TIMA-6)
Addr.
$0020
$0021
$0022
$0023
Register Name
TIMA Status/Control Register (TASC) TOF
Reserved
Bit 7
6
5
4
3
0
2
PS2
R
1
PS1
R
Bit 0
PS0
R
TOIE TSTOP TRST
R
R
14
6
R
13
5
R
12
4
R
11
3
TIMA Counter Register High (TACNTH) Bit 15
TIMA Counter Register Low (TACNTL) Bit 7
10
2
9
Bit 8
Bit 0
Bit 8
Bit 0
1
$0024 TIMA Counter Modulo Reg. High (TAMODH) Bit 15
$0025 TIMA Counter Modulo Reg. Low (TAMODL) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
$0026 TIMA Ch. 0 Status/Control Register (TASC0) CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
$0027
$0028
TIMA Ch. 0 Register High (TACH0H) Bit 15
TIMA Ch. 0 Register Low (TACH0L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
$0029 TIMA Ch. 1 Status/Control Register (TASC1) CH1F CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
$002A
$002B
TIMA Ch. 1 Register High (TACH1H) Bit 15
TIMA Ch. 1 Register Low (TACH1L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
$002C TIMA Ch. 2 Status/Control Register (TASC2) CH2F CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX
$002D
$002E
TIMA Ch. 2 Register High (TACH2H) Bit 15
TIMA Ch. 2 Register Low (TACH2L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
$002F TIMA Ch. 3 Status/Control Register (TASC3) CH3F CH3IE
0
MS3A ELS3B ELS3A TOV3 CH3MAX
$0030
$0031
TIMA Ch. 3 Register High (TACH3H) Bit 15
TIMA Ch. 3 Register Low (TACH3L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
$0032 TIMA Ch. 4 Status/Control Register (TASC4) CH4F CH4IE MS4B MS4A ELS4B ELS4A TOV4 CH4MAX
$0033
$0034
TIMA Ch. 4 Register High (TACH4H) Bit 15
TIMA Ch. 4 Register Low (TACH4L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
$0035 TIMA Ch. 5 Status/Control Register (TASC5) CH5F CH5IE
0
MS5A ELS5B ELS5A TOV5 CH5MAX
$0036
$0037
TIMA Ch. 5 Register High (TACH5H) Bit 15
TIMA Ch. 5 Register Low (TACH5L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
R
=Reserved
Figure 2. TIMA I/O Register Summary
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Functional Description
Func tiona l De sc rip tion
Figure 1 shows the TIMA structure. The central component of the TIMA
is the 16-bit TIMA counter that can operate as a free-running counter or
a modulo up-counter. The TIMA counter provides the timing reference
for the input capture and output compare functions. The TIMA counter
modulo registers, TAMODH–TAMODL, control the modulo value of the
TIMA counter. Software can read the TIMA counter value at any time
without affecting the counting sequence.
The six TIMA channels are programmable independently as input
capture or output compare channels.
TIMA Counte r
Pre sc a le r
The TIMA clock source can be one of the seven prescaler outputs or the
TIMA clock pin, PTD6/TACLK. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS[2:0], in
the TIMA status and control register select the TIMA clock source.
Inp ut Ca p ture
An input capture function has three basic parts: edge select logic, an
input capture latch, and a 16-bit counter. Two 8-bit registers, which make
up the 16-bit input capture register, are used to latch the value of the
free-running counter after the corresponding input capture edge detector
senses a defined transition. The polarity of the active edge is
programmable. The level transition which triggers the counter transfer is
defined by the corresponding input edge bits (ELSxB and ELSxA in
TASC0 through TASC5 control registers with x referring to the active
channel number). When an active edge occurs on the pin of an input
capture channel, the TIMA latches the contents of the TIMA counter into
the TIMA channel registers, TACHxH–TACHxL. Input captures can
generate TIMA CPU interrupt requests. Software can determine that an
input capture event has occurred by enabling input capture interrupts or
by polling the status flag bit.
The result obtained by an input capture will be two more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization.
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The free-running counter contents are transferred to the TIMA channel
status and control register (TACHxH–TACHxL, see TIMA Channel
Registers on page 390), on each proper signal transition regardless of
whether the TIMA channel flag (CH0F–CH5F in TASC0–TASC5
registers) is set or clear. When the status flag is set, a CPU interrupt is
generated if enabled. The value of the count latched or “captured” is the
time of the event. Because this value is stored in the input capture
register 2 bus cycles after the actual event occurs, user software can
respond to this event at a later time and determine the actual time of the
event. However, this must be done prior to another input capture on the
same pin; otherwise, the previous time value will be lost.
By recording the times for successive edges on an incoming signal,
software can determine the period and/or pulse width of the signal. To
measure a period, two successive edges of the same polarity are
captured. To measure a pulse width, two alternate polarity edges are
captured. Software should track the overflows at the 16-bit module
counter to extend its range.
Another use for the input capture function is to establish a time
reference. In this case, an input capture function is used in conjunction
with an output compare function. For example, to activate an output
signal a specified number of clock cycles after detecting an input event
(edge), use the input capture function to record the time at which the
edge occurred. A number corresponding to the desired delay is added to
this captured value and stored to an output compare register (see TIMA
Channel Registers on page 390). Because both input captures and
output compares are referenced to the same 16-bit modulo counter, the
delay can be controlled to the resolution of the counter independent of
software latencies.
Reset does not affect the contents of the input capture channel register
(TACHxH–TACHxL).
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Functional Description
Outp ut Com p a re
With the output compare function, the TIMA can generate a periodic
pulse with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIMA can set, clear, or toggle the channel pin. Output compares can
generate TIMA CPU interrupt requests.
Unb uffe re d
Outp ut Co m p a re
Any output compare channel can generate unbuffered output compare
pulses as described in Output Compare on page 369. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIMA channel registers.
An unsynchronized write to the TIMA channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIMA overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIMA may
pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
• When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
• When changing to a larger output compare value, enable channel
x TIMA overflow interrupts and write the new value in the TIMA
overflow interrupt routine. The TIMA overflow interrupt occurs at
the end of the current counter overflow period. Writing a larger
value in an output compare interrupt routine (at the end of the
current pulse) could cause two output compares to occur in the
same counter overflow period.
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Buffe re d Outp ut
Co m p a re
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the PTE2/TACH0 pin. The TIMA
channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMA channel 0 status and control register
(TASC0) links channel 0 and channel 1. The output compare value in the
TIMA channel 0 registers initially controls the output on the
PTE2/TACH0 pin. Writing to the TIMA channel 1 registers enables the
TIMA channel 1 registers to synchronously control the output after the
TIMA overflows. At each subsequent overflow, the TIMA channel
registers (0 or 1) that control the output are the ones written to last.
TASC0 controls and monitors the buffered output compare function, and
TIMA channel 1 status and control register (TASC1) is unused. While the
MS0B bit is set, the channel 1 pin, PTE3/TACH1, is available as a
general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered output compare
channel whose output appears on the PTF0/TACH2 pin. The TIMA
channel registers of the linked pair alternately control the output.
Setting the MS2B bit in TIMA channel 2 status and control register
(TASC2) links channel 2 and channel 3. The output compare value in the
TIMA channel 2 registers initially controls the output on the
PTF0/TACH2 pin. Writing to the TIMA channel 3 registers enables the
TIMA channel 3 registers to synchronously control the output after the
TIMA overflows. At each subsequent overflow, the TIMA channel
registers (2 or 3) that control the output are the ones written to last.
TASC2 controls and monitors the buffered output compare function, and
TIMA channel 3 status and control register (TASC3) is unused. While the
MS2B bit is set, the channel 3 pin, PTF1/TACH3, is available as a
general-purpose I/O pin.
Channels 4 and 5 can be linked to form a buffered output compare
channel whose output appears on the PTF2 pin. The TIMA channel
registers of the linked pair alternately control the output.
Setting the MS4B bit in TIMA channel 4 status and control register
(TSC4) links channel 4 and channel 5. The output compare value in the
TIMA channel 4 registers initially controls the output on the PTF2 pin.
Writing to the TIMA channel 5 registers enables the TIMA channel 5
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Functional Description
registers to synchronously control the output after the TIMA overflows.
At each subsequent overflow, the TIMA channel registers (4 or 5) that
control the output are the ones written to last. TASC4 controls and
monitors the buffered output compare function, and TIMA channel 5
status and control register (TASC5) is unused. While the MS4B bit is set,
the channel 5 pin, PTF3, is available as a general-purpose I/O pin.
NOTE: In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output
compares.
Pulse Wid th
By using the toggle-on-overflow feature with an output compare channel,
Mod ula tion (PWM)
the TIMA can generate a PWM signal. The value in the TIMA counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIMA counter
modulo registers. The time between overflows is the period of the PWM
signal.
As Figure 3 shows, the output compare value in the TIMA channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIMA to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIMA to set the pin if the state of the PWM
pulse is logic 0.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 3. PWM Period and Pulse Width
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The value in the TIMA counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIMA counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000 (see TIMA Status and Control Register on page 380).
The value in the TIMA channel registers determines the pulse width of
the PWM output. The pulse width of an 8-bit PWM signal is variable in
256 increments. Writing $0080 (128) to the TIMA channel registers
produces a duty cycle of 128/256 or 50%.
Unb uffe re d PWM
Sig na l Ge ne ra tio n
Any output compare channel can generate unbuffered PWM pulses as
described in Pulse Width Modulation (PWM) on page 371. The pulses
are unbuffered because changing the pulse width requires writing the
new pulse width value over the value currently in the TIMA channel
registers.
An unsynchronized write to the TIMA channel registers to change a
pulse width value could cause incorrect operation for up to two PWM
periods. For example, writing a new value before the counter reaches
the old value but after the counter reaches the new value prevents any
compare during that PWM period. Also, using a TIMA overflow interrupt
routine to write a new, smaller pulse width value may cause the compare
to be missed. The TIMA may pass the new value before it is written to
the TIMA channel registers.
Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
• When changing to a longer pulse width, enable channel x TIMA
overflow interrupts and write the new value in the TIMA overflow
interrupt routine. The TIMA overflow interrupt occurs at the end of
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Functional Description
the current PWM period. Writing a larger value in an output
compare interrupt routine (at the end of the current pulse) could
cause two output compares to occur in the same PWM period.
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
Buffe re d PWM
Sig na l Ge ne ra tio n
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the PTE2/TACH0 pin. The TIMA channel registers of
the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIMA channel 0 status and control register
(TASC0) links channel 0 and channel 1. The TIMA channel 0 registers
initially control the pulse width on the PTE2/TACH0 pin. Writing to the
TIMA channel 1 registers enables the TIMA channel 1 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMA channel registers (0 or
1) that control the pulse width are the ones written to last. TASC0
controls and monitors the buffered PWM function, and TIMA channel 1
status and control register (TASC1) is unused. While the MS0B bit is set,
the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O
pin.
Channels 2 and 3 can be linked to form a buffered PWM channel whose
output appears on the PTF0/TACH2 pin. The TIMA channel registers of
the linked pair alternately control the pulse width of the output.
Setting the MS2B bit in TIMA channel 2 status and control register
(TASC2) links channel 2 and channel 3. The TIMA channel 2 registers
initially control the pulse width on the PTF0/TACH2 pin. Writing to the
TIMA channel 3 registers enables the TIMA channel 3 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMA channel registers (2 or
3) that control the pulse width are the ones written to last. TASC2
controls and monitors the buffered PWM function, and TIMA channel 3
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status and control register (TASC3) is unused. While the MS2B bit is set,
the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O
pin.
Channels 4 and 5 can be linked to form a buffered PWM channel whose
output appears on the PTF2 pin. The TIMA channel registers of the
linked pair alternately control the pulse width of the output.
Setting the MS4B bit in TIMA channel 4 status and control register
(TASC4) links channel 4 and channel 5. The TIMA channel 4 registers
initially control the pulse width on the PTF2 pin. Writing to the TIMA
channel 5 registers enables the TIMA channel 5 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMA channel registers (4 or
5) that control the pulse width are the ones written to last. TASC4
controls and monitors the buffered PWM function, and TIMA channel 5
status and control register (TASC5) is unused. While the MS4B bit is set,
the channel 5 pin, PTF3, is available as a general-purpose I/O pin.
NOTE: In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
PWM Initia liza tio n
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
1. In the TIMA status and control register (TASC):
a. Stop the TIMA counter by setting the TIMA stop bit, TSTOP.
b. Reset the TIMA counter by setting the TIMA reset bit, TRST.
2. In the TIMA counter modulo registers (TAMODH–TAMODL), write
the value for the required PWM period.
3. In the TIMA channel x registers (TACHxH–TACHxL), write the
value for the required pulse width.
4. In TIMA channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the mode
select bits, MSxB–MSxA. (See Table 2).
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Functional Description
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB–ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See Table 2.)
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIMA status control register (TASC), clear the TIMA stop bit,
TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMA channel 0 registers (TACH0H–TACH0L)
initially control the buffered PWM output. TIMA status control register 0
(TASC0) controls and monitors the PWM signal from the linked
channels. MS0B takes priority over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered
PWM operation. The TIMA channel 2 registers (TACH2H–TACH2L)
initially control the PWM output. TIMA status control register 2 (TASC2)
controls and monitors the PWM signal from the linked channels. MS2B
takes priority over MS2A.
Setting MS4B links channels 4 and 5 and configures them for buffered
PWM operation. The TIMA channel 4 registers (TACH4H–TACH4L)
initially control the PWM output. TIMA status control register 4 (TASC4)
controls and monitors the PWM signal from the linked channels. MS4B
takes priority over MS4A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on
TIMA overflows. Subsequent output compares try to force the output to
a state it is already in and have no effect. The result is a 0% duty cycle
output.
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Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. (See TIMA Channel
Status and Control Registers on page 384).
Inte rrup ts
The following TIMA sources can generate interrupt requests:
• TIMA overflow flag (TOF) — The TOF bit is set when the TIMA
counter value rolls over to $0000 after matching the value in the
TIMA counter modulo registers. The TIMA overflow interrupt
enable bit, TOIE, enables TIMA overflow CPU interrupt requests.
TOF and TOIE are in the TIMA status and control register.
• TIMA channel flags (CH5F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIMA CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
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Low-Power Modes
Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
Wa it Mod e
The TIMA remains active after the execution of a WAIT instruction. In
wait mode, the TIMA registers are not accessible by the CPU. Any
enabled CPU interrupt request from the TIMA can bring the MCU out of
wait mode.
If TIMA functions are not required during wait mode, reduce power
consumption by stopping the TIMA before executing the WAIT
instruction.
Stop Mod e
The TIMA is inactive after the execution of a STOP instruction. The
STOP instruction does not affect register conditions or the state of the
TIMA counter. TIMA operation resumes when the MCU exits stop mode.
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TIMA During Bre a k Inte rrup ts
A break interrupt stops the TIMA counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See SIM Break Flag Control
Register on page 103).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
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I/O Signals
I/ O Sig na ls
Port D shares one of its pins with the TIMA. Port E shares two of its pins
with the TIMA and port F shares four of its pins with the TIMA.
PTD6/TACLK is an external clock input to the TIMA prescaler. The six
TIMA channel I/O pins are PTE2/TACH0, PTE3/TACH1, PTF0/TACH2,
PTF1/TACH3, PTF2, and PTF3.
TIMA Cloc k Pin
(PTD6/ ATD14/
TCLK)
PTD6/TACLK is an external clock input that can be the clock source for
the TIMA counter instead of the prescaled internal bus clock. Select the
PTD6/TACLK input by writing logic 1s to the three prescaler select bits,
PS[2:0]. (See TIMA Status and Control Register.) The minimum TCLK
pulse width, TCLKLMIN or TCLKHMIN, is:
1
------------------------------------- + t SU
bus frequency
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD6/TACLK is available as a general-purpose I/O pin or ADC channel
when not used as the TIMA clock input. When the PTD6/TACLK pin is
the TIMA clock input, it is an input regardless of the state of the DDRD6
bit in data direction register D.
TIMA Cha nne l I/ O
Pins
(PTF3–PTF0/ TACH2
a nd
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE2/TACH0, PTE6/TACH2, and
PTF2 can be configured as buffered output compare or buffered PWM
pins.
PTE3/ TACH1–PTE2/
TACH0)
17-tima-6
MC68HC08AZ60 — Rev 1.0
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Tim e r Inte rfa c e Mod ule A (TIMA-6)
I/ O Re g iste rs
These I/O registers control and monitor TIMA operation:
• TIMA status and control register (TASC)
• TIMA control registers (TACNTH–TACNTL)
• TIMA counter modulo registers (TAMODH–TAMODL)
• TIMA channel status and control registers (TASC0, TASC1,
TASC2, TASC3, TASC4, and TSAC5)
• TIMA channel registers (TACH0H–TACH0L, TACH1H–TACH1L,
TACH2H–TACH2L, TACH3H–TACH3L, TACH4H–TACH4L, and
TACH5H–TACH5L)
TIMA Sta tus a nd
Control Re g iste r
The TIMA status and control register:
• Enables TIMA overflow interrupts
• Flags TIMA overflows
• Stops the TIMA counter
• Resets the TIMA counter
• Prescales the TIMA counter clock
Address: $0020
Bit 7
TOF
0
6
5
TSTOP
1
4
0
3
0
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
Write:
Reset:
TOIE
TRST
0
R
0
0
0
R
=Reserved
Figure 4. TIMA Status and Control Register (TASC)
18-tima-6
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Timer Interface Module A (TIMA-6)
I/O Registers
TOF — TIMA Overflow Flag Bit
This read/write flag is set when the TIMA counter resets to $0000 after
reaching the modulo value programmed in the TIMA counter modulo
registers. Clear TOF by reading the TIMA status and control register
when TOF is set and then writing a logic 0 to TOF. If another TIMA
overflow occurs before the clearing sequence is complete, then
writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset
clears the TOF bit. Writing a logic 1 to TOF has no effect.
1 = TIMA counter has reached modulo value.
0 = TIMA counter has not reached modulo value.
TOIE — TIMA Overflow Interrupt Enable Bit
This read/write bit enables TIMA overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIMA overflow interrupts enabled
0 = TIMA overflow interrupts disabled
TSTOP — TIMA Stop Bit
This read/write bit stops the TIMA counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMA
counter until software clears the TSTOP bit.
1 = TIMA counter stopped
0 = TIMA counter active
NOTE: Do not set the TSTOP bit before entering wait mode if the TIMA is
required to exit wait mode. Also, when the TSTOP bit is set and input
capture mode is enabled, input captures are inhibited until TSTOP is
cleared.
TRST — TIMA Reset Bit
Setting this write-only bit resets the TIMA counter and the TIMA
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIMA counter is reset and always reads as logic 0. Reset clears
the TRST bit.
1 = Prescaler and TIMA counter cleared
0 = No effect
19-tima-6
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Tim e r Inte rfa c e Mod ule A (TIMA-6)
NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIMA
counter at a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTD6/TACLK pin or one of the
seven prescaler outputs as the input to the TIMA counter as Table 1
shows. Reset clears the PS[2:0] bits.
Table 1. Prescaler Selection
PS[2:0]
000
001
010
011
TIMA Clock Source
Internal Bus Clock ÷1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
PTD6/TACLK
100
101
110
111
TIMA Counte r
Re g iste rs
The two read-only TIMA counter registers contain the high and low bytes
of the value in the TIMA counter. Reading the high byte (TACNTH)
latches the contents of the low byte (TACNTL) into a buffer. Subsequent
reads of TACNTH do not affect the latched TACNTL value until TACNTL
is read. Reset clears the TIMA counter registers. Setting the TIMA reset
bit (TRST) also clears the TIMA counter registers.
NOTE: If TACNTH is read during a break interrupt, be sure to unlatch TACNTL
by reading TACNTL before exiting the break interrupt. Otherwise,
TACNTL retains the value latched during the break.
20-tima-6
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Timer Interface Module A (TIMA-6)
I/O Registers
Register Name and Address TCNTH — $0022
Bit 7
6
BIT 14
R
5
BIT 13
R
4
BIT 12
R
3
BIT 11
R
2
BIT 10
R
1
Bit 0
Read: BIT 15
BIT 9
R
BIT 8
R
Write:
R
0
Reset:
0
0
0
0
0
0
0
Register Name and Address TCNTL — $0023
Bit 7
6
5
BIT 5
R
4
BIT 4
R
3
BIT 3
R
2
BIT 2
R
1
BIT 1
R
Bit 0
BIT 0
R
Read: BIT 7
BIT 6
Write:
R
0
R
Reset:
0
0
0
0
0
0
0
R
=Reserved
Figure 5. TIMA Counter Registers (TCNTH and TCNTL)
TIMA Counte r
Mod ulo Re giste rs
The read/write TIMA modulo registers contain the modulo value for the
TIMA counter. When the TIMA counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIMA counter resumes
counting from $0000 at the next clock. Writing to the high byte
(TAMODH) inhibits the TOF bit and overflow interrupts until the low byte
(TAMODL) is written. Reset sets the TIMA counter modulo registers.
21-tima-6
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Tim e r Inte rfa c e Mod ule A (TIMA-6)
Register Name and Address TAMODH — $0024
Bit 7
BIT 15
1
6
BIT 14
1
5
BIT 13
1
4
BIT 12
1
3
BIT 11
1
2
BIT 10
1
1
BIT 9
1
Bit 0
BIT 8
1
Read:
Write:
Reset:
Register Name and Address TAMODL — $0025
Bit 7
BIT 7
1
6
BIT 6
1
5
BIT 5
1
4
BIT 4
1
3
BIT 3
1
2
BIT 2
1
1
BIT 1
1
Bit 0
BIT 0
1
Read:
Write:
Reset:
Figure 6. TIMA Counter Modulo Registers
(TAMODH and TAMODL)
NOTE: Reset the TIMA counter before writing to the TIMA counter modulo
registers.
TIMA Cha nne l
Each of the TIMA channel status and control registers:
Sta tus a nd Control
Re g iste rs
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input
capture trigger
• Selects output toggling on TIMA overflow
• Selects 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
22-tima-6
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Timer Interface Module A (TIMA-6)
I/O Registers
Register Name and Address TASC0 — $0026
Bit 7
6
CH0IE
0
5
MS0B
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
Bit 0
Read: CH0F
TOV0
0
CH0MAX
0
Write:
0
0
Reset:
Register Name and Address TASC1 — $0029
Bit 7
6
5
0
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Read: CH1F
CH1IE
Write:
0
0
R
0
Reset:
0
R
=Reserved
Figure 7. TIMA Channel Status
and Control Registers (TACC0–TASC5)
23-tima-6
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Tim e r Inte rfa c e Mod ule A (TIMA-6)
Register Name and Address TASC2 — $002C
Bit 7
6
CH2IE
0
5
MS2B
0
4
MS2A
0
3
ELS2B
0
2
ELS2A
0
1
TOV2
0
Bit 0
CH2MAX
0
Read: CH2F
Write:
0
0
Reset:
Register Name and Address TASC3 — $002F
Bit 7
6
CH3IE
0
5
0
4
MS3A
0
3
ELS3B
0
2
ELS3A
0
1
TOV3
0
Bit 0
CH3MAX
0
Read: CH3F
Write:
0
0
R
0
Reset:
Register Name and Address TASC4 — $0032
Bit 7
6
CH4IE
0
5
MS4B
0
4
MS4A
0
3
ELS4B
0
2
ELS4A
0
1
TOV4
0
Bit 0
CH4MAX
0
Read: CH4F
Write:
0
0
Reset:
Register Name and Address TASC5 — $0035
Bit 7
6
5
0
4
MS5A
0
3
ELS5B
0
2
ELS5A
0
1
TOV5
0
Bit 0
CH5MAX
0
Read: CH5F
CH5IE
Write:
0
0
R
0
Reset:
0
R
=Reserved
Figure 7. TIMA Channel Status
and Control Registers (TACC0–TASC5) (Continued)
24-tima-6
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Timer Interface Module A (TIMA-6)
I/O Registers
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIMA
counter registers matches the value in the TIMA channel x registers.
When CHxIE = 0, clear CHxF by reading TIMA channel x status and
control register with CHxF set, and then writing a logic 0 to CHxF. If
another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMA CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIMA channel 0, TIMA channel 2, and TIMA
channel 4 status and control registers.
Setting MS0B disables the channel 1 status and control register and
reverts TACH1 pin to general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and
reverts TACH3 pin to general-purpose I/O.
Setting MS4B disables the channel 5 status and control register and
reverts TACH5 pin to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
25-tima-6
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Tim e r Inte rfa c e Mod ule A (TIMA-6)
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation. See Table
2.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin once PWM, output compare mode, or input capture
mode is enabled. See Table 2. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE: Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIMA status and control register
(TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port E or port F, and pin PTEx/TACHx or pin PTFx/TACHx is
available as a general-purpose I/O pin. However, channel x is at a
state determined by these bits and becomes transparent to the
respective pin when PWM, input capture mode, or output compare
operation mode is enabled. Table 2 shows how ELSxB and ELSxA
work. Reset clears the ELSxB and ELSxA bits.
26-tima-6
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Timer Interface Module A (TIMA-6)
I/O Registers
Table 2. Mode, Edge, and Level Selection
MSxB:MSxA ELSxB:ELSxA
Mode
Configuration
Pin under Port Control;
Initialize Timer
Output Level High
X0
X1
00
00
Output
Preset
Pin under Port Control;
Initialize Timer
Output Level Low
00
00
00
01
01
01
1X
1X
01
10
11
01
10
11
01
10
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Toggle Output on Compare
Input
Capture
Output
Compare Clear Output on Compare
or PWM
Set Output on Compare
Buffered
Output
Compare
orBuffered
PWM
Toggle Output on Compare
Clear Output on Compare
1X
11
Set Output on Compare
NOTE: Before enabling a TIMA channel register for input capture operation,
make sure that the PTEx/TACHx pin or PTFx/TACHx pin is stable for at
least two bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIMA counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIMA counter overflow.
0 = Channel x pin does not toggle on TIMA counter overflow.
NOTE: When TOVx is set, a TIMA counter overflow takes precedence over a
channel x output compare if both occur at the same time.
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CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 0, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 8 shows, the CHxMAX bit takes effect in the cycle after it is set
or cleared. The output stays at the 100% duty cycle level until the
cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTEx/TCHx
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 8. CHxMAX Latency
TIMA Cha nne l
Re g iste rs
These read/write registers contain the captured TIMA counter value of
the input capture function or the output compare value of the output
compare function. The state of the TIMA channel registers after reset is
unknown.
In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the
TIMA channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0), writing to the high byte of
the TIMA channel x registers (TCHxH) inhibits output compares and the
CHxF bit until the low byte (TCHxL) is written.
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Timer Interface Module A (TIMA-6)
I/O Registers
Register Name and Address TACH0H — $0027
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Indeterminate after Reset
Register Name and Address TACH0L — $0028
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Register Name and Address TACH1H — $002A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after Reset
Register Name and Address TACH1L — $002B
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Register Name and Address TACH2H — $002D
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after Reset
Figure 9. TIMA Channel Registers
(TACH0H/L–TACH3H/L) (Sheet 1 of 3)
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Tim e r Inte rfa c e Mod ule A (TIMA-6)
Register Name and Address TACH2L — $002E
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Register Name and Address TACH3H — $0030
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after Reset
Register Name and Address TACH3L — $0031
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Register Name and Address TACH4H — $0033
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after Reset
Register Name and Address TACH4L — $0034
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Figure 9. TIMA Channel Registers
(TACH0H/L–TACH3H/L) (Sheet 2 of 3)
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Timer Interface Module A (TIMA-6)
I/O Registers
Register Name and Address TACH5H — $0036
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Indeterminate after Reset
Register Name and Address TACH5L — $0037
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Figure 9. TIMA Channel Registers
(TACH0H/L–TACH3H/L) (Sheet 3 of 3)
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Ana log -to-Dig ita l Conve rte r (ADC-15)
Ana log -to-Dig ita l Conve rte r (ADC-15)
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
ADC Port I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Voltage Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Conversion Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Continuous Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
ADC Analog Power Pin (VDDAREF)/ADC Voltage Reference Pin
(VREFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
ADC Analog Ground Pin (VSSA)/ADC Voltage Reference Low Pin
(VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 401
ADC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
ADC Input Clock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Introd uc tion
This section describes the analog-to-digital converter (ADC-15). The
ADC is an 8-bit analog-to-digital converter.
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Ana log -to-Dig ita l Conve rte r (ADC-15)
Fe a ture s
Features of the ADC module include:
• 15 Channels with Multiplexed Input
• Linear Successive Approximation
• 8-Bit Resolution
• Single or Continuous Conversion
• Conversion Complete Flag or Conversion Complete Interrupt
• Selectable ADC Clock
Func tiona l De sc rip tion
Fifteen ADC channels are available for sampling external sources at
pins PTD6/TACLK–PTD0 and PTB7/ATD7–PTB0/ATD0. An analog
multiplexer allows the single ADC converter to select one of 15 ADC
channels as ADC voltage in (ADCVIN). ADCVIN is converted by the
successive approximation register-based counters. When the
conversion is completed, ADC places the result in the ADC data register
and sets a flag or generates an interrupt. See Figure 1.
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Functional Description
INTERNAL
DATA BUS
READ DDRB/DDRB
WRITE DDRB/DDRD
DISABLE
DDRBx/DDRDx
PTBx/PTDx
RESET
WRITE PTB/PTD
READ PTB/PTD
PTBx/PTDx
ADC CHANNEL x
DISABLE
ADC DATA REGISTER
CONVERSION
COMPLETE
ADC VOLTAGE IN
ADCVIN
ADCH[4:0]
INTERRUPT
LOGIC
CHANNEL
SELECT
ADC
AIEN
COCO
ADC CLOCK
CGMXCLK
CLOCK
GENERATOR
BUS CLOCK
ADIV[2:0]
ADICLK
Figure 1. ADC Block Diagram
ADC Port I/ O Pins
PTD6/TACLK-PTD0 and PTB7/ATD7-PTB0/ATD0 are general-purpose
I/O pins that share with the ADC channels.
The channel select bits define which ADC channel/port pin will be used
as the input signal. The ADC overrides the port I/O logic by forcing that
pin as input to the ADC. The remaining ADC channels/port pins are
controlled by the port I/O logic and can be used as general-purpose I/O.
Writes to the port register or DDR will not have any affect on the port pin
that is selected by the ADC. Read of a port pin which is in use by the
ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the
DDR bit is at logic 1, the value in the port data latch is read.
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Ana log -to-Dig ita l Conve rte r (ADC-15)
NOTE: Do not use ADC channels ATD14 or ATD12 when using the
PTD6/TACLK or PTD4/TBLCK pins as the clock inputs for the 16-bit
Timers.
Volta g e
Conve rsion
When the input voltage to the ADC equals VREFH (see ADC Analog
Power Pin (VDDAREF)/ADC Voltage Reference Pin (VREFH) on page
400), the ADC converts the signal to $FF (full scale). If the input voltage
equals VSSA, the ADC converts it to $00. Input voltages between VREFH
and VSSA are a straight-line linear conversion. Conversion accuracy of
all other input voltages is not guaranteed. Current injection on unused
ADC pins can also cause conversion inaccuracies.
NOTE: Input voltage should not exceed the analog supply voltages.
Conve rsion Tim e
Conversion starts after a write to the ADSCR (ADC status control
register, $0038), and requires between 16 and 17 ADC clock cycles to
complete. Conversion time in terms of the number of bus cycles is a
function of ADICLK select, CGMXCLK frequency, bus frequency, and
ADIV prescaler bits. For example, with a CGMXCLK frequency of 4
MHz, bus frequency of 8 MHz, and fixed ADC clock frequency of 1 MHz,
one conversion will take between 16 and 17 µs and there will be between
128 bus cycles between each conversion. Sample rate is approximately
60 kHz.
Refer to ADC Analog Power Pin (VDDAREF)/ADC Voltage Reference
Pin (VREFH) on page 400.
16 to 17 ADC Clock Cycles
Conversion Time =
ADC Clock Frequency
Number of Bus Cycles = Conversion Time x Bus Frequency
Continuous
Conve rsion
In the continuous conversion mode, the ADC data register will be filled
with new data after each conversion. Data from the previous conversion
will be overwritten whether that data has been read or not. Conversions
will continue until the ADCO bit (ADC status control register, $0038) is
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Analog-to-Digital Converter (ADC-15)
Interrupts
cleared. The COCO bit is set after the first conversion and will stay set
for the next several conversions until the next write of the ADC status
and control register or the next read of the ADC data register.
Ac c ura c y a nd
Pre c ision
The conversion process is monotonic and has no missing codes. See
ADC Characteristics on page 413 for accuracy information.
Inte rrup ts
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. A CPU interrupt is generated
if the COCO bit (ADC status control register, $0038) is at logic 0. If the
COCO bit is set, an interrupt is generated. The COCO bit is not used as
a conversion complete flag when interrupts are enabled.
Low-Powe r Mod e s
The following subsections describe the low-power modes.
Wa it Mod e
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting the ADCH[4:0] bits in the ADC status
and control register before executing the WAIT instruction.
Stop Mod e
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode. Allow one conversion cycle to stabilize the analog
circuitry before attempting a new ADC conversion after exiting stop
mode.
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Ana log -to-Dig ita l Conve rte r (ADC-15)
I/ O Sig na ls
The ADC module has 15 channels that are shared with I/O ports B and
D and one channel with an input-only port bit on port D. Refer to ADC
Characteristics on page 413 for voltages referenced below.
ADC Ana log
Powe r Pin
(VDDAREF)/ ADC
Volta g e
The ADC analog portion uses VDDAREF as its power pin. Connect the
VDDA/VDDAREF pin to the same voltage potential as VDD. External
filtering may be necessary to ensure clean VDDAREF for good results.
Re fe re nc e Pin
VREFH is the high reference voltage for all analog-to-digital conversions.
Connect the VREFH pin to a voltage potential between 1.5 volts and
VDDAREF/VDDA depending on the desired upper conversion boundary.
(VREFH
)
NOTE: Route VDDAREF carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package. VDDAREF must be
present for operation of the ADC.
ADC Ana log
Ground Pin
(VSSA)/ ADC
Volta g e
The ADC analog portion uses VSSA as its ground pin. Connect the VSSA
pin to the same voltage potential as VSS.
VREFL is the lower reference supply for the ADC.
Re fe re nc e Low Pin
(VREFL
)
ADC Volta g e In
(ADCVIN)
ADCVIN is the input voltage signal from one of the 15 ADC channels to
the ADC module.
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Analog-to-Digital Converter (ADC-15)
I/O Registers
I/ O Re g iste rs
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADICLK)
ADC Sta tus a nd
Control Re g iste r
The following paragraphs describe the function of the ADC status and
control register.
Address: $0038
Bit 7
6
5
ADCO
0
4
CH4
1
3
CH3
1
2
CH2
1
1
CH1
1
Bit 0
CH0
1
Read: COCO
AIEN
Write:
R
0
Reset:
0
R
=Reserved
Figure 2. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed. This bit is cleared whenever
the ADC status and control register is written or whenever the ADC
data register is read.
If the AIEN bit is a logic 1, the COCO is a read/write bit which selects
the CPU to service the ADC interrupt request. Reset clears this bit.
1 = conversion completed (AIEN = 0)
0 = conversion not completed (AIEN = 0)
or
CPU interrupt enabled (AIEN = 1)
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Ana log -to-Dig ita l Conve rte r (ADC-15)
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the
ADR register at the end of each conversion. Only one conversion is
allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH[4:0] — ADC Channel Select Bits
ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field
which is used to select one of 15 ADC channels. The six channels are
detailed in the following table. Care should be taken when using a port
pin as both an analog and a digital input simultaneously to prevent
switching noise from corrupting the analog signal. See Table 1.
The ADC subsystem is turned off when the channel select bits are all
set to one. This feature allows for reduced power consumption for the
MCU when the ADC is not used. Reset sets these bits.
NOTE: Recovery from the disabled state requires one conversion cycle to
stabilize.
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Analog-to-Digital Converter (ADC-15)
I/O Registers
Table 1. Mux Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
PTB0/ATD0
PTB1/ATD1
PTB2/ATD2
PTB3/ATD3
PTB4/ATD4
PTB5/ATD5
PTB6/ATD6
PTB7/ATD7
PTD0
PTD1
PTD2
PTD3
PTD4/TBLCK
PTD5
PTD6/TACLK
Unused (see Note 1)
Unused (see Note 1)
Reserved
Range 01111 ($0F) to 11010 ($1A)
1
1
1
1
1
1
0
1
1
1
0
0
1
0
1
Unused (see Note 1)
V
REFH
(see Note 2)
1
1
1
1
1
1
1
1
0
1
V
SSA/VREFL (see Note 2)
[ADC power off]
NOTES:
1. If any unused channels are selected, the resulting ADC conversion will be
unknown.
2. The voltage levels supplied from internal reference nodes as specified in the
table are used to verify the operation of the ADC converter both in production
test and for user applications.
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Ana log -to-Dig ita l Conve rte r (ADC-15)
ADC Da ta Re g iste r
One 8-bit result register is provided. This register is updated each time
an ADC conversion completes.
Address: $0039
Bit 7
AD7
R
6
AD6
R
5
AD5
R
4
AD4
R
3
AD3
R
2
AD2
R
1
AD1
R
Bit 0
AD0
R
Read:
Write:
Reset:
Indeterminate after Reset
R
=Reserved
Figure 3. ADC Data Register (ADR)
ADC Inp ut Cloc k
Re g iste r
This register selects the clock frequency for the ADC.
Address: $003A
Bit 7
6
5
ADIV0
0
4
ADICLK
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
ADIV2
ADIV1
R
0
R
0
R
0
R
0
0
0
R
=Reserved
Figure 4. ADC Input Clock Register (ADICLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock. Table 2
shows the available clock configurations. The ADC clock should be
set to approximately 1 MHz.
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I/O Registers
Table 2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
ADC Input Clock /1
ADC Input Clock / 2
ADC Input Clock / 4
ADC Input Clock / 8
ADC Input Clock / 16
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
X = don’t care
ADICLK — ADC Input Clock Register Bit
ADICLK selects either bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz,
CGMXCLK can be used as the clock source for the ADC. If
CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as
the clock source. As long as the internal ADC clock is at
approximately 1 MHz, correct operation can be guaranteed. See ADC
Characteristics on page 413.
1 = Internal bus clock
0 = External clock (CGMXCLK)
fXCLK or Bus Frequency
1 MHz =
ADIV[2:0]
NOTE: During the conversion process, changing the ADC clock will result in an
incorrect conversion.
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Sp e c ific a tions
Sp e c ific a tions
Conte nts
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 410
ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
5.0 Vdc ± 0.5 V Serial Peripheral Interface (SPI) Timing . . . . . . . 414
CGM Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
CGM Component Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
CGM Acquisition/Lock Time Information. . . . . . . . . . . . . . . . . . . . 418
Timer Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Mechanical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
64-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
1-specs
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Sp e c ific a tions
Ele c tric a l Sp e c ific a tions
Ma xim um Ra ting s
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 5.0 Volt DC Electrical Characteristics on page 410 for
guaranteed operating conditions.
Rating
Supply Voltage
Symbol
VDD
Value
Unit
V
–0.3 to +6.0
Input Voltage
VIN
VSS –0.3 to VDD +0.3
V
Maximum Current Per Pin
Excluding VDD and VSS
I
± 25
mA
Storage Temperature
TSTG
IMVSS
IMVDD
VHI
–55 to +150
100
°C
mA
mA
V
Maximum Current out of VSS
Maximum Current into VDD
Reset IRQ Input Voltage
100
VDD+2 to VDD + 4
NOTE: Voltages are referenced to VSS
.
NOTE: This device contains circuitry to protect the inputs against damage due
to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIN and VOUT be constrained to the
range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD).
2-specs
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Specifications
Electrical Specifications
Func tiona l
Op e ra ting Ra ng e
Rating
Symbol
TA
Value
Unit
°C
Operating Temperature Range(1)
Operating Voltage Range
–40 to TA(MAX)
VDD
5.0 ± 0.5v
V
1. TA(MAX) = 125°C for part suffix MFU
105°C for part suffix VFU
85°C for part suffix CFU
NOTE: For applications which use the LVI, Motorola guarantee the functionality
of the device down to the LVI trip point (VLVI).
The rm a l
Cha ra c te ristic s
Characteristic
Thermal Resistance
Symbol
θJA
Value
70
Unit
°C/W
W
QFP (64 Pins)
I/O Pin Power Dissipation
PI/O
User Determined
PD = (IDD x VDD) + PI/O
Power Dissipation (see Note 1)
Constant (see Note 2)
PD
W
= K/(TJ + 273 °C
PD x (TA + 273 °C)
K
W/°C
°C
+ (PD2 x θJA
)
Average Junction Temperature
NOTES:
TJ
TA = PD x θJA
1.Power dissipation is a function of temperature.
2.K is a constant unique to the device. K can be determined from a known TA and
measured PD. With this value of K, PD and TJ can be determined for any value of TA.
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Sp e c ific a tions
5.0 Volt DC Ele c tric a l Cha ra c te ristic s
Characteristic
Symbol
Min
Max
Unit
Output High Voltage
(ILOAD = –2.0 mA) All Ports
(ILOAD = –5.0 mA) All Ports
Total source current
VDD –0.8
VDD –1.5
—
—
—
10
V
V
VOH
IOHtot
mA
Output Low Voltage
(ILOAD = 1.6 mA) All Ports
(ILOAD = 10.0 mA) All Ports
Total sink current
—
—
—
0.4
1.5
15
V
V
VOL
IOLtot
VIH
mA
Input High Voltage
0.7 x VDD
VDD
V
V
All Ports, IRQs, RESET, OSC1
Input Low Voltage
VIL
VSS
0.3 x VDD
All Ports, IRQs, RESET, OSC1
VDD Supply Current
Run (see Notes 2 and 9)
Wait (see Notes 3 and 9)
Stop (see Note 4)
LVI enabled, TA=25 °C
LVI disabled, TA=25 °C
LVI enabled, –40 °C to +125 °C
LVI disabled, –40 °C to +125 °C
—
—
35
20
mA
mA
IDD
—
—
—
—
400
50
500
100
µA
µA
µA
µA
I/O Ports Hi-Z Leakage Current
Input Current
IL
—
—
± 1
± 1
µA
µA
IIN
Capacitance
Ports (As Input or Output)
COUT
CIN
—
—
12
8
pF
V
Low-Voltage Reset Inhibit (trip)
(recover)
4.0
VLVI
4.4
200
POR ReArm Voltage (see Note 5)
POR Reset Voltage (see Note 6)
VPOR
VPORRST
RPOR
0
mV
mV
V/ms
V
0
800
POR Rise Time Ramp Rate (see Note 7)
High COP Disable Voltage (see Note 8)
0.02
VDD
—
VHI
VDD + 2
4-specs
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Specifications
Electrical Specifications
Characteristic
Symbol
Min
Max
Unit
NOTES:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +TA (MAX, unless otherwise noted.
2. Run (Operating) IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs
0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports
configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled.
3. Wait IDD measured using external square wave clock source (fOP = 8.0 MHz). All inputs 0.2 Vdc from
rail. No dc loads. Less than 100 pF on all outputs, CL = 20 pF on OSC2. All ports configured as in-
puts.
OSC2 capacitance linearly affects wait IDD. Measured with all modules enabled.
4. Stop IDD measured with OSC1 = VSS
.
5. Maximum is highest voltage that POR is guaranteed.
6. Maximum is highest voltage that POR is possible.
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low
externally until minimum VDD is reached.
8. See COP Module During Break Interrupts on page 158.
9. Although I is proportional to bus frequency, a current of several mA is present even at very low frequencies.
DD
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Sp e c ific a tions
Control Tim ing
Characteristic
Symbol
fBUS
tRL
Min
—
Max
8.4
—
Unit
MHz
tcyc
Bus Operating Frequency (4.5–5.5 V — VDD Only)
RESET Pulse Width Low
1.5
IRQ Interrupt Pulse Width Low (Edge-Triggered)
IRQ Interrupt Pulse Period
tILHI
1.5
—
tcyc
tILIL
Note 4
—
tcyc
16-Bit Timer (see Note 2)
Input Capture Pulse Width (see Note 3)
Input Capture Period
tTH, TL
tTLTL
t
2
—
—
tcyc
Note 4
MSCAN Wake-up Filter Pulse Width (see Note 5)
tWUP
2
5
µs
NOTES:
1.VDD = 5.0 Vdc ± 0.5v, VSS = 0 Vdc, TA = –40 °C to TA(MAX), unless otherwise noted.
2.The 2-bit timer prescaler is the limiting factor in determining timer resolution.
3.Refer to Table 2 . Mode, Edge, and Level Selection on page 389, and supporting note.
4.The minimum period tTLTL or tILIL should not be less than the number of cycles it takes to execute the capture interrupt
service routine plus TBD t
.
cyc
5. The minimum pulse width to wake up the MSCAN module is guaranteed by design but not tested.
6-specs
MC68HC08AZ60 — Rev 1.0
412
Specifications
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Specifications
Electrical Specifications
ADC Cha ra c te ristic s
Characteristic
Min
Max
Unit
Comments
Resolution
8
8
Bits
Absolute Accuracy
(VREFL = 0 V, VDDA/VDDAREF = VREFH = 5 V ±
0.5v)
Includes
Quantization
–1
+1
LSB
Conversion Range (see Note 1)
Power-Up Time
VREFL
16
VREFH
17
V
VREFL = VSSA
Conversion Time
Period
µs
Input Leakage (see Note 3)
Ports B and D
—
± 1
µA
ADC
Clock
Cycles
Includes Sampling
Time
Conversion Time
16
17
Monotonicity
Inherent within Total Error
Zero Input Reading
Full-Scale Reading
00
01
FF
Hex
Hex
VIN = VREFL
VIN = VREFH
FE
ADC
Clock
Cycles
Sample Time (see Note 2)
5
—
Input Capacitance
ADC Internal Clock
Analog Input Voltage
NOTES:
—
8
pF
Hz
V
Not Tested
500 k
VREFL
1.048 M
VREFH
Tested Only at 1 MHz
1.VDD = 5.0 Vdc ± 0.5v, VSS = 0 Vdc, VDDA/VDDAREF = 5.0 Vdc ± 0.5v, VSSA = 0 Vdc, VREFH = 5.0 Vdc ± 0.5v
2.Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
3.The external system error caused by input leakage current is approximately equal to the product of R
source and input current.
7-specs
MC68HC08AZ60 — Rev 1.0
413
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Sp e c ific a tions
5.0 Vd c ± 0.5 V Se ria l Pe rip he ra l Inte rfa c e (SPI) Tim ing
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency (see Note 3)
Master
Slave
fBUS(M)
fBUS(S)
fBUS/128
dc
fBUS/2
fBUS
MHz
Cycle Time
Master
Slave
1
tcyc(M)
tcyc(S)
2
1
128
—
tcyc
2
3
Enable Lead Time
Enable Lag Time
tLead
tLag
15
15
—
—
ns
ns
Clock (SCK) High Time
4
5
6
7
Master
Slave
tW(SCKH)M
tW(SCKH)S
100
50
—
—
ns
ns
ns
ns
Clock (SCK) Low Time
Master
Slave
tW(SCKL)M
tW(SCKL)S
100
50
—
—
Data Setup Time (Inputs)
Master
Slave
tSU(M)
tSU(S)
45
5
—
—
Data Hold Time (Inputs)
Master
Slave
tH(M)
tH(S)
0
15
—
—
Access Time, Slave (see Note 4)
CPHA = 0
tA(CP0)
tA(CP1)
0
0
40
20
ns
ns
ns
8
9
CPHA = 1
Slave Disable Time (Hold Time to High-Impedance State)
tDIS
—
25
Enable Edge Lead Time to Data Valid (see Note 6)
Master
Slave
10
tEV(M)
tEV(S)
—
—
10
40
Data Hold Time (Outputs, after Enable Edge)
Master
Slave
11
12
tHO(M)
tHO(S)
0
5
—
—
ns
Data Valid
Master (Before Capture Edge)
tV(M)
90
—
—
ns
ns
Data Hold Time (Outputs)
Master (Before Capture Edge)
13
tHO(M)
100
NOTES:
1. All timing is shown with respect to 30% VDD and 70% VDD, unless otherwise noted; assumes 100 pF load on all SPI
pins.
2. Item numbers refer to dimensions in Figure 1 and Figure 2.
3. fBUS = the currently active bus frequency for the microcontroller.
4. Time to data active from high-impedance state.
5. With 100 pF on all SPI pins
8-specs
MC68HC08AZ60 — Rev 1.0
414
Specifications
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Specifications
Electrical Specifications
SS
(INPUT)
SS pin of master held high.
1
5
4
SCK (CPOL = 0)
(OUTPUT)
NOTE
NOTE
4
5
SCK (CPOL = 1)
(OUTPUT)
6
7
MISO
MSB IN
BITS 6–1
BITS 6–1
LSB IN
(INPUT)
10
11
10
11
MOSI
(OUTPUT)
MASTER MSB OUT
13
MASTER LSB OUT
12
NOTE: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
(INPUT)
SS pin of master held high.
1
SCK (CPOL = 0)
(OUTPUT)
5
4
NOTE
NOTE
4
5
SCK (CPOL = 1)
(OUTPUT)
6
7
LSB IN
11
MISO
MSB IN
BITS 6–1
BITS 6–1
(INPUT)
10
11
10
MOSI
(OUTPUT)
MASTER MSB OUT
12 13
MASTER LSB OUT
NOTE: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 1. SPI Master Timing Diagram
9-specs
MC68HC08AZ60 — Rev 1.0
415
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Sp e c ific a tions
SS
(INPUT)
3
1
SCK (CPOL = 0)
(INPUT)
11
4
2
SCK (CPOL = 1)
(INPUT)
5
4
9
8
MISO
SLAVE MSB OUT
BITS 6–1
BITS 6–1
SLAVE LSB OUT
11
NOTE
(INPUT)
11
6
7
10
MOSI
(OUTPUT)
MSB IN
LSB IN
NOTE: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
SCK (CPOL = 0)
(INPUT)
5
4
5
2
3
SCK (CPOL = 1)
(INPUT)
4
10
9
8
MISO
NOTE
SLAVE MSB OUT
BITS 6–1
BITS 6–1
SLAVE LSB OUT
(OUTPUT)
11
6
7
10
MOSI
(INPUT)
MSB IN
LSB IN
NOTE: Not defined but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 2. SPI Slave Timing Diagram
10-specs
MC68HC08AZ60 — Rev 1.0
416
Specifications
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Specifications
Electrical Specifications
CGM Op e ra ting Cond itions
Characteristic
Operating Voltage
Symbol
VDD
Min
4.5 V
1
Typ
—
Max
5.5 V
8
Comments
Crystal Reference Frequency
fRCLK
4.9152 MHz
Module Crystal Reference
Frequency
Same Frequency as
fRCLK
fXCLK
fNOM
fVRS
—
4.9152 MHz
—
—
Range Nom. Multiplier (MHz)
—
4.9152
—
4.5–5.5 V, VDD only
4.5–5.5 V, VDD only
VCO Center-of-Range Frequency
(MHz)
4.9152
4.9152
32.0
32.0
VCO Operating Frequency (MHZ)
fVCLK
—
CGM Com p one nt Inform a tion
Description
Symbol
Min
Typ
Max
Comments
Consult Crystal
Manufacturer’s Data
Crystal Load Capacitance
CL
—
—
—
Consult Crystal
Manufacturer’s Data
Crystal Fixed Capacitance
C1
—
—
2 x CL
—
—
Consult Crystal
Manufacturer’s Data
Crystal Tuning Capacitance
C2
2 x CL
0.0154
Filter Capacitor Multiply Factor
CFACT
F/s V
See External Filter
Capacitor Pin
(CGMXFC) on page
117
C
FACT x
(VDDA
fXCLK
Filter Capacitor
CF
—
—
/
)
—
—
CBYP must provide
low AC impedance
from f = fXCLK/100 to
100 x fVCLK, so series
resistance must be
considered.
Bypass Capacitor
CBYP
0.1 µF
11-specs
MC68HC08AZ60 — Rev 1.0
417
MOTOROLA
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Sp e c ific a tions
CGM Ac q uisition/ Loc k Tim e Inform a tion
Description
Symbol
Min
Typ
Max
Notes
If CF Chosen
Correctly
Manual Mode Time to Stable
tACQ
—
(8 x VDDA)/(fXCLK x KACQ)
—
If CF Chosen
Correctly
Manual Stable to Lock Time
Manual Acquisition Time
tAL
—
—
0
(4 x VDDA)/(fXCLK x KTRK
)
—
—
tLOCK
DTRK
tACQ+tAL
—
Tracking Mode Entry
Frequency Tolerance
± 3.6%
Acquisition Mode Entry
Frequency Tolerance
DUNT
± 6.3%
—
± 7.2%
LOCK Entry Freq. Tolerance
LOCK Exit Freq. Tolerance
DLOCK
DUNL
0
—
—
± 0.9%
± 1.8%
± 0.9%
Reference Cycles per
Acquisition Mode
Measurement
nACQ
—
—
32
—
—
Reference Cycles per
Tracking Mode
nTRK
128
Measurement
Automatic Mode Time
to Stable
If CF Chosen
Correctly
tACQ
nACQ XCLK
/f
(8 x VDDA)/(fXCLK x KACQ)
Automatic Stable to Lock
Time
If CF Chosen
Correctly
tAL
nTRK XCLK
/f
(4 x VDDA)/(fXCLK x KTRK
tACQ+tAL
)
—
Automatic Lock Time
tLOCK
—
0
—
PLL Jitter, Deviation of
Average Bus Frequency
over 2 ms
± (fCRYS
x (.025%)
x (N/4)
)
N = VCO
Freq. Mult.
(GBNT)
—
NOTES:
1.GBNT guaranteed but not tested
2.VDD = 5.0 Vdc ± 0.5v, VSS = 0 Vdc, TA = –40 °C to TA(MAX), unless otherwise noted.
Tim e r Mod ule Cha ra c te ristic s
Characteristic
Input Capture Pulse Width
Symbol
tTIH, TIL
Min
Max
Unit
ns
t
125
—
—
Input Clock Pulse Width
t
TCH, tTCL (1/fOP) + 5
ns
12-specs
MC68HC08AZ60 — Rev 1.0
418
Specifications
MOTOROLA
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Specifications
Electrical Specifications
Me m ory Cha ra c te ristic s
Characteristic
RAM Data Retention Voltage
Symbol
VRDR
Min
0.7
10
Max
—
Unit
V
EEPROM Programming Time per Byte
EEPROM Erasing Time per Byte
EEPROM Erasing Time per Block
EEPROM Erasing Time per Bulk
EEPROM Programming Voltage Discharge Period
tEEPGM
tEEBYTE
tEEBLOCK
tEEBULK
tEEFPV
—
ms
ms
ms
ms
µs
10
—
10
—
10
—
100
—
EEPROM Write/Erase Cycles
@ 10 ms Write Time +125 °C
10,000
10
—
—
Cycles
Years
EEPROM Data Retention
After 10,000 Write/Erase Cycles
EEPROM enable recovery time
EEPROM stop recovery time
tEEOFF
600
600
—
—
µs
µs
tEESTOP
13-specs
MC68HC08AZ60 — Rev 1.0
419
MOTOROLA
Specifications
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Sp e c ific a tions
Me c ha nic a l Sp e c ific a tions
64-Pin Qua d Fla t Pa c k (QFP)
L
B
B
48
33
P
49
32
- A, B, D -
- A -
- B -
Detail A
L
B
V
F
Detail A
64
17
N
J
1
16
S
- D -
0.20
Base
Metal
D
A
C A– B
D
D
0.20
C A– B
D
S
M
S
S
M
S
0.05 A – B
Section B–B
S
U
0.20
H A– B
M
S
T
Detail C
M
M
E
R
Q
C
Datum
Plane
-H-
K
-C-
G
0.01
H
W
Seating
Plane
Detail C
X
Dim.
Min.
13.90
13.90
2.15
Max.
Notes
Dim.
M
N
Min.
5°
Max.
10°
A
B
C
D
E
F
14.10 1. Dimensions and tolerancing per ANSI Y 14.5M, 1982.
2. All dimensions in mm.
3. Datum Plane –H– is located at bottom of lead and is coincident with
the lead where the lead exits the plastic body at the bottom of the part-
ing line.
4. Datums A–B and –D to be determined at Datum Plane –H–.
5. Dimensions S and V to be determined at seating plane –C–.
6. Dimensions A and B do not include mould protrusion. Allowable
mould protrusion is 0.25mm per side. Dimensions A and B do include
mould mismatch and are determined at Datum Plane –H–.
7. Dimension D does not include dambar protrusion. Allowable dam-
bar protrusion shall be 0.08 total in excess of the D dimension at max-
imum material condition. Dambar cannot be located on the lower
radius or the foot.
14.10
2.45
0.45
2.40
0.40
0.13
0.17
P
0.40 BSC
0.30
Q
0°
7°
0.30
17.45
—
2.00
R
0.13
16.95
0.13
0°
0.30
S
G
H
J
0.80 BSC
T
—
0.25
0.23
0.95
U
—
0.13
0.65
V
16.95
0.35
17.45
0.45
K
W
L
12.00 REF
X
1.6 REF
14-specs
MC68HC08AZ60 — Rev 1.0
420
Specifications
MOTOROLA
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Ap p e nd ix A: Future EEPROM Re g iste rs
Ap p e nd ix A: Future EEPROM Re g iste rs
NOTE: The following are proposed register addresses. Writing to them in
current software will have no effect.
EEPROM Tim e b a se Divid e r Control Re g iste rs
To program or erase the EEPROM content, the EEPROM control
hardware requires a constant timebase of 35µs to drive its internal timer.
EEPROM Timebase Divider EEDIV is a clock-divider which divides the
selected reference clock source to generate this constant timebase. The
reference clock input of the EEDIV is driven by either the CGMXCLK or
the system bus clock. The selection of this reference clock is defined by
the EEDIVCLK bit in the Configuration Register.
EEPROM Timebase Divider EEDIV are defined by two registers
(EEDIVH and EEDIVL) and must be programmed with a proper value
before starting any EEPROM erase/program steps. EEDIV registers
must be re-programmed when ever its reference clock is changed. The
EEDIV value can be either pre-programmed in the EEDIVHNVR and
EEDIVLNVR non-volatide memory registers, (which upon reset will load
their contents into the EEDIVH and EEDIVL registers,) or programmed
directly by software into the EEDIVH and EEDIVL registers at system
initialization . The function of the divider is to provide a constant clock
source with a period of 35µs (better be within ± 2ms) to the internal timer
and related EEPROM circuits for proper program/erase operations. The
recommended frequency range of the reference clock is 250KHz to
32MHz.
1-appA
MC68HC08AZ60 — Rev 1.0
MOTOROLA
Appendix A: Future EEPROM Registers
421
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Ap p e nd ix A: Future EEPROM Re g iste rs
EEDIVH a nd EEDIVL Re g iste rs
EEDIVH and EEDIVL are used to store the 11-bit EEDIV value which
can be programmed by software at system initialization or during runtime
if the EEDIVSECD bit in the EEDIVH is not cleared. The EEDIV value is
calculated by the following formula:
EEDIV = INT[Reference Frequency (Hz) × 35 × 10–6 + 0.5]
Where the result inside the bracket [ ]is rounded down to the nearest
interger value.
For example, if the Reference Frequency is 4.9152MHz, the EEDIV
value in the above formula will be 172. To examine the timebase output
of the divider, the Reference Frequency is divided by the calculated
EEDIV value (172), which equals to 28.577KHz in frequency or 34.99µs
in period.
Programming/erasing the EEPROM with an improper EEDIV value may
result in data lost and reduce endurance of the EEPROM device.
Address:
$FE1A
Bit 7
6
x
5
4
x
3
x
2
1
Bit 0
Read:
Write:
EEDIVSECD
EEDIV10
EEDIV9
EEDIV8
Reset: EEDIVH-NVR
x
EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR
= Unimplemented
Figure 3. EEPROM-2 Divider High Register (EEDIVH)
Address:
$FE1B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
EEDIV7
EEDIV6
EEDIV5
EEDIV4
EEDIV3
EEDIV2
EEDIV1
EEDIV0
Reset: EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR
= Unimplemented
Figure 4. EEPROM-2 Divider Low Register (EEDIVL)
2-appA
MC68HC08AZ60 — Rev 1.0
422
Appendix A: Future EEPROM Registers
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Appendix A: Future EEPROM Registers
EEDIV Non-volatile Registers
EEDIVSECD — EEPROM Divider Security Disable
This bit enables/disables the security feature of the EEDIV registers.
When EEDIV security feature is enabled, the state of the registers
EEDIVH and EEDIVL are locked (inclucding this EEDIVSECD bit).
Also the EEDIVHNVR and EEDIVLNVR non-volatile memory
registers are protected from being erased/programmed.
1 = EEDIV security feature disabled
0 = EEDIV security feature enabled
EEDIV10–EEDIV0 — EEPROM timebase prescalar.
These prescalar bits store the value of EEDIV which is used as the
divisor to derive a timebase of 35µs from the selected reference clock
source for the EEPROM related internal timer and circuits.
EEDIV0–10 are readable at any time. They are writable when EELAT
is not set and EEDIVSECD is not cleared.
EEDIV Non-vola tile Re g iste rs
Address:
$FE10
Bit 7
6
5
4
3
2
1
Bit 0
EEDIV8
PV
Read:
Write:
Reset:
EEDIVSECD
PV
EEDIV10
PV
EEDIV9
PV
PV
PV
PV
PV
= Unimplemented
Figure 5. EEPROM-2 Divider High Non-volatile Register (EEDIVHNVR)
Address:
$FE11
Bit 7
EEDIV7
PV
6
5
4
3
2
1
Bit 0
EEDIV0
PV
Read:
Write:
Reset:
EEDIV6
PV
EEDIV5
EEDIV4
PV
EEDIV3
PV
EEDIV2
PV
EEDIV1
PV
PV
= Unimplemented
Figure 6. EEPROM-2 Divider Low Non-volatile Register (EEDIVLNVR)
3-appA
MC68HC08AZ60 — Rev 1.0
423
MOTOROLA
Appendix A: Future EEPROM Registers
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Ap p e nd ix A: Future EEPROM Re g iste rs
PV = Programmed Value or ’1’ in the erased state.
The EEPROM Divider non-volatile registers (EEDIVHNVR and
EEDIVLNVR) store the reset values of the EEDIV0–10 and EEDIVSECD
bits which are non-volatile and are not modified by reset. On reset, these
two special registers load the EEDIV0–10 and EEDIVSECD bits into the
corresponding volatile EEDIV registers (EEDIVH and EEDIVL).
The EEDIVHNVR and EEDIVLNVR can be programmed/erased like
normal EEPROM bytes if the Divider Security Disable bit (EEDIVSECD)
in the EEDIVH is not cleared. The new 11-bit EEDIV value in the
non-volatile registers (EEDIVHNVR and EEDIVLNVR) together with the
EEPROM Divider Security Disable bit (EEDIVSECD) will only be loaded
into the EEDIVH & EEDIVL registers with a system reset.
NOTE: Once EEDIVSECD in the EEDIVHNVR is programmed to ‘0’ and after a
system reset, the EEDIV security feature is permanently enabled
because the EEDIVSECD bit in the EEDIVH is always loaded with a ‘0’
thereafter. Once this security feature is armed, erase and program
modes are disabled for EEDIVHNVR and EEDIVLNVR. Modifications to
the EEDIVH and EEDIVL registers are also disabled. Therefore, great
care should be taken before programming a value into the EEDIVHNVR.
4-appA
MC68HC08AZ60 — Rev 1.0
424
Appendix A: Future EEPROM Registers
MOTOROLA
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Ap p e nd ix B: HC08AZ48 Me m ory Ma p
HC08AZ48 Me m ory Ma p
Conte nts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Introd uc tion
The MC68HC08AZ48 can address 48 Kbytes of memory space. It is
basically identical to the MC68HC08AZ60 part except that ROM and
EEPROM size are smaller. The memory map, shown in Figure 1,
includes:
• 48 Kbytes of ROM
• 1536 Bytes of RAM
• 768 Bytes of EEPROM with Protect Option
• 52 Bytes of User-Defined Vectors
• 224 Bytes of Monitor ROM
The following definitions apply to the memory map representation of
reserved and unimplemented locations.
•
•
Reserved — Accessing a reserved location can have
unpredictable effects on MCU operation.
Unimplemented — Accessing an unimplemented location
causes an illegal address reset if illegal address resets are
enabled.
1-mem48
MC68HC08AZ60 — Rev 1.0
425
MOTOROLA
Appendix B: HC08AZ48 Memory Map
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Ap p e nd ix B: HC08AZ48 Me m ory Ma p
Figure 1. Memory Map
$0000
↓
$0000
↓
I/O REGISTERS (64 BYTES)
$003F
$0040
↓
$003F
$0040
↓
I/O REGISTERS, 16 BYTES
RAM-1, 1024 BYTES
RESERVED
$004F
$0050
↓
$004F
$0050
↓
$044F
$0450
↓
$044F
$0450
↓
$04FF
$0500
↓
$04FF
$0500
↓
CAN CONTROL AND MESSAGE
BUFFERS, 128 BYTES
$057F
$0580
↓
$057F
$0580
↓
RESERVED
EEPROM-2, 256 BYTES
RESERVED
$05FF
$0600
↓
$05FF
$0600
↓
$06FF
$0700
↓
$06FF
$0700
↓
$07FF
$0800
↓
$07FF
$0800
↓
EEPROM-1, 512 BYTES
RAM-2, 512 BYTES
RESERVED
$09FF
$0A00
↓
$09FF
$0A00
↓
$0BFF
$0C00
↓
$0BFF
$0C00
↓
$0DFF
$0E00
↓
$0DFF
$0E00
↓
RESERVED
$3FFF
$3FFF
2-mem48
MC68HC08AZ60 — Rev 1.0
426
Appendix B: HC08AZ48 Memory Map
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Appendix B: HC08AZ48 Memory Map
Introduction
Figure 1. Memory Map (Continued)
$4000
↓
$4000
↓
ROM-2, 16384 BYTES
$7FFF
$8000
↓
$7FFF
$8000
↓
ROM-1, 32,256BYTES
$FDFF
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
$FDFF
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
SIM BREAK STATUS REGISTER (SBSR)
SIM RESET STATUS REGISTER (SRSR)
RESERVED
SIM BREAK FLAG CONTROL REGISTER (SBFCR)
RESERVED
RESERVED
UNIMPLEMENTED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BREAK ADDRESS REGISTER HIGH (BRKH)
BREAK ADDRESS REGISTER LOW (BRKL)
$FE0E BREAK STATUS AND CONTROL REGISTER (BSCR) $FE0E
$FE0F
$FE10
$FE11
$FE12
↓
LVI STATUS REGISTER (LVISR)
RESERVED
$FE0F
$FE10
$FE11
$FE12
↓
RESERVED
UNIMPLEMENTED (5BYTES)
$FE17
$FE18
$FE19
$FE1A
$FE1B
$FE1C
$FE1D
$FE1E
$FE1F
$FE20
↓
$FE17
$FE18
$FE19
$FE1A
$FE1B
$FE1C
$FE1D
$FE1E
$FE1F
$FE20
↓
EEPROM NON-VOLATILE REGISTER (EENVR2)
EEPROM CONTROL REGISTER (EECR2)
RESERVED
EEPROM ARRAY CONFIGURATION (EEACR2)
EEPROM NON-VOLATILE REGISTER (EENVR1)
EEPROM CONTROL REGISTER (EECR1)
RESERVED
EEPROM ARRAY CONFIGURATION (EEACR1)
MONITOR ROM (224 BYTES)
$FEFF
$FEFF
3-mem48
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427
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Ap p e nd ix B: HC08AZ48 Me m ory Ma p
Figure 1. Memory Map (Continued)
$FF00
↓
$FF00
↓
UNIMPLEMENTED (128 BYTES)
$FF7F
$FF7F
$FF80
$FF81
$FF82
↓
RESERVED
RESERVED
$FF80
$FF81
$FF82
↓
RESERVED (75 BYTES)
VECTORS (52BYTES)
$FFCB
$FFCC
↓
$FFCB
$FFCC
↓
$FFFF
$FFFF
I/ O Se c tion
Addresses $0000–$003F, shown in Figure 2, contain most of the
control, status, and data registers. Additional I/O registers have these
addresses:
• $FE00 (SIM break status register, SBSR)
• $FE01 (SIM reset status register, SRSR)
• $FE03 (SIM break flag control register, SBFCR)
• $FE09 (configuration write-once register, CONFIG-2)
• $FE0C and $FE0D (break address registers, BRKH and BRKL)
• $FE0E (break status and control register, BRKSCR)
• $FE0F (LVI status register, LVISR)
• $FE18 (EEPROM non-volatile register, EENVR2)
• $FE19 (EEPROM control register, EECR2)
• $FE1B (EEPROM array configuration register, EEACR2)
• $FE1C (EEPROM non-volatile register, EENVR1)
• $FE1D (EEPROM control register, EECR1)
• $FE1F (EEPROM array configuration register, EEACR1)
• $FFFF (COP control register, COPCTL)
•
Table 1 is a list of vector locations.
4-mem48
MC68HC08AZ60 — Rev 1.0
428
Appendix B: HC08AZ48 Memory Map
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Appendix B: HC08AZ48 Memory Map
I/O Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$0000
Port A Data Register (PTA)
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
Port B Data Register (PTB)
Port C Data Register (PTC)
Port D Data Register (PTD)
PTB7
0
PTB6
0
PTB5
PTC5
PTD5
PTB4
PTC4
PTD4
PTB3
PTC3
PTD3
PTB2
PTC2
PTD2
PTB1
PTC1
PTD1
PTB0
PTC0
PTD0
PTD7
PTD6
Data Direction Register A
(DDRA)
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Data Direction Register B
(DDRB)
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
0
Data Direction Register C
(DDRC)
MCLKEN
DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Data Direction Register D
(DDRD)
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDR2 DDRD1 DDRD0
Port E Data Register (PTE)
Port F Data Register (PTF)
Port G Data Register (PTG)
Port H Data Register (PTH)
PTE7
0
PTE6
PTE5
PTE4
PTE3
PTE2
PTF2
PTE1
PTF1
PTG1
PTH1
PTE0
PTF0
PTG0
PTH0
PTF6
0
PTF5
0
PTF4
0
PTF3
0
0
0
PTG2
0
0
0
0
0
Data Direction Register E
(DDRE)
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
0
Data Direction Register F
(DDRF)
DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
0
0
0
0
0
0
0
0
0
0
Data Direction Register G
(DDRG)
DDRG2 DDRG1 DDRG0
0
Data Direction Register H
(DDRH)
DDRH1 DDRH0
SPI Control Register (SPCR)
SPRIE
R
SPMSTR CPOL
CPHA SPWOM SPE
SPTIE
= Unimplemented
R
= Reserved
Figure 2. Control, Status, and Data Registers (Sheet 1 of 6)
5-mem48
MC68HC08AZ60 — Rev 1.0
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Ap p e nd ix B: HC08AZ48 Me m ory Ma p
Addr.
Register Name
Bit 7
Read: SPRF
Write:
6
5
4
3
2
1
Bit 0
OVRF
MODF
SPTE
SPI Status and Control
Register (SPSCR)
MODFE
N
$0011
ERRIE
SPR1
SPR0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0020
$0021
$0022
SPI Data Register (SPDR)
SCI Control Register 1 (SCC1)
SCI Control Register 2 (SCC2)
SCI Control Register 3 (SCC3)
SCI Status Register 1 (SCS1)
SCI Status Register 2 (SCS2)
SCI Data Register (SCDR)
LOOPS ENSCI TXINV
M
WAKE
TE
ILTY
RE
PEN
PTY
SBK
SCTIE
R8
TCIE
SCRIE
ILIE
RWU
T8
R
R
ORIE
OR
NEIE
NF
FEIE
FE
PEIE
PE
Read: SCTE
Write:
TC
SCRF
IDLE
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
0
0
0
0
0
BKF
RPF
R7
T7
0
R6
T6
0
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SCI Baud Rate Register (SCBR)
SCP1
0
SCP0
0
SCR2
SCR1
SCR0
0
0
0
IRQF
KEYF
1
0
ACK1
0
IRQ Status and Control
Register (ISCR)
IMASK1 MODE1
IMASKK MODEK
0
0
0
Keyboard Status and Control
Register (KBSCR)
ACKK
1
PLLF
LOCK
1
0
1
0
PLL Control Register (PCTL)
PLLIE
AUTO
MUL7
PLLON
ACQ
BCS
XLD
0
0
PLL Bandwidth Control
Register (PBWC)
PLL Programming Register
(PPG)
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
Read: LVISTOP ROMSEC LVIRST LVIPWR SSREC COPS
STOP
R
COPD
R
Mask Option
Register (MOR)
Write:
R
R
TOIE
0
R
TSTOP
0
R
0
R
0
R
Read: TOF
Timer A Status and Control
Register (TASC)
PS2
PS1
PS0
Write:
Read:
Write:
0
0
TRST
Keyboard Interrupt Enable Register
(KBIE)
KBIE4
12
KBIE3
11
KBIE2
10
KBIE1
9
KBIE0
Bit 8
Read: Bit 15
Write:
14
13
Timer A Counter Register
High (TACNTH)
Figure 2. Control, Status, and Data Registers (Sheet 2 of 6)
6-mem48
MC68HC08AZ60 — Rev 1.0
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Appendix B: HC08AZ48 Memory Map
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Appendix B: HC08AZ48 Memory Map
I/O Section
Addr.
Register Name
Bit 7
Read: Bit 7
Write:
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
Timer A Counter Register
Low (TACNTL)
$0023
Read:
Bit 15
Write:
Timer A Modulo Register
High (TAMODH)
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002C
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
Read:
Bit 7
Timer A Modulo Register
Low (TAMODL)
Write:
Read: CH0F
Timer A Channel 0 Status and
Control Register (TASC0)
CH0IE
14
MS0B
13
MS0A
12
ELS0B ELS0A TOV0 CH0MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 0 Register
High (TACH0H)
Bit 15
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 0 Register
Low (TACH0L)
Bit 7
6
5
0
4
Read: CH1F
Timer A Channel 1 Status and
Control Register (TASC1)
CH1IE
14
MS1A
12
ELS1B ELS1A TOV1 CH1MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 1 Register
High (TACH1H)
Bit 15
13
5
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 1 Register
Low (TACH1L)
Bit 7
6
4
Read: CH2F
Timer A Channel 2 Status and
Control Register (TASC2)
CH2IE
14
MS2B
13
MS2A
12
ELS2B ELS2A TOV2 CH2MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 2 Register
High (TACH2H)
Bit 15
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 2 Register
Low (TACH2L)
Bit 7
6
5
0
4
Read: CH3F
Timer A Channel 3 Status and
Control Register (TASC3)
CH3IE
14
MS3A
12
ELS3B ELS3A TOV3 CH3MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 3 Register
High (TACH3H)
Bit 15
13
5
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 3 Register
Low (TACH3L)
Bit 7
6
4
Read: CH4F
Timer A Channel 4 Status and
Control Register (TASC4)
CH4IE
14
MS4B
13
MS4A
12
ELS4B ELS4A TOV4 CH4MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 4 Register High
(TACH4H)
Bit 15
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 4 Register Low
(TACH4L)
Bit 7
6
5
4
Figure 2. Control, Status, and Data Registers (Sheet 3 of 6)
7-mem48
MC68HC08AZ60 — Rev 1.0
431
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Ap p e nd ix B: HC08AZ48 Me m ory Ma p
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH5F
0
Timer A Channel 5 Status and
Control Register (TASC5)
$0035
CH5IE
MS5A
ELS5B ELS5A TOV5 CH5MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 5 Register
High (TACH5H)
$0036
$0037
$0038
$0039
$003A
$0040
$0041
$0042
$0043
$0044
$0045
$0046
$0047
Bit 15
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 5 Register
Low (TACH5L)
Bit 7
Read: COCO
Analog-to-Digital Status and
Control Register (ADSCR)
AIEN
AD6
ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write:
R
Read: AD7
Write:
AD5
AD4
AD3
0
AD2
0
AD1
0
AD0
0
Analog-to-Digital Data Register
(ADR)
Read:
ADIV2
Write:
Analog-to-Digital Input Clock
Register (ADICLK)
ADIV1 ADIV0 ADICLK
0
Read: TOF
Write:
0
Timer B Status and Control
Register (TBSCR)
TOIE
TSTOP
PS2
10
PS1
9
PS0
Bit 8
TRST
12
Read: Bit 15
Write:
14
13
11
3
Timer B Counter Register High
(TBCNTH)
Read: Bit 7
Write:
6
5
4
2
1
Bit 0
Timer B Counter Register Low
(TBCNTL)
Read:
Bit 15
Write:
Timer B Modulo Register High
(TBMODH)
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
Read:
Bit 7
Timer B Modulo Register Low
(TBMODL)
Write:
Read: CH0F
Timer B CH0 Status and Control
Register (TBSC0)
CH0IE
14
MS0B
13
MS0A
12
ELS0B ELS0A TOV0 CH0MAX
Write:
Read:
Write:
Read:
Write:
0
Timer B CH0 Register High
(TBCH0H)
Bit 15
11
3
10
2
9
1
Bit 8
Bit 0
Timer B CH0 Register Low
(TBCH0L)
Bit 7
6
5
0
4
Read: CH1F
Timer B CH1 Status and Control
Register (TBSC1)
CH1IE
14
MS1A
12
ELS1B ELS1A TOV1 CH1MAX
$0048
$0049
Write:
Read:
Write:
Read:
Write:
0
Timer B CH1 Register High
(TBCH1H)
Bit 15
13
5
11
10
2
9
1
Bit 8
Bit 0
PS0
Timer B CH1 Register Low
(TBCH1L)
$004A
$004B
Bit 7
6
4
3
0
Read: TOF
Write:
0
TIM Status and Control Register
(TSC)
TOIE
TSTOP
PS2
PS1
TRST
Figure 2. Control, Status, and Data Registers (Sheet 4 of 6)
8-mem48
MC68HC08AZ60 — Rev 1.0
432
Appendix B: HC08AZ48 Memory Map
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Appendix B: HC08AZ48 Memory Map
I/O Section
Addr.
Register Name
Bit 7
Read: Bit 15
Write:
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
TIM Counter Register High
(TCNTH)
$004C
Read: Bit 7
Write:
6
5
4
3
2
1
Bit 0
TIM Counter Register Low
(TCNTL)
$004D
$004E
$004F
$FE00
Read:
Bit 15
Write:
TIM Modulo Register High
(TMODH)
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
Read:
Bit 7
TIM Modulo Register Low
(TMODL)
Write:
Read:
R
SIM Break Status Register
(SBSR)
R
R
R
R
R
0
SBSW
LVI
R
0
Write:
Read: POR
Write:
PIN
COP
ILOP
ILAD
$FE01 SIM Reset Status Register (SRSR)
Read:
BCFE
Write:
SIM Break Flag Control Register
$FE03
R
R
R
14
6
R
R
R
R
R
R
R
R
R
R
R
9
R
R
(SBFCR)
Read:
R
$FE09
$FE0B
$FE0C
$FE0D
$FE0E
$FE0F
$FE11
$FE18
$FE19
$FE1A
$FE1B
RESERVED
RESERVED
Write:
Read:
R
R
R
R
R
R
Write:
Read:
Bit 15
Write:
Break Address Register High
(BRKH)
13
12
11
10
Bit 8
Read:
Bit 7
Break Address Register Low
(BRKL)
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Write:
Read:
BRKE
Write:
Break Status and Control
Register (BRKSCR)
BRKA
0
Read: LVIOUT
Write:
0
0
0
0
0
0
LVI Status Register (LVISR)
RESERVED
Read:
R
R
R
R
R
R
R
R
Write:
Read:
EEPROM Nonvolatile Register
(EENVR2)
EERA CON2
CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0
0
Write:
Read:
Write:
Read:
Write:
0
EEPROM Control
Register (EECR2)
EEBCLK
EEOFF EERAS1 EERAS0 EELAT
EEPGM
Reserved
R
R
R
R
R
R
R
R
Read: EERA CON2
Write:
CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0
EEPROM Array Control Register
(EEACR2)
Figure 2. Control, Status, and Data Registers (Sheet 5 of 6)
9-mem48
MC68HC08AZ60 — Rev 1.0
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Ap p e nd ix B: HC08AZ48 Me m ory Ma p
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
EEPROM Nonvolatile Register
(EENVR1)
$FE1C
EERA CON2
CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0
0
0
EEPROM Control
Register (EECR1)
$FE1D
$FE1E
$FE1F
$FF80
$FF81
EEBCLK
EEOFF EERAS1 EERAS0 EELAT
EEPGM
R
Reserved
R
R
R
R
R
R
R
Read: EERA CON2
CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0
EEPROM Array Control Register
(EEACR1)
Write:
Read:
Write:
Read:
Write:
R
R
R
R
R
R
R
R
RESERVED
RESERVED
Read:
Write:
LOW BYTE OF RESET VECTOR
$FFFF COP Control Register (COPCTL)
WRITING TO $FFFF CLEARS COP COUNTER
Figure 2. Control, Status, and Data Registers (Sheet 6 of 6)
10-mem48
MC68HC08AZ60 — Rev 1.0
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Appendix B: HC08AZ48 Memory Map
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I/O Section
Table 1. Vector Addresses
Address
Vector
TIMA Channel 5 Vector (High)
TIMA Channel 5 Vector (Low)
TIMA Channel 4 Vector (High)
TIMA Channel 4 Vector (Low)
ADC Vector (High)
$FFCC
$FFCD
$FFCE
$FFCF
$FFD0
$FFD1
$FFD2
$FFD3
$FFD4
$FFD5
$FFD6
$FFD7
$FFD8
$FFD9
$FFDA
$FFDB
$FFDC
$FFDD
$FFDE
$FFDF
$FFE0
$FFE1
$FFE2
$FFE3
$FFE4
$FFE5
$FFE6
$FFE7
$FFE8
$FFE9
$FFEA
$FFEB
$FFEC
$FFED
$FFEE
$FFEF
ADC Vector (Low)
Keyboard Vector (High)
Keyboard Vector (Low)
SCI Transmit Vector (High)
SCI Transmit Vector (Low)
SCI Receive Vector (High)
SCI Receive Vector (Low)
SCI Error Vector (High)
SCI Error Vector (Low)
CAN Transmit Vector (High)
CAN Transmit Vector (Low)
CAN Receive Vector (High)
CAN Receive Vector (Low)
CAN Error Vector (High)
CAN Error Vector (Low)
CAN Wakeup Vector (High)
CAN Wakeup Vector (Low)
SPI Transmit Vector (High)
SPI Transmit Vector (Low)
SPI Receive Vector (High)
SPI Receive Vector (Low)
TIMB Overflow Vector (High)
TIMB Overflow Vector (Low)
TIMB CH1 Vector (High)
TIMB CH1 Vector (Low)
TIMB CH0 Vector (High)
TIMB CH0 Vector (Low)
TIMA Overflow Vector (High)
TIMA Overflow Vector (Low)
TIMA CH3 Vector (High)
TIMA CH3 Vector (Low)
11-mem48
MC68HC08AZ60 — Rev 1.0
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Table 1. Vector Addresses (Continued)
Address
$FFF0
$FFF1
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
$FFF8
$FFF9
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
Vector
TIMA CH2 Vector (High)
TIMA CH2 Vector (Low)
TIMA CH1 Vector (High)
TIMA CH1 Vector (Low)
TIMA CH0 Vector (High)
TIMA CH0 Vector (Low)
TIM Vector (High)
TIM Vector (Low)
PLL Vector (High)
PLL Vector (Low)
IRQ1 Vector (High)
IRQ1 Vector (Low)
SWI Vector (High)
SWI Vector (Low)
Reset Vector (High)
$FFFF
Reset Vector (Low)
Note that all available ROM locations that not defined by the user will,
by default, be filled with the software interrupt instruction (SWI, opcode
83) – see Central Processor Unit (CPU). Please take this into account
when defining vector addresses. It is recommended that all vector
addresses are defined.
12-mem48
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A — See “accumulator (A).”
accumulator (A) — An 8-bit general-purpose register in the CPU08. The CPU08 uses the
accumulator to hold operands and results of arithmetic and logic operations.
acquisition mode — A mode of PLL operation during startup before the PLL locks on a
frequency. Also see "tracking mode."
address bus — The set of wires that the CPU or DMA uses to read and write memory locations.
addressing mode — The way that the CPU determines the operand address for an instruction.
The M68HC08 CPU has 16 addressing modes.
ALU — See “arithmetic logic unit (ALU).”
arithmetic logic unit (ALU) — The portion of the CPU that contains the logic circuitry to perform
arithmetic, logic, and manipulation operations on operands.
asynchronous — Refers to logic circuits and operations that are not synchronized by a common
reference signal.
baud rate — The total number of bits transmitted per unit of time.
BCD — See “binary-coded decimal (BCD).”
binary — Relating to the base 2 number system.
binary number system — The base 2 number system, having two digits, 0 and 1. Binary
arithmetic is convenient in digital circuit design because digital circuits have two
permissible voltage levels, low and high. The binary digits 0 and 1 can be interpreted to
correspond to the two digital voltage levels.
binary-coded decimal (BCD) — A notation that uses 4-bit binary numbers to represent the 10
decimal digits and that retains the same positional structure of a decimal number. For
example,
234 (decimal) = 0010 0011 0100 (BCD)
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bit — A binary digit. A bit has a value of either logic 0 or logic 1.
branch instruction — An instruction that causes the CPU to continue processing at a memory
location other than the next sequential address.
break module — A module in the M68HC08 Family. The break module allows software to halt
program execution at a programmable point in order to enter a background routine.
breakpoint — A number written into the break address registers of the break module. When a
number appears on the internal address bus that is the same as the number in the break
address registers, the CPU executes the software interrupt instruction (SWI).
break interrupt — A software interrupt caused by the appearance on the internal address bus
of the same value that is written in the break address registers.
bus — A set of wires that transfers logic signals.
bus clock — The bus clock is derived from the CGMOUT output from the CGM. The bus clock
frequency, fop, is equal to the frequency of the oscillator output, CGMXCLK, divided by
four.
byte — A set of eight bits.
C — The carry/borrow bit in the condition code register. The CPU08 sets the carry/borrow bit
when an addition operation produces a carry out of bit 7 of the accumulator or when a
subtraction operation requires a borrow. Some logical operations and data manipulation
instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and
shifts and rotates).
CCR — See “condition code register.”
central processor unit (CPU) — The primary functioning unit of any computer system. The
CPU controls the execution of instructions.
CGM — See “clock generator module (CGM).”
clear — To change a bit from logic 1 to logic 0; the opposite of set.
clock — A square wave signal used to synchronize events in a computer.
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clock generator module (CGM) — A module in the M68HC08 Family. The CGM generates a
base clock signal from which the system clocks are derived. The CGM may include a
crystal oscillator circuit and or phase-locked loop (PLL) circuit.
comparator — A device that compares the magnitude of two inputs. A digital comparator defines
the equality or relative differences between two binary numbers.
computer operating properly module (COP) — A counter module in the M68HC08 Family that
resets the MCU if allowed to overflow.
condition code register (CCR) — An 8-bit register in the CPU08 that contains the interrupt
mask bit and five bits that indicate the results of the instruction just executed.
control bit — One bit of a register manipulated by software to control the operation of the
module.
control unit — One of two major units of the CPU. The control unit contains logic functions that
synchronize the machine and direct various operations. The control unit decodes
instructions and generates the internal control signals that perform the requested
operations. The outputs of the control unit drive the execution unit, which contains the
arithmetic logic unit (ALU), CPU registers, and bus interface.
COP — See "computer operating properly module (COP)."
counter clock — The input clock to the TIM counter. This clock is the output of the TIM
prescaler.
CPU — See “central processor unit (CPU).”
CPU08 — The central processor unit of the M68HC08 Family.
CPU clock — The CPU clock is derived from the CGMOUT output from the CGM. The CPU
clock frequency is equal to the frequency of the oscillator output, CGMXCLK, divided by
four.
CPU cycles — A CPU cycle is one period of the internal bus clock, normally derived by dividing
a crystal oscillator source by two or more so the high and low times will be equal. The
length of time required to execute an instruction is measured in CPU clock cycles.
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CPU registers — Memory locations that are wired directly into the CPU logic instead of being
part of the addressable memory map. The CPU always has direct access to the
information in these registers. The CPU registers in an M68HC08 are:
• A (8-bit accumulator)
• H:X (16-bit index register)
• SP (16-bit stack pointer)
• PC (16-bit program counter)
• CCR (condition code register containing the V, H, I, N, Z, and C bits)
CSIC — customer-specified integrated circuit
cycle time — The period of the operating frequency: tCYC = 1/fOP.
decimal number system — Base 10 numbering system that uses the digits zero through nine.
direct memory access module (DMA) — A M68HC08 Family module that can perform data
transfers between any two CPU-addressable locations without CPU intervention. For
transmitting or receiving blocks of data to or from peripherals, DMA transfers are faster
and more code-efficient than CPU interrupts.
DMA — See "direct memory access module (DMA)."
DMA service request — A signal from a peripheral to the DMA module that enables the DMA
module to transfer data.
duty cycle — A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is
usually represented by a percentage.
EEPROM — Electrically erasable, programmable, read-only memory. A nonvolatile type of
memory that can be electrically reprogrammed.
EPROM — Erasable, programmable, read-only memory. A nonvolatile type of memory that can
be erased by exposure to an ultraviolet light source and then reprogrammed.
exception — An event such as an interrupt or a reset that stops the sequential execution of the
instructions in the main program.
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external interrupt module (IRQ) — A module in the M68HC08 Family with both dedicated
external interrupt pins and port pins that can be enabled as interrupt pins.
fetch — To copy data from a memory location into the accumulator.
firmware — Instructions and data programmed into nonvolatile memory.
free-running counter — A device that counts from zero to a predetermined number, then rolls
over to zero and begins counting again.
full-duplex transmission — Communication on a channel in which data can be sent and
received simultaneously.
H — The upper byte of the 16-bit index register (H:X) in the CPU08.
H — The half-carry bit in the condition code register of the CPU08. This bit indicates a carry from
the low-order four bits of the accumulator value to the high-order four bits. The half-carry
bit is required for binary-coded decimal arithmetic operations. The decimal adjust
accumulator (DAA) instruction uses the state of the H and C bits to determine the
appropriate correction factor.
hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A
through F.
high byte — The most significant eight bits of a word.
illegal address — An address not within the memory map
illegal opcode — A nonexistent opcode.
I — The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts
are disabled.
index register (H:X) — A 16-bit register in the CPU08. The upper byte of H:X is called H. The
lower byte is called X. In the indexed addressing modes, the CPU uses the contents of
H:X to determine the effective address of the operand. H:X can also serve as a temporary
data storage location.
input/output (I/O) — Input/output interfaces between a computer system and the external world.
A CPU reads an input to sense the level of an external signal and writes to an output to
change the level on an external signal.
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instructions — Operations that a CPU can perform. Instructions are expressed by programmers
as assembly language mnemonics. A CPU interprets an opcode and its associated
operand(s) and instruction.
interrupt — A temporary break in the sequential execution of a program to respond to signals
from peripheral devices by executing a subroutine.
interrupt request — A signal from a peripheral to the CPU intended to cause the CPU to
execute a subroutine.
I/O — See “input/output (I/0).”
IRQ — See "external interrupt module (IRQ)."
jitter — Short-term signal instability.
latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power
is applied to the circuit.
latency — The time lag between instruction completion and data movement.
least significant bit (LSB) — The rightmost digit of a binary number.
logic 1 — A voltage level approximately equal to the input power voltage (VDD).
logic 0 — A voltage level approximately equal to the ground voltage (VSS).
low byte — The least significant eight bits of a word.
low voltage inhibit module (LVI) — A module in the M68HC08 Family that monitors power
supply voltage.
LVI — See "low voltage inhibit module (LVI)."
M68HC08 — A Motorola family of 8-bit MCUs.
mark/space — The logic 1/logic 0 convention used in formatting data in serial communication.
mask — 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used
in integrated circuit fabrication to transfer an image onto silicon.
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mask option — A optional microcontroller feature that the customer chooses to enable or
disable.
mask option register (MOR) — An EPROM location containing bits that enable or disable
certain MCU features.
MCU — Microcontroller unit. See “microcontroller.”
memory location — Each M68HC08 memory location holds one byte of data and has a unique
address. To store information in a memory location, the CPU places the address of the
location on the address bus, the data information on the data bus, and asserts the write
signal. To read information from a memory location, the CPU places the address of the
location on the address bus and asserts the read signal. In response to the read signal,
the selected memory location places its data onto the data bus.
memory map — A pictorial representation of all memory locations in a computer system.
microcontroller — Microcontroller unit (MCU). A complete computer system, including a CPU,
memory, a clock oscillator, and input/output (I/O) on a single integrated circuit.
modulo counter — A counter that can be programmed to count to any number from zero to its
maximum possible modulus.
monitor ROM — A section of ROM that can execute commands from a host computer for testing
purposes.
MOR — See "mask option register (MOR)."
most significant bit (MSB) — The leftmost digit of a binary number.
multiplexer — A device that can select one of a number of inputs and pass the logic level of that
input on to the output.
N — The negative bit in the condition code register of the CPU08. The CPU sets the negative bit
when an arithmetic operation, logical operation, or data manipulation produces a negative
result.
nibble — A set of four bits (half of a byte).
object code — The output from an assembler or compiler that is itself executable machine code,
or is suitable for processing to produce executable machine code.
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opcode — A binary code that instructs the CPU to perform an operation.
open-drain — An output that has no pullup transistor. An external pullup device can be
connected to the power supply to provide the logic 1 output voltage.
operand — Data on which an operation is performed. Usually a statement consists of an
operator and an operand. For example, the operator may be an add instruction, and the
operand may be the quantity to be added.
oscillator — A circuit that produces a constant frequency square wave that is used by the
computer as a timing and sequencing reference.
OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that
cannot be reprogrammed.
overflow — A quantity that is too large to be contained in one byte or one word.
page zero — The first 256 bytes of memory (addresses $0000–$00FF).
parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted.
In a system that uses odd parity, every byte is expected to have an odd number of logic
1s. In an even parity system, every byte should have an even number of logic 1s. In the
transmitter, a parity generator appends an extra bit to each byte to make the number of
logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts
the number of logic 1s in each byte. The parity checker generates an error signal if it finds
a byte with an incorrect number of logic 1s.
PC — See “program counter (PC).”
peripheral — A circuit not under direct CPU control.
phase-locked loop (PLL) — A oscillator circuit in which the frequency of the oscillator is
synchronized to a reference signal.
PLL — See "phase-locked loop (PLL)."
pointer — Pointer register. An index register is sometimes called a pointer register because its
contents are used in the calculation of the address of an operand, and therefore points to
the operand.
polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different
voltage levels, VDD and VSS.
polling — Periodically reading a status bit to monitor the condition of a peripheral device.
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port — A set of wires for communicating with off-chip devices.
prescaler — A circuit that generates an output signal related to the input signal by a fractional
scale factor such as 1/2, 1/8, 1/10 etc.
program — A set of computer instructions that cause a computer to perform a desired operation
or operations.
program counter (PC) — A 16-bit register in the CPU08. The PC register holds the address of
the next instruction or operand that the CPU will use.
pull — An instruction that copies into the accumulator the contents of a stack RAM location. The
stack RAM address is in the stack pointer.
pullup — A transistor in the output of a logic gate that connects the output to the logic 1 voltage
of the power supply.
pulse-width — The amount of time a signal is on as opposed to being in its off state.
pulse-width modulation (PWM) — Controlled variation (modulation) of the pulse width of a
signal with a constant frequency.
push — An instruction that copies the contents of the accumulator to the stack RAM. The stack
RAM address is in the stack pointer.
PWM period — The time required for one complete cycle of a PWM waveform.
RAM — Random access memory. All RAM locations can be read or written by the CPU. The
contents of a RAM memory location remain valid until the CPU writes a different value or
until power is turned off.
RC circuit — A circuit consisting of capacitors and resistors having a defined time constant.
read — To copy the contents of a memory location to the accumulator.
register — A circuit that stores a group of bits.
reserved memory location — A memory location that is used only in special factory test modes.
Writing to a reserved location has no effect. Reading a reserved location returns an
unpredictable value.
reset — To force a device to a known condition.
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ROM — Read-only memory. A type of memory that can be read but cannot be changed (written).
The contents of ROM must be specified before manufacturing the MCU.
SCI — See "serial communication interface module (SCI)."
serial — Pertaining to sequential transmission over a single line.
serial communications interface module (SCI) — A module in the M68HC08 Family that
supports asynchronous communication.
serial peripheral interface module (SPI) — A module in the M68HC08 Family that supports
synchronous communication.
set — To change a bit from logic 0 to logic 1; opposite of clear.
shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to
them and that can shift the logic levels to the right or left through adjacent circuits in the
chain.
signed — A binary number notation that accommodates both positive and negative numbers.
The most significant bit is used to indicate whether the number is positive or negative,
normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the
magnitude of the number.
software — Instructions and data that control the operation of a microcontroller.
software interrupt (SWI) — An instruction that causes an interrupt and its associated vector
fetch.
SPI — See "serial peripheral interface module (SPI)."
stack — A portion of RAM reserved for storage of CPU register contents and subroutine return
addresses.
stack pointer (SP) — A 16-bit register in the CPU08 containing the address of the next available
storage location on the stack.
start bit — A bit that signals the beginning of an asynchronous serial transmission.
status bit — A register bit that indicates the condition of a device.
stop bit — A bit that signals the end of an asynchronous serial transmission.
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subroutine — A sequence of instructions to be used more than once in the course of a program.
The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each
place in the main program where the subroutine instructions are needed, a jump or branch
to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the
flow of the main program to execute the instructions in the subroutine. When the RTS
instruction is executed, the CPU returns to the main program where it left off.
synchronous — Refers to logic circuits and operations that are synchronized by a common
reference signal.
TIM — See "timer interface module (TIM)."
timer interface module (TIM) — A module used to relate events in a system to a point in time.
timer — A module used to relate events in a system to a point in time.
toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0.
tracking mode — Mode of low-jitter PLL operation during which the PLL is locked on a
frequency. Also see "acquisition mode."
two’s complement — A means of performing binary subtraction using addition techniques. The
most significant bit of a two’s complement number indicates the sign of the number (1
indicates negative). The two’s complement negative of a number is obtained by inverting
each bit in the number and then adding 1 to the result.
unbuffered — Utilizes only one register for data; new data overwrites current data.
unimplemented memory location — A memory location that is not used. Writing to an
unimplemented location has no effect. Reading an unimplemented location returns an
unpredictable value. Executing an opcode at an unimplemented location causes an illegal
address reset.
V —The overflow bit in the condition code register of the CPU08. The CPU08 sets the V bit when
a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE,
and BLT use the overflow bit.
variable — A value that changes during the course of program execution.
VCO — See "voltage-controlled oscillator."
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vector — A memory location that contains the address of the beginning of a subroutine written
to service an interrupt or reset.
voltage-controlled oscillator (VCO) — A circuit that produces an oscillating output signal of a
frequency that is controlled by a dc voltage applied to a control input.
waveform — A graphical representation in which the amplitude of a wave is plotted against time.
wired-OR — Connection of circuit outputs so that if any output is high, the connection point is
high.
word — A set of two bytes (16 bits).
write — The transfer of a byte of data from the CPU to a memory location.
X — The lower byte of the index register (H:X) in the CPU08.
Z — The zero bit in the condition code register of the CPU08. The CPU08 sets the zero bit when
an arithmetic operation, logical operation, or data manipulation produces a result of $00.
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