MC68HC908AZ60VFU_技术文档

List of Sections

List of Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

FLASH-1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

FLASH-2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

EEPROM-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

EEPROM-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . 87

System Integration Module (SIM). . . . . . . . . . . . . . . . . 105

Clock Generator Module (CGM). . . . . . . . . . . . . . . . . 127

Configuration Register (CONFIG-1). . . . . . . . . . . . . . . 155

Configuration Register (CONFIG-2). . . . . . . . . . . . . . . 159

Break Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

MOTOROLA

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List of Sections

Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Computer Operating Properly Module (COP) . . . . . . 179

Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . . . . 185

External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . 191

Serial Communications Interface Module (SCI). . . . . 199

Serial Peripheral Interface Module (SPI) . . . . . . . . . . . 237

Timer Interface Module B (TIMB) . . . . . . . . . . . . . . . . . 269

Programmable Interrupt Timer (PIT). . . . . . . . . . . . . . . 295

I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

MSCAN Controller (MSCAN08). . . . . . . . . . . . . . . . . . . 331

Keyboard Module (KBD). . . . . . . . . . . . . . . . . . . . . . . . 381

Timer Interface Module A (TIMA-6) . . . . . . . . . . . . . . . 389

Analog-to-Digital Converter (ADC-15) . . . . . . . . . . . . 421

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

Appendix A: Future EEPROM Registers . . . . . . . . . . . . 449

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Literature Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

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MOTOROLA

Table of Contents

List of Sections

Table of Contents

General Description

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Memory Map

RAM

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

FLASH-1 Memory

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Future FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

FLASH-1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

FLASH Charge Pump Frequency Control . . . . . . . . . . . . . . . . . . . . .41

FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . . . . . . .43

FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

FLASH-1 Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

FLASH-2 Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

FLASH-2 Memory

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Future FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

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Table of Contents

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

FLASH Charge Pump Frequency Control . . . . . . . . . . . . . . . . . . . . .55

FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . . . . . . .57

FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

EEPROM-1

EEPROM-2

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Future EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Future EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Central Processor

Unit (CPU)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

System Integration

Module (SIM)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . .109

Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Program Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

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Table of Contents

Clock Generator

Module (CGM)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . . . . . 149

Configuration

Register

(CONFIG-1)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Configuration

Register

(CONFIG-2)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Break Module

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Monitor ROM

(MON)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Computer

Operating

Properly Module

(COP)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 184

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Table of Contents

Low-Voltage

Inhibit (LVI)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

External Interrupt

Module (IRQ)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . .196

IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .197

Serial

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .219

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219

I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

Communications

Interface Module

(SCI)

Serial Peripheral

Interface Module

(SPI)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

Pin Name and Register Name Conventions . . . . . . . . . . . . . . . . . . .239

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255

Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

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Timer Interface

Module B (TIMB)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

TIMB During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Programmable

Interrupt Timer (PIT)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

PIT Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

PIT During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

I/O Ports

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

MSCAN Controller

(MSCAN08)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

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Table of Contents

Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355

Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . .355

Programmer’s Model of Control Registers . . . . . . . . . . . . . . . . . . . .360

Keyboard Module

(KBD)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382

Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386

Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . . . . . .386

I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387

Timer Interface

Module A (TIMA-6)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403

TIMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405

I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406

Analog-to-Digital

Converter (ADC-15)

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426

I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427

Specifications

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .433

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .434

Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447

Appendix A: Future

EEPROM Registers

EEPROM Timebase Divider Control Registers . . . . . . . . . . . . . . . .449

EEDIVH and EEDIVL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .450

EEDIV Non-volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451

MC68HC908AZ60 — Rev 2.0

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MOTOROLA

Table of Contents

Glossary

Literature Updates

Literature Distribution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

Customer Focus Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

Microcontroller Division’s Web Site . . . . . . . . . . . . . . . . . . . . . . . . . 466

Revision History

Major Changes Between Revision 2.0 and Revision 1.0 . . . . . . . . 469

MC68HC908AZ60 — Rev 2.0

MOTOROLA

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MC68HC908AZ60 — Rev 2.0

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MOTOROLA

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . . . . . . 16

Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . 16

External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Analog Power Supply Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . 17

Analog Ground Pin (VSSA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . 17

Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . . . . . . . . . 17

Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) . . . . . . . . . . . . . . . . . . 17

Port C I/O Pins (PTC5–PTC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Port D I/O Pins (PTD7–PTD0/ATD8) . . . . . . . . . . . . . . . . . . . . . . . 18

Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) . . . . . . . . . . . . . . . . . . 18

Port F I/O Pins (PTF6–PTF0/TACH2). . . . . . . . . . . . . . . . . . . . . . . 18

Port G I/O Pins (PTG2/KBD2–PTG0/KBD0). . . . . . . . . . . . . . . . . . 18

Port H I/O Pins (PTH1/KBD4–PTH0/KBD3) . . . . . . . . . . . . . . . . . . 18

CAN Transmit Pin (CANTx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CAN Receive Pin (CANRx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

MC Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Introduction

The MC68HC908AZ60 is a member of the low-cost, high-performance

M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08

Family is based on the customer-specified integrated circuit (CSIC)

design strategy. All MCUs in the family use the enhanced M68HC08

1-gen

MC68HC908AZ60 — Rev 2.0

MOTOROLA

General Description

11

General Description

central processor unit (CPU08) and are available with a variety of

modules, memory sizes and types, and package types.

This part is designed to emulate the MC68HC08AZxx automotive family.

In AZxx mode the MC68HC908AZ60 offers extra features which are not

available on the MC68HC08AZ32 device. It is the user’s responsibility to

ensure compatibility between the features used on the

MC68HC908AZ60 and those which are available on the device which

will ultimately be used in the application.

Features

Features of the MC68HC908AZ60 include:

• High-Performance M68HC08 Architecture

• Fully Upward-Compatible Object Code with M6805, M146805,

and M68HC05 Families

• 8.4 MHz Internal Bus Frequency

• 60 Kbytes of FLASH Electrically Erasable Read-Only Memory

(FLASH)

• FLASH Data Security

• 1 Kbyte of On-Chip Electrically Erasable Programmable

Read-Only Memory with Security Option (EEPROM)

• 2 Kbyte of On-Chip RAM

• Clock Generator Module (CGM)

• Serial Peripheral Interface Module (SPI)

• Serial Communications Interface Module (SCI)

• 8-Bit, 15-Channel Analog-to-Digital Converter (ADC-15)

• 16-Bit, 6-Channel Timer Interface Module (TIMA-6)

• Programmable Interrupt Timer (PIT)

• System Protection Features

2-gen

MC68HC908AZ60 — Rev 2.0

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General Description

MOTOROLA

General Description

MCU Block Diagram

– Computer Operating Properly (COP) with Optional Reset

– Low-Voltage Detection with Optional Reset

– Illegal Opcode Detection with Optional Reset

– Illegal Address Detection with Optional Reset

• Low-Power Design (Fully Static with Stop and Wait Modes)

• Master Reset Pin and Power-On Reset

• 16-Bit, 2-Channel Timer Interface Module (TIMB)

• 5-Bit Keyboard Interrupt Module

• MSCAN Controller (Motorola Scalable CAN) implements CAN

2.0b Protocol as Defined in BOSCH Specification September

1991

Features of the CPU08 include:

• Enhanced HC05 Programming Model

• Extensive Loop Control Functions

• 16 Addressing Modes (Eight More Than the HC05)

• 16-Bit Index Register and Stack Pointer

• Memory-to-Memory Data Transfers

• Fast 8 × 8 Multiply Instruction

• Fast 16/8 Divide Instruction

• Binary-Coded Decimal (BCD) Instructions

• Optimization for Controller Applications

• C Language Support

MCU Block Diagram

Figure 1 shows the structure of the MC68HC908AZ60.

3-gen

MC68HC908AZ60 — Rev 2.0

13

MOTOROLA

General Description

Pin Assignments

Figure 2 shows the MC68HC908AZ60 pin assignments.

PTC4

IRQ

PTH0/KBD3

PTD3/ATD11

PTD2/ATD10

1

48

2

47

46

45

44

43

42

41

40

39

38

37

36

35

34

RST

3

PTF0/TACH2

PTF1/TACH3

PTF2/TACH4

PTF3/TACH5

PTF4/TBCH0

CANRx

AV /V

4

SS REFL

V

5

DDAREF

PTD1/ATD9

6

PTD0/ATD8

PTB7/ATD7

7

8

PTB6/ATD6

PTB5/ATD5

PTB4/ATD4

PTB3/ATD3

PTB2/ATD2

PTB1/ATD1

PTB0/ATD0

PTA7

9

CANTx

10

11

12

13

14

15

PTF5/TBCH1

PTF6

PTE0/TxD

PTE1/RxD

PTE2/TACH0

PTE3/TACH1

16

33

Figure 2. MC68HC908AZ60 (64-Pin QFP)

NOTE: The following pin descriptions are just a quick reference. For a more

detailed representation, see I/O Ports on page 305.

5-gen

MC68HC908AZ60 — Rev 2.0

MOTOROLA

General Description

15

General Description

Power Supply Pins

(V and V )

V

and V are the power supply and ground pins. The MCU operates

DD SS

from a single power supply.

DD

SS

Fast signal transitions on MCU pins place high, short-duration current

demands on the power supply. To prevent noise problems, take special

care to provide power supply bypassing at the MCU as shown in Figure

3. Place the C1 bypass capacitor as close to the MCU as possible. Use

a high-frequency response ceramic capacitor for C1. C2 is an optional

bulk current bypass capacitor for use in applications that require the port

pins to source high current levels.

MCU

V_DD

V

SS

C1

0.1 µF

+

C2

V_DD

NOTE: Component values shown represent typical applications.

Figure 3. Power supply bypassing

V

is also the ground for the port output buffers and the ground return

SS

for the serial clock in the serial peripheral interface module (SPI). See

Serial Peripheral Interface Module (SPI) on page 237.

NOTE:

V

must be grounded for proper MCU operation.

SS

Oscillator Pins

The OSC1 and OSC2 pins are the connections for the on-chip oscillator

(OSC1 and OSC2)

circuit. See Clock Generator Module (CGM) on page 127.

6-gen

MC68HC908AZ60 — Rev 2.0

16

General Description

MOTOROLA

General Description

Pin Assignments

External Reset Pin

(RST)

A logic 0 on the RST pin forces the MCU to a known startup state. RST

is bidirectional, allowing a reset of the entire system. It is driven low when

any internal reset source is asserted. See

System Integration Module (SIM) on page 105 for more information.

External Interrupt

Pin (IRQ)

IRQ is an asynchronous external interrupt pin. See

External Interrupt Module (IRQ) on page 191.

Analog Power

V

is the power supply pin for the analog portion of the chip. This pin

DDA

Supply Pin (V

)

will supply the clock generator module (CGM). See

DDA

Clock Generator Module (CGM) on page 127.

Analog Ground

Pin (V

The V

analog ground pin is used only for the ground connections for

SSA

)

the analog sections of the circuit and should be decoupled as per the

digital ground pin. The analog sections consist of a clock generator

SSA

V

SS

module (CGM). See Clock Generator Module (CGM) on page 127.

External Filter

Capacitor Pin

(CGMXFC)

CGMXFC is an external filter capacitor connection for the CGM. See

Clock Generator Module (CGM) on page 127

Port A

Input/Output (I/O)

PTA7–PTA0 are general-purpose bidirectional I/O port pins. See I/O

Ports on page 305.

Pins (PTA7–PTA0)

Port B I/O Pins

(PTB7/ATD7ÐPTB0/

ATD0)

Port B is an 8-bit special function port that shares all eight pins with the

analog-to-digital converter (ADC). See

Analog-to-Digital Converter (ADC-15) on page 421 and I/O Ports on

page 305.

Port C I/O Pins

(PTC5ÐPTC0)

PTC5–PTC3 and PTC1–PTC0 are general-purpose bidirectional I/O

port pins. PTC2/MCLK is a special function port that shares its pin with

7-gen

MC68HC908AZ60 — Rev 2.0

MOTOROLA

General Description

17

General Description

the system clock which has a frequency equivalent to the system clock.

See I/O Ports on page 305.

Port D I/O Pins

(PTD7ÐPTD0/ATD8)

Port D is an 8-bit special-function port that shares seven of its pins with

the analog-to-digital converter module (ADC-15), one of its pins with the

timer interface module (TIMA), and one more of its pins with the timer

interface module (TIMB). See Timer Interface Module A (TIMA-6) on

page 389, Analog-to-Digital Converter (ADC-15) on page 421 and I/O

Ports on page 305.

Port E I/O Pins

(PTE7/SPSCKÐPTE0/

TxD)

Port E is an 8-bit special function port that shares two of its pins with the

timer interface module (TIMA), four of its pins with the serial peripheral

interface module (SPI), and two of its pins with the serial communication

interface module (SCI). See

Serial Communications Interface Module (SCI) on page 199,

Serial Peripheral Interface Module (SPI) on page 237,

Timer Interface Module A (TIMA-6) on page 389, and I/O Ports on

page 305.

Port F I/O Pins

(PTF6ÐPTF0/TACH2)

Port F is a 7-bit special function port that shares its pins with the timer

interface module (TIMB). Six of its pins are shared with the timer

interface module (TIMA-6). See Timer Interface Module A (TIMA-6) on

page 389, Timer Interface Module B (TIMB) on page 269, and I/O

Ports on page 305.

Port G I/O Pins

(PTG2/KBD2ÐPTG0

/KBD0)

Port G is a 3-bit special function port that shares all of its pins with the

keyboard interrupt module (KBD). See Keyboard Module (KBD) on

page 381 and I/O Ports on page 305.

Port H I/O Pins

(PTH1/KBD4ÐPTH0/

KBD3)

Port H is a 2-bit special-function port that shares all of its pins with the

keyboard interrupt module (KBD). See Keyboard Module (KBD) on

page 381 and I/O Ports on page 305.

8-gen

MC68HC908AZ60 — Rev 2.0

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General Description

MOTOROLA

General Description

Pin Assignments

CAN Transmit Pin

(CANTx)

This pin is the digital output from the CAN module (CANTx). See

MSCAN Controller (MSCAN08) on page 331.

CAN Receive Pin

(CANRx)

This pin is the digital input to the CAN module (CANRx). See MSCAN

Controller (MSCAN08) on page 331.

Table 1. External Pins Summary

Driver

Type

Hysteresis

(note 1)

Pin Name

Function

Reset State

Input Hi-Z

PTA7–PTA0

General-Purpose I/O

Dual State

No

General-Purpose I/O

ADC Channel

PTB7/ATD7–PTB0/ATD0

PTC5–PTC0

PTD7

General-Purpose I/O

General Purpose I/O/

Dual State

No

Input Hi-Z

General-Purpose I/O

ADC Channel/Timer

External Input Clock

PTD6/ATD14/TACLK ADC Channel

PTD5/ATD13 ADC Channel

Dual State

No

Input Hi-Z

General-Purpose I/O

ADC Channel

Input Hi-Z

General-Purpose I/O

ADC Channel/Timer

External Input Clock

PTD4/ATD12/TBCLK ADC Channel

Dual State

General-Purpose I/O

ADC Channel

Input Hi-Z

PTD3/ATD11–PTD0/ATD8 ADC Channels

PTE7/SPSCK

No

Yes

General-Purpose I/O

SPI Clock

Dual State

Open Drain

Input Hi-Z

General-Purpose I/O

SPI Data Path

Dual State

Open Drain

PTE6/MOSI

General-Purpose I/O

SPI Data Path

Dual State

Open Drain

PTE5/MISO

General-Purpose I/O

SPI Slave Select

PTE4/SS

Dual State

General-Purpose I/O

Timer Channel 1

PTE3/TACH1

General-Purpose I/O

Timer Channel 0

PTE2/TACH0

General-Purpose I/O

SCI Receive Data

PTE1/RxD

9-gen

MC68HC908AZ60 — Rev 2.0

19

MOTOROLA

General Description

Table 1. External Pins Summary (Continued)

Driver

Type

Hysteresis

(note 1)

Pin Name

Function

Reset State

General-Purpose I/O

SCI Transmit Data

PTE0/TxD

PTF6

Dual State

No

Input Hi-Z

General-Purpose I/O

General-Purpose

I/O/Timer B Channel

PTF5/TBCH1–PTF4/TBCH0

Yes

General-Purpose I/O

Timer A Channel 5

PTF3/TACH5

PTF2/TACH4

Dual State

Yes

Input Hi-Z

General-Purpose I/O

Timer A Channel 4

General-Purpose I/O

Timer A Channel 3

PTF1/TACH3

General-Purpose I/O

Timer A Channel 2

PTF0/TACH2

General-Purpose I/O/

Keyboard Wakeup Pin

PTG2/KBD2–PTG0/KBD0

PTH1/KBD4 –PTH0/KBD3

General-Purpose I/O/

Keyboard Wakeup Pin

V

Chip Power Supply

Chip Ground

N/A

DD

V

SS

ADC Power Supply/

ADC Reference

Voltage

V

N/A

DDAREF

ADC Ground/ADC

Reference Voltage

A

/V

N/A

VSS REFL

A/D Reference

Voltage

V

REFH

OSC1

OSC2

External Clock In

External Clock Out

PLL Loop Filter Cap

N/A

Input Hi-Z

Output

N/A

CGMXFC

External Interrupt

Request

IRQ

N/A

Input Hi-Z

RST

Reset

N/A

Yes

No

Output Low

Input Hi-Z

Output

CANRx

CANTx

CAN Serial Input

CAN Serial Output

Output

10-gen

MC68HC908AZ60 — Rev 2.0

20

General Description

MOTOROLA

General Description

Pin Assignments

Table 2. Clock Source Summary

Module

ADC

CAN

COP

CPU

EEPROM

SPI

Clock Source

CGMXCLK or Bus Clock

CGMXCLK or CGMOUT

CGMXCLK

Bus Clock

RC OSC or Bus Clock

Bus Clock/SPSCK

CGMXCLK

SCI

TIMA-6

TIMB

PIT

Bus Clock or PTD6/ATD14/TACLK

Bus Clock or PTD4/TBCLK

Bus Clock

SIM

CGMOUT and CGMXCLK

Bus Clock

IRQ

BRK

Bus Clock

LVI

Bus Clock

CGM

OSC1 and OSC2

Note 1: Hysteresis is not 100% tested but is typically a minimum of

300mV

11-gen

MC68HC908AZ60 — Rev 2.0

MOTOROLA

General Description

21

General Description

Ordering Information

This section contains instructions for ordering the MC68HC908AZ60.

MC Order

Numbers

Table 3. MC Order Numbers

Operating

Temperature Range

MC Order Number

MC68HC908AZ60CFU

–40 °C to + 85°C

MC68HC908AZ60VFU

MC68HC908AZ60MFU

–40 °C to + 105 °C

–40 °C to + 125 °C

12-gen

MC68HC908AZ60 — Rev 2.0

22

General Description

MOTOROLA

Memory Map

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Introduction

The CPU08 can address 64 Kbytes of memory space. The memory

map, shown in Figure 1, includes:

• 60 Kbytes of FLASH EEPROM

• 2048 Bytes of RAM

• 1024 Bytes of EEPROM with Protect Option

• 52 Bytes of User-Defined Vectors

• 224 Bytes of Monitor ROM

The following definitions apply to the memory map representation of

reserved and unimplemented locations.

•

Reserved — Accessing a reserved location can have

unpredictable effects on MCU operation.

Unimplemented — Accessing an unimplemented location

causes an illegal address reset if illegal address resets are

enabled.

1-mem

MC68HC908AZ60 — Rev 2.0

23

MOTOROLA

Memory Map

Figure 1. Memory Map

$0000

↓

$0000

↓

I/O REGISTERS (64 BYTES)

$003F

$0040

↓

$003F

$0040

↓

I/O REGISTERS, 16 BYTES

RAM-1, 1024 BYTES

$004F

$0050

↓

$004F

$0050

↓

$044F

$0450

↓

$044F

$0450

↓

FLASH-2, 176 BYTES

$04FF

$0500

↓

$04FF

$0500

↓

CAN CONTROL AND MESSAGE

BUFFERS, 128 BYTES

$057F

$0580

↓

$057F

$0580

↓

FLASH-2, 128 BYTES

EEPROM-2, 512 BYTES

EEPROM-1, 512 BYTES

RAM-2 , 1024 BYTES

$05FF

$0600

↓

$05FF

$0600

↓

$07FF

$0800

↓

$07FF

$0800

↓

$09FF

$0A00

↓

$09FF

$0A00

↓

$0DFF

$0E00

↓

$0DFF

$0E00

↓

FLASH-2, 29,184 BYTES

FLASH-1, 32,256BYTES

$7FFF

$8000

↓

$7FFF

$8000

↓

$FDFF

$FE00

$FE01

$FE02

$FE03

$FDFF

$FE00

$FE01

$FE02

$FE03

SIM BREAK STATUS REGISTER (SBSR)

SIM RESET STATUS REGISTER (SRSR)

RESERVED

SIM BREAK FLAG CONTROL REGISTER (SBFCR)

2-mem

MC68HC908AZ60 — Rev 2.0

24

Memory Map

MOTOROLA

Memory Map

Introduction

Figure 1. Memory Map (Continued)

$FE04

$FE05

$FE06

$FE07

$FE08

RESERVED

$FE04

$FE05

$FE06

$FE07

$FE08

UNIMPLEMENTED

RESERVED

CONFIGURATION WRITE-ONCE REGISER

(CONFIG-2)

$FE09

$FE0A

$FE0B

$FE0C

$FE0D

RESERVED

$FE0A

$FE0B

$FE0C

$FE0D

$FE0E

$FE0F

$FE10

$FE11

$FE12

↓

FLASH CONTROL REGISTER (FLCR1)

BREAK ADDRESS REGISTER HIGH (BRKH)

BREAK ADDRESS REGISTER LOW (BRKL)

$FE0E BREAK STATUS AND CONTROL REGISTER (BSCR)

$FE0F

$FE10

$FE11

$FE12

↓

LVI STATUS REGISTER (LVISR)

RESERVED

FLASH CONTROL REGISTER (FLCR2)

UNIMPLEMENTED (5BYTES)

$FE17

$FE18

$FE19

$FE1A

$FE1B

$FE1C

$FE1D

$FE1E

$FE1F

$FE20

↓

$FE17

$FE18

$FE19

$FE1A

$FE1B

$FE1C

$FE1D

$FE1E

$FE1F

$FE20

↓

EEPROM NON-VOLATILE REGISTER (EENVR2)

EEPROM CONTROL REGISTER (EECR2)

RESERVED

EEPROM ARRAY CONFIGURATION (EEACR2)

EEPROM NON-VOLATILE REGISTER (EENVR1)

EEPROM CONTROL REGISTER (EECR1)

RESERVED

EEPROM ARRAY CONFIGURATION (EEACR1)

MONITOR ROM (224 BYTES)

$FEFF

$FF00

↓

$FF00

↓

UNIMPLEMENTED (128 BYTES)

$FF7F

$FF80

$FF81

$FF82

↓

FLASH BLOCK PROTECT REGISTER (FLBPR1)

FLASH BLOCK PROTECT REGISTER (FLBPR2)

$FF80

$FF81

$FF82

↓

RESERVED (75 BYTES)

$FFCB

3-mem

MC68HC908AZ60 — Rev 2.0

25

MOTOROLA

Memory Map

Figure 1. Memory Map (Continued)

$FFCC

↓

$FFCC

↓

VECTORS (52BYTES)

$FFFF

I/O Section

Addresses $0000–$003F, shown in Figure 2, contain most of the

control, status, and data registers. Additional I/O registers have these

addresses:

• $FE00 (SIM break status register, SBSR)

• $FE01 (SIM reset status register, SRSR)

• $FE03 (SIM break flag control register, SBFCR)

• $FE09 (configuration write-once register, CONFIG-2)

• $FE0B (FLASH control register, FLCR1)

• $FE0C and $FE0D (break address registers, BRKH and BRKL)

• $FE0E (break status and control register, BRKSCR)

• $FE0F (LVI status register, LVISR)

• $FE11 (FLASH control register, FLCR2)

• $FE18 (EEPROM non-volatile register, EENVR2)

• $FE19 (EEPROM control register, EECR2)

• $FE1B (EEPROM array configuration register, EEACR2)

• $FE1C (EEPROM non-volatile register, EENVR1)

• $FE1D (EEPROM control register, EECR1)

• $FE1F (EEPROM array configuration register, EEACR1)

• $FF80 (FLASH block protect register, FLBPR1)

• $FF81 (FLASH block protect register, FLBPR2)

• $FFFF (COP control register, COPCTL)

Table 1 is a list of vector locations.

4-mem

MC68HC908AZ60 — Rev 2.0

26

Memory Map

MOTOROLA

Memory Map

I/O Section

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

$0000

Port A Data Register (PTA)

PTA7

PTA6

PTA5

PTA4

PTA3

PTA2

PTA1

PTB1

PTC1

PTD1

PTA0

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

Port B Data Register (PTB)

Port C Data Register (PTC)

Port D Data Register (PTD)

PTB7

0

PTB6

0

PTB5

PTC5

PTD5

PTB4

PTC4

PTD4

PTB3

PTC3

PTD3

PTB2

PTC2

PTD2

PTB0

PTC0

PTD0

PTD7

PTD6

Data Direction Register A

(DDRA)

DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0

Data Direction Register B

(DDRB)

DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

0

Data Direction Register C

(DDRC)

MCLKEN

DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0

Data Direction Register D

(DDRD)

DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDR2 DDRD1 DDRD0

Port E Data Register (PTE)

Port F Data Register (PTF)

Port G Data Register (PTG)

Port H Data Register (PTH)

PTE7

0

PTE6

PTE5

PTE4

PTE3

PTE2

PTF2

PTE1

PTF1

PTG1

PTH1

PTE0

PTF0

PTG0

PTH0

PTF6

0

PTF5

0

PTF4

0

PTF3

0

PTG2

0

Data Direction Register E

(DDRE)

DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0

0

Data Direction Register F

(DDRF)

DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0

0

Data Direction Register G

(DDRG)

DDRG2 DDRG1 DDRG0

0

Data Direction Register H

(DDRH)

DDRH1 DDRH0

SPI Control Register (SPCR)

SPRIE

R

SPMSTR CPOL

CPHA SPWOM SPE

SPTIE

Figure 2. Control, Status, and Data Registers (Sheet 1 of 6)

5-mem

MC68HC908AZ60 — Rev 2.0

27

MOTOROLA

Memory Map

Addr.

Register Name

Bit 7

6

5

4

3

R

2

1

Bit 0

= Unimplemented

= Reserved

Read: SPRF

Write:

OVRF

MODF

SPTE

SPI Status and Control

Register (SPSCR)

MODFE

N

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

$0020

$0021

ERRIE

SPR1

SPR0

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

R7

T7

R6

T6

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

R0

T0

SPI Data Register (SPDR)

SCI Control Register 1 (SCC1)

SCI Control Register 2 (SCC2)

SCI Control Register 3 (SCC3)

SCI Status Register 1 (SCS1)

SCI Status Register 2 (SCS2)

SCI Data Register (SCDR)

LOOPS ENSCI TXINV

M

WAKE

TE

ILTY

RE

PEN

PTY

SBK

SCTIE

R8

TCIE

SCRIE

ILIE

RWU

T8

R

ORIE

OR

NEIE

NF

FEIE

FE

PEIE

PE

Read: SCTE

Write:

TC

SCRF

IDLE

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

0

BKF

RPF

R7

T7

0

R6

T6

0

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

R0

T0

SCI Baud Rate Register (SCBR)

SCP1

0

SCP0

0

SCR2

0

SCR1

SCR0

0

IRQF

KEYF

1

IRQ Status and Control

Register (ISCR)

IMASK1 MODE1

IMASKK MODEK

ACK1

0

Keyboard Status and Control

Register (KBSCR)

ACKK

1

PLLF

LOCK

1

0

1

0

PLL Control Register (PCTL)

PLLIE

AUTO

PLLON

ACQ

BCS

XLD

0

PLL Bandwidth Control

Register (PBWC)

PLL Programming Register

(PPG)

MUL7

MUL6

R

MUL5

MUL4

VRS7

VRS6

VRS5

STOP

PS1

VRS4

COPD

PS0

Conﬁguration Write-Once

Register (CONFIG-1)

LVISTOP

LVIRST LVIPWR SSREC COPL

Read: TOF

0

Timer A Status and Control

Register (TASC)

TOIE

0

TSTOP

0

PS2

Write:

Read:

Write:

0

TRST

Keyboard Interrupt Enable Register

(KBIE)

KBIE4

KBIE3

KBIE2

KBIE1

KBIE0

Figure 2. Control, Status, and Data Registers (Sheet 2 of 6)

6-mem

MC68HC908AZ60 — Rev 2.0

28

Memory Map

MOTOROLA

Memory Map

I/O Section

Addr.

Register Name

Bit 7

Read: Bit 15

Write:

6

5

4

3

2

1

Bit 0

14

13

12

11

10

9

Bit 8

Timer A Counter Register

High (TACNTH)

$0022

Read: Bit 7

Write:

6

5

4

3

2

1

Bit 0

Timer A Counter Register

Low (TACNTL)

$0023

$0024

$0025

$0026

$0027

$0028

$0029

$002A

$002B

$002C

$002D

$002E

$002F

$0030

$0031

$0032

$0033

Read:

Bit 15

Write:

Timer A Modulo Register

High (TAMODH)

14

6

13

5

12

4

11

3

10

2

9

1

Bit 8

Bit 0

Read:

Bit 7

Timer A Modulo Register

Low (TAMODL)

Write:

Read: CH0F

Timer A Channel 0 Status and

Control Register (TASC0)

CH0IE

14

MS0B

13

MS0A

12

ELS0B ELS0A TOV0 CH0MAX

Write:

Read:

Write:

Read:

Write:

0

Timer A Channel 0 Register

High (TACH0H)

Bit 15

11

3

10

2

9

1

Bit 8

Bit 0

Timer A Channel 0 Register

Low (TACH0L)

Bit 7

6

5

0

4

Read: CH1F

Timer A Channel 1 Status and

Control Register (TASC1)

CH1IE

14

MS1A

12

ELS1B ELS1A TOV1 CH1MAX

Write:

Read:

Write:

Read:

Write:

0

Timer A Channel 1 Register

High (TACH1H)

Bit 15

13

5

11

3

10

2

9

1

Bit 8

Bit 0

Timer A Channel 1 Register

Low (TACH1L)

Bit 7

6

4

Read: CH2F

Timer A Channel 2 Status and

Control Register (TASC2)

CH2IE

14

MS2B

13

MS2A

12

ELS2B ELS2A TOV2 CH2MAX

Write:

Read:

Write:

Read:

Write:

0

Timer A Channel 2 Register

High (TACH2H)

Bit 15

11

3

10

2

9

1

Bit 8

Bit 0

Timer A Channel 2 Register

Low (TACH2L)

Bit 7

6

5

0

4

Read: CH3F

Timer A Channel 3 Status and

Control Register (TASC3)

CH3IE

14

MS3A

12

ELS3B ELS3A TOV3 CH3MAX

Write:

Read:

Write:

Read:

Write:

0

Timer A Channel 3 Register

High (TACH3H)

Bit 15

13

5

11

3

10

2

9

1

Bit 8

Bit 0

Timer A Channel 3 Register

Low (TACH3L)

Bit 7

6

4

Read: CH4F

Timer A Channel 4 Status and

Control Register (TASC4)

CH4IE

14

MS4B

13

MS4A

12

ELS4B ELS4A TOV4 CH4MAX

Write:

Read:

Write:

0

Timer A Channel 4 Register High

(TACH4H)

Bit 15

11

10

9

Bit 8

Figure 2. Control, Status, and Data Registers (Sheet 3 of 6)

7-mem

MC68HC908AZ60 — Rev 2.0

29

MOTOROLA

Memory Map

Addr.

Register Name

Bit 7

6

5

0

4

3

2

1

Bit 0

Read:

Write:

Timer A Channel 4 Register Low

(TACH4L)

$0034

Bit 7

6

4

3

2

1

Bit 0

Read: CH5F

Timer A Channel 5 Status and

Control Register (TASC5)

$0035

$0036

$0037

$0038

$0039

$003A

$0040

$0041

$0042

$0043

$0044

$0045

$0046

$0047

CH5IE

14

MS5A

12

ELS5B ELS5A TOV5 CH5MAX

Write:

Read:

Write:

Read:

Write:

Read:

Write:

0

Timer A Channel 5 Register

High (TACH5H)

Bit 15

13

5

11

3

10

2

9

1

Bit 8

Bit 0

Timer A Channel 5 Register

Low (TACH5L)

Bit 7

6

4

Analog-to-Digital Status and

Control Register (ADSCR)

COCO

AIEN

AD6

ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0

Read: AD7

Write:

AD5

AD4

AD3

0

AD2

0

AD1

0

AD0

0

Analog-to-Digital Data Register

(ADR)

Read:

ADIV2

Write:

Analog-to-Digital Input Clock

Register (ADICLK)

ADIV1

ADIV0 ADICLK

Read: TOF

Write:

0

TSTOP

0

Timer B Status and Control

Register (TBSCR)

TOIE

14

PS2

10

PS1

9

PS0

Bit 8

TRST

Read: Bit 15

Write:

13

5

12

11

3

Timer B Counter Register High

(TBCNTH)

Read: Bit 7

Write:

6

4

2

1

Bit 0

Timer B Counter Register Low

(TBCNTL)

Read:

Bit 15

Write:

Timer B Modulo Register High

(TBMODH)

14

6

13

5

12

4

11

3

10

2

9

1

Bit 8

Bit 0

Read:

Bit 7

Timer B Modulo Register Low

(TBMODL)

Write:

Read: CH0F

Timer B CH0 Status and Control

Register (TBSC0)

CH0IE

14

MS0B

13

MS0A

12

ELS0B ELS0A TOV0 CH0MAX

Write:

Read:

Write:

Read:

Write:

0

Timer B CH0 Register High

(TBCH0H)

Bit 15

11

3

10

2

9

1

Bit 8

Bit 0

Timer B CH0 Register Low

(TBCH0L)

Bit 7

6

5

0

4

Read: CH1F

Timer B CH1 Status and Control

Register (TBSC1)

CH1IE

14

MS1A

12

ELS1B ELS1A TOV1 CH1MAX

$0048

$0049

Write:

Read:

Write:

Read:

Write:

0

Timer B CH1 Register High

(TBCH1H)

Bit 15

13

5

11

3

10

2

9

1

Bit 8

Bit 0

Timer B CH1 Register Low

(TBCH1L)

$004A

Bit 7

6

4

Figure 2. Control, Status, and Data Registers (Sheet 4 of 6)

8-mem

MC68HC908AZ60 — Rev 2.0

30

Memory Map

MOTOROLA

Memory Map

I/O Section

Addr.

Register Name

Bit 7

Read: POF

Write:

6

5

PSTOP

13

4

0

3

2

1

Bit 0

PPS0

Bit 8

0

PIT Status and Control Register

(PSC)

$004B

PIE

14

PPS2

10

PPS1

9

PRST

12

Read: Bit 15

Write:

11

3

PIT Counter Register High

(PCNTH)

$004C

Read: Bit 7

Write:

6

5

4

2

1

Bit 0

$004D PIT Counter Register Low (PCNTL)

Read:

Bit 15

Write:

PIT Modulo Register High

$004E

14

6

13

5

12

4

11

3

10

2

9

1

Bit 8

Bit 0

(PMODH)

Read:

Bit 7

$004F PIT Modulo Register Low (PMODL)

Write:

Read:

R

SIM Break Status Register

$FE00

R

0

BW

LVI

R

0

(SBSR)

Write:

Read: POR

Write:

COP

ILOP

ILAD

$FE01 SIM Reset Status Register (SRSR)

Read:

BCFE

Write:

SIM Break Flag Control Register

$FE03

R

0

R

0

R

MSCAND

BLK0

12

R

0

R

0

R

0

R

(SBFCR)

Read:

0

Conﬁguration Write-Once Register

$FE09

AZxx

PGM

Bit 8

(CONFIG-2)

Write:

Read:

FDIV1

Write:

Flash Control Register

$FE0B

FDIV0

14

BLK1

13

HVEN

11

VERF ERASE

(FLCR1)

Read:

Bit 15

Write:

Break Address Register High

$FE0C

(BRKH)

10

9

Read:

Bit 7

Break Address Register Low

$FE0D

(BRKL)

6

5

0

4

0

3

0

2

0

1

0

Bit 0

0

Write:

Read:

BRKE

Write:

Break Status and Control

$FE0E

BRKA

0

Register (BRKSCR)

Read: LVIOUT

Write:

0

$FE0F

$FE11

$FE18

$FE19

$FE1A

LVI Status Register (LVISR)

Read:

FDIV1

Write:

Flash Control Register

(FLCR2)

FDIV0

BLK1

BLK0

HVEN

VERF ERASE

PGM

Read:

EEPROM Nonvolatile Register

(EENVR2)

EERA CON2

CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0

0

Write:

Read:

Write:

Read:

Write:

0

EEPROM Control

Register (EECR2)

EEBCLK

EEOFF EERAS1 EERAS0 EELAT

EEPGM

Reserved

R

Figure 2. Control, Status, and Data Registers (Sheet 5 of 6)

9-mem

MC68HC908AZ60 — Rev 2.0

31

MOTOROLA

Memory Map

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read: EERA CON2

Write:

CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0

EEPROM Array Control Register

(EEACR2)

$FE1B

Read:

EEPROM Nonvolatile Register

(EENVR1)

$FE1C

$FE1D

$FE1E

$FE1F

$FF80

$FF81

EERA CON2

Write:

CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0

0

Read:

Write:

Read:

Write:

0

EEPROM Control

Register (EECR1)

EEBCLK

R

EEOFF EERAS1 EERAS0 EELAT

EEPGM

Reserved

R

Read: EERA CON2

CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0

EEPROM Array Control Register

(EEACR1)

Write:

Read:

Write:

Read:

Write:

BPR3

BPR2

BPR1

BPR0

FLASH Block Protect Register

(FLBPR1)

FLASH Block Protect Register

(FLBPR2)

Read:

Write:

LOW BYTE OF RESET VECTOR

$FFFF COP Control Register (COPCTL)

WRITING TO $FFFF CLEARS COP COUNTER

Figure 2. Control, Status, and Data Registers (Sheet 6 of 6)

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Memory Map

MOTOROLA

Memory Map

I/O Section

Table 1. Vector Addresses

Address

Vector

TIMA Channel 5 Vector (High)

TIMA Channel 5 Vector (Low)

TIMA Channel 4 Vector (High)

TIMA Channel 4 Vector (Low)

ADC Vector (High)

$FFCC

$FFCD

$FFCE

$FFCF

$FFD0

$FFD1

$FFD2

$FFD3

$FFD4

$FFD5

$FFD6

$FFD7

$FFD8

$FFD9

$FFDA

$FFDB

$FFDC

$FFDD

$FFDE

$FFDF

$FFE0

$FFE1

$FFE2

$FFE3

$FFE4

$FFE5

$FFE6

$FFE7

$FFE8

$FFE9

$FFEA

$FFEB

$FFEC

$FFED

$FFEE

$FFEF

ADC Vector (Low)

Keyboard Vector (High)

Keyboard Vector (Low)

SCI Transmit Vector (High)

SCI Transmit Vector (Low)

SCI Receive Vector (High)

SCI Receive Vector (Low)

SCI Error Vector (High)

SCI Error Vector (Low)

CAN Transmit Vector (High)

CAN Transmit Vector (Low)

CAN Receive Vector (High)

CAN Receive Vector (Low)

CAN Error Vector (High)

CAN Error Vector (Low)

CAN Wakeup Vector (High)

CAN Wakeup Vector (Low)

SPI Transmit Vector (High)

SPI Transmit Vector (Low)

SPI Receive Vector (High)

SPI Receive Vector (Low)

TIMB Overﬂow Vector (High)

TIMB Overﬂow Vector (Low)

TIMB CH1 Vector (High)

TIMB CH1 Vector (Low)

TIMB CH0 Vector (High)

TIMB CH0 Vector (Low)

TIMA Overﬂow Vector (High)

TIMA Overﬂow Vector (Low)

TIMA CH3 Vector (High)

TIMA CH3 Vector (Low)

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MOTOROLA

Memory Map

Table 1. Vector Addresses (Continued)

Address

$FFF0

$FFF1

$FFF2

$FFF3

$FFF4

$FFF5

$FFF6

$FFF7

$FFF8

$FFF9

$FFFA

$FFFB

$FFFC

$FFFD

$FFFE

Vector

TIMA CH2 Vector (High)

TIMA CH2 Vector (Low)

TIMA CH1 Vector (High)

TIMA CH1 Vector (Low)

TIMA CH0 Vector (High)

TIMA CH0 Vector (Low)

PIT Vector (High)

PIT Vector (Low)

PLL Vector (High)

PLL Vector (Low)

IRQ1 Vector (High)

IRQ1 Vector (Low)

SWI Vector (High)

SWI Vector (Low)

Reset Vector (High)

$FFFF

Reset Vector (Low)

It is recommended that all vector addresses are deﬁned.

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Memory Map

MOTOROLA

RAM

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Introduction

This section describes the 2048 bytes of random-access memory

(RAM).

Functional Description

Addresses $0050 through $044F and $0A00 through $0DFF are RAM

locations. The location of the stack RAM is programmable with the reset

stack pointer instruction (RSP). The 16-bit stack pointer allows the stack

RAM to be anywhere in the 64K-byte memory space.

NOTE: For correct operation, the stack pointer must point only to RAM

locations.

Within page zero are 176 bytes of RAM. Because the location of the

stack RAM is programmable, all page zero RAM locations can be used

for input/output (I/O) control and user data or code. When the stack

pointer is moved from its reset location at $00FF, direct addressing

mode instructions can access all page zero RAM locations efficiently.

Page zero RAM, therefore, provides ideal locations for frequently

accessed global variables.

Before processing an interrupt, the CPU uses five bytes of the stack to

save the contents of the CPU registers.

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RAM

35

RAM

NOTE: For M68HC05, M6805, and M146805 compatibility, the H register is not

stacked.

During a subroutine call, the CPU uses two bytes of the stack to store

the return address. The stack pointer decrements during pushes and

increments during pulls.

NOTE: Be careful when using nested subroutines. The CPU could overwrite

data in the RAM during a subroutine or during the interrupt stacking

operation.

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RAM

MOTOROLA

FLASH-1 Memory

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Future FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

FLASH-1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

FLASH Charge Pump Frequency Control. . . . . . . . . . . . . . . . . . . . . . 41

FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . . . . . . . 43

Smart Programming Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

FLASH-1 Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

FLASH-2 Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

WAIT Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Introduction

This section describes the operation of the embedded FLASH-1

memory. This memory can be read, programmed, and erased from a

single external supply. The program and erase operations are enabled

through the use of an internal charge pump.

Future FLASH Memory

Design is underway to introduce an improved Flash memory module.

The new module will offer improved write erase cycling and faster

programming times. However Flash program and erase algorithms will

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37

FLASH-1 Memory

change, as will the block protection. The new silicon can be identified by

an ‘A’ suffix, i.e. 68HC908AZ60A, and by mask set.

NOTE: In order that current software is compatible and also to prevent problems

if code should runaway, Flash program and erase algorithms should not

be embedded in software.

Functional Description

The FLASH memory physically consists of two independent arrays of 32K

bytes with an additional 52 bytes of user vectors and two bytes of block

protection. An erased bit reads as a logic 0 and a programmed bit reads

as a logic 1. Program and erase operations are facilitated through control

bits in a memory mapped register. Details for these operations appear

later in this section. Memory in the FLASH array is organized into pages

within rows. There are 8 pages of memory per row with 8 bytes per page.

The minimum erase block size is a single row, 64 bytes. Programming is

performed on a per page basis; eight bytes at a time. The address ranges

for the user memory, control register and vectors are:

• $8000–$FDFF

• $FF80–FF81 (Block Protect Registers)

• $FE0B FLASH Control Register

• $FFCC–$FFFF (These locations are reserved for user-defined

interrupt and reset vectors.)

When programming the FLASH, just enough program time must be used

to program a page. Too much program time can result in a program

disturb condition; in which case an erased bit on the row being

programmed becomes unintentionally programmed. Program disturb is

avoided by using an iterative program and margin read technique known

as the smart programming algorithm. The smart programming algorithm

is required whenever programming the FLASH (See FLASH

Program/Margin Read Operation on page 43). As well, to avoid the

program disturb issue, each storage page of the row should not be

programmed more than once before it is erased. The 8 program cycle

maximum per row aligns with the architecture’s 8 pages of storage per

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MOTOROLA

FLASH-1 Memory

FLASH-1 Control Register

row. The margin read step of the smart programming algorithm is used

to insure programmed bits are programmed to sufficient margin for data

retention over the device lifetime. The following is the row architecture

for this array:

• $8000–$803F (Row0)

• $8040–$807F (Row1)

• $8080–$80BF (Row2)

• ----------------------------

• $FFC0–$FFFF(Row 511)

Programming tools are available from Motorola. Contact your local

Motorola representative for more information.

1

NOTE: A security feature prevents viewing of the FLASH contents.

FLASH-1 Control Register

The FLASH-1 control register controls FLASH-1 program, erase, and

margin read operations.

Address: $FE0B

Bit 7

FDIV1

0

6

FDIV0

0

5

BLK1

0

4

BLK0

0

3

2

1

Bit 0

PGM

0

Read:

Write:

Reset:

HVEN MARGIN ERASE

0

Figure 1. FLASH-1 Control Register (FLCR1)

FDIV1 — Frequency Divide Control Bit

This read/write bit together with FDIV0 selects the factor by which the

charge pump clock is divided from the system clock. See FLASH

Charge Pump Frequency Control on page 41.

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or

copying the FLASH difficult for unauthorized users.

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FLASH-1 Memory

FDIV0 — Frequency Divide Control Bit

This read/write bit together with FDIV1 selects the factor by which the

charge pump clock is divided from the system clock. See FLASH

Charge Pump Frequency Control on page 41.

BLK1— Block Erase Control Bit

This read/write bit together with BLK0 allows erasing of blocks of

varying size. See FLASH Erase Operation on page 41 for a

description of available block sizes.

BLK0 — Block Erase Control Bit

This read/write bit together with BLK1 allows erasing of blocks of

varying size. See FLASH Erase Operation on page 41 for a

description of available block sizes.

HVEN — High-Voltage Enable Bit

This read/write bit enables the charge pump to drive high voltages for

program and erase operations in the array. HVEN can only be set if

either PGM = 1 or ERASE = 1 and the proper sequence for

program/margin read or erase is followed.

1 = High voltage enabled to array and charge pump on

0 = High voltage disabled to array and charge pump off

MARGIN — Margin Read Control Bit

This read/write bit configures the memory for margin read operation.

MARGIN cannot be set if the HVEN = 1. MARGIN will automatically

return to unset (0) if asserted when HVEN = 1.

1 = Margin read operation selected

0 = Margin read operation unselected

ERASE — Erase Control Bit

This read/write bit configures the memory for erase operation.

ERASE is interlocked with the PGM bit such that both bits cannot be

set at the same time.

1 = Erase operation selected

0 = Erase operation unselected

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FLASH-1 Memory

FLASH Charge Pump Frequency Control

PGM — Program Control Bit

This read/write bit configures the memory for program operation.

PGM is interlocked with the ERASE bit such that both bits cannot be

set at the same time.

1 = Program operation selected

0 = Program operation unselected

FLASH Charge Pump Frequency Control

The internal charge pump, required for program, margin read, and erase

operations, is designed to operate most efficiently with a 2MHz clock.

The charge pump clock is derived from the bus clock. Table 1 shows

how the FDIV bits are used to select a charge pump frequency based on

the bus clock frequency. Program, margin read and erase operations

cannot be performed if the bus clock frequency is below 2 MHz.

Table 1. Charge Pump Clock Frequency

FDIV1

FDIV0

Pump Clock Frequency

Bus Frequency ÷ 1

Bus Frequency ÷ 2

Bus Frequency ÷ 4

Bus Clock Frequency

2 MHz ± 10%

0

1

0

1

0

1

4 MHz ± 10%

8 MHz ± 10%

NOTE: FDIV0 and FDIV1 must be set to the same value in both flash arrays.

FLASH Erase Operation

Memory Characteristics on page 445 has a detailed description of the

times used in this algorithm. Use the following procedure to erase a

block of FLASH memory:

1. Set the ERASE bit, the BLK0, BLK1, FDIV0, and FDIV1 bits in the

FLASH-1 control register. See Table 2 for block sizes. See Table

1 for FDIV settings.

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FLASH-1 Memory

2. Insure target portion of array is unprotected, read the block protect

register: address $FF80. See FLASH Block Protection on page 46

and FLASH-1 Block Protect Register on page 47 for more

information.

3. Write to any FLASH address with any data within the block

address range desired.

4. Set the HVEN bit.

5. Wait for a time, t

.

ERASE

6. Clear the HVEN bit.

7. Wait for a time, t

, for the high voltages to dissipate.

KILL

8. Clear the ERASE bit.

9. After time t , the memory can be accessed in read mode again.

HVD

NOTE: While these operations must be performed in the order shown, other

unrelated operations may occur between the steps.

Table 2 shows the various block sizes which can be erased in one erase

operation.

Table 2. Erase Block Sizes

BLK1

BLK0

Block Size, Addresses Cared

Full Array: 24 Kbytes

0

1

0

1

0

1

One-Half Array: 16 Kbytes (A14 )

Eight Rows: 512 Bytes (A14–A9)

Single Row: 64 Bytes (A14–A6)

In step 2 of the erase operation, the cared addresses are latched and

used to determine the location of the block to be erased. For instance,

with BLK0 = BLK1 = 0, writing to any Flash address in the range $8000

to $FFFF will enable the full-array erase.

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MOTOROLA

FLASH-1 Memory

FLASH Program/Margin Read Operation

NOTE: After a total of 8 program operations have been applied to a row, the row

must be erased before further programming in order to avoid program

disturb. An erased byte will read $00.

Programming of the FLASH memory is done on a page basis. A page

consists of eight consecutive bytes starting from address $XXX0 or

$XXX8. The purpose of the margin read mode is to ensure that data has

been programmed with sufficient margin for long-term data retention.

While performing a margin read the operation is the same as for ordinary

read mode except that a built-in counter stretches the data access for an

additional eight cycles to allow sensing of the lower cell current. Margin

read mode imposes a more stringent read condition on the bitcell to

insure the bitcell is programmed with enough margin for long-term data

retention. During these eight cycles the COP counter continues to run.

The user must account for these extra cycles within COP feed loops. A

margin read cycle can only follow a page programming operation. To

program and margin read the FLASH memory, use the following

algorithm. Memory Characteristics on page 445, has a detailed

description of the times used in this algorithm.

1. Set the PGM bit. This configures the memory for program

operation and enables the latching of address and data for

programming.

2. Read from the block protect register.

3. Write data to the eight bytes of the page being programmed. This

requires eight separate write operations.

4. Set the HVEN bit.

5. Wait for time, t

.

PROG

6. Clear the HVEN bit.

7. Wait for time, t

.

HVTV

8. Set the MARGIN bit.

9. Wait for time, t

.

VTP

10. Clear the PGM bit.

11. Wait for time, t

.

HVD

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FLASH-1 Memory

12. Read back data in margin read mode. This is done in eight

separate read operations which are each stretched by eight

cycles.

13. Clear the MARGIN bit.

NOTE: While these operations must be performed in the order shown, other

unrelated operations may occur between the steps. It is highly

recommended that the interrupt mask is set during programming. Under

very controlled situations it may be possible to omit this step, but it

remains the user’s responsibility to ensure that any interrupts do not

interfere with the Flash being programmed properly.

This program/margin read sequence is repeated throughout the memory

until all data is programmed. The Smart Programming Algorithm is

always required when programming any part of the array. This algorithm

insures the minimum possible program time and avoids the deleterious

program disturb effect. (See FLASH Erase Operation on page 41).

NOTE: In order to ensure proper FLASH read operation after completion of the

smart programming algorithm, a series of 500 dummy FLASH reads

must be performed of any address before accurate data is read from the

FLASH.

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MOTOROLA

FLASH-1 Memory

FLASH Program/Margin Read Operation

Smart

Programming

Algorithm

Program FLASH 2TS

Page Program/Margin Read Procedure

Note:This algorithm is mandatory for

programming the FLASH 2TS.

Set Interrupt Mask: SEI Instruction

(see note above)

Note: This page program algorithm

assumes the page/s to be programmed

are initially erased.

Initialize Attempt Counter

to Zero

Set PGM Bit and FDIV bits

Read Flash Block Protect Register

Write Data to

Selected Page

Set HVEN Bit

Wait t

STEP

Clear HVEN Bit

Wait t

HVTV

Set MARGIN Bit

Wait t

VTP

Clear PGM Bit

Wait t

HVD

Margin Read Page of Data

N

Clear MARGIN Bit

Margin Read Data

Equal To

Write Data?

Increment Attempt Counter

Y

Clear MARGIN Bit

N

Attempt Count

Equal To

Clear Interrupt Mask: CLI Instr.

(see note above)

fls_PULSES

?

Y

Programming Operation

Complete

Programming Operation

Failed

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MOTOROLA

FLASH-1 Memory

FLASH Block Protection

NOTE: In performing a program or erase operation the FLASH Block Protect

Register must be read after setting the PGM or ERASE bit and before

asserting the HVEN bit.

Due to the ability of the on-board charge pump to erase and program the

FLASH memory in the target application, provision is made for protecting

blocks of memory from unintentional erase or program operations due to

system malfunction. This protection is done by reserving a location in the

memory for block protect information and requiring that this location be

read from to enable setting of the HVEN bit. When the block protect

register is read, its contents are latched by the FLASH control logic. If

the address range for an erase or program operation includes a

protected block, the PGM or ERASE bit is cleared which prevents the

HVEN bit in the FLASH control register from being set so that no high

voltage is allowed in the array.

When the block protect register is erased (all 0s), the entire memory is

accessible for program and erase. When bits within the register are

programmed, they lock blocks of memory address ranges as shown in

FLASH-1 Block Protect Register on page 47. The block protect register

itself can be erased or programmed only with an external voltage V

HI

present on the IRQ pin. The presence of V on the IRQ pin also allows

HI

entry in to monitor mode out of reset. Therefore, the ability to change the

block protect register is voltage dependent and can occur in either user

or monitor modes.

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FLASH-1 Memory

MOTOROLA

FLASH-1 Memory

FLASH-1 Block Protect Register

The block protect register is implemented as a byte within the FLASH-1

memory. Each bit, when programmed, protects a range of addresses in

the FLASH-1 array.

Address: $FF80

Bit 7

0

6

0

5

0

4

0

3

BPR3

0

2

BPR2

0

1

BPR1

0

Bit 0

BPR0

0

Read:

Write:

Reset:

0

= Unimplemented

Figure 2. FLASH-1 Block Protect Register (FLBPR1)

BPR3 — Block Protect Register Bit 3

This bit protects the memory contents in the address range $C000 to

$FFFF.

1 = Address range protected from erase or program

0 = Address range open to erase or program

BPR2 — Block Protect Register Bit 2

This bit protects the memory contents in the address range $A000 to

$FFFF.

1 = Address range protected from erase or program

0 = Address range open to erase or program

BPR1 — Block Protect Register Bit 1

This bit protects the memory contents in the address range $9000 to

$FFFF.

1 = Address range protected from erase or program

0 = Address range open to erase or program

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47

FLASH-1 Memory

BPR0 — Block Protect Register Bit 0

This bit protects the memory contents in the address range $8000 to

$FFFF.

1 = Address range protected from erase or program

0 = Address range open to erase or program

By programming the block protect bits, a portion of the memory will be

locked so that no further erase or program operations may be

performed. Programming more than one bit at a time is redundant. If

both bit 1 and bit 2 are set, for instance, the address range $9000

through $FFFF is locked. If all bits are erased, then all of the memory is

available for erase and program. The presence of a voltage V on the

HI

IRQ pin will bypass the block protection so that all of the memory,

including the block protect register, is open for program and erase

operations.

FLASH-2 Block Protect Register

NOTE: This block protect register controls the FLASH-2 array block protection.

However, since it is physically located in FLASH-1 array, the FLASH-1

control register must be used to program/erase this register.

The block protect register is implemented as a byte within the FLASH-1

memory. Each bit, when programmed, protects a range of addresses in

the FLASH-2 array.

Address: $FF81

Bit 7

0

6

0

5

0

4

0

3

BPR3

0

2

BPR2

0

1

BPR1

0

Bit 0

BPR0

0

Read:

Write:

Reset:

0

= Unimplemented

Figure 3. FLASH-2 Block Protect Register (FLBPR2)

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FLASH-1 Memory

MOTOROLA

FLASH-1 Memory

FLASH-2 Block Protect Register

BPR3 — Block Protect Register Bit 3

This bit protects the memory contents in the address range $4000 to

$7FFF.

1 = Address range protected from erase or program

0 = Address range open to erase or program

BPR2 — Block Protect Register Bit 2

This bit protects the memory contents in the address range $2000 to

$7FFF.

1 = Address range protected from erase or program

0 = Address range open to erase or program

BPR1 — Block Protect Register Bit 1

This bit protects the memory contents in the address range $1000 to

$7FFF.

1 = Address range protected from erase or program

0 = Address range open to erase or program

BPR0 — Block Protect Register Bit 0

This bit protects the memory contents in the address range $0450 to

$7FFF.

1 = Address range protected from erase or program

0 = Address range open to erase or program

By programming the block protect bits, a portion of the memory will be

locked so that no further erase or program operations may be

performed. Programming more than one bit at a time is redundant. If

both bit 1 and bit 2 are set, for instance, the address range $1000

through $FFFF is locked. If all bits are erased, then all of the memory is

available for erase and program. The presence of a voltage V on the

HI

IRQ pin will bypass the block protection so that all of the memory,

including the block protect register, is open for program and erase

operations.

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49

FLASH-1 Memory

Low-Power Modes

The WAIT and STOP instructions put the MCU in low power

consumption standby modes.

WAIT Mode

Putting the MCU into wait mode while the FLASH is in read mode does

not affect the operation of the FLASH memory directly, but there will not

be any memory activity since the CPU is inactive.

The WAIT instruction should not be executed while performing a

program or erase operation on the FLASH. When the MCU is put into

wait mode, the charge pump for the FLASH is disabled so that either a

program or erase operation will not continue. If the memory is in either

program mode (PGM = 1, HVEN = 1) or erase mode (ERASE = 1, HVEN

= 1), then it will remain in that mode during wait. Exit from wait must now

be done with a reset rather than an interrupt because if exiting wait with

an interrupt, the memory will not be in read mode and the interrupt vector

cannot be read from the memory.

STOP Mode

When the MCU is put into stop mode, if the FLASH is in read mode, it

will be put into low power standby.

The STOP instruction should not be executed while performing a

program or erase operation on the FLASH. When the MCU is put into

stop mode, the charge pump for the FLASH is disabled so that either a

program or erase operation will not continue. If the memory is in either

program mode (PGM = 1, HVEN = 1) or erase mode (ERASE = 1, HVEN

= 1), then it will remain in that mode during stop. Exit from stop must now

be done with a reset rather than an interrupt because if exiting stop with

an interrupt, the memory will not be in read mode and the interrupt vector

cannot be read from the memory.

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MOTOROLA

FLASH-2 Memory

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Future FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

FLASH Charge Pump Frequency Control. . . . . . . . . . . . . . . . . . . . . . 55

FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . . . . . . . 57

Smart Programming Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

WAIT Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Introduction

This section describes the operation of the embedded FLASH-2

memory. This memory can be read, programmed, and erased from a

single external supply. The program and erase operations are enabled

through the use of an internal charge pump.

Future FLASH Memory

Design is underway to introduce an improved Flash memory module.

The new module will offer improved write erase cycling and faster

programming times. However Flash program and erase algorithms will

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FLASH-2 Memory

change, as will the block protection. The new silicon can be identified by

mask set.

NOTE: In order that current software is compatible and also to prevent problems

if code should runaway, Flash program and erase algorithms should not

be embedded in software.

Functional Description

The FLASH-2 memory is an array of up to 29,488 bytes. An erased bit

reads as a logic 0 and a programmed bit reads as a logic 1. Program and

erase operations are facilitated through control bits in a memory mapped

register. Details for these operations appear later in this section. Memory

in the FLASH array is organized into pages within rows. There are 8

pages of memory per row with 8 bytes per page. The minimum erase

block size is a single row, 64 bytes. Programming is performed on a per

page basis; eight bytes at a time. The address ranges for the user

memory and the control register are:

• $0450–$04FF

• $0580–$05FF

• $0E00–$7FFF

• $FE11 FLASH-2 Control Register

When programming the FLASH, just enough program time must be used

to program a page. Too much program time can result in a program

disturb condition; in which case an erased bit on the row being

programmed becomes unintentionally programmed. Program disturb is

avoided by using an iterative program and margin read technique known

as the smart programming algorithm. The smart programming algorithm

is required whenever programming the FLASH (See FLASH

Program/Margin Read Operation on page 57). As well, to avoid the

program disturb issue each storage page of the row should not be

programmed more than once before it is erased. The 8 program cycle

maximum per row aligns with the architecture’s 8 pages of storage per

row. The margin read step of the smart programming algorithm is used

to insure programmed bits are programmed to sufficient margin for data

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FLASH-2 Memory

FLASH Control Register

retention over the device lifetime. The following is the row architecture

for this array:

• $7F40–$7F7F (Row 509)

• $7F80–$7FBF (Row 510)

• $7FC0–$7FFF (Row 511)

Programming tools are available from Motorola. Contact your local

Motorola representative for more information.

1

NOTE: A security feature prevents viewing of the FLASH contents.

FLASH Control Register

The FLASH-2 control register controls FLASH-2 program, erase, and

margin read operations.

Address: $FE11

Bit 7

FDIV1

0

6

FDIV0

0

5

BLK1

0

4

BLK0

0

3

2

1

Bit 0

PGM

0

Read:

Write:

Reset:

HVEN MARGIN ERASE

0

Figure 1. FLASH-2 Control Register (FLCR2)

FDIV1 — Frequency Divide Control Bit

This read/write bit together with FDIV0 selects the factor by which the

charge pump clock is divided from the system clock. See FLASH

Charge Pump Frequency Control on page 55.

FDIV0 — Frequency Divide Control Bit

This read/write bit together with FDIV1 selects the factor by which the

charge pump clock is divided from the system clock. See FLASH

Charge Pump Frequency Control on page 55.

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or

copying the FLASH difficult for unauthorized users.

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BLK1— Block Erase Control Bit

This read/write bit together with BLK0 allows erasing of blocks of

varying size. See FLASH Erase Operation on page 55 for a

description of available block sizes.

BLK0 — Block Erase Control Bit

This read/write bit together with BLK1 allows erasing of blocks of

varying size. See FLASH Erase Operation on page 55 for a

description of available block sizes.

HVEN — High-Voltage Enable Bit

This read/write bit enables the charge pump to drive high voltages for

program and erase operations in the array. HVEN can only be set if

either PGM = 1 or ERASE = 1 and the proper sequence for

program/margin read or erase is followed.

1 = High voltage enabled to array and charge pump on

0 = High voltage disabled to array and charge pump off

MARGIN — Margin Read Control Bit

This read/write bit configures the memory for margin read operation.

MARGIN cannot be set if the HVEN = 1. MARGIN will automatically

return to unset (0) if asserted when HVEN = 1.

1 = Margin read operation selected

0 = Margin read operation unselected

ERASE — Erase Control Bit

This read/write bit configures the memory for erase operation.

ERASE is interlocked with the PGM bit such that both bits cannot be

set at the same time.

1 = Erase operation selected

0 = Erase operation unselected

PGM — Program Control Bit

This read/write bit configures the memory for program operation.

PGM is interlocked with the ERASE bit such that both bits cannot be

set at the same time.

1 = Program operation selected

0 = Program operation unselected

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FLASH Charge Pump Frequency Control

The internal charge pump, required for program, margin read, and erase

operations, is designed to operate most efficiently with a 2MHz clock.

The charge pump clock is derived from the bus clock. Table 1 shows

how the FDIV bits are used to select a charge pump frequency based on

the bus clock frequency. Program, margin read and erase operations

cannot be performed if the bus clock frequency is below 2 MHz.

Table 1. Charge Pump Clock Frequency

FDIV1

FDIV0

Pump Clock Frequency

Bus Frequency ÷ 1

Bus Frequency ÷ 2

Bus Frequency ÷ 4

Bus Clock Frequency

2 MHz ± 10%

0

1

0

1

0

1

4 MHz ± 10%

8 MHz ± 10%

NOTE: FDIV0 and FDIV1 must be set to the same value in both flash arrays.

FLASH Erase Operation

Memory Characteristics on page 445 has a detailed description of the

times used in this algorithm. Use the following procedure to erase a

block of FLASH-2 memory:

1. Set the ERASE bit, the BLK0, BLK1, FDIV0, and FDIV1 bits in the

FLASH control register. See Table 2 for block sizes. See Table 1

for FDIV settings.

2. Insure target portion of array is unprotected, read the block protect

register: address $FF81. See Section FLASH Block Protection

on page 60 and Section FLASH Block Protect Register on page

60 for more information.

3. Write to any FLASH address with any data within the block

address range desired.

4. Set the HVEN bit.

5. Wait for a time, t

.

ERASE

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6. Clear the HVEN bit.

7. Wait for a time, t

, for the high voltages to dissipate.

KILL

8. Clear the ERASE bit.

9. After time t , the memory can be accessed in read mode again.

HVD

NOTE: While these operations must be performed in the order shown, other

unrelated operations may occur between the steps.

Table 2 shows the various block sizes which can be erased in one erase

operation.

Table 2. Erase Block Sizes

BLK1

BLK0

Block Size, Addresses Cared

Full Array: 24 Kbytes

0

1

0

1

0

1

One-Half Array: 16 Kbytes (A14 )

Eight Rows: 512 Bytes (A14–A9)

Single Row: 64 Bytes (A14–A6)

In step 2 of the erase operation, the cared addresses are latched and

used to determine the location of the block to be erased. For instance,

with BLK0 = BLK1 = 0, writing to any Flash address in the range

$0450-$05FF or $0E00-$7FFF will enable the full-array erase.

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