MC68HC908JK1MP [MOTOROLA]
8-BIT, FLASH, 8MHz, MICROCONTROLLER, PDIP20, PLASTIC, DIP-20;
| 型号： | MC68HC908JK1MP |
| 厂家： | 
MOTOROLA |
| 描述： | 8-BIT, FLASH, 8MHz, MICROCONTROLLER, PDIP20, PLASTIC, DIP-20 光电二极管 |
| 文件： | 总215页 (文件大小：2324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68HC08JL3/H
Rev. 4
MC68HC08JK1
MC68HRC08JK1
MC68HC08JK3
MC68HRC08JK3
MC68HC08JL3
MC68HRC08JL3
HCMOS Mic roc ontrolle r Unit
TECHNICAL DATA
Te c hnic a l Da ta — MC68H(R)C08JL3
List of Se c tions
Section 1. General Description . . . . . . . . . . . . . . . . . . . .21
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Section 3. Random-Access Memory (RAM) . . . . . . . . . .37
Section 4. Read-Only Memory (ROM) . . . . . . . . . . . . . . .39
Section 5. Configuration Register (CONFIG) . . . . . . . . .41
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . .45
Section 7. System Integration Module (SIM) . . . . . . . . .65
Section 8. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . .89
Section 9. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . .95
Section 10. Timer Interface Module (TIM) . . . . . . . . . . .105
Section 11. Analog-to-Digital Converter (ADC) . . . . . .127
Section 12. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Section 13. External Interrupt (IRQ) . . . . . . . . . . . . . . .149
Section 14. Keyboard Interrupt Module (KBI). . . . . . . .155
Section 15. Computer Operating Properly (COP) . . . .163
Section 16. Low Voltage Inhibit (LVI) . . . . . . . . . . . . . .169
Section 17. Break Module (BREAK) . . . . . . . . . . . . . . .173
Section 18. Electrical Specifications. . . . . . . . . . . . . . .181
Section 19. Mechanical Specifications . . . . . . . . . . . . .193
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
List of Sections
3
List of Se c tions
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
4
List of Sections
Te c hnic a l Da ta — MC68H(R)C08JL3
Ta b le of Conte nts
Section 1. General Description
1.1
1.2
1.3
1.4
1.5
1.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Section 2. Memory
2.1
2.2
2.3
2.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Section 3. Random-Access Memory (RAM)
3.1
3.2
3.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Section 4. Read-Only Memory (ROM)
4.1
4.2
4.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
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Section 5. Configuration Register (CONFIG)
5.1
5.2
5.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Section 6. Central Processor Unit (CPU)
6.1
6.2
6.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
6.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .49
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.6
6.6.1
6.6.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.7
6.8
6.9
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .53
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Section 7. System Integration Module (SIM)
7.1
7.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
7.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .69
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . .69
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . .69
7.3.1
7.3.2
7.3.3
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7.4
7.4.1
7.4.2
7.4.2.1
7.4.2.2
7.4.2.3
7.4.2.4
7.4.2.5
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .70
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . .71
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Computer Operating Properly (COP) Reset . . . . . . . . . .73
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .73
LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . .74
SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . .74
SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .75
7.5.1
7.5.2
7.5.3
7.6
7.6.1
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .79
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . .80
Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . . .80
Interrupt Status Register 3. . . . . . . . . . . . . . . . . . . . . . . .81
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . .81
7.6.1.1
7.6.1.2
7.6.2
7.6.2.1
7.6.2.2
7.6.2.3
7.6.3
7.6.4
7.6.5
7.7
7.7.1
7.7.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
7.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . .85
Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . .86
Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . .88
7.8.1
7.8.2
7.8.3
Section 8. Oscillator (OSC)
8.1
8.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
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8.3
8.4
X-tal Oscillator (MC68HC08xxx). . . . . . . . . . . . . . . . . . . . . . . .90
RC Oscillator (MC68HRC08xxx) . . . . . . . . . . . . . . . . . . . . . . .91
8.5
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . .92
Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK). . . . . . .92
Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . .92
X-tal Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . .92
RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . .93
Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . .93
Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.6
8.6.1
8.6.2
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.7
Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . .94
Section 9. Monitor ROM (MON)
9.1
9.2
9.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
9.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
Section 10. Timer Interface Module (TIM)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
10.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
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10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
10.5.3.1
10.5.3.2
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .110
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .110
10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .111
10.5.4.1
10.5.4.2
10.5.4.3
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .112
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .113
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
10.7 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
10.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
10.10.1 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . .117
10.10.2 TIM Counter Registers (TCNTH:TCNTL). . . . . . . . . . . . . .119
10.10.3 TIM Counter Modulo Registers (TMODH:TMODL) . . . . . .120
10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1).121
10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . .125
Section 11. Analog-to-Digital Converter (ADC)
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
11.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
11.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
11.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
11.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .130
11.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
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11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.7.1 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . .132
11.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
11.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .132
11.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
11.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . .135
Section 12. I/O Ports
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
12.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . .139
12.3.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . .140
12.3.3 Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . .141
12.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
12.4.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . .143
12.4.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . .143
12.5 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
12.5.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . .145
12.5.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . .146
12.5.3 Port D Control Register (PDCR). . . . . . . . . . . . . . . . . . . . .147
Section 13. External Interrupt (IRQ)
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
13.4.1 IRQ1 Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
13.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .153
13.6 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .153
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Section 14. Keyboard Interrupt Module (KBI)
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
14.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
14.4.2 Keyboard Status and Control Register. . . . . . . . . . . . . . . .159
14.4.3 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . .160
14.5 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
14.6 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
14.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .161
Section 15. Computer Operating Properly (COP)
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
15.4.1 2OSCOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
15.4.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
15.4.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
15.4.4 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
15.4.5 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
15.4.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
15.4.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . .166
15.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
15.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
15.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
15.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
15.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
15.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
15.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .168
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Section 16. Low Voltage Inhibit (LVI)
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
16.5 LVI Control Register (CONFIG2/CONFIG1). . . . . . . . . . . . . .170
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
Section 17. Break Module (BREAK)
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
17.4.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . .176
17.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .176
17.4.3 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . .176
17.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .176
17.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
17.5.1 Break Status and Control Register (BRKSCR) . . . . . . . . .177
17.5.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .178
17.5.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
17.5.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . .180
17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
Section 18. Electrical Specifications
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
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18.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .182
18.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .183
18.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
18.6 5V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .184
18.7 5V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
18.8 5V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .186
18.9 3V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .187
18.10 3V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
18.11 3V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .189
18.12 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
18.13 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
Section 19. Mechanical Specifications
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
19.3 20-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
19.4 20-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
19.5 28-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
19.6 28-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
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List of Fig ure s
Figure
Title
Page
1-1
1-2
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
MCU Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2-1
2-2
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .30
5-1
5-2
Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .42
Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .43
6-1
6-2
6-3
6-4
6-5
6-6
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .50
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .68
SIM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Interrupt Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
7-10 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
7-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . .78
7-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . .80
7-13 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . .80
7-14 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . . .81
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List of Fig ure s
Figure
Title
Page
7-15 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7-16 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . .83
7-17 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . .83
7-18 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
7-19 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . . .85
7-20 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . .85
7-21 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . .87
7-22 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . .88
8-1
8-2
X-tal Oscillator External Connections . . . . . . . . . . . . . . . . . . . .90
RC Oscillator External Connections . . . . . . . . . . . . . . . . . . . . .91
9-1
9-2
9-3
9-4
9-5
Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .100
Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
10-1 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
10-2 TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .108
10-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .112
10-4 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . .117
10-5 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . .120
10-6 TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . .121
10-7 TIM Channel Status and Control Registers (TSC0:TSC1) . . .122
10-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
10-9 TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . .126
11-1 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .128
11-2 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
11-3 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . .132
11-4 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . .135
11-5 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . .135
12-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .138
12-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .139
12-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .140
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List of Figures
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List of Figures
Figure
Title
Page
12-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
12-5 Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . . . .142
12-6 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .143
12-7 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .143
12-8 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
12-9 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .145
12-10 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . .146
12-11 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
12-12 Port D Control Register (PDCR). . . . . . . . . . . . . . . . . . . . . . .147
13-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .151
13-2 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .151
13-3 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . .153
13-4 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .154
14-1 KBI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .156
14-2 Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . .156
14-3 Keyboard Status and Control Register (KBSCR) . . . . . . . . . .159
14-4 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . .160
15-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
15-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .166
15-3 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .167
16-1 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .170
16-2 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .170
16-3 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .171
17-1 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .175
17-2 Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .175
17-3 Break Status and Control Register (BRKSCR). . . . . . . . . . . .177
17-4 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . .178
17-5 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . .178
17-6 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . .178
17-7 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . .180
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List of Figures
17
List of Fig ure s
Figure
Title
Page
18-1 RC vs. Frequency (5V @25°C) . . . . . . . . . . . . . . . . . . . . . . .186
18-2 RC vs. Frequency (3V @25°C) . . . . . . . . . . . . . . . . . . . . . . .189
18-3 Typical Operating I , with all Modules Turned On (25 °C) . .190
DD
18-4 Typical Wait Mode I , with ADC Turned On (25 °C) . . . . . .190
DD
18-5 Typical Stop Mode I , with all Modules Disabled (25 °C). . .190
DD
19-1 20-Pin PDIP (Case #738) . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
19-2 20-Pin SOIC (Case #751D) . . . . . . . . . . . . . . . . . . . . . . . . . .194
19-3 28-Pin PDIP (Case #710) . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
19-4 28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . .195
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List of Figures
MOTOROLA
Te c hnic a l Da ta — MC68H(R)C08JL3
List of Ta b le s
Table
Title
Page
1-1
1-2
Summary of Device Variations . . . . . . . . . . . . . . . . . . . . . . . . .21
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2-1
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
6-1
6-2
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
7-1
7-2
7-3
7-4
Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
Monitor Mode Entry Requirements and Options. . . . . . . . . . . .98
Monitor Mode Vector Differences . . . . . . . . . . . . . . . . . . . . . . .99
Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .100
READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .102
WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .102
IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .103
IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .103
READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .104
RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . .104
10-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
10-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
10-3 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .124
11-1 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
11-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
List of Tables
19
List of Ta b le s
Table
Title
Page
12-1 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
12-2 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
12-3 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
18-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .182
18-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
18-3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
18-4 DC Electrical Characteristics (5V) . . . . . . . . . . . . . . . . . . . . .184
18-5 Control Timing (5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
18-6 Oscillator Component Specifications (5V) . . . . . . . . . . . . . . .186
18-7 DC Electrical Characteristics (3V) . . . . . . . . . . . . . . . . . . . . .187
18-8 Control Timing (3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
18-9 Oscillator Component Specifications (3V) . . . . . . . . . . . . . . .189
18-10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
Technical Data
MC68H(R)C08JL3 — Rev. 4
20
List of Tables
MOTOROLA
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 1. Ge ne ra l De sc rip tion
1.1 Conte nts
1.2
1.3
1.4
1.5
1.6
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.2 Introd uc tion
The MC68H(R)C08JL3 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
Table 1-1. Summary of Device Variations
Device
ROM Size
4096 bytes
4096 bytes
1536 bytes
Pin Count
28 pins
MC68H(R)C08JL3
MC68H(R)C08JK3
MC68H(R)C08JK1
20 pins
20 pins
All references to the MC68H(R)C08JL3 in this data book apply equally
to the MC68H(R)C08JK3 and MC68H(R)C08JK1, unless otherwise
stated.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
General Description
21
Ge ne ra l De sc rip tion
1.3 Fe a ture s
Features of the MC68H(R)C08JL3 include the following:
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families
• Low-power design; fully static with stop and wait modes
• 5V and 3V operating voltages
• 8MHz internal bus operation
• RC-oscillator circuit or crystal-oscillator options
1
• ROM security
• User read-only memory (ROM)
– 4096 bytes for MC68H(R)C08JL3/JK3
– 1536 bytes for MC68H(R)C08JK1
• 128 bytes of on-chip random-access memory (RAM)
• 2-channel, 16-bit timer interface module (TIM)
• 12-channel, 8-bit analog-to-digital converter (ADC)
• 23 general purpose I/O ports for MC68H(R)C08JL3:
– 7 keyboard interrupt with internal pull-up
– 10 LED drivers
– 2 × 25mA open-drain I/O with pull-up
– 2 ICAP/OCAP/PWM
• 15 general purpose I/O ports for MC68H(R)C08JK3/JK1:
– 1 keyboard interrupt with internal pull-up
(with RC oscillator option selected)
– 4 LED drivers
– 2 × 25mA open-drain I/O with pull-up
– 2 ICAP/OCAP/PWM
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the ROM difficult for unauthorized users.
Technical Data
MC68H(R)C08JL3 — Rev. 4
22
General Description
MOTOROLA
General Description
MCU Block Diagram
• System protection features:
– Optional computer operating properly (COP) reset
– Optional low-voltage detection with reset and selectable trip
points for 3V and 5V operation.
– Illegal opcode detection with reset
– Illegal address detection with reset
• Master reset pin with internal pull-up and power-on reset
• IRQ1 with programmable pull-up and schmitt-trigger input
• 28-pin PDIP and 28-pin SOIC packages for MC68H(R)C08JL3
• 20-pin PDIP and 20-pin SOIC packages for
MC68H(R)C08JK3/JK1
Features of the CPU08 include the following:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
1.4 MCU Bloc k Dia g ra m
Figure 1-1 shows the structure of the MC68H(R)C08JL3.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
General Description
23
PTD[0:7]
PTB[0:7]
VDD
VSS
POWER SUPPLY
AND
VOLTAGE REGULATOR
PTD
PTB
DDRD
DDRB
OSC2/RCCLK/PTA6
OSC1
X-TAL OSCILLATOR
OR
RC-OSCILLATOR
CPU CONTROL
ALU
68HC08 CPU
SYSTEM INTEGRATION
MODULE
ACCUM
RST
CPU REGISTERS
INDEX REG
MODE SELECT
MODULE
IRQ1
STK PNTR
ADC[0:7]/
PTB[0:7]
BREAK
MODULE
PROGRAM COUNTER
COND CODE REG 1 1 H I N Z C
ADC[11:8]/
PTD[0:3]
POWER-ON RESET
MODULE
V
TCH0/PTD4
TCH1/PTD5
16-BIT
TIMER MODULE
MC68H(R)C08JL3/JK3: 4096 BYTES
MC68H(R)C08JK1: 1536 BYTES
USER ROM
128 BYTES RAM
COP
MODULE
MONITOR ROM
960 BYTES
RST, IRQ1: PIN HAS INTERNAL 30K PULL-UP
PTD[6:7]: PINS HAVE 25mA OPEN-DRAIN OUTPUT & PROGRAMMABLE 5K PULL-UP
PTA[0:5], PTD[2:3], PTD[6:7]: PIN HAS LED DRIVE
PTA[0:6]: PINS HAVE PROGRAMMABLE KEYBOARD INTERRUPT AND PULL-UP
PTA[0:5] and PTD[0:1]: NOT AVAILABLE ON 20-PIN DEVICES – MC68H(R)C08JK3/JK1
Figure 1-1. MCU Block Diagram
General Description
Pin Assignments
1.5 Pin Assig nm e nts
The MC68H(R)C08JL3 is available in 28-pin packages and the
MC68H(R)C08JK3/JK1 in 20-pin packages. Figure 1-2 shows the pin
assignment for the two packages.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
IRQ1
PTA0
RST
2
PTA5
PTD4
PTD5
PTD2
PTA4
PTD3
PTB0
PTB1
PTD1
PTB2
PTB3
PTD0
PTB4
3
VSS
4
OSC1
OSC2/PTA6
PTA1
5
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
IRQ1
VSS
RST
6
PTD4
PTD5
PTD2
PTD3
PTB0
PTB1
PTB2
PTB3
PTB4
7
VDD
OSC1
8
PTA2
OSC2/PTA6
VDD
9
PTA3
10
11
12
13
14
PTB7
PTB7
PTB6
PTB6
PTB5
PTB5
PTD7
PTD7
PTD6
PTD6
28-PIN ASSIGNMENT
MC68H(R)C08JL3
20-PIN ASSIGNMENT
MC68H(R)C08JK3/JK1
Pins not bonded out on 20-pin package:
PTA0, PTA1, PTA2, PTA3, PTA4, PTA5,
PTD0, PTD1.
Figure 1-2. MCU Pin Assignments
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
General Description
25
Ge ne ra l De sc rip tion
1.6 Pin Func tions
Description of the pin functions are provided in Table 1-2.
Table 1-2. Pin Functions
PIN NAME
VDD
PIN DESCRIPTION
IN/OUT
In
VOLTAGE LEVEL
5V or 3V
Power supply.
VSS
Power supply ground
Out
0V
RESET input, active low.
With Internal pull-up and schmitt trigger input.
RST
Input
VDD
External IRQ pin.
With software programmable internal pull-up and
schmitt trigger input.
VDD to VDD+V
IRQ1
Input
HI
This pin is also used for mode entry selection.
OSC1
X-tal or RC oscillator input.
In
Analog
Analog
For X-tal oscillator option:
X-tal oscillator output, this is the inverting OSC1
signal.
Out
OSC2
For RC oscillator option:
Default is RCCLK output.
In/Out
VDD
Shared with PTA6/KBI6, with programmable pull-up.
7-bit general purpose I/O port.
In/Out
In
VDD
VDD
PTA[0:6]
PTB[0:7]
Shared with 7 keyboard interrupts KBI[0:6].
Each pin has programmable internal pull-up device.
8-bit general purpose I/O port.
In
VDD
In/Out
In
VDD
Shared with 8 ADC inputs, ADC[0:7].
8-bit general purpose I/O port.
Analog
VDD
In/Out
Input
In/Out
PTD[3:0] shared with 4 ADC inputs, ADC[8:11].
PTD[4:5] shared with TIM channels, TCH0 and TCH1.
Analog
VDD
PTD[0:7]
PTD[6:7] can be configured as 25mA open-drain
output with pull-up.
In/Out
VDD
NOTE: On the 20-pin package, the following pins are not available:
PTA0, PTA1, PTA2, PTA3, PTA4, PTA5, PTD0, and PTD1.
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
26
General Description
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 2. Me m ory
2.1 Conte nts
2.2
2.3
2.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.2 Introd uc tion
The CPU08 can address 64 Kbytes of memory space. The memory
map, shown in Figure 2-1, includes:
• 4096 bytes of user ROM for MC68H(R)C08JL3/JK3
1536 bytes of user ROM for MC68H(R)C08JK1
• 128 bytes of RAM
• 48 bytes of user-defined vectors
• 960 bytes of Monitor ROM
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Memory
27
Me m ory
$0000
↓
$003F
I/O REGISTERS
64 BYTES
$0040
↓
$007F
RESERVED
64 BYTES
$0080
↓
$00FF
RAM
128 BYTES
$0100
↓
$EBFF
UNIMPLEMENTED
60160 BYTES
$0100
↓
$F5FF
UNIMPLEMENTED
62720 BYTES
$EC00
↓
$FBFF
USER ROM
MC68H(R)C08JL3/JK3
4096 BYTES
USER ROM
MC68H(R)C08JK1
1536 BYTES
$F600
↓
$FBFF
$FC00
↓
$FDFF
MONITOR ROM
512 BYTES
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
$FE0E
$FE0F
BREAK STATUS REGISTER (BSR)
RESET STATUS REGISTER (RSR)
RESERVED (UBAR)
BREAK FLAG CONTROL REGISTER (BFCR)
INTERRUPT STATUS REGISTER 1 (INT1)
INTERRUPT STATUS REGISTER 2 (INT2)
INTERRUPT STATUS REGISTER 3 (INT3)
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BREAK ADDRESS HIGH REGISTER (BRKH)
BREAK ADDRESS LOW REGISTER (BRKL)
BREAK STATUS AND CONTROL REGISTER (BRKSCR)
RESERVED
$FE10
↓
$FFCF
MONITOR ROM
448 BYTES
$FFD0
↓
$FFFF
USER VECTORS
48 BYTES
Figure 2-1. Memory Map
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
28
Memory
Memory
I/O Section
2.3 I/ O Se c tion
Addresses $0000–$003F, shown in Figure 2-2, contain most of the
control, status, and data registers. Additional I/O registers have the
following addresses:
• $FE00 (Break Status Register, BSR)
• $FE01 (Reset Status Register, RSR)
• $FE02 (Reserved, SUBAR)
• $FE03 (Break Flag Control Register, BFCR)
• $FE04 (Interrupt Status Register 1, INT1)
• $FE05 (Interrupt Status Register 2, INT2)
• $FE06 (Interrupt Status Register 3, INT3)
• $FE07 (Reserved)
• $FE08 (Reserved)
• $FE09 (Reserved)
• $FE0A (Reserved)
• $FE0B (Reserved)
• $FE0C (Break Address Register High, BRKH)
• $FE0D (Break Address Register Low, BRKL)
• $FE0E (Break Status and Control Register, BRKSCR)
• $FE0F (Reserved)
• $FFFF (COP Control Register, COPCTL)
2.4 Monitor ROM
The 960 bytes at addresses $FC00–$FDFF and $FE10–$FFCF are
reserved ROM addresses that contain the instructions for the monitor
functions. (See Section 9. Monitor ROM (MON).)
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Memory
29
Me m ory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
0
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Port A Data Register
(PTA)
$0000
Unaffected by reset
PTB4 PTB3
Unaffected by reset
PTB7
PTB6
PTB5
PTB2
PTB1
PTB0
Port B Data Register
(PTB)
$0001
$0002
$0003
$0004
$0005
$0006
$0007
Unimplemented Write:
Read:
PTD7
0
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Port D Data Register
Write:
(PTD)
Reset:
Read:
Unaffected by reset
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Data Direction Register A
Write:
(DDRA)
Reset:
Read:
0
DDRB7
0
0
DDRB6
0
0
DDRB5
0
0
DDRB4
0
0
DDRB3
0
0
DDRB2
0
0
DDRB1
0
0
DDRB0
0
Data Direction Register B
Write:
(DDRB)
Reset:
Read:
Unimplemented Write:
Read:
DDRD7
0
DDRD6
0
DDRD5
0
DDRD4
0
DDRD3
0
DDRD2
0
DDRD1
0
DDRD0
0
Data Direction Register D
Write:
(DDRD)
Reset:
Read:
$0008
↓
Unimplemented Write:
$0009
Read:
0
0
0
0
0
0
0
0
SLOWD7 SLOWD6 PTDPU7 PTDPU6
Port D Control Register
$000A
Write:
(PDCR)
Reset:
0
0
0
0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
30
Memory
Memory
Monitor ROM
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
$000B
↓
Unimplemented Write:
$000C
Read:
Port A Input Pull-up
PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
$000D
Enable Register Write:
(PTAPUE)
Reset:
0
0
0
0
0
0
0
0
$000E
↓
$0019
Read:
Write:
Unimplemented
Read:
0
0
0
0
KEYF
0
ACKK
0
Keyboard Status and
MODEK
IMASKK
$001A
Control Register Write:
(KBSCR)
Reset:
0
0
0
KBIE6
0
0
KBIE5
0
0
KBIE4
0
0
KBIE3
0
0
KBIE1
0
0
KBIE0
0
Read:
Keyboard Interrupt
KBIE2
0
$001B
$001C
Enable Register Write:
(KBIER)
Reset:
0
Read:
Unimplemented Write:
Read:
0
0
0
0
IRQF1
0
ACK1
0
IRQ Status and Control
IMASK1
MODE1
$001D
$001E
$001F
Register Write:
(INTSCR)
Reset:
0
0
R
0
0
R
0
0
LVIT1
0*
0
LVIT0
0*
0
0
Read:
IRQPUD
R
R
R
Configuration Register 2
Write:
Reset:
Read:
Write:
Reset:
†
(CONFIG2)
0
COPRS
0
0
SSREC
0
0
STOP
0
0
COPD
0
R
R
LVID
R
Configuration Register 1
†
(CONFIG1)
0
0
0
0
† One-time writable register after each reset. * LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only.
Read:
TOF
0
0
TRST
0
0
TIM Status and Control
TOIE
TSTOP
PS2
PS1
0
PS0
0
$0020
Register Write:
(TSC)
Reset:
0
0
1
0
0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5)
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Memory
31
Me m ory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TIM Counter Register
High Write:
$0021
(TCNTH)
Reset:
Read:
0
0
0
0
0
0
0
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TIM Counter Register
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
Low Write:
(TCNTL)
Reset:
Read:
0
Bit15
1
0
Bit14
1
0
Bit13
1
0
Bit12
1
0
Bit11
1
0
Bit10
1
0
Bit9
1
0
TIM Counter Modulo
Bit8
Register High Write:
(TMODH)
Reset:
1
Read:
TIM Counter Modulo
Bit7
Bit6
1
Bit5
1
Bit4
1
Bit3
1
Bit2
1
Bit1
1
Bit0
Register Low Write:
(TMODL)
Reset:
1
CH0F
0
1
CH0MAX
0
Read:
TIM Channel 0 Status and
CH0IE
0
MS0B
0
MS0A
0
ELS0B
0
ELS0A
0
TOV0
0
Control Register Write:
(TSC0)
Reset:
0
Read:
TIM Channel 0
Bit15
Bit7
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Register High Write:
(TCH0H)
Reset:
Indeterminate after reset
Bit4 Bit3
Indeterminate after reset
Read:
TIM Channel 0
Bit6
Bit5
0
Bit2
Bit1
Bit0
Register Low Write:
(TCH0L)
Reset:
Read:
CH1F
TIM Channel 1 Status and
CH1MAX
CH1IE
0
MS1A
0
ELS1B
0
ELS1A
0
TOV1
0
Control Register Write:
0
0
(TSC1)
Reset:
0
0
Read:
TIM Channel 1
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Register High Write:
(TCH1H)
Reset:
Indeterminate after reset
Bit4 Bit3
Read:
TIM Channel 1
Bit7
Bit6
Bit5
Bit2
Bit1
Bit0
Register Low Write:
(TCH1L)
Reset:
Indeterminate after reset
R
= Unimplemented
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5)
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
32
Memory
Memory
Monitor ROM
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$002B
↓
$003B
Read:
Write:
Unimplemented
Read: COCO
ADC Status and Control
Register Write:
AIEN
ADCO
CH4
CH3
CH2
CH1
CH0
$003C
$003D
(ADSCR)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
0
0
0
1
1
1
1
1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
ADC Data Register
(ADR)
Indeterminate after reset
0
0
0
0
0
0
0
0
ADIV2
0
ADIV1
0
ADIV0
0
ADC Input Clock Register
(ADICLK)
$003E
$003F
0
0
Unimplemented Write:
Read:
SBSW
See note
0
R
R
R
R
R
R
R
0
Break Status Register
$FE00
Write:
(BSR)
Reset:
Note: Writing a logic 0 clears SBSW.
Read:
Write:
POR:
Read:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
Reset Status Register
$FE01
(RSR)
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
$FE02
$FE03
$FE04
Reserved Write:
Read:
Break Flag Control
BCFE
R
R
R
R
R
R
R
Register Write:
(BFCR)
Reset:
0
0
Read:
IF5
R
IF4
R
IF3
R
0
R
0
IF1
0
R
0
0
R
0
Interrupt Status Register 1
Write:
R
0
R
(INT1)
Reset:
0
0
0
0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Memory
33
Me m ory
Addr.
Register Name
Bit 7
IF14
R
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Interrupt Status Register 2
(INT2)
$FE05
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
0
0
0
0
0
0
0
IF15
R
Interrupt Status Register 3
(INT3)
$FE06
R
R
0
R
0
R
0
R
0
R
0
R
0
0
0
$FE07
↓
R
R
R
R
R
R
R
R
Reserved Write:
$FE0B
Read:
Break Address High
Bit15
0
Bit14
0
Bit13
0
Bit12
0
Bit11
0
Bit10
0
Bit9
0
Bit8
0
$FE0C
$FE0D
$FE0E
Register Write:
(BRKH)
Reset:
Read:
Break Address low
Bit7
0
Bit6
0
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Register Write:
(BRKL)
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Break Status and Control
BRKE
0
BRKA
0
Register Write:
(BRKSCR)
Reset:
0
0
0
0
0
0
Read:
Low byte of reset vector
COP Control Register
$FFFF
Write:
Writing clears COP counter (any value)
Unaffected by reset
(COPCTL)
Reset:
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 5)
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
34
Memory
Memory
Monitor ROM
.
Table 2-1. Vector Addresses
Vector Priority Vector Address
Vector
Lowest
$FFDE
ADC Conversion Complete Vector (High)
ADC Conversion Complete Vector (Low)
Keyboard Vector (High)
IF15
IF14
$FFDF
$FFE0
$FFE1
Keyboard Vector (Low)
IF13
to
—
Not Used
IF6
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
—
TIM Overflow Vector (High)
TIM Overflow Vector (Low)
TIM Channel 1 Vector (High)
TIM Channel 1 Vector (Low)
TIM Channel 0 Vector (High)
TIM Channel 0 Vector (Low)
Not Used
IF5
IF4
IF3
IF2
IF1
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
IRQ Vector (High)
IRQ Vector (Low)
SWI Vector (High)
—
—
SWI Vector (Low)
Reset Vector (High)
Highest
Reset Vector (Low)
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Memory
35
Me m ory
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
36
Memory
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 3. Ra nd om -Ac c e ss Me m ory (RAM)
3.1 Conte nts
3.2
3.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.2 Introd uc tion
This section describes the 128 bytes of RAM.
3.3 Func tiona l De sc rip tion
Addresses $0080 through $00FF are RAM locations. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to
be anywhere in the 64-Kbyte memory space.
NOTE: For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 128 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF, direct addressing mode instructions can
access efficiently all page zero RAM locations. Page zero RAM,
therefore, provides ideal locations for frequently accessed global
variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE: For M6805 compatibility, the H register is not stacked.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Random-Access Memory (RAM)
37
Ra nd om -Ac c e ss Me m ory (RAM)
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
Technical Data
MC68H(R)C08JL3 — Rev. 4
38
Random-Access Memory (RAM)
MOTOROLA
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 4. Re a d -Only Me m ory (ROM)
4.1 Conte nts
4.2
4.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.2 Introd uc tion
This section describes the 4096 or 1536 bytes of read-only memory
(ROM) and 48 bytes of user vectors.
4.3 Func tiona l De sc rip tion
These addresses are user ROM locations:
$EC00–$FBFF; user memory, 4096 bytes on MC68H(R)C08JL3/JK3.
$F600–$FBFF; user memory, 1536 bytes on MC68H(R)C08JK1.
$FFD0–$FFFF (These locations are reserved for user-defined interrupt
and reset vectors.)
1
NOTE: A security feature prevents viewing of the ROM contents.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the ROM contents difficult for unauthorized users.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Read-Only Memory (ROM)
39
Re a d -Only Me m ory (ROM)
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
40
Read-Only Memory (ROM)
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 5. Config ura tion Re g iste r (CONFIG)
5.1 Conte nts
5.2
5.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
5.2 Introd uc tion
This section describes the configuration registers (CONFIG1 and
CONFIG2). The configuration registers enables or disables the following
options:
• Stop mode recovery time (32 × 2OSCOUT cycles or
4096 × 2OSCOUT cycles)
• STOP instruction
• Computer operating properly module (COP)
13
4
• COP reset period (COPRS), (2 –2 ) × 2OSCOUT or
18
4
(2 –2 ) × 2OSCOUT
• Enable LVI circuit
• Select LVI trip voltage
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Configuration Register (CONFIG)
41
Config ura tion Re g iste r (CONFIG)
5.3 Func tiona l De sc rip tion
The configuration register is used in the initialization of various options.
The configuration register can be written once after each reset. All of the
configuration register bits are cleared during reset. Since the various
options affect the operation of the MCU it is recommended that this
register be written immediately after reset. The configuration register is
located at $001E and $001F, and may be read at anytime.
NOTE: The CONFIG registers are one-time writable by the user after each
reset. Upon a reset, the CONFIG registers default to predetermined
settings as shown in Figure 5-1 and Figure 5-2.
Address:
$001E
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
POR:
IRQPUD
R
R
LVIT1
LVIT0
R
R
Not affected Not affected
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
= Reserved
Figure 5-1. Configuration Register 2 (CONFIG2)
IRQPUD — IRQ1 Pin Pull-up control bit
1 = Internal Pull-up is disconnected
0 = Internal Pull-up is connected between IRQ1 pin and V
DD
LVIT1, LVIT0 — Low Voltage Inhibit trip voltage selection bits
Detail description of the LVI control signals is given in Section 16.
Technical Data
MC68H(R)C08JL3 — Rev. 4
42
Configuration Register (CONFIG)
MOTOROLA
Configuration Register (CONFIG)
Functional Description
Address:
$001F
Bit 7
6
5
R
0
4
LVID
0
3
R
0
2
SSREC
0
1
STOP
0
Bit 0
COPD
0
Read:
Write:
Reset:
COPRS
R
0
0
R
= Reserved
Figure 5-2. Configuration Register 1 (CONFIG1)
COPRS — COP reset period selection bit
13
4
1 = COP reset cycle = (2 – 2 ) × 2OSCOUT
18
4
0 = COP reset cycle = (2 – 2 ) × 2OSCOUT
LVID — Low Voltage Inhibit Disable Bit
1 = Low Voltage Inhibit disabled
0 = Low Voltage Inhibit enabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of
32 × OSCXCLK cycles instead of a 4096 × 2OSCOUT cycle delay.
1 = Stop mode recovery after 32 × 2OSCOUT cycles
0 = Stop mode recovery after 4096 × 2OSCOUT cycles
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 15. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Configuration Register (CONFIG)
43
Config ura tion Re g iste r (CONFIG)
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
44
Configuration Register (CONFIG)
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 6. Ce ntra l Proc e ssor Unit (CPU)
6.1 Conte nts
6.2
6.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
6.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .49
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.6
6.6.1
6.6.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.7
6.8
6.9
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .53
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.2 Introd uc tion
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08
Reference Manual (Motorola document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes,
and architecture.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Central Processor Unit (CPU)
45
Ce ntra l Proc e ssor Unit (CPU)
6.3 Fe a ture s
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with x-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64 Kbytes
• Low-power stop and wait modes
6.4 CPU Re g iste rs
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
Technical Data
MC68H(R)C08JL3 — Rev. 4
46
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
CPU Registers
7
0
0
0
0
ACCUMULATOR (A)
15
15
15
H
X
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
7
0
V
1
1
H
I
N
Z
C
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
6.4.1 Ac c um ula tor
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 6-2. Accumulator (A)
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Central Processor Unit (CPU)
47
Ce ntra l Proc e ssor Unit (CPU)
6.4.2 Ind e x Re g iste r
The 16-bit index register allows indexed addressing of a 64-Kbyte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X = Indeterminate
Figure 6-3. Index Register (H:X)
6.4.3 Sta c k Pointe r
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Technical Data
MC68H(R)C08JL3 — Rev. 4
48
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
CPU Registers
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 6-4. Stack Pointer (SP)
NOTE: The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
6.4.4 Prog ra m Counte r
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
Loaded with Vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
6.4.5 Cond ition Cod e Re g iste r
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Central Processor Unit (CPU)
49
Ce ntra l Proc e ssor Unit (CPU)
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit 7
6
1
1
5
1
1
4
H
X
3
I
2
N
X
1
Z
X
Bit 0
Read:
Write:
Reset:
V
C
X
X
1
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or add-
with-carry (ADC) operation. The half-carry flag is required for binary-
coded decimal (BCD) arithmetic operations. The DAA instruction uses
the states of the H and C flags to determine the appropriate correction
factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
Technical Data
MC68H(R)C08JL3 — Rev. 4
50
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
CPU Registers
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE: To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Central Processor Unit (CPU)
51
Ce ntra l Proc e ssor Unit (CPU)
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.5 Arithm e tic / Log ic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Motorola document order
number CPU08RM/AD) for a description of the instructions and
addressing modes and more detail about the architecture of the CPU.
6.6 Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low power-consumption
standby modes.
6.6.1 Wa it Mod e
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
Technical Data
MC68H(R)C08JL3 — Rev. 4
52
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
CPU During Break Interrupts
6.6.2 Stop Mod e
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
6.7 CPU During Bre a k Inte rrup ts
If a break module is present on the MCU, the CPU starts a break
interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
6.8 Instruc tion Se t Sum m a ry
6.9 Op c od e Ma p
See Table 6-2.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Central Processor Unit (CPU)
53
Ce ntra l Proc e ssor Unit (CPU)
Table 6-1. Instruction Set Summary
Effect on
CCR
Source
Operation
Form
Description
V H
I N Z C
ADC #opr
ADC opr
ADC opr
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
ADC opr,X
Add with Carry
ADC opr,X
A ← (A) + (M) + (C)
↕ ↕ – ↕ ↕ ↕
ADC ,X
ADC opr,SP
ADC opr,SP
SP1
SP2
9EE9 ff
9ED9 ee ff
ADD #opr
ADD opr
ADD opr
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
ADD opr,X
Add without Carry
ADD opr,X
A ← (A) + (M)
↕ ↕ – ↕ ↕ ↕
ADD ,X
ADD opr,SP
ADD opr,SP
SP1
SP2
9EEB ff
9EDB ee ff
AIS #opr
AIX #opr
Add Immediate Value (Signed) to SP
Add Immediate Value (Signed) to H:X
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
–
–
–
–
–
–
–
–
–
–
– IMM
– IMM
A7
AF
ii
ii
2
2
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Logical AND
A ← (A) & (M)
0
–
–
–
↕ ↕ –
SP1
SP2
9EE4 ff
9ED4 ee ff
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
4
1
1
4
3
5
Arithmetic Shift Left
(Same as LSL)
↕ –
↕ ↕ ↕
C
0
b7
b7
b0
b0
SP1
9E68 ff
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
4
1
1
4
3
5
C
Arithmetic Shift Right
↕ –
–
–
↕ ↕ ↕
ff
SP1
9E67 ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
–
–
–
– REL
DIR (b0)
24
rr
3
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
BCLR n, opr
Clear Bit n in M
Mn ← 0
–
–
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
54
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Opcode Map
Table 6-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H
I
N Z C
BCS rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (Z) = 1
–
–
–
–
–
–
–
–
–
–
– REL
– REL
25
27
rr
rr
3
3
BEQ rel
BGE opr
Branch if Greater Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (N V) = 0
–
–
–
–
–
–
–
–
–
–
– REL
– REL
90
92
rr
rr
3
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 + rel ? (Z) | (N V) =
BGT opr
3
3
0
BHCC rel
BHCS rel
BHI rel
Branch if Half Carry Bit Clear
Branch if Half Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? (H) = 0
PC ← (PC) + 2 + rel ? (H) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
28
29
22
rr
rr
rr
3
3
3
Branch if Higher or Same
(Same as BCC)
BHS rel
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
– REL
24
rr
BIH rel
BIL rel
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
–
–
–
–
–
–
–
–
–
–
– REL
– REL
2F
2E
rr
rr
3
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Bit Test
(A) & (M)
0
–
–
↕ ↕ –
SP1
SP2
9EE5 ff
9ED5 ee ff
Branch if Less Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (Z) | (N V) =
BLE opr
–
–
–
–
–
– REL
93
rr
3
1
BLO rel
BLS rel
BLT opr
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
– REL
– REL
– REL
– REL
– REL
– REL
25
23
91
2C
2B
2D
26
2A
20
rr
rr
rr
rr
rr
rr
rr
rr
rr
3
3
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N V) =1
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? (I) = 0
PC ← (PC) + 2 + rel ? (N) = 1
PC ← (PC) + 2 + rel ? (I) = 1
PC ← (PC) + 2 + rel ? (Z) = 0
PC ← (PC) + 2 + rel ? (N) = 0
PC ← (PC) + 2 + rel
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Central Processor Unit (CPU)
55
Ce ntra l Proc e ssor Unit (CPU)
Table 6-1. Instruction Set Summary
Effect on
CCR
Source
Operation
Form
Description
V H
I
N Z C
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRCLR n,opr,rel Branch if Bit n in M Clear
PC ← (PC) + 3 + rel ? (Mn) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
↕
BRN rel
Branch Never
PC ← (PC) + 2
– REL
DIR (b0)
21
rr
3
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
BRSET n,opr,rel Branch if Bit n in M Set
PC ← (PC) + 3 + rel ? (Mn) = 1
↕
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BSET n,opr
Set Bit n in M
Mn ← 1
–
–
–
–
–
–
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
BSR rel
Branch to Subroutine
–
–
–
–
–
–
–
–
–
–
– REL
AD
rr
4
PC ← (PC) + rel
CBEQ opr,rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
IMM
31
41
51
61
71
dd rr
ii rr
ii rr
ff rr
rr
5
4
4
5
4
6
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
IMM
IX1+
Compare and Branch if Equal
–
IX+
SP1
CBEQ opr,SP,rel
9E61 ff rr
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
–
–
–
–
–
0
–
–
–
–
0 INH
– INH
98
9A
1
2
Clear Interrupt Mask
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
– INH
IX1
IX
3F
4F
5F
8C
6F
7F
dd
ff
3
1
1
1
3
2
4
Clear
0
–
–
0
1
CLR opr,SP
SP1
9E6F ff
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
56
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Opcode Map
Table 6-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H
I
N Z C
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Compare A with M
(A) – (M)
↕ –
–
↕ ↕ ↕
SP1
SP2
9EE1 ff
9ED1 ee ff
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
33
43
53
63
73
dd
ff
4
1
1
4
3
5
Complement (One’s Complement)
Compare H:X with M
0
–
–
–
↕ ↕ 1
SP1
9E63 ff
CPHX #opr
CPHX opr
IMM
DIR
65
75
ii ii+1
dd
3
4
(H:X) – (M:M + 1)
↕ –
↕ ↕ ↕
CPX #opr
CPX opr
CPX opr
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
CPX ,X
Compare X with M
(X) – (M)
↕ –
–
–
–
↕ ↕ ↕
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
SP1
SP2
9EE3 ff
9ED3 ee ff
DAA
Decimal Adjust A
(A)
U –
↕ ↕ ↕ INH
72
2
10
A ← (A) – 1 or M ← (M) – 1 or X ← (X) –
1
5
3
3
5
4
6
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DIR
INH
– INH
IX1
IX
SP1
3B
4B
5B
6B
7B
dd rr
rr
rr
ff rr
rr
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
Decrement and Branch if Not Zero
–
–
–
–
9E6B ff rr
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
dd
ff
4
1
1
4
3
5
Decrement
Divide
↕ –
–
–
↕ ↕ –
SP1
9E6A ff
A ← (H:A)/(X)
H ← Remainder
DIV
–
–
–
↕ ↕ INH
52
7
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Central Processor Unit (CPU)
57
Ce ntra l Proc e ssor Unit (CPU)
Table 6-1. Instruction Set Summary
Effect on
CCR
Source
Operation
Form
Description
V H
I
N Z C
EOR #opr
EOR opr
EOR opr
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
EOR opr,X
Exclusive OR M with A
EOR opr,X
A ← (A M)
0
–
–
↕ ↕ –
EOR ,X
EOR opr,SP
EOR opr,SP
SP1
SP2
9EE8 ff
9ED8 ee ff
INC opr
INCA
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
dd
ff
4
1
1
4
3
5
INCX
Increment
INC opr,X
↕ –
–
↕ ↕ –
INC ,X
INC opr,SP
SP1
9E6C ff
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT
– IX2
IX1
IX
BC
CC
DC
EC
FC
dd
2
3
4
3
2
hh ll
ee ff
ff
Jump
PC ← Jump Address
–
–
–
–
–
–
–
–
–
–
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT
– IX2
IX1
BD
CD
DD
ED
FD
dd
4
5
6
5
4
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
hh ll
ee ff
ff
Jump to Subroutine
IX
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Load A from M
Load H:X from M
Load X from M
A ← (M)
H:X ← (M:M + 1)
X ← (M)
0
0
0
–
–
–
–
–
–
↕ ↕ –
↕ ↕ –
↕ ↕ –
SP1
SP2
9EE6 ff
9ED6 ee ff
LDHX #opr
LDHX opr
IMM
DIR
45
55
ii jj
dd
3
4
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
SP1
SP2
9EEE ff
9EDE ee ff
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
4
1
1
4
3
5
Logical Shift Left
(Same as ASL)
C
0
↕ –
–
↕ ↕ ↕
b7
b0
SP1
9E68 ff
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
58
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Opcode Map
Table 6-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H
I
N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
ff
4
1
1
4
3
5
0
C
Logical Shift Right
↕ –
–
0 ↕ ↕
b7
b0
LSR opr,SP
SP1
9E64 ff
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
DD
4E
5E
6E
7E
dd dd
dd
ii dd
dd
5
4
4
4
(M)
← (M)
Source
Destination
DIX+
IMD
IX+D
Move
0
–
–
0
–
–
↕ ↕ –
H:X ← (H:X) + 1 (IX+D, DIX+)
X:A ← (X) × (A)
MUL
Unsigned multiply
–
–
0 INH
42
5
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
DIR
INH
INH
IX1
IX
30
40
50
60
70
dd
ff
4
1
1
4
3
5
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
Negate (Two’s Complement)
↕ –
–
↕ ↕ ↕
SP1
9E60 ff
NOP
NSA
No Operation
Nibble Swap A
None
–
–
–
–
–
–
–
–
–
–
– INH
– INH
9D
1
3
A ← (A[3:0]:A[7:4])
62
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Inclusive OR A and M
A ← (A) | (M)
0
–
–
↕ ↕ –
SP1
SP2
9EEA ff
9EDA ee ff
PSHA
PSHH
PSHX
PULA
PULH
PULX
Push A onto Stack
Push H onto Stack
Push X onto Stack
Pull A from Stack
Pull H from Stack
Pull X from Stack
Push (A); SP ← (SP) – 1
Push (H); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
SP ← (SP + 1); Pull (A)
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
– INH
– INH
– INH
87
8B
89
86
8A
88
2
2
2
2
2
2
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
DIR
INH
INH
IX1
IX
39
49
59
69
79
dd
ff
4
1
1
4
3
5
C
Rotate Left through Carry
↕ –
–
↕ ↕ ↕
b7
b0
SP1
9E69 ff
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Central Processor Unit (CPU)
59
Ce ntra l Proc e ssor Unit (CPU)
Table 6-1. Instruction Set Summary
Effect on
CCR
Source
Operation
Form
Description
V H
I
N Z C
ROR opr
RORA
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
ff
4
1
1
4
3
5
RORX
C
Rotate Right through Carry
ROR opr,X
↕ –
–
–
↕ ↕ ↕
b7
b0
ROR ,X
ROR opr,SP
SP1
9E66 ff
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $FF
–
–
–
–
– INH
9C
1
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
↕ ↕ ↕ ↕ ↕ ↕ INH
80
81
7
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
RTS
Return from Subroutine
Subtract with Carry
–
–
–
–
–
–
– INH
4
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
A ← (A) – (M) – (C)
↕ –
↕ ↕ ↕
SP1
SP2
9EE2 ff
9ED2 ee ff
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
–
–
–
–
–
1
–
–
–
–
1 INH
– INH
99
9B
1
2
Set Interrupt Mask
STA opr
STA opr
DIR
EXT
IX2
B7
C7
D7
E7
F7
dd
3
4
4
3
2
4
5
hh ll
ee ff
ff
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
M ← (A)
0
–
–
↕ ↕ – IX1
IX
SP1
SP2
9EE7 ff
9ED7 ee ff
STHX opr
STOP
Store H:X in M
(M:M + 1) ← (H:X)
0
–
–
–
–
0
↕ ↕ – DIR
35
8E
dd
4
1
Enable IRQ Pin; Stop Oscillator
I ← 0; Stop Oscillator
–
–
– INH
STX opr
STX opr
DIR
EXT
IX2
BF
CF
DF
EF
FF
dd
3
4
4
3
2
4
5
hh ll
ee ff
ff
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M
M ← (X)
0
–
–
↕ ↕ – IX1
IX
SP1
SP2
9EEF ff
9EDF ee ff
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
60
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Opcode Map
Table 6-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H
I
N Z C
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Subtract
A ← (A) – (M)
↕ –
–
↕ ↕ ↕
SP1
SP2
9EE0 ff
9ED0 ee ff
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
Software Interrupt
–
–
1
–
–
– INH
83
9
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
TAX
TPA
Transfer A to CCR
Transfer A to X
CCR ← (A)
X ← (A)
↕ ↕ ↕ ↕ ↕ ↕ INH
84
97
85
2
1
1
–
–
–
–
–
–
–
–
–
–
– INH
– INH
Transfer CCR to A
A ← (CCR)
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
dd
ff
3
1
1
3
2
4
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0
–
–
↕ ↕ –
SP1
9E6D ff
TSX
TXA
TXS
Transfer SP to H:X
Transfer X to A
H:X ← (SP) + 1
A ← (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
95
9F
94
2
1
2
Transfer H:X to SP
(SP) ← (H:X) – 1
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Central Processor Unit (CPU)
61
Ce ntra l Proc e ssor Unit (CPU)
Table 6-1. Instruction Set Summary
Effect on
CCR
Source
Operation
Form
Description
V H
Any bit
opr Operand (one or two bytes)
PC Program counter
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
I N Z C
A
C
Accumulator
Carry/borrow bit
n
CCR Condition code register
dd Direct address of operand
dd rr Direct address of operand and relative offset of branch instruction
DD Direct to direct addressing mode
DIR Direct addressing mode
rel
rr
Relative program counter offset byte
Relative program counter offset byte
DIX+ Direct to indexed with post increment addressing mode
ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode
SP Stack pointer
U
V
X
Z
&
|
ff
H
H
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
hh ll High and low bytes of operand address in extended addressing
I
Interrupt mask
ii
Immediate operand byte
IMD Immediate source to direct destination addressing mode
IMM Immediate addressing mode
INH Inherent addressing mode
( )
IX
Indexed, no offset addressing mode
–( ) Negation (two’s complement)
IX+
Indexed, no offset, post increment addressing mode
#
Immediate value
Sign extend
Loaded with
If
IX+D Indexed with post increment to direct addressing mode
IX1 Indexed, 8-bit offset addressing mode
IX1+ Indexed, 8-bit offset, post increment addressing mode
«
←
?
IX2
M
N
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
:
↕
—
Concatenated with
Set or cleared
Not affected
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
62
Central Processor Unit (CPU)
Table 6-2. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
3
INH
4
INH
IX1
SP1
9E6
IX
7
INH
INH
IMM
A
DIR
B
EXT
C
IX2
SP2
IX1
E
SP1
9EE
IX
F
MSB
0
1
2
5
6
8
9
D
9ED
LSB
5
4
3
4
1
NEGA
INH
1
NEGX
INH
4
5
3
7
3
2
3
4
4
5
3
4
2
0
BRSET0 BSET0
BRA
NEG
NEG
NEG
NEG
IX
RTI
BGE
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
IX
3
DIR
5
2
DIR
4
2
2
2
2
2
2
2
2
REL 2 DIR
1
1
2
IX1 3 SP1
5
1
2
1
1
1
2
1
1
1
1
1
2
1
1
2
1
1
1
INH
2
2
2
2
1
1
REL 2 IMM 2 DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
EXT 3 IX2
4
4
4
4
4
4
4
4
4
4
4
4
SP2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IX1
3
3
3
3
3
3
3
3
3
3
3
3
SP1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
BRN
REL 3 DIR
3
BHI
REL
3
BLS
REL 2 DIR
3
BCC
REL 2 DIR
3
BCS
REL 2 DIR
3
BNE
REL 2 DIR
3
BEQ
REL 2 DIR
3
5
4
4
6
4
CBEQ
IX+
2
DAA
INH
3
COM
IX
3
LSR
IX
4
CPHX
DIR
3
ROR
IX
3
ASR
IX
3
LSL
IX
3
ROL
IX
3
DEC
IX
4
DBNZ
IX
3
INC
IX
4
3
BLT
2
CMP
3
CMP
4
CMP
EXT 3 IX2
4
SBC
EXT 3 IX2
4
CPX
EXT 3 IX2
4
AND
EXT 3 IX2
4
BIT
EXT 3 IX2
4
LDA
EXT 3 IX2
4
STA
EXT 3 IX2
4
EOR
EXT 3 IX2
4
ADC
EXT 3 IX2
4
ORA
EXT 3 IX2
4
ADD
EXT 3 IX2
3
JMP
EXT 3 IX2
5
JSR
EXT 3 IX2
4
LDX
EXT 3 IX2
4
STX
EXT 3 IX2
4
CMP
5
3
4
2
CMP
IX
2
SBC
IX
2
CPX
IX
2
AND
IX
2
BIT
IX
2
LDA
IX
2
STA
IX
2
EOR
IX
2
ADC
IX
2
ORA
IX
2
ADD
IX
2
JMP
IX
4
JSR
IX
2
LDX
IX
2
STX
IX
1
2
BRCLR0 BCLR0
CBEQ CBEQA CBEQX CBEQ
CBEQ
RTS
CMP
CMP
CMP
3
DIR
5
2
DIR
4
3
1
IMM 3 IMM 3 IX1+
4
SP1
INH
REL 2 IMM 2 DIR
SP2
IX1
SP1
5
7
3
3
BGT
2
SBC
3
SBC
4
SBC
5
3
4
BRSET1 BSET1
MUL
DIV
INH
NSA
SBC
SBC
SBC
3
DIR
5
2
DIR
4
INH
1
1
2
2
3
2
2
2
2
2
INH
REL 2 IMM 2 DIR
SP2
IX1
SP1
4
1
1
4
COM
IX1
4
LSR
IX1
3
CPHX
IMM
4
ROR
IX1
4
ASR
IX1
4
LSL
IX1
4
ROL
IX1
4
DEC
IX1
5
9
3
BLE
2
CPX
3
CPX
4
CPX
5
3
4
3
BRCLR1 BCLR1
COM
COMA
COMX
COM
SWI
CPX
CPX
CPX
3
DIR
5
2
DIR
4
1
INH
1
INH
3
3
SP1
1
1
1
1
1
1
1
1
1
1
INH
REL 2 IMM 2 DIR
SP2
IX1
SP1
4
LSR
1
LSRA
INH
1
LSRX
INH
5
2
2
2
AND
IMM 2 DIR
3
AND
4
AND
5
3
4
4
BRSET2 BSET2
LSR
TAP
TXS
AND
AND
AND
3
DIR
5
2
DIR
4
1
3
1
SP1
INH
INH
2
2
2
2
2
2
2
2
SP2
IX1
SP1
4
3
4
1
2
2
BIT
3
BIT
4
BIT
5
BIT
SP2
3
4
BIT
SP1
5
BRCLR2 BCLR2
STHX
LDHX
LDHX
TPA
TSX
BIT
3
DIR
5
2
DIR
4
IMM 2 DIR
INH
INH
IMM 2 DIR
IX1
4
ROR
1
1
5
2
PULA
INH
2
PSHA
INH
2
PULX
INH
2
PSHX
INH
2
PULH
INH
2
PSHH
INH
1
CLRH
INH
2
LDA
IMM 2 DIR
2
AIS
IMM 2 DIR
2
EOR
IMM 2 DIR
2
ADC
IMM 2 DIR
2
ORA
IMM 2 DIR
2
ADD
IMM 2 DIR
3
LDA
4
LDA
5
3
4
6
BRSET3 BSET3
RORA
RORX
ROR
LDA
LDA
LDA
3
DIR
5
2
DIR
4
1
INH
1
INH
3
3
3
3
3
4
3
3
SP1
5
SP2
IX1
SP1
4
ASR
1
ASRA
INH
1
LSLA
INH
1
ROLA
INH
1
DECA
INH
1
ASRX
INH
1
LSLX
INH
1
ROLX
INH
1
DECX
INH
1
3
STA
4
STA
5
3
4
7
BRCLR3 BCLR3
ASR
TAX
STA
STA
STA
3
DIR
5
2
DIR
4
1
1
1
1
1
1
1
1
SP1
5
1
1
1
1
1
1
1
INH
SP2
IX1
SP1
4
LSL
1
3
EOR
4
EOR
5
3
4
8
BRSET4 BSET4 BHCC
LSL
CLC
EOR
EOR
EOR
3
DIR
5
2
DIR
4
2
REL 2 DIR
3
SP1
5
INH
SP2
IX1
SP1
4
ROL
1
3
ADC
4
ADC
5
3
4
9
BRCLR4 BCLR4 BHCS
ROL
SEC
ADC
ADC
ADC
3
DIR
5
2
DIR
4
2
2
2
2
2
2
2
REL 2 DIR
SP1
5
INH
SP2
IX1
SP1
3
BPL
REL 2 DIR
3
BMI
REL 3 DIR
3
BMC
REL 2 DIR
3
BMS
REL 2 DIR
3
BIL
4
DEC
2
CLI
INH
2
SEI
INH
3
ORA
4
ORA
5
3
4
A
B
C
D
E
F
BRSET5 BSET5
DEC
ORA
ORA
ORA
3
DIR
5
2
DIR
4
SP1
6
SP2
IX1
SP1
5
3
3
5
3
ADD
4
ADD
5
3
4
BRCLR5 BCLR5
DBNZ DBNZA DBNZX DBNZ
DBNZ
ADD
ADD
ADD
3
DIR
5
2
DIR
4
2
1
1
3
1
INH
1
2
1
1
2
1
INH
1
3
2
2
3
2
IX1
4
INC
IX1
3
TST
IX1
4
MOV
IMD
3
CLR
IX1
SP1
5
SP2
IX1
SP1
4
INC
1
2
JMP
4
JMP
3
BRSET6 BSET6
INCA
INCX
INC
RSP
JMP
3
DIR
5
2
DIR
4
INH
1
TSTA
INH
5
MOV
DD
1
CLRA
INH
INH
1
TSTX
INH
4
MOV
DIX+
1
CLRX
INH
SP1
4
INH
2
DIR
4
IX1
3
TST
2
TST
IX
1
4
BSR
REL 2 DIR
2
LDX
IMM 2 DIR
2
AIX
IMM 2 DIR
6
JSR
5
BRCLR6 BCLR6
TST
SP1
NOP
JSR
JSR
3
DIR
5
2
DIR
4
INH
2
2
2
IX1
4
1
STOP
INH
1
WAIT
INH
3
LDX
4
LDX
5
3
4
BRSET7 BSET7
MOV
IX+D
LDX
LDX
LDX
*
1
TXA
INH
3
DIR
5
2
DIR
4
REL
3
BIH
1
1
4
4
SP2
IX1
3
3
SP1
3
CLR
4
2
CLR
IX
3
STX
4
STX
5
3
4
BRCLR7 BCLR7
DIR DIR
CLR
SP1
STX
STX
STX
3
2
REL 2 DIR
3
1
SP2
IX1
SP1
INH Inherent
REL Relative
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
MSB
LSB
0
High Byte of Opcode in Hexadecimal
Cycles
IMM Immediate
DIR Direct
IX
Indexed, No Offset
IX1 Indexed, 8-Bit Offset
IX2 Indexed, 16-Bit Offset
IMD Immediate-Direct
EXT Extended
DD Direct-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
5
Low Byte of Opcode in Hexadecimal
0
BRSET0 Opcode Mnemonic
DIR Number of Bytes / Addressing Mode
3
Ce ntra l Proc e ssor Unit (CPU)
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
64
Central Processor Unit (CPU)
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 7. Syste m Inte g ra tion Mod ule (SIM)
7.1 Conte nts
7.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
7.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .69
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . .69
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . .69
7.3.1
7.3.2
7.3.3
7.4
7.4.1
7.4.2
7.4.2.1
7.4.2.2
7.4.2.3
7.4.2.4
7.4.2.5
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .70
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . .71
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Computer Operating Properly (COP) Reset . . . . . . . . . .73
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .73
LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . .74
SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . .74
SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .75
7.5.1
7.5.2
7.5.3
7.6
7.6.1
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .79
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . .80
Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . . .80
Interrupt Status Register 3. . . . . . . . . . . . . . . . . . . . . . . .81
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . .81
7.6.1.1
7.6.1.2
7.6.2
7.6.2.1
7.6.2.2
7.6.2.3
7.6.3
7.6.4
7.6.5
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
System Integration Module (SIM)
65
Syste m Inte g ra tion Mod ule (SIM)
7.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
7.7.1
7.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
7.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . .85
Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . .86
Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . .88
7.8.1
7.8.2
7.8.3
7.2 Introd uc tion
This section describes the system integration module (SIM), which
supports up to 24 external and/or internal interrupts. Together with the
CPU, the SIM controls all MCU activities. A block diagram of the SIM is
shown in Figure 7-1. Figure 7-2 is a summary of the SIM I/O registers.
The SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Technical Data
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System Integration Module (SIM)
MOTOROLA
System Integration Module (SIM)
Introduction
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO OSCILLATOR)
SIM
COUNTER
COP CLOCK
2OSCOUT (FROM OSCILLATOR)
OSCOUT (FROM OSCILLATOR)
÷2
VDD
CLOCK
CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
INTERNAL
PULL-UP
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
MASTER
RESET
CONTROL
COP TIMEOUT (FROM COP MODULE)
USB RESET (FROM USB MODULE)
SIM RESET STATUS REGISTER
RESET
INTERRUPT SOURCES
CPU INTERFACE
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 7-1. SIM Block Diagram
Table 7-1. Signal Name Conventions
Signal Name
Description
2OSCOUT
Buffered clock from the X-tal oscillator circuit or the RC oscillator circuit.
The 2OSCOUT frequency divided by two. This signal is again divided by two in the
SIM to generate the internal bus clocks. (Bus clock = 2OSCOUT ÷ 4)
OSCOUT
IAB
IDB
Internal address bus
Internal data bus
PORRST
IRST
Signal from the power-on reset module to the SIM
Internal reset signal
R/W
Read/write signal
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Syste m Inte g ra tion Mod ule (SIM)
Addr.
Register Name
Bit 7
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
Bit 0
Read:
Write:
Reset:
SBSW
NOTE
0
R
0
R
0
Break Status Register
(BSR)
$FE00
Note: Writing a logic 0 clears SBSW.
Read:
Write:
POR:
Read:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
Reset Status Register
$FE01
(RSR)
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
$FE02
$FE03
$FE04
$FE05
$FE06
Reserved Write:
Reset:
Read:
Break Flag Control
BCFE
R
R
R
R
R
R
R
Register Write:
(BFCR)
Reset:
0
0
Read:
IF5
R
0
IF4
R
0
IF3
R
0
0
R
0
IF1
0
R
0
0
R
Interrupt Status Register 1
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
R
R
(INT1)
0
0
0
IF14
R
0
0
0
0
0
0
0
Interrupt Status Register 2
(INT2)
R
0
R
0
R
0
R
0
R
R
0
R
0
0
0
0
0
0
0
0
0
0
IF15
R
Interrupt Status Register 3
(INT3)
R
R
0
R
0
R
0
R
0
R
R
0
0
0
0
= Unimplemented
R
= Reserved
Figure 7-2. SIM I/O Register Summary
Technical Data
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System Integration Module (SIM)
System Integration Module (SIM)
SIM Bus Clock Control and Generation
7.3 SIM Bus Cloc k Control a nd Ge ne ra tion
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, OSCOUT, as shown in Figure 7-3.
From
OSCILLATOR
2OSCOUT
OSCOUT
SIM COUNTER
From
OSCILLATOR
BUS CLOCK
GENERATORS
÷ 2
SIM
Figure 7-3. SIM Clock Signals
7.3.1 Bus Tim ing
In user mode, the internal bus frequency is the oscillator frequency
(2OSCOUT) divided by four.
7.3.2 Cloc k Sta rt-Up from POR
When the power-on reset module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after
the 4096 2OSCOUT cycle POR time-out has completed. The RST pin is
driven low by the SIM during this entire period. The IBUS clocks start
upon completion of the time-out.
7.3.3 Cloc ks in Stop Mod e a nd Wa it Mod e
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
2OSCOUT to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay time-out. This time-out is
selectable as 4096 or 32 2OSCOUT cycles. (See 7.7.2 Stop Mode.)
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Syste m Inte g ra tion Mod ule (SIM)
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
7.4 Re se t a nd Syste m Initia liza tion
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
Monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see 7.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the reset status register (RSR). (See 7.8 SIM Registers.)
7.4.1 Exte rna l Pin Re se t
The RST pin circuits include an internal pull-up device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the reset
status register (RSR) is set as long as RST is held low for a minimum of
67 2OSCCLK cycles, assuming that the POR was not the source of the
reset. See Table 7-2 for details. Figure 7-4 shows the relative timing.
Table 7-2. PIN Bit Set Timing
Reset Type
POR
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
Technical Data
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System Integration Module (SIM)
System Integration Module (SIM)
Reset and System Initialization
OSCOUT
RST
VECT H VECT L
IAB
PC
Figure 7-4. External Reset Timing
7.4.2 Ac tive Re se ts from Inte rna l Sourc e s
All internal reset sources actively pull the RST pin low for 32 2OSCOUT
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles (Figure 7-5).
An internal reset can be caused by an illegal address, illegal opcode,
COP time-out, or POR. (See Figure 7-6 . Sources of Internal Reset.)
Note that for POR resets, the SIM cycles through 4096 2OSCOUT
cycles during which the SIM forces the RST pin low. The internal reset
signal then follows the sequence from the falling edge of RST shown in
Figure 7-5.
IRST
RSTPULLED LOW BY MCU
32 CYCLES
RST
32 CYCLES
2OSCOUT
IAB
VECTOR HIGH
Figure 7-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
INTERNAL RESET
LVI
Figure 7-6. Sources of Internal Reset
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Syste m Inte g ra tion Mod ule (SIM)
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
7.4.2.1 Po we r-On Re se t
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 2OSCOUT cycles. Sixty-four 2OSCOUT cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, the following events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables the oscillator to drive 2OSCOUT.
• Internal clocks to the CPU and modules are held inactive for 4096
2OSCOUT cycles to allow stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the reset status register (RSR) is set and all other
bits in the register are cleared.
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
2OSCOUT
OSCOUT
RST
IAB
$FFFE
$FFFF
Figure 7-7. POR Recovery
Technical Data
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System Integration Module (SIM)
System Integration Module (SIM)
Reset and System Initialization
7.4.2.2 Co m p ute r Op e ra ting Pro p e rly (COP) Re se t
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
reset status register (RSR). The SIM actively pulls down the RST pin for
all internal reset sources.
To prevent a COP module time-out, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and stages 12 through
5 of the SIM counter. The SIM counter output, which occurs at least
12
4
every (2 – 2 ) 2OSCOUT cycles, drives the COP counter. The COP
should be serviced as soon as possible out of reset to guarantee the
maximum amount of time before the first time-out.
The COP module is disabled if the RST pin or the IRQ1 pin is held at
VDD + VHI while the MCU is in monitor mode. The COP module can be
disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ1 pin. This prevents the COP from
becoming disabled as a result of external noise. During a break state,
V
DD + VHI on the RST pin disables the COP module.
7.4.2.3 Ille g a l Op c o d e Re se t
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the reset status register (RSR) and
causes a reset.
If the stop enable bit, STOP, in the mask option register is logic zero, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
7.4.2.4 Ille g a l Ad d re ss Re se t
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the reset status register (RSR) and resetting
the MCU. A data fetch from an unmapped address does not generate a
reset. The SIM actively pulls down the RST pin for all internal reset
sources.
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Technical Data
System Integration Module (SIM)
73
Syste m Inte g ra tion Mod ule (SIM)
7.4.2.5 LVI Re se t
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V voltage falls to the LVI trip voltage V . The LVI bit in the SIM
DD
TRIP
reset status register (SRSR) is set, and the external reset pin (RSTB) is
held low while the SIM counter counts out 4096 2OSCCLK cycles. Sixty-
four 2OSCOUT cycles later, the CPU and memories are released from
reset to allow the reset vector sequence to occur. The SIM actively pulls
down the (RSTB) pin for all internal reset sources.
7.5 SIM Counte r
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM
counter uses 12 stages for counting, followed by a 13th stage that
triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of 2OSCOUT.
7.5.1 SIM Counte r During Powe r-On Re se t
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the oscillator to drive the bus clock state machine.
7.5.2 SIM Counte r During Stop Mod e Re c ove ry
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic one, then the stop recovery is
reduced from the normal delay of 4096 2OSCOUT cycles down to 32
2OSCOUT cycles. This is ideal for applications using canned oscillators
that do not require long start-up times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC
cleared in the configuration register (CONFIG).
Technical Data
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System Integration Module (SIM)
MOTOROLA
System Integration Module (SIM)
Exception Control
7.5.3 SIM Counte r a nd Re se t Sta te s
External reset has no effect on the SIM counter. (See 7.7.2 Stop Mode
for details.) The SIM counter is free-running after all reset states. (See
7.4.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
7.6 Exc e p tion Control
Normal, sequential program execution can be changed in three different
ways:
• Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
7.6.1 Inte rrup ts
An interrupt temporarily changes the sequence of program execution to
respond to a particular event. Figure 7-8 flow charts the handling of
system interrupts.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared).
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Syste m Inte g ra tion Mod ule (SIM)
FROM RESET
YES
BREAK INTERRUPT?
NO
YES
I BIT SET?
NO
YES
YES
IRQ
INTERRUPT?
NO
TIMER
INTERRUPT?
NO
STACK CPU REGISTERS.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
(As many interrupts as exist on chip)
FETCH NEXT
INSTRUCTION
SWI
YES
YES
INSTRUCTION?
NO
RTI
UNSTACK CPU REGISTERS.
EXECUTE INSTRUCTION.
INSTRUCTION?
NO
Figure 7-8. Interrupt Processing
Technical Data
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System Integration Module (SIM)
System Integration Module (SIM)
Exception Control
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 7-9 shows interrupt entry timing. Figure
7-10 shows interrupt recovery timing.
MODULE
INTERRUPT
I BIT
IAB
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4
VECT H
VECT L
START ADDR
IDB
R/W
DUMMY
PC – 1[7:0] PC – 1[15:8]
X
A
CCR
V DATA H
V DATA L
OPCODE
Figure 7-9. Interrupt Entry
MODULE
INTERRUPT
I BIT
IAB
SP – 4
SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
IDB
R/W
CCR
A
X
PC – 1[7:0] PC – 1[15:8] OPCODE
OPERAND
Figure 7-10. Interrupt Recovery
7.6.1.1 Ha rd wa re Inte rrup ts
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register), and if the corresponding interrupt enable bit is
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Syste m Inte g ra tion Mod ule (SIM)
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first. Figure 7-11
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
CLI
LDA #$FF
PSHH
BACKGROUND ROUTINE
INT1
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 7-11. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE: To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
Technical Data
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System Integration Module (SIM)
MOTOROLA
System Integration Module (SIM)
Exception Control
7.6.1.2 SWI Instruc tio n
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE: A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
7.6.2 Inte rrup t Sta tus Re g iste rs
The flags in the interrupt status registers identify maskable interrupt
sources. Table 7-3 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 7-3. Interrupt Sources
INT
Register
Flag
1
Source
Flag
Vector Address
Priority
Mask
Highest
Reset
—
—
—
—
$FFFE–$FFFF
$FFFC–$FFFD
$FFFA–$FFFB
$FFF6–$FFF7
$FFF4–$FFF5
$FFF2–$FFF3
$FFE0–$FFE1
$FFDE–$FFDF
SWI Instruction
IRQ1 Pin
—
—
IRQF1
CH0F
CH1F
TOF
IMASK1
CH0IE
CH1IE
TOIE
IF1
IF3
IF4
IF5
IF14
IF15
Timer Channel 0 Interrupt
Timer Channel 1 Interrupt
Timer Overflow Interrupt
Keyboard Interrupt
KEYF
COCO
IMASKK
AIEN
Lowest
ADC Conversion Complete Interrupt
Note:
1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI
instruction.
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Syste m Inte g ra tion Mod ule (SIM)
7.6.2.1 Inte rrup t Sta tus Re g iste r 1
Address:
$FE04
Bit 7
0
6
5
IF4
R
4
IF3
R
3
0
2
IF1
R
1
0
Bit 0
0
Read:
Write:
Reset:
IF5
R
R
R
0
R
0
R
0
0
0
0
0
0
R
= Reserved
Figure 7-12. Interrupt Status Register 1 (INT1)
IF1, IF3 to IF5 — Interrupt Flags
These flags indicate the presence of interrupt requests from the
sources shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0, 1, 3 and 7 — Always read 0
7.6.2.2 Inte rrup t Sta tus Re g iste r 2
Address:
$FE05
Bit 7
IF14
R
6
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
R
R
0
R
0
R
0
R
0
R
0
R
0
0
0
R
= Reserved
Figure 7-13. Interrupt Status Register 2 (INT2)
IF14 — Interrupt Flags
This flag indicates the presence of interrupt requests from the sources
shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0 to 6 — Always read 0
Technical Data
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System Integration Module (SIM)
MOTOROLA
System Integration Module (SIM)
Exception Control
7.6.2.3 Inte rrup t Sta tus Re g iste r 3
Address:
$FE06
Bit 7
0
6
5
0
4
0
3
0
2
0
1
0
Bit 0
IF15
R
Read:
Write:
Reset:
0
R
R
R
0
R
0
R
0
R
0
R
0
0
0
0
R
= Reserved
Figure 7-14. Interrupt Status Register 3 (INT3)
IF15 — Interrupt Flags
These flags indicate the presence of interrupt requests from the
sources shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 1 to 7 — Always read 0
7.6.3 Re se t
All reset sources always have equal and highest priority and cannot be
arbitrated.
7.6.4 Bre a k Inte rrup ts
The break module can stop normal program flow at a software-
programmable break point by asserting its break interrupt output. (See
Section 17. Break Module (BREAK).) The SIM puts the CPU into the
break state by forcing it to the SWI vector location. Refer to the break
interrupt subsection of each module to see how each module is affected
by the break state.
7.6.5 Sta tus Fla g Prote c tion in Bre a k Mod e
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
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Syste m Inte g ra tion Mod ule (SIM)
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a two-step clearing mechanism — for example, a read
of one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the
flag as normal.
7.7 Low-Powe r Mod e s
Executing the WAIT or STOP instruction puts the MCU in a low-power-
consumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described
below. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
7.7.1 Wa it Mod e
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run. Figure 7-15 shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the break
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System Integration Module (SIM)
MOTOROLA
System Integration Module (SIM)
Low-Power Modes
status register (BSR). If the COP disable bit, COPD, in the mask option
register is logic zero, then the computer operating properly module
(COP) is enabled and remains active in wait mode.
IAB
IDB
R/W
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 7-15. Wait Mode Entry Timing
Figure 7-16 and Figure 7-17 show the timing for WAIT recovery.
IAB
$6E0B
$A6
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 7-16. Wait Recovery from Interrupt or Break
32
Cycles
32
Cycles
IAB
IDB
RST
$6E0B
$A6
RSTVCTH
RSTVCTL
$A6
$A6
2OSCOUT
Figure 7-17. Wait Recovery from Internal Reset
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
System Integration Module (SIM)
83
Syste m Inte g ra tion Mod ule (SIM)
7.7.2 Stop Mod e
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (OSCOUT and 2OSCOUT) in
stop mode, stopping the CPU and peripherals. Stop recovery time is
selectable using the SSREC bit in the configuration register (CONFIG).
If SSREC is set, stop recovery is reduced from the normal delay of 4096
2OSCOUT cycles down to 32. This is ideal for applications using canned
oscillators that do not require long start-up times from stop mode.
NOTE: External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the break status register (BSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 7-18 shows stop mode entry timing.
NOTE: To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
CPUSTOP
IAB
IDB
R/W
STOP ADDR
STOP ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 7-18. Stop Mode Entry Timing
Technical Data
MC68H(R)C08JL3 — Rev. 4
84
System Integration Module (SIM)
MOTOROLA
System Integration Module (SIM)
SIM Registers
STOP RECOVERY PERIOD
2OSCOUT
INT/BREAK
IAB
STOP + 2
STOP + 2
SP
SP – 1
SP – 2
SP – 3
STOP +1
Figure 7-19. Stop Mode Recovery from Interrupt or Break
7.8 SIM Re g iste rs
The SIM has three memory mapped registers. Table 7-4 shows the
mapping of these registers.
Table 7-4. SIM Registers
Address
$FE00
$FE01
$FE03
Register
BSR
Access Mode
User
RSR
User
BFCR
User
7.8.1 Bre a k Sta tus Re g iste r (BSR)
The break status register contains a flag to indicate that a break caused
an exit from stop or wait mode.
Address:
$FE00
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
SBSW
R
R
R
R
R
R
(1)
Note
0
R
= Reserved
1. Writing a logic zero clears SBSW.
Figure 7-20. Break Status Register (BSR)
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
System Integration Module (SIM)
85
Syste m Inte g ra tion Mod ule (SIM)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic zero to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this. Writing zero to the SBSW bit clears
it.
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the
; break service routine software.
HIBYTE EQU
LOBYTE EQU
5
6
;
If not SBSW, do RTI
BRCLR SBSW,BSR, RETURN ; See if wait mode or stop mode was exited
; by break.
TST
BNE
DEC
DEC
LOBYTE,SP
DOLO
; If RETURNLO is not zero,
; then just decrement low byte.
; Else deal with high byte, too.
; Point to WAIT/STOP opcode.
; Restore H register.
HIBYTE,SP
LOBYTE,SP
DOLO
RETURN PULH
RTI
7.8.2 Re se t Sta tus Re g iste r (RSR)
This register contains six flags that show the source of the last reset.
Clear the SIM reset status register by reading it. A power-on reset sets
the POR bit and clears all other bits in the register.
Technical Data
MC68H(R)C08JL3 — Rev. 4
86
System Integration Module (SIM)
MOTOROLA
System Integration Module (SIM)
SIM Registers
Address:
$FE01
Bit 7
6
5
4
3
2
1
Bit 0
0
Read:
Write:
POR:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
1
0
0
0
0
0
0
0
= Unimplemented
Figure 7-21. Reset Status Register (RSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MODRST — Monitor Mode Entry Module Reset bit
1 = Last reset caused by monitor mode entry when vector locations
$FFFE and $FFFF are $00 after POR while IRQB = V
0 = POR or read of SRSR
DD
LVI — Low Voltage Inhibit Reset bit
1 = Last reset caused by LVI circuit
0 = POR or read of SRSR
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
System Integration Module (SIM)
87
Syste m Inte g ra tion Mod ule (SIM)
7.8.3 Bre a k Fla g Control Re g iste r (BFCR)
The break control register contains a bit that enables software to clear
status bits while the MCU is in a break state.
Address:
Bit 7
$FE03
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
R
= Reserved
Figure 7-22. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
Technical Data
MC68H(R)C08JL3 — Rev. 4
88
System Integration Module (SIM)
MOTOROLA
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 8. Osc illa tor (OSC)
8.1 Conte nts
8.2
8.3
8.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
X-tal Oscillator (MC68HC08xxx). . . . . . . . . . . . . . . . . . . . . . . .90
RC Oscillator (MC68HRC08xxx) . . . . . . . . . . . . . . . . . . . . . . .91
8.5
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . .92
Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK). . . . . . .92
Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . .92
X-tal Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . .92
RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . .93
Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . .93
Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.6
8.6.1
8.6.2
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.7
Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . .94
8.2 Introd uc tion
The oscillator module provides the reference clock for the MCU system
and bus. Two types of oscillator modules are available:
• MC68HC08xxx— built-in oscillator module (X-tal oscillator) that
requires an external crystal or ceramic-resonator. This option also
allows an external clock that can be driven directly into OSC1.
• MC68HRC08xxx — built-in oscillator module (RC oscillator) that
requires an external RC connection only.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Oscillator (OSC)
89
Osc illa tor (OSC)
8.3 X-ta l Osc illa tor (MC68HC08xxx)
The X-tal oscillator circuit is designed for use with an external crystal or
ceramic resonator to provide accurate clock source.
In its typical configuration, the X-tal oscillator is connected in a Pierce
oscillator configuration, as shown in Figure 8-1. This figure shows only
the logical representation of the internal components and may not
represent actual circuitry. The oscillator configuration uses five
components:
• Crystal, X
1
• Fixed capacitor, C
1
• Tuning capacitor, C (can also be a fixed capacitor)
2
• Feedback resistor, RB
• Series resistor, RS (optional)
From SIM
To SIM
2OSCOUT
To SIM
OSCOUT
XTALCLK
÷ 2
SIMOSCEN
MCU
OSC1
OSC2
RS*
R
B
*RS can be zero (shorted) when used with higher-frequency crystals.
Refer to manufacturer’s data.
X
1
See Section 18. for component value requirements.
C
C
2
1
Figure 8-1. X-tal Oscillator External Connections
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
90
Oscillator (OSC)
Oscillator (OSC)
RC Oscillator (MC68HRC08xxx)
The series resistor (RS) is included in the diagram to follow strict Pierce
oscillator guidelines and may not be required for all ranges of operation,
especially with high frequency crystals. Refer to the crystal
manufacturer’s data for more information.
8.4 RC Osc illa tor (MC68HRC08xxx)
The RC oscillator circuit is designed for use with external R and C to
provide a clock source with tolerance less than 10%.
In its typical configuration, the RC oscillator requires two external
components, one R and one C. Component values should have a
tolerance of 1% or less, to obtain a clock source with less than 10%
tolerance. The oscillator configuration uses two components:
• C
• R
EXT
EXT
From SIM
To SIM
2OSCOUT
To SIM
OSCOUT
SIMOSCEN
Ext-RC
Oscillator
RCCLK
EN
÷ 2
0
1
PTA6
I/O
PTA6
PTA6EN
MCU
OSC1
PTA6/RCCLK (OSC2)
V
DD
See Section 18. for component value requirements.
R
C
EXT
EXT
Figure 8-2. RC Oscillator External Connections
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Oscillator (OSC)
91
Osc illa tor (OSC)
8.5 I/ O Sig na ls
The following paragraphs describe the oscillator I/O signals.
8.5.1 Crysta l Am p lifie r Inp ut Pin (OSC1)
OSC1 pin is an input to the crystal oscillator amplifier or the input to the
RC oscillator circuit.
8.5.2 Crysta l Am p lifie r Outp ut Pin (OSC2/ PTA6/ RCCLK)
For the X-tal oscillator device, OSC2 pin is the output of the crystal
oscillator inverting amplifier.
For the RC oscillator device, OSC2 pin can be configured as a general
purpose I/O pin PTA6, or the output of the internal RC oscillator clock,
RCCLK.
Option
OSC2 pin function
X-tal oscillator
Inverting OSC1
Controlled by PTAEN bit in PTAPUER ($0D)
PTA6EN = 0: RCCLK output
RC oscillator
PTA6EN = 1: PTA6 I/O
8.5.3 Osc illa tor Ena b le Sig na l (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM)
and enables/disables the X-tal oscillator circuit or the RC-oscillator.
8.5.4 X-ta l Osc illa tor Cloc k (XTALCLK)
XTALCLK is the X-tal oscillator output signal. It runs at the full speed of
the crystal (f ) and comes directly from the crystal oscillator circuit.
XCLK
Figure 8-1 shows only the logical relation of XTALCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
XTALCLK is unknown and may depend on the crystal and other external
factors. Also, the frequency and amplitude of XTALCLK can be unstable
at start-up.
Technical Data
MC68H(R)C08JL3 — Rev. 4
92
Oscillator (OSC)
MOTOROLA
Oscillator (OSC)
Low Power Modes
8.5.5 RC Osc illa tor Cloc k (RCCLK)
RCCLK is the RC oscillator output signal. Its frequency is directly
proportional to the time constant of the external R and C. Figure 8-2
shows only the logical relation of RCCLK to OSC1 and may not
represent the actual circuitry.
8.5.6 Osc illa tor Out 2 (2OSCOUT)
2OSCOUT is same as the input clock (XTALCLK or RCCLK). This signal
is driven to the SIM module and is used to determine the COP cycles.
8.5.7 Osc illa tor Out (OSCOUT)
The frequency of this signal is equal to half of the 2OSCOUT, this signal
is driven to the SIM for generation of the bus clocks used by the CPU
and other modules on the MCU. OSCOUT will be divided again in the
SIM and results in the internal bus frequency being one fourth of the
XTALCLK or RCCLK frequency.
8.6 Low Powe r Mod e s
The WAIT and STOP instructions put the MCU in low-power
consumption standby modes.
8.6.1 Wa it Mod e
8.6.2 Stop Mod e
The WAIT instruction has no effect on the oscillator logic. OSCOUT and
2OSCOUT continues to drive to the SIM module.
The STOP instruction disables the XTALCLK or the RCCLK output,
hence OSCOUT and 2OSCOUT.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Oscillator (OSC)
93
Osc illa tor (OSC)
8.7 Osc illa tor During Bre a k Mod e
The oscillator continues to drive OSCOUT and 2OSCOUT when the
device enters the break state.
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
94
Oscillator (OSC)
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 9. Monitor ROM (MON)
9.1 Conte nts
9.2
9.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
9.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.2 Introd uc tion
This section describes the monitor ROM (MON). The monitor ROM
allows complete testing of the MCU through a single-wire interface with
a host computer.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Monitor ROM (MON)
95
Monitor ROM (MON)
9.3 Fe a ture s
Features of the monitor ROM include the following:
• Normal user-mode pin functionality
• One pin dedicated to serial communication between monitor ROM
and host computer
• Standard mark/space non-return-to-zero (NRZ) communication
with host computer
• 4800 Baud to 28.8 k-Baud communication with host computer
• Execution of code in RAM or ROM
9.4 Func tiona l De sc rip tion
The monitor ROM receives and executes commands from a host
computer. Figure 9-1 shows a example circuit used to enter monitor
mode and communicate with a host computer via a standard RS-232
interface.
While simple monitor commands can access any memory address, the
MCU has a ROM security feature that requires proper procedures to be
followed before the ROM can be accessed. Access to the ROM is denied
to unauthorized users of customer-specified software.
In monitor mode, the MCU can execute host-computer code in RAM
while all MCU pins except PTB0 retain normal operating mode functions.
All communication between the host computer and the MCU is through
the PTB0 pin. A level-shifting and multiplexing interface is required
between PTB0 and the host computer. PTB0 is used in a wired-OR
configuration and requires a pull-up resistor.
Technical Data
MC68H(R)C08JL3 — Rev. 4
96
Monitor ROM (MON)
MOTOROLA
Monitor ROM (MON)
Functional Description
RST
0.1 µF
VDD + V
HI
(SEE NOTE 2)
H(R)C08JL3
H(R)C08JK3
H(R)C08JK1
10k Ω
IRQ1
V
DD
VDD
V
V
DD
SS
9.8304 MHz
0.1 µF
(SEE NOTE 3)
9.8304MHz
C
1
20
MC145407
OSC1
OSC2
+
+
+
+
10 µF
10 µF
10 µF
10 µF
D
C
SW2
3
4
18
17
20 pF
D
VDD
VDD
20 pF
2
19
10 kΩ
X-TAL CIRCUIT
SW1
A
DB-25
2
5
6
16
15
PTB3
(SEE NOTE 1)
B
3
7
10 kΩ
VDD
14
VDD
1
MC74HC125
2
6
4
3
5
10 kΩ
PTB0
VDD
10 kΩ
7
PTB1
PTB2
10 kΩ
NOTES:
1. SW1: Position A — Bus clock = OSC1 clock ÷ 4
SW1: Position B — Bus clock = OSC1 clock ÷ 2
2. See Table 18-4 for IRQ1 voltage level requirements.
3. SW2: Position C— External oscillator clock input
SW2: Position D— Crystal oscillator clock input
External oscillator must have a 50% duty cycle
Figure 9-1. Monitor Mode Circuit
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Monitor ROM (MON)
97
Monitor ROM (MON)
9.4.1 Ente ring Monitor Mod e
Table 9-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a POR and will
allow communication at 9600 baud provided one of the following sets of
conditions is met:
1. If IRQ1 = V + V :
DD
HI
– OSC1 is 4.9125MHz
– PTB3 = low
2. If IRQ1 = V + V :
DD
HI
– OSC1 is 9.8304MHz
– PTB3 = high
Table 9-1. Monitor Mode Entry Requirements and Options
Clock Source
Bus
and
Comments
Frequency
Frequency
OSC1 at
4.9152MHz
Bypasses RC oscillator (in
HRC08xxx); OSC1 input
must be x-tal oscillator or
external oscillator clock.
9600 baud communication
on PTB0. COP disabled.
VDD + VHI
VDD + VHI
0
1
0
0
1
1
1
1
2.4576MHz
OSC1 at
9.8304MHz
2.4576MHz
X-tal or RC
oscillator at
XTALCLK ÷ 4
or
V
X
X
X
X
Enters User mode
DD
desired frequency
RCCLK ÷ 4
Notes:
1. PTB3 = 0: Bypasses the divide-by-two prescaler to SIM.
The OSC1 clock must be 50% duty cycle for this condition.
2. XTALCLK is the X-tal oscillator output, for MC68HC08xxx. See Figure 8-1.
4. RCCLK is the RC oscillator output, for MC68HRC08xxx. See Figure 8-2.
5. See Table 18-4 for V + V voltage level requirements.
DD
HI
If V +V is applied to IRQ1 and PTB3 is low upon monitor mode entry
DD
HI
(Table 9-1 condition set 1), the bus frequency is a divide-by-two of the
clock input to OSC1. If PTB3 is high with V +V applied to IRQ1 upon
DD
HI
monitor mode entry (Table 9-1 condition set 2), the bus frequency is a
divide-by-four of the clock input to OSC1. Holding the PTB3 pin low
when entering monitor mode causes a bypass of a divide-by-two stage
at the internal clock circuit. In this event, the OSCOUT frequency is
Technical Data
MC68H(R)C08JL3 — Rev. 4
98
Monitor ROM (MON)
MOTOROLA
Monitor ROM (MON)
Functional Description
equal to the 2OSCOUT frequency, and OSC1 input directly generates
internal bus clocks. In this case, the OSC1 signal must have a 50% duty
cycle at maximum bus frequency.
In monitor mode, the COP is disabled as long as V + V is applied to
DD
HI
either the IRQ1 or the RST pin. (See Section 7. System Integration
Module (SIM) for more information on modes of operation.)
Enter monitor mode with the pin configuration shown above by pulling
RST low and then high. The rising edge of RST latches monitor mode.
Once monitor mode is latched, the values on the specified pins can
change.
Once out of reset, the MCU sends a break signal (10 consecutive logic
zeros) to the host computer, indicating that it is ready to receive a
command. The break signal also provides a timing reference to allow the
host to determine the necessary baud rate.
In monitor mode, the MCU uses different vectors for reset, SWI, and
break interrupt. The alternate vectors are in the $FE page instead of the
$FF page and allow code execution from the internal monitor firmware
instead of user code.
Table 9-2 is a summary of the vector differences between user mode
and monitor mode.
Table 9-2. Monitor Mode Vector Differences
Functions
Reset
Vector Vector Vector Vector Vector Vector
High Low High Low High Low
Reset
Break
Break
SWI
SWI
Modes
COP
User
Enabled
$FFFE $FFFF $FFFC $FFFD $FFFC $FFFD
$FEFE $FEFF $FEFC $FEFD $FEFC $FEFD
(1)
Monitor Disabled
Notes:
1. If the high voltage (V + V ) is removed from the IRQ1 pin or the RST pin, the SIM
DD
HI
asserts its COP enable output. The COP is a mask option enabled or disabled by the
COPD bit in the configuration register.
When the host computer has completed downloading code into the MCU
RAM, the host then sends a RUN command, which executes an RTI,
which sends control to the address on the stack pointer.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Monitor ROM (MON)
99
Monitor ROM (MON)
9.4.2 Ba ud Ra te
The communication baud rate is dependant on oscillator frequency and
the state of PTB3 upon monitor mode entry. When PTB3 is high, the
divide by ratio is 1024. If the PTB3 pin is at logic zero upon entry into
monitor mode, the divide by ratio is 512.
Table 9-3. Monitor Baud Rate Selection
Oscillator Input Frequency
4.9152 MHz
PTB3
Baud Rate
9600 bps
9600 bps
4800 bps
0
1
1
9.8304 MHz
4.9152 MHz
9.4.3 Da ta Form a t
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. (See Figure 9-2 and Figure 9-3.)
NEXT
START
BIT
START
BIT
STOP
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Figure 9-2. Monitor Data Format
NEXT
START
BIT
START
STOP
$A5
BIT 0
BIT 0
BIT 1
BIT 1
BIT 2
BIT 2
BIT 3
BIT 3
BIT 4
BIT 4
BIT 5
BIT 5
BIT 6
BIT 6
BIT 7
BIT 7
BIT
BIT
STOP
BIT
START
BIT
NEXT
START
BIT
BREAK
Figure 9-3. Sample Monitor Waveforms
The data transmit and receive rate can be anywhere from 4800 baud to
28.8k-baud. Transmit and receive baud rates must be identical.
9.4.4 Ec hoing
As shown in Figure 9-4, the monitor ROM immediately echoes each
received byte back to the PTB0 pin for error checking.
Technical Data
MC68H(R)C08JL3 — Rev. 4
100
Monitor ROM (MON)
MOTOROLA
Monitor ROM (MON)
Functional Description
SENT TO
MONITOR
READ
READ
ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW
DATA
ECHO
RESULT
Figure 9-4. Read Transaction
Any result of a command appears after the echo of the last byte of the
command.
9.4.5 Bre a k Sig na l
A start bit followed by nine low bits is a break signal. (See Figure 9-5.)
When the monitor receives a break signal, it drives the PTB0 pin high for
the duration of two bits before echoing the break signal.
MISSING STOP BIT
TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 9-5. Break Transaction
9.4.6 Com m a nd s
The monitor ROM uses the following commands:
• READ (read memory)
• WRITE (write memory)
• IREAD (indexed read)
• IWRITE (indexed write)
• READSP (read stack pointer)
• RUN (run user program)
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Monitor ROM (MON)
101
Monitor ROM (MON)
Table 9-4. READ (Read Memory) Command
Description
Read byte from memory
Operand
Specifies 2-byte address in high byte:low byte order
Returns contents of specified address
$4A
Data Returned
Opcode
Command Sequence
SENT TO
MONITOR
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
ECHO
RESULT
Table 9-5. WRITE (Write Memory) Command
Description
Write byte to memory
Operand
Specifies 2-byte address in high byte:low byte order; low byte followed by data byte
Data Returned
Opcode
None
$49
Command Sequence
SENT TO
MONITOR
WRITE
WRITE
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
DATA
ECHO
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
102
Monitor ROM (MON)
Monitor ROM (MON)
Functional Description
Table 9-6. IREAD (Indexed Read) Command
Description
Read next 2 bytes in memory from last address accessed
Specifies 2-byte address in high byte:low byte order
Returns contents of next two addresses
$1A
Operand
Data Returned
Opcode
Command Sequence
SENT TO
MONITOR
IREAD
IREAD
DATA
DATA
RESULT
ECHO
Table 9-7. IWRITE (Indexed Write) Command
Description
Write to last address accessed + 1
Operand
Specifies single data byte
Data Returned
Opcode
None
$19
Command Sequence
SENT TO
MONITOR
IWRITE
IWRITE
DATA
DATA
ECHO
NOTE: A sequence of IREAD or IWRITE commands can sequentially access a
block of memory over the full 64-Kbyte memory map.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Monitor ROM (MON)
103
Monitor ROM (MON)
Table 9-8. READSP (Read Stack Pointer) Command
Description
Reads stack pointer
Operand
None
Data Returned
Opcode
Returns stack pointer in high byte:low byte order
$0C
Command Sequence
SENT TO
MONITOR
READSP
READSP
SP HIGH
SP LOW
RESULT
ECHO
Table 9-9. RUN (Run User Program) Command
Description
Executes RTI instruction
Operand
None
None
$28
Data Returned
Opcode
Command Sequence
SENT TO
MONITOR
RUN
RUN
ECHO
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
104
Monitor ROM (MON)
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 10. Tim e r Inte rfa c e Mod ule (TIM)
10.1 Conte nts
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
10.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
10.5.3.1
10.5.3.2
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .110
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .110
10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .111
10.5.4.1
10.5.4.2
10.5.4.3
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .112
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .113
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
10.7 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
10.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
10.10.1 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . .117
10.10.2 TIM Counter Registers (TCNTH:TCNTL). . . . . . . . . . . . . .119
10.10.3 TIM Counter Modulo Registers (TMODH:TMODL) . . . . . .120
10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1).121
10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . .125
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Timer Interface Module (TIM)
105
Tim e r Inte rfa c e Mod ule (TIM)
10.2 Introd uc tion
This section describes the timer interface module (TIM2, Version B). The
TIM is a two-channel timer that provides a timing reference with input
capture, output compare, and pulse-width-modulation functions.
Figure 10-1 is a block diagram of the TIM.
10.3 Fe a ture s
Features of the TIM include the following:
• Two input capture/output compare channels
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
• Buffered and unbuffered pulse width modulation (PWM) signal
generation
• Programmable TIM clock input with 7-frequency internal bus clock
prescaler selection
• Free-running or modulo up-count operation
• Toggle any channel pin on overflow
• TIM counter stop and reset bits
• Modular architecture expandable to eight channels
10.4 Pin Na m e Conve ntions
The TIM share two I/O pins with two port D I/O pins. The full name of the
TIM I/O pins are listed in Table 10-1. The generic pin name appear in the
text that follows.
Table 10-1. Pin Name Conventions
TIM Generic Pin Names:
Full TIM Pin Names:
TCH0
TCH1
PTD4/TCH0
PTD5/TCH1
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
106
Timer Interface Module (TIM)
Timer Interface Module (TIM)
Functional Description
10.5 Func tiona l De sc rip tion
Figure 10-1 shows the structure of the TIM. The central component of
the TIM is the 16-bit TIM counter that can operate as a free-running
counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM
counter modulo registers, TMODH:TMODL, control the modulo value of
the TIM counter. Software can read the TIM counter value at any time
without affecting the counting sequence.
The two TIM channels are programmable independently as input
capture or output compare channels.
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
TRST
PS2
PS1
PS0
16-BIT COUNTER
TOF
INTERRUPT
LOGIC
TOIE
16-BIT COMPARATOR
TMODH:TMODL
TOV0
ELS0B
ELS0A
PORT
LOGIC
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
CH0MAX
TCH0
CH0F
INTERRUPT
LOGIC
16-BIT LATCH
MS0A
CH0IE
MS0B
CH1F
TOV1
ELS1B
ELS1A
PORT
LOGIC
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
CH1MAX
TCH1
INTERRUPT
LOGIC
16-BIT LATCH
MS1A
CH1IE
Figure 10-1. TIM Block Diagram
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Timer Interface Module (TIM)
107
Tim e r Inte rfa c e Mod ule (TIM)
Addr.
Register Name
Bit 7
TOF
0
6
5
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
TIM Status and Control
Register
TOIE
TSTOP
PS2
PS1
PS0
$0020
TRST
0
(TSC)
0
0
1
0
0
0
0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TIM Counter Register High
(TCNTH)
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
0
0
0
0
0
0
0
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TIM Counter Register Low
(TCNTL)
0
Bit15
1
0
Bit14
1
0
Bit13
1
0
Bit12
1
0
Bit11
1
0
Bit10
1
0
Bit9
1
0
Bit8
1
TIM Counter Modulo
Register High
(TMODH)
TIM Counter Modulo
Register Low
(TMODL)
Bit7
1
Bit6
1
Bit5
1
Bit4
1
Bit3
1
Bit2
1
Bit1
1
Bit0
1
Read: CH0F
TIM Channel 0 Status and
Control Register
(TSC0)
CH0MAX
0
CH0IE
0
MS0B
0
MS0A
0
ELS0B
0
ELS0A
0
TOV0
0
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
TIM Channel 0
Register High
(TCH0H)
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Indeterminate after reset
TIM Channel 0
Register Low
(TCH0L)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Indeterminate after reset
Read: CH1F
0
0
TIM Channel 1 Status and
Control Register
(TSC1)
CH1MAX
0
CH1IE
0
MS1A
0
ELS1B
0
ELS1A
0
TOV1
0
Write:
0
0
Reset:
Figure 10-2. TIM I/O Register Summary
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
108
Timer Interface Module (TIM)
Timer Interface Module (TIM)
Functional Description
Read:
Write:
Reset:
Read:
Write:
Reset:
TIM Channel 1
Register High
(TCH1H)
Bit15
Bit7
Bit14
Bit6
Bit13
Bit5
Bit12
Bit11
Bit10
Bit2
Bit9
Bit1
Bit8
Bit0
$0029
$002A
Indeterminate after reset
TIM Channel 1
Register Low
(TCH1L)
Bit4
Bit3
Indeterminate after reset
= Unimplemented
Figure 10-2. TIM I/O Register Summary
10.5.1 TIM Counte r Pre sc a le r
The TIM clock source is one of the seven prescaler outputs. The
prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIM status and control register
(TSC) select the TIM clock source.
10.5.2 Inp ut Ca p ture
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM CPU interrupt
requests.
10.5.3 Outp ut Com p a re
With the output compare function, the TIM can generate a periodic pulse
with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIM can set, clear, or toggle the channel pin. Output compares can
generate TIM CPU interrupt requests.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Timer Interface Module (TIM)
109
Tim e r Inte rfa c e Mod ule (TIM)
10.5.3.1 Unb uffe re d Outp ut Co m p a re
Any output compare channel can generate unbuffered output compare
pulses as described in 10.5.3 Output Compare. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass
the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
• When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
• When changing to a larger output compare value, enable
channel x TIM overflow interrupts and write the new value in the
TIM overflow interrupt routine. The TIM overflow interrupt occurs
at the end of the current counter overflow period. Writing a larger
value in an output compare interrupt routine (at the end of the
current pulse) could cause two output compares to occur in the
same counter overflow period.
10.5.3.2 Buffe re d Outp ut Co m p a re
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the TCH0 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The output compare value in the TIM
Technical Data
MC68H(R)C08JL3 — Rev. 4
110
Timer Interface Module (TIM)
MOTOROLA
Timer Interface Module (TIM)
Functional Description
channel 0 registers initially controls the output on the TCH0 pin. Writing
to the TIM channel 1 registers enables the TIM channel 1 registers to
synchronously control the output after the TIM overflows. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
output are the ones written to last. TSC0 controls and monitors the
buffered output compare function, and TIM channel 1 status and control
register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.
NOTE: In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output
compares.
10.5.4 Pulse Wid th Mod ula tion (PWM)
By using the toggle-on-overflow feature with an output compare channel,
the TIM can generate a PWM signal. The value in the TIM counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIM counter
modulo registers. The time between overflows is the period of the PWM
signal.
As Figure 10-3 shows, the output compare value in the TIM channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIM to clear the channel pin on output compare if the state of the PWM
pulse is logic one. Program the TIM to set the pin if the state of the PWM
pulse is logic zero.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Timer Interface Module (TIM)
111
Tim e r Inte rfa c e Mod ule (TIM)
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 10-3. PWM Period and Pulse Width
The value in the TIM counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is 000 (see 10.10.1 TIM Status and Control Register (TSC)).
The value in the TIM channel registers determines the pulse width of the
PWM output. The pulse width of an 8-bit PWM signal is variable in 256
increments. Writing $0080 (128) to the TIM channel registers produces
a duty cycle of 128/256 or 50%.
10.5.4.1 Unb uffe re d PWM Sig na l Ge ne ra tio n
Any output compare channel can generate unbuffered PWM pulses as
described in 10.5.4 Pulse Width Modulation (PWM). The pulses are
unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel
registers.
An unsynchronized write to the TIM channel registers to change a pulse
width value could cause incorrect operation for up to two PWM periods.
For example, writing a new value before the counter reaches the old
value but after the counter reaches the new value prevents any compare
during that PWM period. Also, using a TIM overflow interrupt routine to
Technical Data
MC68H(R)C08JL3 — Rev. 4
112
Timer Interface Module (TIM)
MOTOROLA
Timer Interface Module (TIM)
Functional Description
write a new, smaller pulse width value may cause the compare to be
missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
• When changing to a longer pulse width, enable channel x TIM
overflow interrupts and write the new value in the TIM overflow
interrupt routine. The TIM overflow interrupt occurs at the end of
the current PWM period. Writing a larger value in an output
compare interrupt routine (at the end of the current pulse) could
cause two output compares to occur in the same PWM period.
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
10.5.4.2 Buffe re d PWM Sig na l Ge ne ra tio n
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the TCH0 pin. The TIM channel registers of the linked
pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The TIM channel 0 registers initially
control the pulse width on the TCH0 pin. Writing to the TIM channel 1
registers enables the TIM channel 1 registers to synchronously control
the pulse width at the beginning of the next PWM period. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the
buffered PWM function, and TIM channel 1 status and control register
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Timer Interface Module (TIM)
113
Tim e r Inte rfa c e Mod ule (TIM)
(TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1,
is available as a general-purpose I/O pin.
NOTE: In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
10.5.4.3 PWM Initia liza tio n
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter by setting the TIM reset bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the
value for the required PWM period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for
the required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the mode
select bits, MSxB:MSxA. (See Table 10-3.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See Table 10-3.)
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit,
TSTOP.
Technical Data
MC68H(R)C08JL3 — Rev. 4
114
Timer Interface Module (TIM)
MOTOROLA
Timer Interface Module (TIM)
Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels. MS0B
takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. (See 10.10.4 TIM
Channel Status and Control Registers (TSC0:TSC1).)
10.6 Inte rrup ts
The following TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter value rolls over to $0000 after matching the value in the
TIM counter modulo registers. The TIM overflow interrupt enable
bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and
TOIE are in the TIM status and control register.
• TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests
are enabled when CHxIE=1. CHxF and CHxIE are in the TIM
channel x status and control register.
10.7 Wa it Mod e
The WAIT instruction puts the MCU in low-power-consumption standby
mode.
The TIM remains active after the execution of a WAIT instruction. In wait
mode the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Timer Interface Module (TIM)
115
Tim e r Inte rfa c e Mod ule (TIM)
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
10.8 TIM During Bre a k Inte rrup ts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the break flag control register (BFCR) enables software to clear status
bits during the break state. (See 7.8.3 Break Flag Control Register
(BFCR).)
To allow software to clear status bits during a break interrupt, write a
logic one to the BCFE bit. If a status bit is cleared during the break state,
it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic zero to the
BCFE bit. With BCFE at logic zero (its default state), software can read
and write I/O registers during the break state without affecting status
bits. Some status bits have a two-step read/write clearing procedure. If
software does the first step on such a bit before the break, the bit cannot
change during the break state as long as BCFE is at logic zero. After the
break, doing the second step clears the status bit.
10.9 I/ O Sig na ls
Port D shares two of its pins with the TIM. The two TIM channel I/O pins
are PTD4/TCH0 and PTD5/TCH1.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTD4/TCH0 can be configured as
a buffered output compare or buffered PWM pin.
Technical Data
MC68H(R)C08JL3 — Rev. 4
116
Timer Interface Module (TIM)
MOTOROLA
Timer Interface Module (TIM)
I/O Registers
10.10 I/ O Re g iste rs
The following I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM control registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0 and TSC1)
• TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
10.10.1 TIM Sta tus a nd Control Re g iste r (TSC)
The TIM status and control register does the following:
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
Address:
$0020
Bit 7
TOF
0
6
TOIE
0
5
TSTOP
1
4
0
3
0
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
Write:
Reset:
TRST
0
0
0
= Unimplemented
Figure 10-4. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter resets to $0000 after
reaching the modulo value programmed in the TIM counter modulo
registers. Clear TOF by reading the TIM status and control register
when TOF is set and then writing a logic zero to TOF. If another TIM
MC68H(R)C08JL3 — Rev. 4
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Technical Data
Timer Interface Module (TIM)
117
Tim e r Inte rfa c e Mod ule (TIM)
overflow occurs before the clearing sequence is complete, then
writing logic zero to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset
clears the TOF bit. Writing a logic one to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM
counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIM counter is reset and always reads as logic zero. Reset clears
the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIM counter
at a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the
input to the TIM counter as Table 10-2 shows. Reset clears the
PS[2:0] bits.
Technical Data
MC68H(R)C08JL3 — Rev. 4
118
Timer Interface Module (TIM)
MOTOROLA
Timer Interface Module (TIM)
I/O Registers
Table 10-2. Prescaler Selection
PS2
0
PS1
0
PS0
0
TIM Clock Source
Internal Bus Clock ÷ 1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
Not available
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
10.10.2 TIM Counte r Re g iste rs (TCNTH:TCNTL)
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
MC68H(R)C08JL3 — Rev. 4
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Technical Data
Timer Interface Module (TIM)
119
Tim e r Inte rfa c e Mod ule (TIM)
Address:
$0021
Bit 7
TCNTH
6
5
4
3
2
1
Bit 0
Bit8
Read:
Write:
Reset:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
0
0
0
0
0
0
0
0
Address:
$0022
Bit 7
Bit7
TCNTL
6
5
4
3
2
1
Bit 0
Bit0
Read:
Write:
Reset:
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-5. TIM Counter Registers (TCNTH:TCNTL)
10.10.3 TIM Counte r Mod ulo Re g iste rs (TMODH:TMODL)
The read/write TIM modulo registers contain the modulo value for the
TIM counter. When the TIM counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next clock. Writing to the high byte (TMODH) inhibits
the TOF bit and overflow interrupts until the low byte (TMODL) is written.
Reset sets the TIM counter modulo registers.
Technical Data
MC68H(R)C08JL3 — Rev. 4
120
Timer Interface Module (TIM)
MOTOROLA
Timer Interface Module (TIM)
I/O Registers
Address:
$0023
Bit 7
TMODH
6
5
Bit13
1
4
Bit12
1
3
Bit11
1
2
Bit10
1
1
Bit9
1
Bit 0
Bit8
1
Read:
Write:
Reset:
Bit15
1
Bit14
1
Address:
$0024
Bit 7
TMODL
6
5
Bit5
1
4
Bit4
1
3
Bit3
1
2
Bit2
1
1
Bit1
1
Bit 0
Bit0
1
Read:
Write:
Reset:
Bit7
1
Bit6
1
Figure 10-6. TIM Counter Modulo Registers (TMODH:TMODL)
NOTE: Reset the TIM counter before writing to the TIM counter modulo registers.
10.10.4 TIM Cha nne l Sta tus a nd Control Re g iste rs (TSC0:TSC1)
Each of the TIM channel status and control registers does the following:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input
capture trigger
• Selects output toggling on TIM overflow
• Selects 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Timer Interface Module (TIM)
121
Tim e r Inte rfa c e Mod ule (TIM)
Address:
$0025
Bit 7
CH0F
0
TSC0
6
5
MS0B
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Read:
Write:
Reset:
CH0IE
0
0
Address:
$0028
Bit 7
CH1F
0
TSC1
6
5
0
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Read:
Write:
Reset:
CH1IE
0
0
0
= Unimplemented
Figure 10-7. TIM Channel Status and Control Registers (TSC0:TSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE=1), clear
CHxF by reading the TIM channel x status and control register with
CHxF set and then writing a logic zero to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic zero to CHxF has no effect. Therefore, an interrupt request
cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic one to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on
channel x. Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
Technical Data
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Timer Interface Module (TIM)
MOTOROLA
Timer Interface Module (TIM)
I/O Registers
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM channel 0 status and control register.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation.
See Table 10-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin. (See Table 10-3.) Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE: Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to an I/O port, and pin TCHx is available as a general-purpose I/O
pin. Table 10-3 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
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Technical Data
Timer Interface Module (TIM)
123
Tim e r Inte rfa c e Mod ule (TIM)
Table 10-3. Mode, Edge, and Level Selection
MSxB MSxA ELSxB ELSxA
Mode
Configuration
Pin under Port Control;
Initial Output Level High
X
X
0
1
0
0
0
0
Output
Preset
Pin under Port Control;
Initial Output Level Low
0
0
0
0
0
0
1
1
0
0
0
1
1
1
X
X
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Toggle Output on Compare
Input
Capture
Output
Compare Clear Output on Compare
or PWM
Set Output on Compare
Buffered
Output
Compareor
Buffered
PWM
Toggle Output on Compare
Clear Output on Compare
1
X
1
1
Set Output on Compare
NOTE: Before enabling a TIM channel register for input capture operation, make
sure that the TCHx pin is stable for at least two bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE: When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic zero, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 10-8 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
Technical Data
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124
Timer Interface Module (TIM)
MOTOROLA
Timer Interface Module (TIM)
I/O Registers
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
OUTPUT
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
COMPARE
CHxMAX
Figure 10-8. CHxMAX Latency
10.10.5 TIM Cha nne l Re g iste rs (TCH0H/ L:TCH1H/ L)
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
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Technical Data
Timer Interface Module (TIM)
125
Tim e r Inte rfa c e Mod ule (TIM)
Address:
$0026
Bit 7
TCH0H
6
5
4
3
2
1
Bit 0
Bit8
Read:
Write:
Reset:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Indeterminate after reset
Address:
$0027
Bit 7
TCH0L
6
5
4
3
2
1
Bit 0
Bit0
Read:
Write:
Reset:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Indeterminate after reset
Address:
$0029
Bit 7
TCH1H
6
5
4
3
2
1
Bit 0
Bit8
Read:
Write:
Reset:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Indeterminate after reset
Address:
$02A
Bit 7
TCH1L
6
5
4
3
2
1
Bit 0
Bit0
Read:
Write:
Reset:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Indeterminate after reset
Figure 10-9. TIM Channel Registers (TCH0H/L:TCH1H/L)
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
126
Timer Interface Module (TIM)
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 11. Ana log -to-Dig ita l Conve rte r (ADC)
11.1 Conte nts
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
11.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
11.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
11.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
11.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .130
11.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.7.1 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . .132
11.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
11.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .132
11.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
11.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . .135
11.2 Introd uc tion
This section describes the analog-to-digital converter (ADC). The ADC
is an 8-bit, 12-channels analog-to-digital converter.
MC68H(R)C08JL3 — Rev. 4
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Technical Data
Analog-to-Digital Converter (ADC)
127
Ana log -to-Dig ita l Conve rte r (ADC)
11.3 Fe a ture s
Features of the ADC module include:
• 12 channels with multiplexed input
• Linear successive approximation with monotonicity
• 8-bit resolution
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
• Selectable ADC clock
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: COCO
ADC Status and Control
AIEN
ADCO
CH4
CH3
CH2
CH1
CH0
$003C
Register Write:
(ADSCR)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
0
1
1
1
1
1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
ADC Data Register
(ADR)
$003D
$003E
Indeterminate after reset
0
0
0
0
0
0
0
0
ADIV2
0
ADIV1
0
ADIV0
0
ADC Input Clock Register
(ADICLK)
0
0
Figure 11-1. ADC I/O Register Summary
11.4 Func tiona l De sc rip tion
Twelve ADC channels are available for sampling external sources at
pins PTB0–PTB7 and PTD0–PTD3. An analog multiplexer allows the
single ADC converter to select one of the 12 ADC channels as ADC
voltage input (ADCVIN). ADCVIN is converted by the successive
approximation register-based counters. The ADC resolution is 8 bits.
When the conversion is completed, ADC puts the result in the ADC data
register and sets a flag or generates an interrupt. Figure 11-2 shows a
block diagram of the ADC.
Technical Data
MC68H(R)C08JL3 — Rev. 4
128
Analog-to-Digital Converter (ADC)
MOTOROLA
Analog-to-Digital Converter (ADC)
Functional Description
INTERNAL
DATA BUS
READ DDRB/DDRD
WRITE DDRB/DDRD
DISABLE
DDRBx/DDRDx
PTBx/PTDx
RESET
WRITE PTB/PTD
READ PTB/PTD
ADCx
DISABLE
ADC CHANNEL x
ADC DATA REGISTER
ADC VOLTAGE IN
ADCVIN
CONVERSION
COMPLETE
CHANNEL
SELECT
(1 OF 12 CHANNELS)
INTERRUPT
LOGIC
CH[4:0]
ADC
ADC CLOCK
AIEN
COCO
CLOCK
GENERATOR
BUS CLOCK
ADIV[2:0]
ADICLK
Figure 11-2. ADC Block Diagram
11.4.1 ADC Port I/ O Pins
PTB0–PTB7 and PTD0–PTD3 are general-purpose I/O pins that are
shared with the ADC channels. The channel select bits (ADC Status and
Control register, $003C), define which ADC channel/port pin will be used
as the input signal. The ADC overrides the port I/O logic by forcing that
pin as input to the ADC. The remaining ADC channels/port pins are
controlled by the port I/O logic and can be used as general-purpose I/O.
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Technical Data
Analog-to-Digital Converter (ADC)
129
Ana log -to-Dig ita l Conve rte r (ADC)
Writes to the port register or DDR will not have any affect on the port pin
that is selected by the ADC. Read of a port pin which is in use by the
ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the
DDR bit is at logic 1, the value in the port data latch is read.
11.4.2 Volta g e Conve rsion
When the input voltage to the ADC equals V , the ADC converts the
DD
signal to $FF (full scale). If the input voltage equals V
the ADC
SS,
converts it to $00. Input voltages between V and V are a
DD
SS
straight-line linear conversion. All other input voltages will result in $FF
if greater than V and $00 if less than V .
DD
SS
NOTE: Input voltage should not exceed the analog supply voltages.
11.4.3 Conve rsion Tim e
Sixteen ADC internal clocks are required to perform one conversion. The
ADC starts a conversion on the first rising edge of the ADC internal clock
immediately following a write to the ADSCR. If the ADC internal clock is
selected to run at 1MHz, then one conversion will take 16µs to complete.
With a 1MHz ADC internal clock the maximum sample rate is 62.5kHz.
16 ADC Clock Cycles
Conversion Time =
ADC Clock Frequency
Number of Bus Cycles = Conversion Time × Bus Frequency
11.4.4 Continuous Conve rsion
In the continuous conversion mode, the ADC continuously converts the
selected channel filling the ADC data register with new data after each
conversion. Data from the previous conversion will be overwritten
whether that data has been read or not. Conversions will continue until
the ADCO bit is cleared. The COCO bit (ADC Status & Control register,
$003C) is set after each conversion and can be cleared by writing the
ADC status and control register or reading of the ADC data register.
Technical Data
MC68H(R)C08JL3 — Rev. 4
130
Analog-to-Digital Converter (ADC)
MOTOROLA
Analog-to-Digital Converter (ADC)
Interrupts
11.4.5 Ac c ura c y a nd Pre c ision
The conversion process is monotonic and has no missing codes.
11.5 Inte rrup ts
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. A CPU interrupt is generated
if the COCO bit is at logic 0. The COCO bit is not used as a conversion
complete flag when interrupts are enabled.
11.6 Low-Powe r Mod e s
The following subsections describe the ADC in low-power modes.
11.6.1 Wa it Mod e
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting the CH[4:0] bits in the ADC Status and
Control register to logic 1’s before executing the WAIT instruction.
11.6.2 Stop Mod e
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode. Allow one conversion cycle to stabilize the analog
circuitry before attempting a new ADC conversion after exiting stop
mode.
11.7 I/ O Sig na ls
The ADC module has 12 channels that are shared with I/O port B and
port D.
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Technical Data
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131
Ana log -to-Dig ita l Conve rte r (ADC)
11.7.1 ADC Volta g e In (ADCVIN)
ADCVIN is the input voltage signal from one of the 12 ADC channels to
the ADC module.
11.8 I/ O Re g iste rs
These I/O registers control and monitor ADC operation:
• ADC Status and Control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADICLK)
11.8.1 ADC Sta tus a nd Control Re g iste r
The following paragraphs describe the function of the ADC Status and
Control register.
Address:
$003C
Bit 7
6
AIEN
0
5
ADCO
0
4
CH4
1
3
CH3
1
2
CH2
1
1
CH1
1
Bit 0
CH0
1
Read:
Write:
Reset:
COCO
0
= Unimplemented
Figure 11-3. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed. This bit is cleared whenever
the ADC status and control register is written or whenever the ADC
data register is read. Reset clears this bit.
1 = conversion completed (AIEN = 0)
0 = conversion not completed (AIEN = 0)
When the AIEN bit is a logic 1 (CPU interrupt enabled), the COCO is
a read-only bit, and will always be logic 0 when read.
Technical Data
MC68H(R)C08JL3 — Rev. 4
132
Analog-to-Digital Converter (ADC)
MOTOROLA
Analog-to-Digital Converter (ADC)
I/O Registers
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the
ADR register at the end of each conversion. Only one conversion is
allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH[4:0] — ADC Channel Select Bits
ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field
which is used to select one of the ADC channels. The five channel
select bits are detailed in the following table. Care should be taken
when using a port pin as both an analog and a digital input
simultaneously to prevent switching noise from corrupting the analog
signal. (See Table 11-1.)
The ADC subsystem is turned off when the channel select bits are all
set to one. This feature allows for reduced power consumption for the
MCU when the ADC is not used. Reset sets all of these bits to a
logic 1.
NOTE: Recovery from the disabled state requires one conversion cycle to
stabilize.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Analog-to-Digital Converter (ADC)
133
Ana log -to-Dig ita l Conve rte r (ADC)
Table 11-1. MUX Channel Select
CH4
CH3
CH2
CH1
CH0
ADC Channel
Input Select
0
0
0
0
0
0
0
0
0
1
1
1
1
1
:
0
0
0
0
1
1
1
1
0
0
0
0
1
:
0
0
1
1
0
0
1
1
0
0
1
1
0
:
0
1
0
1
0
1
0
1
0
1
0
1
0
:
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
ADC11
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
PTD3
PTD2
PTD1
PTD0
0
0
0
0
0
0
0
0
0
0
0
0
Unused
(see Note 1)
:
—
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
—
—
Reserved
Unused
1
1
V
V
(see Note 2)
(see Note 2)
DDA
SSA
1
1
ADC power off
NOTES:
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the
operation of the ADC converter both in production test and for user applications.
11.8.2 ADC Da ta Re g iste r
One 8-bit result register is provided. This register is updated each time
an ADC conversion completes.
Technical Data
MC68H(R)C08JL3 — Rev. 4
134
Analog-to-Digital Converter (ADC)
MOTOROLA
Analog-to-Digital Converter (ADC)
I/O Registers
Address:
$003D
Bit 7
6
5
4
3
2
1
Bit 0
AD0
Read:
Write:
Reset:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
Indeterminate after reset
= Unimplemented
Figure 11-4. ADC Data Register (ADR)
11.8.3 ADC Inp ut Cloc k Re g iste r
This register selects the clock frequency for the ADC.
Address:
$003E
Bit 7
6
ADIV1
0
5
ADIV0
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
ADIV2
0
0
0
0
0
0
= Unimplemented
Figure 11-5. ADC Input Clock Register (ADICLK)
ADIV2:ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock. Table 11-2
shows the available clock configurations. The ADC clock should be
set to approximately 1MHz.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Analog-to-Digital Converter (ADC)
135
Ana log -to-Dig ita l Conve rte r (ADC)
Table 11-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
ADC Input Clock ÷ 1
ADC Input Clock ÷ 2
ADC Input Clock ÷ 4
ADC Input Clock ÷ 8
ADC Input Clock ÷ 16
0
0
0
1
1
X
0
1
0
1
X
0
0
0
1
X = don’t care
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
136
Analog-to-Digital Converter (ADC)
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 12. I/ O Ports
12.1 Conte nts
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
12.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . .139
12.3.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . .140
12.3.3 Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . .141
12.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
12.4.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . .143
12.4.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . .143
12.5 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
12.5.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . .145
12.5.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . .146
12.5.3 Port D Control Register (PDCR). . . . . . . . . . . . . . . . . . . . .147
12.2 Introd uc tion
Twenty three bidirectional input-output (I/O) pins form three parallel
ports. All I/O pins are programmable as inputs or outputs.
NOTE: Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
I/O Ports
137
I/ O Ports
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
0
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Port A Data Register
(PTA)
$0000
Unaffected by reset
PTB4 PTB3
Unaffected by reset
PTD4 PTD3
Unaffected by reset
PTB7
PTB6
PTD6
PTB5
PTD5
PTB2
PTD2
PTB1
PTD1
PTB0
PTD0
Port B Data Register
(PTB)
$0001
$0003
$0004
$0005
$0007
$000A
$000D
PTD7
0
Port D Data Register
(PTD)
DDRA6
0
DDRA5
0
DDRA4
0
DDRA3
DDRA2
DDRA1
DDRA0
Data Direction Register A
(DDRA)
0
0
DDRB3
0
0
DDRB2
0
0
DDRB1
0
0
DDRB0
0
DDRB7
0
DDRB6
0
DDRB5
0
DDRB4
0
Data Direction Register B
(DDRB)
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
0
DDRD2
0
DDRD1
0
DDRD0
0
Data Direction Register D
(DDRD)
0
0
0
0
0
0
0
0
SLOWD7 SLOWD6 PTDPU7 PTDPU6
Port D Control Register
(PDCR)
0
0
0
0
0
0
0
0
Port A Input Pull-up
PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Enable Register Write:
(PTAPUE)
Reset:
0
0
0
0
0
0
0
0
Figure 12-1. I/O Port Register Summary
12.3 Port A
Port A is an 7-bit special function port that shares all seven of its pins
with the Keyboard Interrupt (KBI) Module, See Section 14. Each port A
pin also has software configurable pull-up device if the corresponding
port pin is configured as input port. PTA0 to PTA5 has direct LED drive
capability.
Technical Data
MC68H(R)C08JL3 — Rev. 4
138
I/O Ports
MOTOROLA
I/O Ports
Port A
12.3.1 Port A Da ta Re g iste r (PTA)
The port A data register (PTA) contains a data latch for each of the seven
port A pins.
Address:
$0000
Bit 7
0
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Unaffected by Reset
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
Additional Functions:
30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up
Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Figure 12-2. Port A Data Register (PTA)
PTA[6:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
KBI[6:0] — Port A Keyboard Interrupts
The keyboard interrupt enable bits, KBIE6-KBIE0, in the keyboard
interrupt control register (KBAIER) enable the port A pins as external
interrupt pins, (see Section 14. Keyboard Interrupt Module (KBI)).
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
I/O Ports
139
I/ O Ports
12.3.2 Da ta Dire c tion Re g iste r A (DDRA)
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic one to a DDRA bit enables the output buffer
for the corresponding port A pin; a logic zero disables the output buffer.
Address:
$0004
Bit 7
0
6
DDRA6
0
5
DDRA5
0
4
DDRA4
0
3
DDRA3
0
2
DDRA2
0
1
DDRA1
0
Bit 0
DDRA0
0
Read:
Write:
Reset:
0
Figure 12-3. Data Direction Register A (DDRA)
DDRA[6:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[6:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 12-4 shows the port A I/O logic.
Technical Data
MC68H(R)C08JL3 — Rev. 4
140
I/O Ports
MOTOROLA
I/O Ports
Port A
READ DDRA ($0004)
WRITE DDRA ($0004)
PTAPUEx
DDRAx
PTAx
RESET
30k
WRITE PTA ($0000)
READ PTA ($0000)
PTAx
To Keyboard Interrupt Circuit
Figure 12-4. Port A I/O Circuit
When DDRAx is a logic 1, reading address $0000 reads the PTAx data
latch. When DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
12.3.3 Port A Inp ut Pull-up Ena b le Re g iste r (PTAPUE)
The Port A Input Pull-up Enable Register (PTAPUE) contains a software
configurable pull-up device for each if the seven port A pins. Each bit is
individually configurable and requires the corresponding data direction
register, DDRAx be configured as input. Each pull-up device is
automatically and dynamically disabled when its corresponding DDRAx
bit is configured as output.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
I/O Ports
141
I/ O Ports
Address:
$000D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE2 PTAPUE0
0
0
0
0
0
0
0
0
Figure 12-5. Port A Input Pull-up Enable Register (PTAPUE)
PTA6EN — Enable PTA6 on OSC2
This read/write bit configures the OSC2 pin function when RC
oscillator option is selected. This bit has no effect for X-tal oscillator
option.
1 = OSC2 pin configured for PTA6 I/O, and has all the interrupt and
pull-up functions.
0 = OSC2 pin outputs the RC oscillator clock (RCCLK)
PTAPUE[6:0] — Port A Input Pull-up Enable bits
These read/write bits are software programmable to enable pull-up
devices on port A pins
1 = Corresponding port A pin configured to have internal pull if its
DDRA bit is set to 0
0 = Pull-up device is disconnected on the corresponding port A pin
regardless of the state of its DDRA bit.
Table 12-1 summarizes the operation of the port B pins.
Table 12-1. Port A Pin Functions
Accesses to DDRB
Read/Write
Accesses to PTB
DDRA
Bit
PTAPUE Bit
PTA Bit
I/O Pin Mode
Read
Write
(1)
(2)
(3)
(3)
1
0
X
0
0
1
X
Input, V
DDRA6-DDRA0
DDRA6-DDRA0
DDRA6-DDRA0
Pin
Pin
PTA6-PTA0
PTA6-PTA0
DD
(4)
X
X
Input, Hi-Z
Output
PTA6-PTA0
PTA6-PTA0
1. X = Don’t care.
2. I/O pin pulled to V by internal pull-up.
DD
3. Writing affects data register, but does not affect input.
4. Hi-Z = High Impedence
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
142
I/O Ports
I/O Ports
Port B
12.4 Port B
Port B is an 8-bit special function port that shares all eight of its port pins
with the Analog-to-Digital converter (ADC) module, See Section 11.
12.4.1 Port B Da ta Re g iste r (PTB)
The port B data register contains a data latch for each of the eight port B
pins.
Address:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Reset:
Unaffected by reset
ADC4 ADC3
Alternative Function:
ADC7
ADC6
ADC5
ADC2
ADC2
ADC0
Figure 12-6. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
12.4.2 Da ta Dire c tion Re g iste r B (DDRB)
Data direction register B determines whether each port B pin is an input
or an output. Writing a logic one to a DDRB bit enables the output buffer
for the corresponding port B pin; a logic zero disables the output buffer.
Address:
$0005
Bit 7
6
DDRB6
0
5
DDRB5
0
4
DDRB4
0
3
DDRB3
0
2
DDRB2
0
1
DDRB1
0
Bit 0
DDRB0
0
Read:
Write:
Reset:
DDRB7
0
Figure 12-7. Data Direction Register B (DDRB)
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
I/O Ports
143
I/ O Ports
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1. Figure 12-8 shows
the port B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005)
DDRBx
RESET
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
To Analog-To-Digital Converter
Figure 12-8. Port B I/O Circuit
When DDRBx is a logic 1, reading address $0001 reads the PTBx data
latch. When DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 12-2summarizes the operation
of the port B pins.
Table 12-2. Port B Pin Functions
Accesses to DDRB Accesses to PTB
DDRB Bit PTB Bit I/O Pin Mode
Read/Write
Read
Write
(1)
(2)
(3)
0
X
Input, Hi-Z
Output
DDRB7-DDRB0
DDRB7-DDRB0
Pin
PTB[7:0]
1
X
Pin
PTB[7:0]
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect the input.
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
144
I/O Ports
I/O Ports
Port D
12.5 Port D
Port D is an 8-bit special function port that shares two of its pins with
Timer Interface Module, (see Section 10.) and shares four of its pins
with Analog to Digital Conversion Module (see Section 11.). PTD6 and
PTD7 each has high current drive (25mA sink) and programmable pull-
up. PTD2, PTD3, PTD6 and PTD7 each has LED driving capability.
12.5.1 Port D Da ta Re g iste r (PTD)
The port D data register contains a data latch for each of the eight port D
pins.
Address:
$0003
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Reset:
Additional Functions
LED
LED
LED
LED
ADC8
ADC9
ADC10
ADC11
TCH1
TCH0
25mA sink 25mA sink
(Slow Edge) (Slow Edge)
5k pull-up 5k pull-up
Figure 12-9. Port D Data Register (PTD)
PTD[7:0] — Port D Data Bits
These read/write bits are software programmable. Data direction of
each port D pin is under the control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
I/O Ports
145
I/ O Ports
12.5.2 Da ta Dire c tion Re g iste r D (DDRD)
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic one to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic zero disables the output buffer.
Address:
$0007
Bit 7
6
DDRD6
0
5
DDRD5
0
4
DDRD4
0
3
DDRD3
0
2
DDRD2
0
1
DDRD1
0
Bit 0
DDRD0
0
Read:
Write:
Reset:
DDRD7
0
Figure 12-10. Data Direction Register D (DDRD)
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1. Figure 12-11 shows
the port D I/O logic.
READ DDRD ($0007)
PTDPU[6:7]
WRITE DDRD ($0007)
DDRDx
RESET
5k
WRITE PTD ($0003)
READ PTD ($0003)
PTDx
PTDx
PTD[0:3] To Analog-To-Digital Converter
PTD[4:5] To Timer
Figure 12-11. Port D I/O Circuit
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
146
I/O Ports
I/O Ports
Port D
When DDRDx is a logic 1, reading address $0003 reads the PTDx data
latch. When DDRDx is a logic 0, reading address $0003 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 12-3 summarizes the operation
of the port D pins.
Table 12-3. Port D Pin Functions
Accesses
Accesses to PTD
DDRD
Bit
I/O Pin
Mode
to DDRA
Read/Write
DDRD[7:0]
DDRD[7:0]
PTD Bit
Read
Pin
Write
(1)
(2)
(3)
0
1
X
Input, Hi-Z
Output
PTD[7:0]
X
Pin
PTD[7:0]
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect the input.
12.5.3 Port D Control Re g iste r (PDCR)
The Port D Control Register enables/disables the pull-up resistor and
slow-edge high current capability of pins PTD6 and PTD7.
Address:
$000A
Bit 7
0
6
5
4
3
SLOWD7
0
2
SLOWD6
0
1
PTDPU7
0
Bit 0
PTDPU6
0
Read:
Write:
Reset:
0
0
0
0
0
0
0
Figure 12-12. Port D Control Register (PDCR)
SLOWDx — Slow Edge Enable
The SLOWD6 and SLOWD7 bits enable the Slow-edge, open-drain,
high current output (25mA sink) of port pins PTD6 and PTD7
respectively. DDRx bit is not affected by SLOWDx.
1 = Slow edge enabled; pin is open-drain output
0 = Slow edge disabled; pin is push-pull
PTDPUx — Pull-up Enable
The PTDPU6 and PTDPU7 bits enable the 5k pull-up on PTD6 and
PTD7 respectively, regardless the status of DDRDx bit.
1 = Enable 5k pull-up
0 = Disable 5k pull-up
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
I/O Ports
147
I/ O Ports
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
148
I/O Ports
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 13. Exte rna l Inte rrup t (IRQ)
13.1 Conte nts
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
13.4.1 IRQ1 Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
13.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .153
13.6 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .153
13.2 Introd uc tion
13.3 Fe a ture s
The IRQ (external interrupt) module provides a maskable interrupt input.
Features of the IRQ module include the following:
• A dedicated external interrupt pin, IRQ1
• IRQ1 interrupt control bits
• Hysteresis buffer
• Programmable edge-only or edge and level interrupt sensitivity
• Automatic interrupt acknowledge
• Selectable internal pullup resistor
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
External Interrupt (IRQ)
149
Exte rna l Inte rrup t (IRQ)
13.4 Func tiona l De sc rip tion
A logic zero applied to the external interrupt pin can latch a CPU interrupt
request. Figure 13-1 shows the structure of the IRQ module.
Interrupt signals on the IRQ1 pin are latched into the IRQ1 latch. An
interrupt latch remains set until one of the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the IRQ latch.
• Software clear — Software can clear the interrupt latch by writing
to the acknowledge bit in the interrupt status and control register
(ISCR). Writing a logic one to the ACK1 bit clears the IRQ1 latch.
• Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered and is software-
configurable to be either falling-edge or falling-edge and low-level-
triggered. The MODE1 bit in the ISCR controls the triggering sensitivity
of the IRQ1 pin.
When the interrupt pin is edge-triggered only, the CPU interrupt request
remains set until a vector fetch, software clear, or reset occurs.
When the interrupt pin is both falling-edge and low-level-triggered, the
CPU interrupt request remains set until both of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic one
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic one. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE1 control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK1 bit in the ISCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the IMASK1 bit is clear.
Technical Data
MC68H(R)C08JL3 — Rev. 4
150
External Interrupt (IRQ)
MOTOROLA
External Interrupt (IRQ)
Functional Description
NOTE: The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.(See 7.6
Exception Control.)
ACK1
RESET
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
VDD
IRQPUD
VDD
I
NTERNAL
IRQF1
PULLUP
DEVICE
CLR
D
Q
SYNCHRO-
NIZER
IRQ1
INTERRUPT
REQUEST
CK
IRQ1
IRQ1
FF
IMASK1
MODE1
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
Figure 13-1. IRQ Module Block Diagram
Addr.
Register Name
IRQ Status and Control
Bit 7
6
5
4
3
2
0
1
IMASK1
0
Bit 0
MODE1
0
Read:
0
0
0
0
IRQF1
$001D
Register Write:
(INTSCR)
ACK1
0
Reset:
0
0
0
0
0
= Unimplemented
Figure 13-2. IRQ I/O Register Summary
13.4.1 IRQ1 Pin
A logic zero on the IRQ1 pin can latch an interrupt request into the IRQ1
latch. A vector fetch, software clear, or reset clears the IRQ1 latch.
If the MODE1 bit is set, the IRQ1 pin is both falling-edge-sensitive and
low-level-sensitive. With MODE1 set, both of the following actions must
occur to clear IRQ1:
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
External Interrupt (IRQ)
151
Exte rna l Inte rrup t (IRQ)
• Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic one to
the ACK1 bit in the interrupt status and control register (ISCR).
The ACK1 bit is useful in applications that poll the IRQ1 pin and
require software to clear the IRQ1 latch. Writing to the ACK1 bit
prior to leaving an interrupt service routine can also prevent
spurious interrupts due to noise. Setting ACK1 does not affect
subsequent transitions on the IRQ1 pin. A falling edge that occurs
after writing to the ACK1 bit latches another interrupt request. If
the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program
counter with the vector address at locations $FFFA and $FFFB.
• Return of the IRQ1 pin to logic one — As long as the IRQ1 pin is
at logic zero, IRQ1 remains active.
The vector fetch or software clear and the return of the IRQ1 pin to logic
one may occur in any order. The interrupt request remains pending as
long as the IRQ1 pin is at logic zero. A reset will clear the latch and the
MODE1 control bit, thereby clearing the interrupt even if the pin stays
low.
If the MODE1 bit is clear, the IRQ1 pin is falling-edge-sensitive only.
With MODE1 clear, a vector fetch or software clear immediately clears
the IRQ1 latch.
The IRQF1 bit in the ISCR register can be used to check for pending
interrupts. The IRQF1 bit is not affected by the IMASK1 bit, which makes
it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
NOTE: An internal pull-up resistor to V is connected to the IRQ1 pin; this can
DD
be disabled by setting the IRQPUD bit in the CONFIG2 register ($001E).
Technical Data
MC68H(R)C08JL3 — Rev. 4
152
External Interrupt (IRQ)
MOTOROLA
External Interrupt (IRQ)
IRQ Module During Break Interrupts
13.5 IRQ Mod ule During Bre a k Inte rrup ts
The system integration module (SIM) controls whether the IRQ1 latch
can be cleared during the break state. The BCFE bit in the break flag
control register (BFCR) enables software to clear the latches during the
break state. (See Section 7. System Integration Module (SIM).)
To allow software to clear the IRQ1 latch during a break interrupt, write
a logic one to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a logic zero to the
BCFE bit. With BCFE at logic zero (its default state), writing to the ACK1
bit in the IRQ status and control register during the break state has no
effect on the IRQ latch.
13.6 IRQ Sta tus a nd Control Re g iste r (ISCR)
The IRQ Status and Control Register (ISCR) controls and monitors
operation of the IRQ module. The ISCR has the following functions:
• Shows the state of the IRQ1 flag
• Clears the IRQ1 latch
• Masks IRQ1 and interrupt request
• Controls triggering sensitivity of the IRQ1 interrupt pin
Address:
$001D
Bit 7
0
6
0
5
0
4
0
3
2
1
IMASK1
0
Bit 0
MODE1
0
Read:
Write:
Reset:
IRQF1
ACK1
0
0
0
0
0
0
= Unimplemented
Figure 13-3. IRQ Status and Control Register (INTSCR)
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
External Interrupt (IRQ)
153
Exte rna l Inte rrup t (IRQ)
IRQF1 — IRQ1 Flag
This read-only status bit is high when the IRQ1 interrupt is pending.
1 = IRQ1 interrupt pending
0 = IRQ1 interrupt not pending
ACK1 — IRQ1 Interrupt Request Acknowledge Bit
Writing a logic one to this write-only bit clears the IRQ1 latch. ACK1
always reads as logic zero. Reset clears ACK1.
IMASK1 — IRQ1 Interrupt Mask Bit
Writing a logic one to this read/write bit disables IRQ1 interrupt
requests. Reset clears IMASK1.
1 = IRQ1 interrupt requests disabled
0 = IRQ1 interrupt requests enabled
MODE1 — IRQ1 Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ1 pin.
Reset clears MODE1.
1 = IRQ1 interrupt requests on falling edges and low levels
0 = IRQ1 interrupt requests on falling edges only
Address:
$001E
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
POR:
IRQPUD
R
R
LVIT1
LVIT0
R
R
Not affected Not affected
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
= Reserved
Figure 13-4. Configuration Register 2 (CONFIG2)
IRQPUD — IRQ1 Pin Pull-up control bit
1 = Internal pull-up is disconnected
0 = Internal pull-up is connected between IRQ1 pin and V
DD
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
154
External Interrupt (IRQ)
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 14. Ke yb oa rd Inte rrup t Mod ule (KBI)
14.1 Conte nts
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
14.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
14.4.2 Keyboard Status and Control Register. . . . . . . . . . . . . . . .159
14.4.3 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . .160
14.5 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
14.6 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
14.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .161
14.2 Introd uc tion
14.3 Fe a ture s
The keyboard interrupt module (KBI) provides seven independently
maskable external interrupts which are accessible via PTA0–PTA6 pins.
Features of the keyboard interrupt module include the following:
• Seven keyboard interrupt pins with separate keyboard interrupt
enable bits and one keyboard interrupt mask
• Software configurable pull-up device if input pin is configured as
input port bit
• Programmable edge-only or edge- and level- interrupt sensitivity
• Exit from low-power modes
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Keyboard Interrupt Module (KBI)
155
Ke yb oa rd Inte rrup t Mod ule (KBI)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
IMASKK
0
Bit 0
MODEK
0
Read:
0
0
0
0
KEYF
0
ACKK
0
Keyboard Status
and Control Register Write:
$001A
(KBSCR)
Reset:
0
0
0
KBIE6
0
0
KBIE5
0
0
KBIE4
0
0
KBIE3
0
Read:
KBIE2
0
KBIE1
0
KBIE0
0
Keyboard Interrupt Enable
Write:
$001B
Register (KBIER)
Reset:
0
= Unimplemented
Figure 14-1. KBI I/O Register Summary
14.4 Func tiona l De sc rip tion
INTERNAL BUS
VECTOR FETCH
DECODER
KBI0
ACKK
V
DD
KEYF
RESET
CLR
.
D
Q
SYNCHRONIZER
Keyboard
Interrupt
Request
KBIE0
.
TO PULLUP ENABLE
.
CK
KEYBOARD
INTERRUPT FF
IMASKK
KBI6
MODEK
KBIE6
TO PULLUP ENABLE
Figure 14-2. Keyboard Interrupt Block Diagram
Writing to the KBIE6–KBIE0 bits in the keyboard interrupt enable register
independently enables or disables each port A pin as a keyboard
interrupt pin. Enabling a keyboard interrupt pin in port A also enables its
internal pull-up device irrespective of PTAPUEx bits in the port A input
pull-up enable register (see 12.3.3). A logic 0 applied to an enabled
keyboard interrupt pin latches a keyboard interrupt request.
Technical Data
MC68H(R)C08JL3 — Rev. 4
156
Keyboard Interrupt Module (KBI)
MOTOROLA
Keyboard Interrupt Module (KBI)
Functional Description
A keyboard interrupt is latched when one or more keyboard pins goes
low after all were high. The MODEK bit in the keyboard status and
control register controls the triggering mode of the keyboard interrupt.
• If the keyboard interrupt is edge-sensitive only, a falling edge on a
keyboard pin does not latch an interrupt request if another
keyboard pin is already low. To prevent losing an interrupt request
on one pin because another pin is still low, software can disable
the latter pin while it is low.
• If the keyboard interrupt is falling edge- and low level-sensitive, an
interrupt request is present as long as any keyboard pin is low.
If the MODEK bit is set, the keyboard interrupt pins are both falling edge-
and low level-sensitive, and both of the following actions must occur to
clear a keyboard interrupt request:
• Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the interrupt request.
Software may generate the interrupt acknowledge signal by
writing a logic 1 to the ACKK bit in the keyboard status and control
register KBSCR. The ACKK bit is useful in applications that poll
the keyboard interrupt pins and require software to clear the
keyboard interrupt request. Writing to the ACKK bit prior to leaving
an interrupt service routine can also prevent spurious interrupts
due to noise. Setting ACKK does not affect subsequent transitions
on the keyboard interrupt pins. A falling edge that occurs after
writing to the ACKK bit latches another interrupt request. If the
keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the
program counter with the vector address at locations $FFE0 and
$FFE1.
• Return of all enabled keyboard interrupt pins to logic 1 — As long
as any enabled keyboard interrupt pin is at logic 0, the keyboard
interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard
interrupt pins to logic 1 may occur in any order.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Keyboard Interrupt Module (KBI)
157
Ke yb oa rd Inte rrup t Mod ule (KBI)
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-
sensitive only. With MODEK clear, a vector fetch or software clear
immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing
the interrupt request even if a keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register
can be used to see if a pending interrupt exists. The KEYF bit is not
affected by the keyboard interrupt mask bit (IMASKK) which makes it
useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, disable the pull-
up device, use the data direction register to configure the pin as an input
and then read the data register.
NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction
register. However, the data direction register bit must be a logic 0 for
software to read the pin.
14.4.1 Ke yb oa rd Initia liza tion
When a keyboard interrupt pin is enabled, it takes time for the internal
pull-up to reach a logic 1. Therefore a false interrupt can occur as soon
as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the
keyboard status and control register.
2. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
3. Write to the ACKK bit in the keyboard status and control register
to clear any false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged
immediately after enabling the pin. An interrupt signal on an edge- and
Technical Data
MC68H(R)C08JL3 — Rev. 4
158
Keyboard Interrupt Module (KBI)
MOTOROLA
Keyboard Interrupt Module (KBI)
Functional Description
level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate
DDRA bits in the data direction register A.
2. Write logic 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
14.4.2 Ke yb oa rd Sta tus a nd Control Re g iste r
• Flags keyboard interrupt requests.
• Acknowledges keyboard interrupt requests.
• Masks keyboard interrupt requests.
• Controls keyboard interrupt triggering sensitivity.
Address:
$001A
Bit 7
0
6
0
5
0
4
0
3
2
1
IMASKK
0
Bit 0
MODEK
0
Read:
Write:
Reset:
KEYF
0
ACKK
0
0
0
0
0
0
= Unimplemented
Figure 14-3. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as logic 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port-
A. Reset clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Keyboard Interrupt Module (KBI)
159
Ke yb oa rd Inte rrup t Mod ule (KBI)
ACKK — Keyboard Acknowledge Bit
Writing a logic 1 to this write-only bit clears the keyboard interrupt
request on port-A. ACKK always reads as logic 0. Reset clears ACKK.
IMASKK— Keyboard Interrupt Mask Bit
Writing a logic 1 to this read/write bit prevents the output of the
keyboard interrupt mask from generating interrupt requests on port-A.
Reset clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard
interrupt pins on port-A. Reset clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
14.4.3 Ke yb oa rd Inte rrup t Ena b le Re g iste r
The port-A keyboard interrupt enable register enables or disables each
port-A pin to operate as a keyboard interrupt pin.
Address:
$001B
Bit 7
0
6
KBIE6
0
5
KBIE5
0
4
KBIE4
0
3
KBIE3
0
2
KBIE2
0
1
KBIE1
0
Bit 0
KBIE0
0
Read:
Write:
Reset:
0
Figure 14-4. Keyboard Interrupt Enable Register (KBIER)
KBIE6–KBIE0 — Port-A Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard
interrupt pin on port-A to latch interrupt requests. Reset clears the
keyboard interrupt enable register.
1 = KBIx pin enabled as keyboard interrupt pin
0 = KBIx pin not enabled as keyboard interrupt pin
Technical Data
MC68H(R)C08JL3 — Rev. 4
160
Keyboard Interrupt Module (KBI)
MOTOROLA
Keyboard Interrupt Module (KBI)
Wait Mode
14.5 Wa it Mod e
The keyboard modules remain active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.
14.6 Stop Mod e
The keyboard module remains active in stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of stop mode.
14.7 Ke yb oa rd Mod ule During Bre a k Inte rrup ts
The system integration module (SIM) controls whether the keyboard
interrupt latch can be cleared during the break state. The BCFE bit in the
break flag control register (BFCR) enables software to clear status bits
during the break state.
To allow software to clear the keyboard interrupt latch during a break
interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the
break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the keyboard
acknowledge bit (ACKK) in the keyboard status and control register
during the break state has no effect.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Keyboard Interrupt Module (KBI)
161
Ke yb oa rd Inte rrup t Mod ule (KBI)
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
162
Keyboard Interrupt Module (KBI)
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 15. Com p ute r Op e ra ting Prop e rly (COP)
15.1 Conte nts
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
15.4.1 2OSCOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
15.4.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
15.4.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
15.4.4 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
15.4.5 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
15.4.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
15.4.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . .166
15.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
15.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
15.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
15.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
15.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
15.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
15.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .168
15.2 Introd uc tion
The computer operating properly (COP) module contains a free-running
counter that generates a reset if allowed to overflow. The COP module
helps software recover from runaway code. Prevent a COP reset by
clearing the COP counter periodically. The COP module can be disabled
through the COPD bit in the CONFIG1 register.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Computer Operating Properly (COP)
163
Com p ute r Op e ra ting Prop e rly (COP)
15.3 Func tiona l De sc rip tion
Figure 15-1 shows the structure of the COP module.
SIM
2OSCOUT
SIM RESET CIRCUIT
12-BIT SIM COUNTER
RESET STATUS REGISTER
(1)
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
CLEAR
COPEN (FROM SIM)
COPD (FROM CONFIG1)
RESET
COP COUNTER
COPCTL WRITE
COP RATE SEL
(COPRS FROM CONFIG1)
NOTE:
1. See SIM section for more details.
Figure 15-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by the 12-bit
system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
18
4
13
4
2 – 2 or 2 – 2 2OSCOUT cycles; depending on the state of the
18
4
COP rate select bit, COPRS, in configuration register 1. With a 2 – 2
2OSCOUT cycle overflow option, a 8MHz crystal gives a COP timeout
period of 32.766 ms. Writing any value to location $FFFF before an
overflow occurs prevents a COP reset by clearing the COP counter and
stages 12 through 5 of the SIM counter.
Technical Data
MC68H(R)C08JL3 — Rev. 4
164
Computer Operating Properly (COP)
MOTOROLA
Computer Operating Properly (COP)
I/O Signals
NOTE: Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 × 2OSCOUT cycles and sets
the COP bit in the reset status register (RSR). (See 7.8.2 Reset Status
Register (RSR).).
NOTE: Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
15.4 I/ O Sig na ls
The following paragraphs describe the signals shown in Figure 15-1.
15.4.1 2OSCOUT
2OSCOUT is the oscillator output signal. 2OSCOUT frequency is equal
to the crystal frequency or the RC-oscillator frequency.
15.4.2 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 15.5 COP
Control Register) clears the COP counter and clears bits 12 through 5
of the SIM counter. Reading the COP control register returns the low
byte of the reset vector.
15.4.3 Powe r-On Re se t
The power-on reset (POR) circuit in the SIM clears the SIM counter
4096 × 2OSCOUT cycles after power-up.
15.4.4 Inte rna l Re se t
An internal reset clears the SIM counter and the COP counter.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Computer Operating Properly (COP)
165
Com p ute r Op e ra ting Prop e rly (COP)
15.4.5 Re se t Ve c tor Fe tc h
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the SIM counter.
15.4.6 COPD (COP Disa b le )
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register (CONFIG). (See Section 5. Configuration
Register (CONFIG).)
15.4.7 COPRS (COP Ra te Se le c t)
The COPRS signal reflects the state of the COP rate select bit (COPRS)
in the configuration register 1.
Address:
$001F
Bit 7
6
5
R
0
4
LVID
0
3
R
0
2
SSREC
0
1
STOP
0
Bit 0
COPD
0
Read:
Write:
Reset:
COPRS
R
0
0
R
= Reserved
Figure 15-2. Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
13
4
1 = COP timeout period is (2 – 2 ) × 2OSCOUT cycles
18
4
0 = COP timeout period is (2 – 2 ) × 2OSCOUT cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
166
Computer Operating Properly (COP)
Computer Operating Properly (COP)
COP Control Register
15.5 COP Control Re g iste r
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address:
$FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Low byte of reset vector
Clear COP counter
Unaffected by reset
Figure 15-3. COP Control Register (COPCTL)
15.6 Inte rrup ts
The COP does not generate CPU interrupt requests.
15.7 Monitor Mod e
The COP is disabled in monitor mode when V + V is present on the
DD
HI
IRQ1 pin or on the RST pin.
15.8 Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low-power
consumption standby modes.
15.8.1 Wa it Mod e
The COP continues to operate during wait mode. To prevent a COP
reset during wait mode, periodically clear the COP counter in a CPU
interrupt routine.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Computer Operating Properly (COP)
167
Com p ute r Op e ra ting Prop e rly (COP)
15.8.2 Stop Mod e
Stop mode turns off the 2OSCOUT input to the COP and clears the SIM
counter. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
15.9 COP Mod ule During Bre a k Mod e
The COP is disabled during a break interrupt when V + V is present
DD
HI
on the RST pin.
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
168
Computer Operating Properly (COP)
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 16. Low Volta g e Inhib it (LVI)
16.1 Conte nts
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
16.5 LVI Control Register (CONFIG2/CONFIG1). . . . . . . . . . . . . .170
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
16.2 Introd uc tion
This section describes the low-voltage inhibit module (LVI), which
monitors the voltage on the V pin and generates a reset when the V
DD
DD
voltage falls to the LVI trip (LVI
) voltage.
TRIP
16.3 Fe a ture s
Features of the LVI module include the following:
• Selectable LVI trip voltage
• Selectable LVI circuit disable
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Low Voltage Inhibit (LVI)
169
Low Volta g e Inhib it (LVI)
16.4 Func tiona l De sc rip tion
Figure 16-1 shows the structure of the LVI module. The LVI is enabled
after a reset. The LVI module contains a bandgap reference circuit and
comparator. Setting LVI disable bit (LVID) disables the LVI to monitor
V
voltage. The LVI trip voltage selection bits (LVIT1, LVIT0)
DD
determines at which V level the LVI module should take actions.
DD
The LVI module generates one output signal:
LVI Reset — an reset signal will be generated to reset the CPU when
V
drops to below the set trip point.
DD
V
DD
LVID
VDD > LVI
VDD < LVI
= 0
= 1
TRIP
TRIP
LVI RESET
LOW V
DD
DETECTOR
LVT1
LVT0
Figure 16-1. LVI Module Block Diagram
16.5 LVI Control Re g iste r (CONFIG2/ CONFIG1)
Address:
$001E
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
POR:
IRQPUD
R
R
LVIT1
LVIT0
R
R
Not affected Not affected
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
= Reserved
Figure 16-2. Configuration Register 2 (CONFIG2)
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
170
Low Voltage Inhibit (LVI)
Low Voltage Inhibit (LVI)
Low-Power Modes
Address:
$001F
Bit 7
6
5
R
0
4
LVID
0
3
R
0
2
SSREC
0
1
STOP
0
Bit 0
COPD
0
Read:
Write:
Reset:
COPRS
R
0
0
R
= Reserved
Figure 16-3. Configuration Register 1 (CONFIG1)
LVID — Low Voltage Inhibit Disable Bit
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
LVIT1, LVIT0 — LVI Trip Voltage Selection
These two bits determine at which level of V the LVI module will
DD
come into action. LVIT1 and LVIT0 are cleared by a Power-On Reset
only.
(1)
LVIT1
LVIT0
Comments
For V =3V operation
Trip Voltage
0
0
1
1
0
1
0
1
V
(2.4V)
(2.4V)
(4.0V)
LVR3
DD
V
For V =3V operation
DD
LVR3
LVR5
V
For V =5V operation
DD
Reserved
1. See Section 18. Electrical Specifications for full parameters.
16.6 Low-Powe r Mod e s
The STOP and WAIT instructions put the MCU in low-power-
consumption standby modes.
16.6.1 Wa it Mod e
16.6.2 Stop Mod e
The LVI module, when enabled, will continue to operate in WAIT Mode.
The LVI module, when enabled, will continue to operate in STOP Mode.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Low Voltage Inhibit (LVI)
171
Low Volta g e Inhib it (LVI)
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
172
Low Voltage Inhibit (LVI)
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 17. Bre a k Mod ule (BREAK)
17.1 Conte nts
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
17.4.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . .176
17.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .176
17.4.3 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . .176
17.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .176
17.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
17.5.1 Break Status and Control Register (BRKSCR) . . . . . . . . .177
17.5.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .178
17.5.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
17.5.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . .180
17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
17.2 Introd uc tion
This section describes the break module. The break module can
generate a break interrupt that stops normal program flow at a defined
address to enter a background program.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Break Module (BREAK)
173
Bre a k Mod ule (BREAK)
17.3 Fe a ture s
Features of the break module include the following:
• Accessible I/O registers during the break Interrupt
• CPU-generated break interrupts
• Software-generated break interrupts
• COP disabling during break interrupts
17.4 Func tiona l De sc rip tion
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal (BKPT)
to the SIM. The SIM then causes the CPU to load the instruction register
with a software interrupt instruction (SWI) after completion of the current
CPU instruction. The program counter vectors to $FFFC and $FFFD
($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
• Software writes a logic one to the BRKA bit in the break status and
control register.
When a CPU generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return from interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 17-1 shows the structure of the break module.
Technical Data
MC68H(R)C08JL3 — Rev. 4
174
Break Module (BREAK)
MOTOROLA
Break Module (BREAK)
Functional Description
IAB[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB[15:0]
CONTROL
BKPT
(TO SIM)
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB[7:0]
Figure 17-1. Break Module Block Diagram
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
SBSW
See note
0
R
R
R
R
R
R
R
Break Status Register
(BSR)
$FE00
Break Flag Control
BCFE
0
R
R
R
R
R
R
R
$FE03
$FE0C
$FE0D
$FE0E
Register Write:
(BFCR)
Reset:
Read:
Break Address High
Bit15
0
Bit14
0
Bit13
0
Bit12
0
Bit11
0
Bit10
0
Bit9
0
Bit8
0
Register Write:
(BRKH)
Reset:
Read:
Break Address low
Bit7
0
Bit6
0
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Register Write:
(BRKL)
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Break Status and Control
BRKE
0
BRKA
Register Write:
(BRKSCR)
Reset:
0
0
0
0
0
0
0
Note: Writing a logic 0 clears SBSW.
= Unimplemented
R
= Reserved
Figure 17-2. Break I/O Register Summary
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Break Module (BREAK)
175
Bre a k Mod ule (BREAK)
17.4.1 Fla g Prote c tion During Bre a k Inte rrup ts
The system integration module (SIM) controls whether or not module
status bits can be cleared during the break state. The BCFE bit in the
break flag control register (BFCR) enables software to clear status bits
during the break state. (See 7.8.3 Break Flag Control Register (BFCR)
and see the Break Interrupts subsection for each module.)
17.4.2 CPU During Bre a k Inte rrup ts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
17.4.3 TIM During Bre a k Inte rrup ts
A break interrupt stops the timer counter.
17.4.4 COP During Bre a k Inte rrup ts
The COP is disabled during a break interrupt when VDD + VHI is present
on the RST pin.
17.5 Bre a k Mod ule Re g iste rs
These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• Break status register (BSR)
• Break flag control register (BFCR)
Technical Data
MC68H(R)C08JL3 — Rev. 4
176
Break Module (BREAK)
MOTOROLA
Break Module (BREAK)
Break Module Registers
17.5.1 Bre a k Sta tus a nd Control Re g iste r (BRKSCR)
The break status and control register contains break module enable and
status bits.
Address: $FE0E
Bit 7
BRKE
0
6
BRKA
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 17-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches.
Clear BRKE by writing a logic zero to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
BRKA — Break Active Bit
This read/write status and control bit is set when a break address
match occurs. Writing a logic one to BRKA generates a break
interrupt. Clear BRKA by writing a logic zero to it before exiting the
break routine. Reset clears the BRKA bit.
1 = Break address match
0 = No break address match
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Break Module (BREAK)
177
Bre a k Mod ule (BREAK)
17.5.2 Bre a k Ad d re ss Re g iste rs
The break address registers contain the high and low bytes of the
desired breakpoint address. Reset clears the break address registers.
Address: $FE0C
Bit 7
Bit 15
0
6
14
0
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
Bit 0
Bit 8
0
Read:
Write:
Reset:
Figure 17-4. Break Address Register High (BRKH)
Address: $FE0D
Bit 7
6
6
0
5
5
0
4
4
0
3
3
0
2
2
0
1
1
0
Bit 0
Bit 0
0
Read:
Bit 7
Write:
Reset:
0
Figure 17-5. Break Address Register Low (BRKL)
17.5.3 Bre a k Sta tus Re g iste r
The break status register contains a flag to indicate that a break caused
an exit from stop or wait mode.
Address:
$FE00
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
SBSW
R
R
R
R
R
R
(1)
Note
0
R
= Reserved
1. Writing a logic zero clears SBSW.
Figure 17-6. Break Status Register (BSR)
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
178
Break Module (BREAK)
Break Module (BREAK)
Break Module Registers
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic zero to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this. Writing zero to the SBSW bit clears
it.
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the
; break service routine software.
HIBYTE EQU
LOBYTE EQU
5
6
;
If not SBSW, do RTI
BRCLR SBSW,BSR, RETURN ; See if wait mode or stop mode was exited
; by break.
TST
BNE
DEC
DEC
LOBYTE,SP
DOLO
; If RETURNLO is not zero,
; then just decrement low byte.
; Else deal with high byte, too.
; Point to WAIT/STOP opcode.
; Restore H register.
HIBYTE,SP
LOBYTE,SP
DOLO
RETURN PULH
RTI
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Break Module (BREAK)
179
Bre a k Mod ule (BREAK)
17.5.4 Bre a k Fla g Control Re g iste r (BFCR)
The break control register contains a bit that enables software to clear
status bits while the MCU is in a break state.
Address:
Bit 7
$FE03
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
R
= Reserved
Figure 17-7. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
17.6 Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low-power-
consumption standby modes.
17.6.1 Wa it Mod e
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if SBSW
is set (see 7.7 Low-Power Modes). Clear the SBSW bit by writing logic
zero to it.
17.6.2 Stop Mod e
A break interrupt causes exit from stop mode and sets the SBSW bit in
the break status register. See 7.8 SIM Registers.
Technical Data
MC68H(R)C08JL3 — Rev. 4
180
Break Module (BREAK)
MOTOROLA
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 18. Ele c tric a l Sp e c ific a tions
18.1 Conte nts
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
18.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .182
18.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .183
18.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
18.6 5V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .184
18.7 5V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
18.8 5V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .186
18.9 3V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .187
18.10 3V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
18.11 3V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .189
18.12 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
18.13 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
18.2 Introd uc tion
This section contains electrical and timing specifications.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Electrical Specifications
181
Ele c tric a l Sp e c ific a tions
18.3 Ab solute Ma xim um Ra ting s
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to Sections 18.6 and 18.9 for guaranteed operating
conditions.
Table 18-1. Absolute Maximum Ratings(1)
Characteristic
Supply voltage
Symbol
Value
Unit
V
V
–0.3 to +6.0
DD
V
V
–0.3 to V +0.3
Input voltage
V
IN
SS
DD
V
+V
I
V
–0.3 to +8.5
Mode entry voltage, IRQ1 pin
Maximum current per pin
V
DD
HI
SS
±25
mA
excluding V and V
DD
SS
T
Storage temperature
–55 to +150
100
°C
mA
mA
STG
MVSS
MVDD
Maximum current out of V
Maximum current into V
I
SS
I
100
DD
NOTE:
1. Voltages referenced to V
.
SS
NOTE: This device contains circuitry to protect the inputs against damage due
to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that V and V
be constrained to the
IN
OUT
range V ≤ (V or V
) ≤ V . Reliability of operation is enhanced if
DD
SS
IN
OUT
unused inputs are connected to an appropriate logic voltage level (for
example, either V or V .)
SS
DD
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
182
Electrical Specifications
Electrical Specifications
Functional Operating Range
18.4 Func tiona l Op e ra ting Ra ng e
Table 18-2. Operating Range
Characteristic
Symbol
Value
– 40 to +125
Unit
°C
T
Operating temperature range
Operating voltage range
– 40 to +85
A
V
5V ± 10%
3V ± 10%
V
DD
18.5 The rm a l Cha ra c te ristic s
Table 18-3.Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal resistance
20-Pin PDIP
20-Pin SOIC
28-Pin PDIP
28-Pin SOIC
70
70
70
70
°C/W
°C/W
°C/W
°C/W
θ
JA
P
I/O pin power dissipation
User determined
W
W
I/O
P = (I ×V ) + P =
I/O
D
DD
DD
(1)
P
Power dissipation
D
K/(T + 273 °C)
J
P x (T + 273 °C)
D
A
(2)
K
W/°C
Constant
2
+ P × θJA
D
T
T + (P × θJA)
Average junction temperature
°C
°C
J
A
D
T
Maximum junction temperature
NOTES:
100
JM
1. Power dissipation is a function of temperature.
2. K constant unique to the device. K can be determined for a known T and measured
A
P
With this value of K, P and T can be determined for any value of T .
D.
D J A
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Electrical Specifications
183
Ele c tric a l Sp e c ific a tions
18.6 5V DC Ele c tric a l Cha ra c te ristic s
Table 18-4. DC Electrical Characteristics (5V)
(1)
(2)
Symbol
Min
–0.8
Max
Unit
Characteristic
Typ
Output high voltage (I = –2.0mA)
LOAD
V
V
—
—
—
19
—
V
OH
DD
PTA0–PTA6, PTB0–PTB7, PTD0–PTD7
Output low voltage (I = 1.6mA)
LOAD
V
—
—
10
0.4
0.5
25
V
V
OL
PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5
Output low voltage (I
PTD6, PTD7
= 25mA)
LOAD
V
OL
LED drives (V = 3V)
OL
I
mA
OL
PTA0–PTA5, PTD2, PTD3, PTD6, PTD7
Input high voltage
V
0.7 ×V
V
PTA0–PTA6, PTB0–PTB7, PTD0–PTD7,
RST, IRQ1, OSC1
—
—
V
V
IH
DD
DD
Input low voltage
V
V
0.3 ×V
DD
PTA0–PTA6, PTB0–PTB7, PTD0–PTD7,
RST, IRQ1, OSC1
IL
SS
V
supply current
DD
(3)
Run, f = 4MHz
—
—
—
—
10
1
5
12
1.5
5.5
5
mA
mA
mA
µA
OP
(4)
I
Wait (MC68HRC08xxx)
DD
(4)
Wait (MC68HC08xxx)
(5)
Stop
–40°C to 85°C
1
I
Digital I/O ports Hi-Z leakage current
Input current
—
—
—
—
± 10
± 1
µA
µA
IL
I
IN
C
Capacitance
—
—
—
—
12
8
OUT
pF
Ports (as input or output)
C
IN
(6)
V
R
0
—
—
—
100
—
mV
V/ms
V
POR rearm voltage
POR
(7)
0.035
POR rise time ramp rate
POR
V
+V
1.5 ×V
DD
8.5
Monitor mode entry voltage
DD
HI
(8)
Pullup resistors
R
1.8
16
3.3
26
4.8
36
kΩ
kΩ
PU1
PTD6, PTD7
RST, IRQ1, PTA0–PTA6
R
PU2
V
LVI reset voltage
3.6
4.0
4.4
V
LVR5
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
184
Electrical Specifications
Electrical Specifications
5V Control Timing
Table 18-4. DC Electrical Characteristics (5V)
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Typ
NOTES:
1. V = 4.5 to 5.5 Vdc, V = 0 Vdc, T = T to T , unless otherwise noted.
DD
SS
A
L
H
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less
DD
than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
L
run I . Measured with all modules enabled.
DD
4. Wait I measured using external square wave clock source (f = 4MHz); all inputs 0.2 V from rail; no dc loads;
DD
OP
less than 100 pF on all outputs. C = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly af-
L
fects wait I
.
DD
5. STOP I measured with OSC1 grounded, no port pins sourcing current. LVI is disabled.
DD
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V is not reached before the internal POR reset is released, RST must be driven low externally until
DD
minimum V is reached.
DD
8. R
and R
are measured at V = 5.0V
PU1
PU2 DD
18.7 5V Control Tim ing
Table 18-5. Control Timing (5V)
(1)
Symbol
Min
—
Max
8
Unit
MHz
ns
Characteristic
(2)
f
Internal operating frequency
OP
(3)
t
750
—
RST input pulse width low
IRL
NOTES:
1. V = 4.5 to 5.5 Vdc, V = 0 Vdc, T = T to T ; timing shown with respect to 20% V and 70% V , unless otherwise
DD
SS
A
L
H
DD
SS
noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this in-
formation.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Electrical Specifications
185
Ele c tric a l Sp e c ific a tions
18.8 5V Osc illa tor Cha ra c te ristic s
Table 18-6. Oscillator Component Specifications (5V)
Characteristic
Crystal frequency, XTALCLK
RC oscillator frequency, RCCLK
External clock
Symbol
Min
—
2
Typ
10
Max
32
Unit
MHz
MHz
f
OSCXCLK
f
10
12
RCCLK
f
dc
—
32
MHz
OSCXCLK
(1)
reference frequency
(2)
C
—
—
—
—
—
—
—
—
—
—
—
Crystal load capacitance
L
(2)
C
2 × C
Crystal fixed capacitance
1
L
L
(2)
C
2 × C
Crystal tuning capacitance
2
R
Feedback bias resistor
10 MΩ
B
(2), (3)
R
—
Series resistor
S
R
RC oscillator external R
See Figure 18-1
EXT
C
RC oscillator external C
NOTES:
—
10
—
pF
EXT
1. No more than 10% duty cycle deviation from 50%
2. Consult crystal vendor data sheet
3. Not Required for high frequency crystals
14
12
10
8
C
= 10 pF
EXT
MCU
5V @ 25°C
OSC1
6
V
DD
4
R
C
EXT
EXT
2
0
0
10
20
30
(kΩ)
40
50
Resistor, R
EXT
Figure 18-1. RC vs. Frequency (5V @25°C)
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
186
Electrical Specifications
Electrical Specifications
3V DC Electrical Characteristics
18.9 3V DC Ele c tric a l Cha ra c te ristic s
Table 18-7. DC Electrical Characteristics (3V)
(1)
(2)
Symbol
Min
– 0.4
Max
Unit
Characteristic
Typ
Output high voltage (I
= –1.0mA)
LOAD
V
V
—
—
—
9
—
V
OH
DD
PTA0–PTA6, PTB0–PTB7, PTD0–PTD7
Output low voltage (I = 0.8mA)
LOAD
V
—
—
4
0.4
0.5
12
V
V
OL
PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5
Output low voltage (I
PTD6, PTD7
= 20mA)
LOAD
V
OL
LED drives (V = 1.8V)
OL
I
mA
OL
PTA0–PTA5, PTD2, PTD3, PTD6, PTD7
Input high voltage
V
0.7 ×V
V
PTA0–PTA6, PTB0–PTB7, PTD0–PTD7,
RST, IRQ1, OSC1
—
—
V
V
IH
DD
DD
Input low voltage
V
V
0.3 ×V
DD
PTA0–PTA6, PTB0–PTB7, PTD0–PTD7,
RST, IRQ1, OSC1
IL
SS
V
supply current
DD
(3)
—
—
—
—
5
1
4
1
8
mA
mA
mA
µA
Run, f = 2MHz
OP
(4)
I
1.3
4.5
5
Wait (MC68HRC08xxx)
DD
(4)
Wait (MC68HC08xxx)
(5)
Stop
–40°C to 85°C
I
Digital I/O ports Hi-Z leakage current
Input current
—
—
—
—
± 10
± 1
µA
µA
IL
I
IN
C
Capacitance
—
—
—
—
12
8
OUT
pF
Ports (as input or output)
C
IN
(6)
V
R
0
—
—
—
100
—
mV
V/ms
V
POR rearm voltage
POR
(7)
0.035
POR rise time ramp rate
POR
V
+V
1.5 ×V
DD
8.5
Monitor mode entry voltage
DD
HI
(8)
Pullup resistors
R
1.8
16
3.3
26
4.8
36
kΩ
kΩ
PU1
PTD6, PTD7
RST, IRQ1, PTA0–PTA6
R
PU2
V
LVI reset voltage
2.0
2.4
2.69
V
LVR3
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Electrical Specifications
187
Ele c tric a l Sp e c ific a tions
Table 18-7. DC Electrical Characteristics (3V)
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Typ
NOTES:
1. V = 2.7 to 3.3 Vdc, V = 0 Vdc, T = T to T , unless otherwise noted.
DD
SS
A
L
H
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less
DD
than 100 pF on all outputs. C = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
L
run I . Measured with all modules enabled.
DD
4. Wait I measured using external square wave clock source (f = 4MHz); all inputs 0.2 V from rail; no dc loads;
DD
OP
less than 100 pF on all outputs. C = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly af-
L
fects wait I
.
DD
5. STOP I measured with OSC1 grounded, no port pins sourcing current. LVI is disabled.
DD
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V is not reached before the internal POR reset is released, RST must be driven low externally until
DD
minimum V is reached.
DD
8. R
and R
are measured at V = 5.0V
PU1
PU2 DD
18.10 3V Control Tim ing
Table 18-8. Control Timing (3V)
(1)
Symbol
Min
—
Max
4
Unit
MHz
µs
Characteristic
(2)
f
Internal operating frequency
OP
(3)
t
1.5
—
RST input pulse width low
IRL
NOTES:
1. V = 2.7 to 3.3 Vdc, V = 0 Vdc, T = T to T ; timing shown with respect to 20% V and 70% V , unless otherwise
DD
SS
A
L
H
DD
DD
noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this in-
formation.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
188
Electrical Specifications
Electrical Specifications
3V Oscillator Characteristics
18.11 3V Osc illa tor Cha ra c te ristic s
Table 18-9. Oscillator Component Specifications (3V)
Characteristic
Crystal frequency, XTALCLK
RC oscillator frequency, RCCLK
External clock
Symbol
Min
—
2
Typ
8
Max
16
Unit
MHz
MHz
f
OSCXCLK
f
8
12
RCCLK
f
dc
—
16
MHz
OSCXCLK
(1)
reference frequency
(2)
C
—
—
—
—
—
—
—
—
—
—
—
Crystal load capacitance
L
(2)
C
2 × C
Crystal fixed capacitance
1
L
L
(2)
C
2 × C
Crystal tuning capacitance
2
R
Feedback bias resistor
10 MΩ
B
(2), (3)
R
—
Series resistor
S
R
RC oscillator external R
See Figure 18-2
EXT
C
RC oscillator external C
NOTES:
—
10
—
pF
EXT
1. No more than 10% duty cycle deviation from 50%
2. Consult crystal vendor data sheet
3. Not Required for high frequency crystals
14
12
10
8
C
= 10 pF
EXT
MCU
3V @ 25°C
OSC1
6
V
DD
4
R
C
EXT
EXT
2
0
0
10
20
30
(kΩ)
40
50
Resistor, R
EXT
Figure 18-2. RC vs. Frequency (3V @25°C)
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Electrical Specifications
189
Ele c tric a l Sp e c ific a tions
18.12 Typ ic a l Sup p ly Curre nts
14
12
10
8
6
MC68HRC08xxx
4
5.5 V
3.3 V
2
0
0
1
2
3
4
5
6
7
8
9
f
or f
(MHz)
BUS
OP
Figure 18-3. Typical Operating I , with all Modules Turned On (25 °C)
DD
2
1.75
1.50
1.25
1
MC68HRC08xxx
0.75
0.5
0.25
0
5.5 V
3.3 V
0
1
2
3
4
5
6
7
8
f
or f
(MHz)
OP
BUS
Figure 18-4. Typical Wait Mode I , with ADC Turned On (25 °C)
DD
0.5
0.4
0.3
0.2
MC68HRC08xxx
5.5 V
3.3 V
0.1
0
0
1
2
3
4
5
6
7
8
9
f
or f
(MHz)
BUS
OP
Figure 18-5. Typical Stop Mode I , with all Modules Disabled (25 °C)
DD
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
190
Electrical Specifications
Electrical Specifications
ADC Characteristics
18.13 ADC Cha ra c te ristic s
Table 18-10. ADC Characteristics
Characteristic
Supply voltage
Symbol
Min
Max
Unit
Comments
2.7
5.5
V
V
DDAD
(V min)
(V max)
DD
DD
V
V
V
Input voltages
Resolution
V
ADIN
SS
DD
B
8
8
Bits
LSB
AD
A
Absolute accuracy
± 0.5
± 1.5
Includes quantization
AD
t
= 1/f
, tested
AIC
ADIC
f
ADC internal clock
0.5
1.048
MHz
V
ADIC
only at 1 MHz
R
V
V
Conversion range
Power-up time
AD
SS
DD
t
t
t
t
cycles
16
16
5
ADPU
AIC
AIC
AIC
t
cycles
cycles
Conversion time
17
—
ADC
(1)
t
Sample time
ADS
(2)
Z
V
V
= V
= V
Zero input reading
00
FE
—
01
Hex
Hex
pF
ADI
IN
IN
SS
(3)
F
Full-scale reading
Input capacitance
FF
ADI
DD
C
(20) 8
Not tested
ADI
(3)
Input leakage
—
—
± 1
µA
Port B/port D
NOTES:
1. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
3. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Electrical Specifications
191
Ele c tric a l Sp e c ific a tions
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
192
Electrical Specifications
Te c hnic a l Da ta — MC68H(R)C08JL3
Se c tion 19. Me c ha nic a l Sp e c ific a tions
19.1 Conte nts
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
19.3 20-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
19.4 20-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
19.5 28-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
19.6 28-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
19.2 Introd uc tion
This section gives the dimensions for:
• 20-pin plastic dual in-line package (case #738)
• 20-pin small outline integrated circuit package (case #751D)
• 28-pin plastic dual in-line package (case #710)
• 28-pin small outline integrated circuit package (case #751F)
The following figures show the latest package drawings at the time of
this publication. To make sure that you have the latest package
specifications, contact one of the following:
• Local Motorola Sales Office
• Motorola Mfax
– Phone 602-244-6609
– EMAIL rmfax0@email.sps.mot.com
• Worldwide Web (wwweb) at http://motorola.com/sps
Follow Mfax or Worldwide Web on-line instructions to retrieve the current
mechanical specifications.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Mechanical Specifications
193
Me c ha nic a l Sp e c ific a tions
19.3 20-Pin PDIP
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
10
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
1.070
0.260
0.180
0.022
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
1.010
0.240
0.150
0.015
–T–
SEATING
PLANE
K
E
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
F
G
J
K
L
N
E
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
0.25 (0.010)
M
M
0.25 (0.010)
T B
M
N
0
15
0
15
0.020
0.040
0.51
1.01
M
M
T
A
Figure 19-1. 20-Pin PDIP (Case #738)
19.4 20-Pin SOIC
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
10X P
–B–
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
M
M
0.010 (0.25)
B
1
10
MILLIMETERS
INCHES
20X D
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
0.010 (0.25)
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
Figure 19-2. 20-Pin SOIC (Case #751D)
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
194
Mechanical Specifications
Mechanical Specifications
28-Pin PDIP
19.5 28-Pin PDIP
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D), SHALL
BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
28
1
15
14
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
B
MILLIMETERS
INCHES
DIM
A
B
C
D
F
MIN
36.45
13.72
3.94
0.36
1.02
MAX
37.21
14.22
5.08
0.56
1.52
MIN
MAX
1.465
0.560
0.200
0.022
0.060
1.435
0.540
0.155
0.014
0.040
L
C
A
N
G
H
J
K
L
2.54 BSC
0.100 BSC
1.65
0.20
2.92
2.16
0.38
3.43
0.065
0.008
0.115
0.085
0.015
0.135
J
G
H
F
M
K
15.24 BSC
0.600 BSC
D
SEATING
PLANE
M
N
0°
0.51
15°
1.02
0°
0.020
15°
0.040
Figure 19-3. 28-Pin PDIP (Case #710)
19.6 28-Pin SOIC
NOTES:
-A-
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
15
28
1
14X P
M
M
0.010 (0.25)
B
-B-
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE
14
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
28X D
0.010 (0.25)
M
MILLIMETERS
INCHES
M
S
S
T
A
B
DIM
A
B
C
D
MIN
17.80
7.40
2.35
0.35
0.41
MAX
18.05
7.60
2.65
0.49
0.90
MIN
MAX
0.711
0.299
0.104
0.019
0.035
R
X 45
0.701
0.292
0.093
0.014
0.016
C
-T-
SEATING
PLANE
F
26X G
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.23
0.13
0°
0.32
0.29
8°
0.009
0.005
0°
0.013
0.011
8°
K
F
10.01
0.25
10.55
0.75
0.395
0.010
0.415
0.029
J
Figure 19-4. 28-Pin SOIC (Case #751F)
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Technical Data
Mechanical Specifications
195
Me c ha nic a l Sp e c ific a tions
Technical Data
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
196
Mechanical Specifications
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not
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Semiconductors
Motorola > Semiconductors >
68HC908JK3 : Microcontroller
Page Contents:
The MC68HC08JK3 is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and package types.
Features
Documentation
Reference Designs
Tools
Rich Media
Block Diagram
Orderable Parts
Related Links
68HC908JK3 Features
Other Info:
●
●
●
●
●
●
●
●
●
●
●
High-Performance M68HC08 Architecture
Fully Upward-Compatible Object Code with M6805, M146805, and M68HC05 Families
Low-Power Design (Fully Static with Stop and Wait Modes)
5V Nominal Operating Voltage
3V Low-power Operating Voltage
Up to 8MHz Internal Bus Operation
RC-oscillator circuit or Crystal-oscillator options
4096 Bytes of User FLASH or ROM
960 Bytes of Monitor or Self-Check ROM
128 Bytes of On-Chip Random Access Memory (RAM)
10 Channel 8-bit ADC
FAQs
3rd Party Design Help
Training
3rd Party Tool
Vendors
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68HC908JK3 Documentation
Documentation
Application Note
Size Rev Date Last
Order
ID
Name
Vendor ID Format
K
#
Modified Availability
In-Circuit Programming of FLASH Memory in the
MC68HC908JL3
MOTOROLA
pdf
AN-HK-33
AN1050_D
AN1218/D
AN1219/D
AN1219SW
AN1221/D
AN1221SW
0
1
3/27/2000
Designing for Electromagnetic Compatibility (EMC) with
HCMOS Microcontrollers
MOTOROLA
pdf
82
347
177
77
0
2
1
0
0
0
1/01/2000
1/01/1993
1/01/1997
1/01/1995
1/01/1993
1/01/1995
-
MOTOROLA
pdf
HC05 to HC08 Optimization
MOTOROLA
pdf
M68HC08 Integer Math Routines
Software Files for AN1219 zipped
MOTOROLA
zip
-
-
Hamming Error Control Coding Techniques with the HC08 MOTOROLA
MCU
pdf
zip
63
MOTOROLA
Software Files for AN1221 zipped
55
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
AN1222/D
AN1222SW
AN1259/D
AN1263/D
AN1516/D
AN1705/D
AN1744/D
AN1752/D
AN1771/D
AN1775/D
AN1783/D
AN1818/D
AN1820/D
AN1820SW
Arithmetic Waveform Synthesis with the HC05/08 MCUs
Software Files for AN1222 zipped
pdf
zip
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
zip
24
20
78
104
77
67
80
213
250
86
48
84
55
2
0
0
0
0
2
0
0
1
0
1
1
0
0
0
1/01/1993
1/01/1995
1/01/1995
1/01/1995
1/24/2003
1/01/1999
1/01/1998
5/07/2001
1/01/1998
1/01/1998
1/01/1999
1/01/1999
1/01/1999
1/01/1998
-
System Design and Layout Techniques for Noise
Reduction in MCU-Based Systems
Designing for Electromagnetic Compatibility with Single-
Chip Microcontrollers
Liquid Level Control Using a Motorola Pressure Sensor
Noise Reduction Techniques for Microcontroller-Based
Systems
Resetting Microcontrollers During Power Transitions
Data Structures for 8-Bit Microcontrollers
Precision Sine-Wave Tone Synthesis Using 8-Bit MCUs
Expanding Digital Input with an A/D Converter
Determining MCU Oscillator Start-Up Parameters
Software SCI Routines with the 16-Bit Timer Module
Software I2C Communications
Software files for AN1820 zipped
-
Using MC68HC908 On-Chip FLASH Programming
Routines ROM-Resident Routines in the MC68HC908GR8, MOTOROLA
MC68HC908KX8, MC68HC908JL3, MC68HC908JK3, and
the MC68HC908JB8
AN1831/D
pdf
314
2
9/27/2001
MOTOROLA
AN1837/D
AN1853/D
AN2093/D
AN2103/D
Non-Volatile Memory Technology Overview
pdf
pdf
pdf
pdf
116
221
36
0
0
0
0
3/27/2000
6/22/2000
Embedding Microcontrollers in Domestic Refrigeration
Appliances
MOTOROLA
MOTOROLA
MOTOROLA
Creating Efficient C Code for the MC68HC08
Local Interconnect Network (LIN) Demonstration
1/01/2000
12/01/2000
953
Connecting an M68HC08 Family Microcontroller to an
Internet Service Provider (ISP) Using the Point-to-Point
Protocol (PPP)
MOTOROLA
MOTOROLA
AN2120/D
pdf
741
0
5/20/2001
AN2120SW
AN2149/D
AN2158/D
AN2159/D
AN2159SW
AN2295
Software for AN2120, zip format
zip
pdf
pdf
pdf
zip
pdf
zip
31 1.0 7/31/2002
-
Compressor Induction Motor Stall and Rotation Detection MOTOROLA
using Microcontrollers
127
374
129
182
738
0
0
0
1
4
5/30/2001
Designing with the MC68HC908JL/JK Microcontroller
Family
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
11/20/2001
Digital Direct Current Ignition System Using HC08
Microcontrollers
11/20/2001
AN2159SW
3/08/2002
-
-
10/29/2003
Developer's Serial Bootloader for M68HC08
Software for AN2295
10/21/2003
AN2295SW
725 4.0
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
1628
AN2321/D
AN2342
Designing for Board Level Electromagnetic Compatibility
pdf
pdf
pdf
pdf
zip
0
0
0
0
0
8/15/2002
9/25/2002
Opto Isolation Circuits For In Circuit Debugging of
68HC9(S)12 and 68HC908 Microcontrollers
155
297
530
59
AN2438/D
AN2504
ADC Definitions and Specifications
2/21/2003
10/15/2003
On-Chip FLASH Programming API for CodeWarrior
Software files for application note AN2504
10/21/2003
AN2504SW
-
Brochure
ID
Size Rev Date Last
Order
Name
Vendor ID Format
K
#
Modified Availability
MOTOROLA
pdf
118
8/06/2001
BR1785/D
BR1822
68HC908JL/JK Family Brochure
Embedded Flash MCU Overview
0
MOTOROLA
pdf
174
-
-
MOTOROLA
pdf
5/21/2003
BR68HC08FAMAM/D
FLYREMBEDFLASH/D
68HC08 Family: High Performance and Flexibility
57
68
2
2
Embedded Flash: Changing the Technology World for MOTOROLA
the Better
5/21/2003
pdf
Data Sheets
Size Rev Date Last
Order
ID
Name
Vendor ID Format
K
#
Modified Availability
68HC08JL3, 68HRC08JL3, 68HC08JK3, 68HRC08JK3,
68HC08JK1, 68HRC08JK1 Advance Information
MOTOROLA
pdf
2007
MC68HC08JL3/D
4
3/27/2000
-
MC68H(R)C908JK1/MC68H(R)C908JK3/MC68H(R)C908JL3 MOTOROLA
Technical Data
MC68HC908JL3/H
MC68HC908JL3E/D
pdf
pdf
580
1
2
1/10/1999
MC68H(R)C908JL3E/ MC68H(R)C908JK3E/
MC68H(R)C908JK1E Technical Data
MOTOROLA
1549
12/02/2002
Engineering Bulletin
Size Rev Date Last
Order
ID
Name
Vendor ID Format
K
#
Modified Availability
RAM Data Retention Considerations for Motorola
Microcontrollers
MOTOROLA
pdf
EB349/D
EB367/D
EB389/D
EB390/D
EB396/D
EB398
45
1
6/22/2000
In-Circuit Programming of FLASH Memory Using the
Monitor Mode for the MC68HC908JL/JK
MOTOROLA
pdf
10/13/2000
316
0
1
0
0
0
0
TOF Consideration when Measuring a Long Input Capture MOTOROLA
Event
pdf
pdf
pdf
pdf
pdf
55
4/15/2002
5/09/2002
6/19/2002
8/13/2002
8/14/2002
Porting the AN2120/D UDP/IP Code to the Avnet
Evaluation Board
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
1501
Use of OSC2/XTAL as a Clock Output on Motorola
Microcontrollers
49
0
Techniques to Protect MCU Applications Against
Malfunction Due to Code Run-Away
Interrupt Handling Considerations When Modifying
EEPROM on HC08 Microcontrollers
EB608/D
96
Errata - Click here for important errata information
Size Rev Date Last
Order
ID
Name
Vendor ID Format
K
#
Modified Availability
MOTOROLA
pdf
12/13/2002
-
MSE908JK3_2J88Y/D
Mask Set Errata for MC68HC908JK3 Mask 2J88Y
60
0
Fact Sheets
ID
Date Last
Modified
Name
Vendor ID
Format Size K Rev #
Order Availability
68HC908JK-JLPB/D
8-bit Microcontroller
Development Studio
MOTOROLA
MOTOROLA
pdf
pdf
62
48
1
2
4/03/2002
5/13/2002
CWDEVSTUDFACTHC08
-
Product Change Notices
Size
K
Date Last
Modified
Order
Availability
ID
Name
Vendor ID Format
Rev #
PCN8299
ADD FAB SITE FOR 908JL3E/JK3E/JK1E MOTOROLA
htm
6
0
12/04/2002
-
Reference Manual
ID
Size Rev Date Last
Order
Name
Vendor ID Format
K
#
Modified Availability
MOTOROLA
pdf
1/01/1996
ADCRM/AD
Analog-to-Digital Reference Manual
CPU08RM Central Processor Unit Reference Manual
231
2666
0
MOTOROLA
pdf
4/03/2002
2/20/2001
CPU08RM/AD
3
0
Passive Infrared (PIR) Intruder Detection Using the
MC68HC908JK1/3, Incorporating Remote Control
Adjustment Using the MC68HC908GP32
MOTOROLA
pdf
2504
1845
379
DRM001/D
USB08 Universal Serial Bus Evaluation Board Using the
MC68HC908JB8 Designer Reference Manual
MOTOROLA
pdf
4/12/2001
5/30/2003
1/10/1996
DRM002/D
DRM011/D
TIM08RM/AD
0
0
Direct Current Ignition Reference Design Designer
Reference Manual
MOTOROLA
pdf
MOTOROLA
pdf
TIM08 Timer Interface Module Reference Manual
771 1.0
Selector Guide
ID
Size Rev Date Last
Order
Name
Vendor ID Format
K
#
Modified Availability
MOTOROLA
pdf
579
10/24/2003
SG1002
SG1006
SG1010
SG1011
SG2000CR
Analog Selector Guide - Quarter 4, 2003
Microcontrollers Selector Guide - Quarter 4, 2003
Sensors Selector Guide - Quarter 4, 2003
0
MOTOROLA
pdf
826
219
287
10/24/2003
10/24/2003
10/24/2003
11/11/2003
0
0
0
3
MOTOROLA
pdf
Software and Development Tools Selector Guide - Quarter MOTOROLA
4, 2003
pdf
pdf
MOTOROLA
Application Selector Guide Index and Cross-Reference.
95
0
Application Summary Home Appliances - Cooking
Products. Microcontrollers provide intelligent management MOTOROLA
programs delivering high precision control over the cooking
process.
12/16/2002
SG2036
SG2037
SG2038
pdf
pdf
pdf
1
2
1
Application Selector Guide - Home Appliances
DISHWASHERS
MOTOROLA
MOTOROLA
MOTOROLA
0
6/17/2003
Application Summary - Home Appliances - Refrigerators
and Freezers. Microcontrollers maximize appliance
efficiency while supporting a variety of features in
refrigerators and freezers.
12/16/2002
0
Application Selector Guide - Vacuum Cleaners Vacuum
Cleaners
SG2039
SG2040
pdf
pdf
0
0
0
2
6/17/2003
6/17/2003
Application Selector Guide - Home Applicances WASHING MOTOROLA
MACHINES
Application Summary - Home Appliances. Dryers. New
dryer features make this application more energy efficient MOTOROLA
and better able to meet consumer demands for improved
control.
12/16/2002
SG2044
pdf
0
1
Users Guide
ID
Size Rev Date Last
Order
Name
Vendor ID Format
K
#
Modified Availability
CodeWarrior™ Development Studio for 68HC08 Quick
Start Guide
MOTOROLA
pdf
2847
9/20/2002
-
CDSWHC08QS
2.1
Return to Top
68HC908JK3 Reference Designs
Reference Designs
Size Rev
Order
Availability
ID
Name
Vendor ID Format
K
#
Passive Infra Red (PIR) for Security Peripherals and Other Remote
Networks
MOTOROLA
-
RD68HC08PIR
Return to Top
-
-
-
68HC908JK3 Tools
Hardware Tools
Emulators/Probes/Wigglers
Size Rev
Order
Availability
ID
Name
Vendor ID Format
K
#
IC10000
IC20000
IC40000
ISYS
ISYS
ISYS
iC1000 PowerEmulator
iC2000 PowerEmulator
iC4000 ActiveEmulator
-
-
-
-
-
-
-
-
-
-
-
-
In-Circuit, Real-Time Debugger/Programmer for Motorola 68HC08
Family (USB)
INDART-HC08/D
SOFTEC
-
-
-
-
Evaluation/Development Boards and Systems
ID
Name
Vendor ID
Format Size K Rev # Order Availability
KITMMDS08JL
Modular Development System (MMDS) Kits
MOTOROLA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
KITMMEVS08JL
M68CBL05C
Modular Evaluation System (MMEVS)
Low-noise Flex Cable
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
METROWERKS
M68ICS08JLJK
M68EML08JLJK
M68CYCLONE08
M68ICS08JLJK Development Tool Kit
Emulation Module
MON08 Cyclone
M68MULTILINK08
METROWERKS
OZTECH
MON08 Multilink
-
-
-
-
-
-
OZTEC-08 STARTER KIT
OZTEC-08 Starter Kit
-
Programmers
ID
Name
Vendor ID Format Size K Rev # Order Availability
MP8011A
SOFTEC
SYSGEN
SYSGEN
SYSGEN
Gang Programmer Base Unit
Automated Programming System
Universal Programmer
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AP520
POWERLAB
T9600
High-speed universal gang programmer
Software
Application Software
Code Examples
Size Rev
Order
Availability
ID
Name
Vendor ID Format
K
#
HC08 Software Example: Subroutine that delays for a whole
number of milliseconds
MOTOROLA
zip
HC08DELAYSW
HC08EXSW
2
-
-
HC08 Software Example: Library containing software
examples in assembly for 68HC08
MOTOROLA
zip
14
-
-
Operating Systems
ID
Name
Vendor ID
Format
Size K
Rev #
Order Availability
CMX-TINY+
CMX
CMX-Tiny+
-
-
-
-
Software Tools
Assemblers
Size Rev
Order
Availability
ID
Name
ADX-08 Macro Assembler-Linker and IDE
Vendor ID Format
K
#
ADX-08
AX6808
AVOCET
COSMIC
-
-
-
-
-
AX6808 relocatable and absolute macro assembler for HC08 and
HCS08
-
-
-
Compilers
ID
Name
Vendor ID Format Size K Rev # Order Availability
CX6808S
COSMIC
IMAGE
CX6808 C Cross Compiler for HC08 and HCS08
ICC08 V6 STD
-
-
-
-
-
-
-
-
ICC08
Debuggers
ID
Size Rev
Order
Availability
Name
ZAP 6808 MON08 Debugger and Flash Programmer
Vendor ID Format
K
#
ZAP 6808 MON08 debugger uses the 68HC08’s on-chip monitor
interface to provide a real-time ANSI C and assembly source level
debugger including FLASH programming, FLASH security and
hardware breakpoint support.
ZAP 6808 MON08
MOTOROLA
-
-
-
-
ZAP 6808 MMDS
COSMIC
ZAP 6808 MMDS Debugger
-
-
-
-
ZAP 6808 SIM
NOICE08
COSMIC
IMAGE
ZAP 6808 Simulator Debugger
NoICE08
-
-
-
-
-
-
-
-
IDE (Integrated Development Environment)
Size Rev
Order
Availability
ID
Name
Vendor ID
Format
K
#
CDCWSEHC08
CWHC08PRO
METROWERKS
METROWERKS
CodeWarrior Development Studio™ for HC(S)08 Special Edition
-
-
-
-
-
CodeWarrior Development Studio for Motorola HC08
Microcontrollers Professional Edition
-
-
CodeWarrior Development Studio for Motorola HC08
Microcontrollers Standard Edition
CWHC08STD
CX6808LT4
IDEA08
METROWERKS
COSMIC
COSMIC
ISYS
-
-
-
-
-
-
-
-
-
-
-
-
HC08 Development Tool Suite 4K Lite (FREE)
-
-
-
IDEA08 integrated development environment for HC08 and HCS08
IC-SW-OPR
winIDEA
Return to Top
Rich Media
Rich Media
Webcast
Size Rev
Order
Availability
ID
Name
Vendor ID Format
K
#
CodeWarrior Development Tools for 68HC08 and HCS12
Microcontrollers.
Listen to our webcast for an overview of some of the challenges
that developers face and an explanation of the CodeWarrior
tools that help to address these challenges.
RMWC_CODEWARRIOR
RMWC_QFAMILY
MOTOROLA
html
4
0.0
-
-
8-bit Microcontroller Overview and Q-Family of Flash
Microcontrollers
Listen to our companion webcasts to learn about Motorola's
recent 8-bit products and services-especially the HC08 Q-
Family-that offer maximum design flexibility while helping you
get to market fast.
MOTOROLA
htm
5
1.1
Return to Top
Orderable Parts Information
Budgetary
Tape
and
Reel
Price
QTY 1000+
($US)
Package
Info
Additional
Info
Order
Availability
Life Cycle Description (code)
PartNumber
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
more
more
more
more
more
KMC908JK3CDW
KMC908JK3CP
No
No
No
No
No
$1.65
$1.65
$2.47
$2.47
$1.65
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
KMC908JK3ECDW
KMC908JK3ECP
KMCR908JK3CDW
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PRODUCT STABLE
PDIP 20
SOIC 20W
PDIP 20
more
more
more
more
more
more
more
more
more
more
more
more
more
more
more
more
more
more
more
more
more
more
more
more
more
KMCR908JK3CP
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
$1.40
$2.47
$2.47
$1.65
$1.65
$1.65
$1.65
$1.81
$1.25
$1.81
$1.81
$1.65
$1.65
$1.65
$1.65
$1.81
$1.81
$1.65
$1.65
$1.81
$1.81
$1.73
$1.90
$1.73
$1.90
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
KMCR98JK3ECDW
PRODUCT STABLE
GROWTH/MATURITY(3)
KMCR98JK3ECP
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
MC68HC908JK3CDW
MC68HC908JK3CP
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
MC68HC908JK3ECDW
MC68HC908JK3ECP
MC68HC908JK3EMDW
MC68HC908JK3EMP
MC68HC908JK3MDW
MC68HC908JK3MP
MC68HLC908JK3CDW
MC68HLC908JK3CP
MC68HRC908JK3CDW
MC68HRC908JK3CP
MC68HRC908JK3MDW
MC68HRC908JK3MP
MC68HRC98JK3ECDW
MC68HRC98JK3ECP
MC68HRC98JK3EMDW
MC68HRC98JK3EMP
MCHC908JK3CDWR2
MCHC908JK3MDWR2
MCHRC908JK3CDWR2
MCHRC908JK3MDWR2
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
SOIC 20W
SOIC 20W
SOIC 20W
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
NOTE: Are you looking for an obsolete orderable part? Click HERE to check our distributors' inventory.
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Semiconductors
Motorola > Semiconductors >
68HC908JK1 : Microcontroller
Page Contents:
The MC68HC908JK1 is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and package types.
Features
Documentation
Reference Designs
Tools
Rich Media
Block Diagram
Orderable Parts
Related Links
68HC908JK1 Features
Other Info:
●
●
●
●
●
●
●
●
●
●
●
High-Performance M68HC08 Architecture
Fully Upward-Compatible Object Code with M6805, M146805, and M68HC05 Families
Low-Power Design (Fully Static with Stop and Wait Modes)
5V Nominal Operating Voltage
3V Low-power Operating Voltage
Up to 8MHz Internal Bus Operation
RC-oscillator circuit or Crystal-oscillator options
1.5 KBytes of User FLASH
960 Bytes of Monitor or Self-Check ROM
128 Bytes of On-Chip Random Access Memory (RAM)
10 Channel 8-bit ADC
FAQs
3rd Party Design Help
Training
3rd Party Tool
Vendors
Rate this Page
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Care to Comment?
68HC908JK1 Documentation
Documentation
Application Note
Size Rev Date Last
Order
ID
Name
Vendor ID Format
K
#
Modified Availability
Designing for Electromagnetic Compatibility (EMC) with
HCMOS Microcontrollers
MOTOROLA
pdf
AN1050_D
AN1218/D
AN1219/D
AN1219SW
AN1221/D
AN1221SW
AN1222/D
82
0
1/01/2000
1/01/1993
1/01/1997
1/01/1995
1/01/1993
1/01/1995
1/01/1993
-
MOTOROLA
pdf
HC05 to HC08 Optimization
347
177
77
2
1
0
0
0
0
MOTOROLA
pdf
M68HC08 Integer Math Routines
Software Files for AN1219 zipped
MOTOROLA
zip
-
-
Hamming Error Control Coding Techniques with the HC08 MOTOROLA
MCU
pdf
zip
pdf
63
MOTOROLA
Software Files for AN1221 zipped
55
MOTOROLA
Arithmetic Waveform Synthesis with the HC05/08 MCUs
24
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
AN1222SW
AN1259/D
AN1263/D
AN1516/D
AN1705/D
AN1744/D
AN1752/D
AN1771/D
AN1775/D
AN1783/D
AN1818/D
AN1820/D
AN1820SW
AN1837/D
AN1853/D
AN2093/D
AN2103/D
Software Files for AN1222 zipped
zip
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
zip
pdf
pdf
pdf
pdf
20
78
0
0
0
2
0
0
1
0
1
1
0
0
0
0
0
0
0
1/01/1995
1/01/1995
1/01/1995
1/24/2003
1/01/1999
1/01/1998
5/07/2001
1/01/1998
1/01/1998
1/01/1999
1/01/1999
1/01/1999
1/01/1998
3/27/2000
6/22/2000
-
System Design and Layout Techniques for Noise
Reduction in MCU-Based Systems
Designing for Electromagnetic Compatibility with Single-
Chip Microcontrollers
104
77
Liquid Level Control Using a Motorola Pressure Sensor
Noise Reduction Techniques for Microcontroller-Based
Systems
67
Resetting Microcontrollers During Power Transitions
Data Structures for 8-Bit Microcontrollers
Precision Sine-Wave Tone Synthesis Using 8-Bit MCUs
Expanding Digital Input with an A/D Converter
Determining MCU Oscillator Start-Up Parameters
Software SCI Routines with the 16-Bit Timer Module
Software I2C Communications
80
213
250
86
48
84
55
Software files for AN1820 zipped
2
-
Non-Volatile Memory Technology Overview
116
221
36
Embedding Microcontrollers in Domestic Refrigeration
Appliances
Creating Efficient C Code for the MC68HC08
Local Interconnect Network (LIN) Demonstration
1/01/2000
12/01/2000
953
Connecting an M68HC08 Family Microcontroller to an
Internet Service Provider (ISP) Using the Point-to-Point
Protocol (PPP)
MOTOROLA
MOTOROLA
AN2120/D
pdf
741
0
5/20/2001
AN2120SW
AN2149/D
AN2158/D
AN2159/D
AN2159SW
AN2295
Software for AN2120, zip format
zip
pdf
pdf
pdf
zip
pdf
zip
pdf
pdf
pdf
31 1.0 7/31/2002
-
Compressor Induction Motor Stall and Rotation Detection MOTOROLA
using Microcontrollers
127
374
129
182
738
0
0
0
1
4
5/30/2001
Designing with the MC68HC908JL/JK Microcontroller
Family
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
11/20/2001
Digital Direct Current Ignition System Using HC08
Microcontrollers
11/20/2001
AN2159SW
3/08/2002
-
-
10/29/2003
Developer's Serial Bootloader for M68HC08
Software for AN2295
10/21/2003
AN2295SW
AN2321/D
AN2342
725 4.0
1628
0
Designing for Board Level Electromagnetic Compatibility
8/15/2002
9/25/2002
2/21/2003
Opto Isolation Circuits For In Circuit Debugging of
68HC9(S)12 and 68HC908 Microcontrollers
155
297
0
0
AN2438/D
ADC Definitions and Specifications
MOTOROLA
MOTOROLA
10/15/2003
10/21/2003
AN2504
On-Chip FLASH Programming API for CodeWarrior
Software files for application note AN2504
pdf
zip
530
59
0
0
AN2504SW
-
Brochure
ID
Size Rev Date Last
Order
Name
Vendor ID Format
K
#
Modified Availability
MOTOROLA
pdf
118
8/06/2001
BR1785/D
BR1822
68HC908JL/JK Family Brochure
Embedded Flash MCU Overview
0
MOTOROLA
pdf
174
-
-
MOTOROLA
pdf
5/21/2003
BR68HC08FAMAM/D
FLYREMBEDFLASH/D
68HC08 Family: High Performance and Flexibility
57
68
2
2
Embedded Flash: Changing the Technology World for MOTOROLA
the Better
5/21/2003
pdf
Data Sheets
Size Rev Date Last
Order
ID
Name
Vendor ID Format
K
#
Modified Availability
68HC08JL3, 68HRC08JL3, 68HC08JK3, 68HRC08JK3,
68HC08JK1, 68HRC08JK1 Advance Information
MOTOROLA
pdf
2007
MC68HC08JL3/D
4
3/27/2000
-
MC68H(R)C908JK1/MC68H(R)C908JK3/MC68H(R)C908JL3 MOTOROLA
Technical Data
MC68HC908JL3/H
MC68HC908JL3E/D
pdf
pdf
580
1
2
1/10/1999
MC68H(R)C908JL3E/ MC68H(R)C908JK3E/
MC68H(R)C908JK1E Technical Data
MOTOROLA
1549
12/02/2002
Engineering Bulletin
Size Rev Date Last
Order
ID
Name
Vendor ID Format
K
#
Modified Availability
RAM Data Retention Considerations for Motorola
Microcontrollers
MOTOROLA
pdf
EB349/D
EB367/D
EB389/D
EB390/D
EB396/D
EB398
45
1
6/22/2000
In-Circuit Programming of FLASH Memory Using the
Monitor Mode for the MC68HC908JL/JK
MOTOROLA
pdf
10/13/2000
316
0
1
0
0
0
0
TOF Consideration when Measuring a Long Input Capture MOTOROLA
Event
pdf
pdf
pdf
pdf
pdf
55
4/15/2002
5/09/2002
6/19/2002
8/13/2002
8/14/2002
Porting the AN2120/D UDP/IP Code to the Avnet
Evaluation Board
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
1501
Use of OSC2/XTAL as a Clock Output on Motorola
Microcontrollers
49
0
Techniques to Protect MCU Applications Against
Malfunction Due to Code Run-Away
Interrupt Handling Considerations When Modifying
EEPROM on HC08 Microcontrollers
EB608/D
96
Errata - Click here for important errata information
Size Rev Date Last
Order
ID
Name
Vendor ID Format
K
#
Modified Availability
MOTOROLA
pdf
12/13/2002
-
MSE908JK1_2J88Y/D
Mask Set Errata for MC68HC908JK1 Mask 2J88Y
60
0
Fact Sheets
ID
Date Last
Modified
Name
Vendor ID
Format Size K Rev #
Order Availability
68HC908JK-JLPB/D
8-bit Microcontroller
Development Studio
MOTOROLA
MOTOROLA
pdf
pdf
62
48
1
2
4/03/2002
5/13/2002
CWDEVSTUDFACTHC08
-
Product Change Notices
Size
K
Date Last
Modified
Order
Availability
ID
Name
Vendor ID Format
Rev #
PCN8299
ADD FAB SITE FOR 908JL3E/JK3E/JK1E MOTOROLA
htm
6
0
12/04/2002
-
Reference Manual
ID
Size Rev Date Last
Order
Name
Vendor ID Format
K
#
Modified Availability
MOTOROLA
pdf
1/01/1996
ADCRM/AD
Analog-to-Digital Reference Manual
CPU08RM Central Processor Unit Reference Manual
231
2666
0
MOTOROLA
pdf
4/03/2002
2/20/2001
CPU08RM/AD
3
0
0
Passive Infrared (PIR) Intruder Detection Using the
MC68HC908JK1/3, Incorporating Remote Control
Adjustment Using the MC68HC908GP32
MOTOROLA
pdf
2504
1845
DRM001/D
USB08 Universal Serial Bus Evaluation Board Using the
MC68HC908JB8 Designer Reference Manual
MOTOROLA
pdf
4/12/2001
1/10/1996
DRM002/D
MOTOROLA
pdf
TIM08RM/AD
TIM08 Timer Interface Module Reference Manual
771 1.0
Roadmap
ID
Name
Vendor ID Format Size K Rev # Date Last Modified Order Availability
MOTOROLA pdf 30 9/01/2002
8BITMCURD
8-Bit MCU Family Roadmap
0
-
Selector Guide
ID
Size Rev Date Last
Order
Name
Vendor ID Format
K
#
Modified Availability
MOTOROLA
pdf
579
10/24/2003
SG1002
SG1006
SG1010
SG1011
SG2000CR
Analog Selector Guide - Quarter 4, 2003
Microcontrollers Selector Guide - Quarter 4, 2003
Sensors Selector Guide - Quarter 4, 2003
0
MOTOROLA
pdf
826
219
287
10/24/2003
10/24/2003
10/24/2003
11/11/2003
0
0
0
3
MOTOROLA
pdf
Software and Development Tools Selector Guide - Quarter MOTOROLA
4, 2003
pdf
pdf
MOTOROLA
Application Selector Guide Index and Cross-Reference.
95
0
Application Summary Home Appliances - Cooking
Products. Microcontrollers provide intelligent management MOTOROLA
programs delivering high precision control over the cooking
process.
12/16/2002
SG2036
SG2037
SG2038
pdf
pdf
pdf
1
2
1
Application Selector Guide - Home Appliances
DISHWASHERS
MOTOROLA
MOTOROLA
MOTOROLA
0
6/17/2003
Application Summary - Home Appliances - Refrigerators
and Freezers. Microcontrollers maximize appliance
efficiency while supporting a variety of features in
refrigerators and freezers.
12/16/2002
0
Application Selector Guide - Vacuum Cleaners Vacuum
Cleaners
SG2039
SG2040
pdf
pdf
0
0
0
2
6/17/2003
6/17/2003
Application Selector Guide - Home Applicances WASHING MOTOROLA
MACHINES
Application Summary - Home Appliances. Dryers. New
dryer features make this application more energy efficient MOTOROLA
and better able to meet consumer demands for improved
control.
12/16/2002
SG2044
pdf
0
1
Users Guide
ID
Size Rev Date Last
Order
Name
Vendor ID Format
K
#
Modified Availability
CodeWarrior™ Development Studio for 68HC08 Quick
Start Guide
MOTOROLA
pdf
2847
9/20/2002
-
CDSWHC08QS
2.1
Return to Top
68HC908JK1 Reference Designs
Reference Designs
Size Rev
Order
Availability
ID
Name
Vendor ID Format
K
#
Passive Infra Red (PIR) for Security Peripherals and Other Remote
Networks
MOTOROLA
-
RD68HC08PIR
Return to Top
-
-
-
68HC908JK1 Tools
Hardware Tools
Emulators/Probes/Wigglers
Size Rev
Order
Availability
ID
Name
Vendor ID Format
K
#
IC10000
IC20000
IC40000
ISYS
ISYS
ISYS
iC1000 PowerEmulator
iC2000 PowerEmulator
iC4000 ActiveEmulator
-
-
-
-
-
-
-
-
-
-
-
-
In-Circuit, Real-Time Debugger/Programmer for Motorola 68HC08
Family (USB)
INDART-HC08/D
SOFTEC
-
-
-
-
Evaluation/Development Boards and Systems
ID
Name
Vendor ID
Format Size K Rev # Order Availability
KITMMDS08JL
Modular Development System (MMDS) Kits
MOTOROLA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
KITMMEVS08JL
M68CBL05C
Modular Evaluation System (MMEVS)
Low-noise Flex Cable
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
METROWERKS
M68ICS08JLJK
M68EML08JLJK
M68CYCLONE08
M68ICS08JLJK Development Tool Kit
Emulation Module
MON08 Cyclone
M68MULTILINK08
METROWERKS
OZTECH
MON08 Multilink
-
-
-
-
-
-
OZTEC-08 STARTER KIT
OZTEC-08 Starter Kit
-
Programmers
ID
Name
Vendor ID
Format Size K Rev #
Order Availability
MP8011A
POWERLAB
SOFTEC
SYSGEN
Gang Programmer Base Unit
Universal Programmer
-
-
-
-
-
-
-
-
Software
Application Software
Code Examples
Size Rev
Order
Availability
ID
Name
Vendor ID Format
K
#
HC08 Software Example: Subroutine that delays for a whole
number of milliseconds
MOTOROLA
zip
HC08DELAYSW
HC08EXSW
2
-
-
-
HC08 Software Example: Library containing software
examples in assembly for 68HC08
MOTOROLA
zip
14
-
Operating Systems
ID
Name
Vendor ID
Format
Size K
Rev #
Order Availability
CMX-TINY+
CMX
CMX-Tiny+
-
-
-
-
Software Tools
Assemblers
Size Rev
Order
Availability
ID
Name
ADX-08 Macro Assembler-Linker and IDE
Vendor ID Format
K
#
ADX-08
AX6808
AVOCET
COSMIC
-
-
-
-
-
AX6808 relocatable and absolute macro assembler for HC08 and
HCS08
-
-
-
Compilers
ID
Name
Vendor ID Format Size K Rev # Order Availability
CX6808S
COSMIC
IMAGE
CX6808 C Cross Compiler for HC08 and HCS08
ICC08 V6 STD
-
-
-
-
-
-
-
-
ICC08
Debuggers
ID
Size Rev
Order
Availability
Name
ZAP 6808 MON08 Debugger and Flash Programmer
Vendor ID Format
K
#
ZAP 6808 MON08 debugger uses the 68HC08’s on-chip monitor
interface to provide a real-time ANSI C and assembly source level
debugger including FLASH programming, FLASH security and
hardware breakpoint support.
ZAP 6808 MON08
MOTOROLA
-
-
-
-
ZAP 6808 MMDS
COSMIC
ZAP 6808 MMDS Debugger
-
-
-
-
ZAP 6808 SIM
NOICE08
COSMIC
IMAGE
ZAP 6808 Simulator Debugger
NoICE08
-
-
-
-
-
-
-
-
IDE (Integrated Development Environment)
Size Rev
Order
Availability
ID
Name
Vendor ID
Format
K
#
CDCWSEHC08
CWHC08PRO
METROWERKS
METROWERKS
CodeWarrior Development Studio™ for HC(S)08 Special Edition
-
-
-
-
-
CodeWarrior Development Studio for Motorola HC08
Microcontrollers Professional Edition
-
-
CodeWarrior Development Studio for Motorola HC08
Microcontrollers Standard Edition
CWHC08STD
CX6808LT4
IDEA08
METROWERKS
COSMIC
COSMIC
ISYS
-
-
-
-
-
-
-
-
-
-
-
-
HC08 Development Tool Suite 4K Lite (FREE)
-
-
-
IDEA08 integrated development environment for HC08 and HCS08
IC-SW-OPR
winIDEA
Return to Top
Rich Media
Rich Media
Webcast
Size Rev
Order
Availability
ID
Name
Vendor ID Format
K
#
CodeWarrior Development Tools for 68HC08 and HCS12
Microcontrollers.
Listen to our webcast for an overview of some of the challenges
that developers face and an explanation of the CodeWarrior
tools that help to address these challenges.
RMWC_CODEWARRIOR
MOTOROLA
html
4
0.0
-
-
8-bit Microcontroller Overview and Q-Family of Flash
Microcontrollers
Listen to our companion webcasts to learn about Motorola's
recent 8-bit products and services-especially the HC08 Q-
Family-that offer maximum design flexibility while helping you
get to market fast.
MOTOROLA
htm
RMWC_QFAMILY
5
1.1
Return to Top
Orderable Parts Information
Budgetary
Tape
and
Reel
Price
QTY 1000+
($US)
Package
Info
Additional
Info
Order
Availability
Life Cycle Description (code)
PartNumber
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
more
more
more
more
more
more
more
more
more
more
more
more
MC68HC908JK1CDW
MC68HC908JK1CP
No
No
No
No
No
No
No
No
No
No
No
No
$1.25
$1.25
$1.25
$1.25
$1.38
$1.38
$1.38
$1.36
$1.25
$1.25
$1.25
$1.25
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
MC68HC908JK1ECDW
MC68HC908JK1ECP
MC68HC908JK1EMDW
MC68HC908JK1EMP
MC68HC908JK1MDW
MC68HC908JK1MP
MC68HLC908JK1CDW
MC68HLC908JK1CP
MC68HRC908JK1CDW
MC68HRC908JK1CP
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
more
more
more
more
more
more
more
more
more
more
MC68HRC908JK1MDW
MC68HRC908JK1MP
MC68HRC98JK1ECDW
MC68HRC98JK1ECP
MC68HRC98JK1EMDW
MC68HRC98JK1EMP
MCHC908JK1CDWR2
MCHC908JK1MDWR2
MCHRC908JK1CDWR2
MCHRC908JK1MDWR2
No
No
$1.38
$1.38
$1.25
$1.25
$1.38
$1.38
$1.33
$1.46
$1.33
$1.46
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
No
PRODUCT STABLE
GROWTH/MATURITY(3)
No
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
PDIP 20
No
PRODUCT STABLE
GROWTH/MATURITY(3)
No
PRODUCT STABLE
GROWTH/MATURITY(3)
SOIC 20W
SOIC 20W
SOIC 20W
SOIC 20W
Yes
Yes
Yes
Yes
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
PRODUCT STABLE
GROWTH/MATURITY(3)
NOTE: Are you looking for an obsolete orderable part? Click HERE to check our distributors' inventory.
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