MC68SEC000PB20 [MOTOROLA]
Addendum to M68000 User Manual; 增编M68000用户手册
| 型号： | MC68SEC000PB20 |
| 厂家： | 
MOTOROLA |
| 描述： | Addendum to M68000 User Manual |
| 文件： | 总26页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document by
M68000UMAD/AD
Communications and Advanced
Consumer Technologies Group
M68000
Addendum to
M68000
User Manual
August 7, 1997
This addendum to the M68000UM/AD User’s Manual, Revision 8, provides corrections to the original text as
well as additional information. This document and other information on this product is maintained on the World
Wide Web at http://www.motorola.com/68000.
OVERVIEW
This manual includes hardware details and programming information for the MC68HC000, the MC68HC001,
the MC68EC000, and the MC68SEC000. For ease of reading, the name M68000 MPUs will be used when
referring to all processors. Refer to M68000PM/AD, M68000 Programmer's Reference Manual, for detailed
information on the MC68000 instruction set.
The four microprocessors are very similar to each other and all contain the following features:
•
•
•
•
•
•
•
Sixteen 32-Bit Data and Address Registers
16-Mbyte Direct Addressing Range
Program Counter
6 Instruction Types
Operations on Five Main Data Types
Memory-Mapped Input/Output (I/O)
14 Addressing Modes
The following processors contain additional features:
•
MC68HC001/MC68EC000/MC68SEC000
—
Statically selectable 8- or 16-bit data bus
•
MC68HC000/MC68EC000/MC68HC001/MC68SEC000
—
Low power
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
SEMICONDUCTOR PRODUCT INFORMATION
1997 Motorola, Inc. All Rights Reserved.
The primary features of the MC68SEC000 embedded processor include the following:
• Direct Replacement for the MC68EC000
—
—
Pin-for-pin compatibility with the MC68EC000 in the plastic QFP and TQFP packages
Vast selection of existing third-party development tools for the MC68EC000 support the
MC68SEC000
—
Software written for the MC68EC000 will run unchanged on the MC68SEC000
• Power Management
—
—
—
—
Low-power HCMOS technology
Static design allows for stopping the processor clock
3.3V or 5V operation
Typical 0.5µA current consumption at 3.3V in sleep mode
•
Software Strength
—
—
Fully upward object-code compatible with other M68000 Family products
M68000 architecture allows effective assembly code with a C compiler
• Upgrade
—
—
Fully upward code-compatible with higher performance 680x0 and 68300 Family members
ColdFire code-compatible with minor modifications
®
1. MC68HC000
The primary benefit of the MC68HC000 is reduced power consumption. The device dissipates less power (by
an order of magnitude) than the NMOS MC68000.
The MC68HC000 is an implementation of the M68000 16/-32 bit microprocessor architecture. The
MC68HC000 has a 16-bit data bus implementation of the MC68000 and is upward code-compatible with the
MC68010 and the MC68020 32-bit implementation of the architecture.
1.1 MC68HC001
The MC68HC001 provides a functional extension to the MC68HC000 HCMOS 16-/32-bit microprocessor with
the addition of statically selectable 8- or 16-bit data bus operation. The MC68HC001 is object-code compatible
with the MC68HC000. You can migrate code written for the MC68HC001 without modification to any member
of the M68000 Family.
1.2 MC68EC000
The MC68EC000 is an economical high-performance embedded controller designed to suit the needs of the
cost-sensitive embedded-controller market. The HCMOS MC68EC000 has an internal 32-bit architecture that
is supported by a statically selectable 8- or 16-bit data bus. This architecture provides a fast and efficient
processing device that can satisfy the requirements of sophisticated applications based on high-level
languages.
The MC68EC000 is fully object-code compatible with the MC68000. You can migrate code written for the
MC68EC000 without modification to any member of the M68000 Family.
The MC68EC000 brings the performance level of the M68000 Family to cost levels previously associated with
8-bit microprocessors. The MC68EC000 benefits from the rich M68000 instruction set and its related high code
density with low memory bandwidth requirements.
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M68000 USER’S MANUAL ADDENDUM
MOTOROLA
1.3 MC68SEC000
The MC68SEC000 is a cost-effective static embedded processor engineered for low-power applications. In
addition to providing the substantial cost and performance benefits of the MC68EC000, the low-power mode
of the MC68SEC000 provides significant advantages in power consumption and power management. The
typical current consumption of the MC68SEC000 is only 0.5µA in static standby mode and 15.0mA in normal
3.3V operation. The MC68SEC000 operates in either 3.3V or 5.0V systems. The remarkably low power
consumption, small footprint packages, and static implementation are combined in the MC68SEC000 for low-
power applications such as portable measuring equipment, electronic games, and battery-operated hand-held
consumer products.
The HCMOS MC68SEC000’s static architecture is a direct replacement for the MC68EC000, which offers the
lowest cost entry point to 32-bit processing. The internal 32-bit architecture provides fast and efficient
processing that satisfies the requirements of sophisticated applications based on high-level languages.
All of the existing third-party developer tools widely available for the MC68EC000 will directly support the
MC68SEC000. You can find detailed descriptions of these tools in the High Performance Embedded Systems
Source Catalog.
MOTOROLA
M68000 USER’S MANUAL ADDENDUM
3
2.0 SIGNAL DESCRIPTION
Change Figure 3-3 on Page 3-2.
V
A23-A0
D15-D0
ADDRESS BUS
DATA BUS
CC
GND
CLK
AS
FC0
FC1
FC2
R/W
UDS
LDS
PROCESSOR
STATUS
ASYNCHRONOUS
BUS CONTROL
DTACK
MC68SEC000
BR
BG
BUS ARBITRATION
CONTROL
IPL0
IPL1
BERR
RESET
HALT
SYSTEM
CONTROL
INTERRUPT
CONTROL
IPL2
AVEC
MODE
Figure 1. Input and Output Signals (MC68EC000 and MC68SEC000)
2.1 Data Bus (D15-D0)
In Section 3.2 on page 3-4, replace “The MC68EC000 and MC68HC001 use D7-D0 in 8-bit mode, and D15-
D8 are undefined.” with “Using the MC68HC001, MC68EC000, and MC68SEC000 mode pin, you can
statically select either 8- or 16-bit modes for data transfer. The MC68EC000, MC68SEC000, and
MC68HC001 use D7-D0 in 8-bit mode. D15-D8 are undefined.”
2.2 Bus Arbitration Control
In Section 3.4 on page 3-5, the sentence “In the 48-pin version of the MC68008 and MC68EC000, no pin is
available for the bus grant acknowledge signal; this microprocessor uses a two-wire bus arbitration
scheme.” should read “In the 64-pin MC68EC000 and MC68SEC000, no pin is available for the bus grant
acknowledge signal. These microprocessors use a two-wire bus arbitration scheme.”
2.3 System Control
The Mode subsection heading of Section 3.6 on page 3-7 should read ‘‘Mode (MODE) (MC68HC001/
68EC000/68SEC000).’’
2.4 MC68SEC000 Low-Power Mode
Add the following to Sections 4 and 5, Bus Operation.
The MC68SEC000 has been redesigned to provide fully static- and low-power operation. This section
describes the recommended method for placing the MC68SEC000 into a low-power mode to reduce the
4
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
1
power consumption to its quiescent value while maintaining the internal state of the processor. The
low-power mode described below will be routinely tested as part of the MC68SEC000 test vectors provided
by Motorola.
To successfully enter the low-power mode, the MC68SEC000 must first be in the supervisor mode. A
recommended method for entering the low-power mode is to use the TRAP instruction, which causes the
processor to begin exception processing, thus entering the supervisor mode. External circuitry should
accomplish the following steps during the trap routine:
1. Externally detect a write to the low-power address. You select this address which can be any address
in the 16 Mbyte addressing range of the MC68SEC000. A write to the low-power address can be
detected by polling A23–A0, R/W, and FC2–FC0. When the low-power address is detected, R/W is
a logic low, and the function codes have a five (101) on their output, the processor is writing to the
low-power address in supervisor mode and user-designed circuitry should assert the
ADDRESS_MATCH signal shown in Figure 2 and Figure 3.
D
D
D
Q
Q
Q
Q
Q
Q
ADDRESS_MATCH
CK
CL
CK
CL
CK
AS
AS
CPU_CLK
RESTART
RESET
SYSTEM_CLK
Figure 2. MC68SEC000 Low-Power Circuitry for 16-Bit Data Bus
D
D
D
D
Q
Q
Q
ADDRESS_MATCH
Q
CK
CL
CK
CL
CK
CK
CL
AS
AS
AS
Q
Q
Q
Q
CPU_CLK
RESTART
RESET
SYSTEM_CLK
Figure 3. MC68SEC000 Low-Power Circuitry for 8-Bit Data Bus
2. Execute the STOP instruction. The external circuitry shown in Figure 2 and Figure 3 will count the
number of bus cycles starting with the write to the low-power address and will stop the processor
clock on the first falling edge of the system clock after the bus cycle that reads the immediate data
of the STOP instruction. Figure 3 has one more flip-flop than Figure 2 because the MC68SEC000 in
1.
The preliminary specification for the MC68SEC000’s current drain while in the low-power mode is Idd < 2µA for 3.3V operation and
Idd < 5µA for 5.0V operation.
5
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
8-bit mode requires two bus cycles to fetch the immediate data of the STOP instruction. After the
processor clock is disabled, it is often necessary to disable the clock to other sections of your circuit.
This can be done, but be careful that runt clocks and spurious glitches are not presented to the
MC68SEC000. A timing diagram is shown in Figure 4.
CLK
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7
CPU_CLK
AS
RW
DTACK
Write to
Low-Power
Address
Fetch Immediate
Data of STOP
Instruction
Stop
Figure 4. MC68SEC000 Clock Stop Timing for 16-Bit Data Bus
Note: While the MC68SEC000 is in the low-power mode, all inputs must be driven to V or V , or have a
DD
SS
pull-up or pull-down resistor.
3. This step is optional depending on whether your applications require the MC68SEC000 signals with
three-state capability to be placed into a high-impedance state. To place the MC68SEC000 into a
three-state condition, the proper method for arbitrating the bus (as described in 5.2 Bus Arbitration
in the M68000 User’s Manual, Rev 8) should be completed during the fetch of the status register data
for the STOP instruction. A timing diagram with the bus arbitration sequence is shown in Figure 5.
CLK
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7
CPU_CLK
AS
RW
DTACK
BR
BG
Write to
Low-Power
Fetch Immediate
Data of STOP
Stop
Figure 5. MC68SEC000 ClAocrkStop Timing with IBnsutrusctiAonrbitration for 16-Bit Data Bus
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M68000 USER’S MANUAL ADDENDUM
MOTOROLA
After the previous steps are completed, the MC68SEC000 will remain in the low-power mode until it
recognizes the appropriate interrupt . External logic will also have to poll IPLB2–IPLB0 to detect the proper
interrupt. When the correct interrupt level is received, the following steps will bring the processor out of the
low-power mode:
1. Restart the system clock if it was stopped.
2. Wait for the system clock to become stable.
3. Assert the RESTART signal. This will cause the processor’s clock to start on the next falling edge of
the system clock. Figure 6 shows the timing for bringing the processor out of the low-power mode.
Both the RESTART and RESET signals are subject to the asynchronous setup time as specified in
the Electrical Characteristics section of this addendum.
WARNING
The system clock must be stable before the RESTART signal is asserted
to prevent glitches in the clock. An unstable clock can cause unpredictable
results in the MC68SEC000.
CLK
CPU_CLK
RESTART
Figure 6. MC68SEC000 Clock Start Timing
4. If the MC68SEC000 was placed in a three-state condition, the BR signal must be negated before the
processor can begin executing instructions.
7
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
An example trap routine is as follows:
TRAP_x MOVE.B #0,$low_power_address
/* Write that causes ADDRESS_MATCH to assert */
/* STOP instruction with desired interrupt mask */
/* Return from the exception */
STOP #$2000
RTE
The first instruction (MOVE.B #0,$low_power_address) writes a byte to the low-power address that will
cause the external circuitry to begin the sequence that will stop the processor’s clock. The second
instruction (STOP #$2000) loads the SR with the immediate data. This lets you set the interrupt that will
cause the processor to come out of the low-power mode. The final instruction (RTE) tells the processor to
return from the exception and resume normal processing.
3.0 MC68SEC000 ELECTRICAL SPECIFICATIONS
Add to the following table to Section 10.1.
3.1 MC68SEC000 MAXIMUM RATINGS
RATING
SYMBOL
VALUE
UNIT
Supply Voltage
Input Voltage
V
–0.3 to 6.5
V
CC
V
–0.5 to 6.5
V
in
A
Maximum Operating
Temperature Range
Commercial Extended "C" Grade
T
T
to T
°
°
C
L
H
0 to 70
–40 to 85
Storage Temperature
Tstg
–55 to 150
C
3.2 CMOS CONSIDERATIONS
The following change should be made to Section 10.4, CMOS Considerations.
“Although the MC68HC000 and MC68EC000 is implemented with input protection diodes, care should be
exercised to ensure that the maximum input voltage specification is not exceeded.” should read “Although
the MC68HC000, MC68EC000, and MC68SEC000 are implemented with input protection diodes, be
careful not to exceed the maximum input voltage specification.”
8
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
4.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS
Replace Figure 10-2 on page 10-6 with Figure 7.
DRIVE
TO 2.4 V
2.0 V
2.0 V
0.8 V
CLK
0.8 V
A
DRIVE TO
0.5 V
B
2.0 V
0.8 V
2.0 V
0.8 V
VALID
OUTPUT
VALID
OUTPUT
OUTPUTS(1) CLK
OUTPUTS(2) CLK
A
n
n + 1
B
2.0 V
0.8 V
2.0 V
0.8 V
VALID
OUTPUT
VALID
OUTPUT
n
n+1
C
D
DRIVE TO
2.4 V
2.0 V
0.8 V
2.0 V
0.8 V
VALID
INPUT
INPUTS(3) CLK
DRIVE TO
0.5 V
C
D
DRIVE
2.0 V
0.8 V
2.0 V
0.8 V
TO 2.4 V
VALID
INPUT
INPUTS(4) CLK
ALL SIGNALS(5)
DRIVE
TO 0.5 V
2.0 V
0.8 V
E
F
2.0 V
0.8 V
NOTES:
1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.
2. This output timing is applicable to all parameters specified relative to the falling edge of the clock.
3. This input timing is applicable to all parameters specified relative to the rising edge of the clock.
4. This input timing is applicable to all parameters specified relative to the falling edge of the clock.
5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal.
LEGEND:
A. Maximum output delay specification.
B. Minimum output hold time.
C. Minimum input setup time specification.
D. Minimum input hold time specification.
E. Signal valid to signal valid specification (maximum or minimum).
F. Signal valid to signal invalid specification (maximum or minimum).
Figure 7. Drive Levels and Test Points for AC Specifications - applies to all parts
M68000 USER’S MANUAL ADDENDUM MOTOROLA
9
5.0 MC68SEC000 DC ELECTRICAL SPECIFICATIONS
Add the following table to Section 10.13 on page 10-23.
(V = 5.0 Vdc ±5%, 3.3 Vdc ±10%,; GND = 0 Vdc; T = T to T )
CC
A
L
H
3.3 V
5.0 V
CHARACTERISTIC
SYMBOL
MIN
MAX
MIN
MAX
UNIT
Input High Voltage
Input Low Voltage
V
2.0
V
2.0
V
CC
V
IH
CC
V
GND
0.8
GND –
0.5
0.8
V
IL
Input Leakage Current BERR, BR, DTACK, CLK, I PL2-IPL0, AVEC
MODE, HALT, RESET
Iin
—
2.5
20
—
2.5
20
uA
Three-State (Off State) Input Current
Output High Voltage
I
—
2.5
—
—
2.5
—
uA
V
TSI
V
2.4
V
–0.75
OH
CC
Output Low Voltage
V
V
OL
(IOL = 1.6 mA) HALT
(IOL = 3.2 mA) A23–A0, BG, FC2–FC0
(IOL = 5.0 mA) RESET
—
—
—
—
0.5
0.5
0.5
0.5
—
0.5
0.5
0.5
0.5
—
—
—
(IOL = 5.3 mA) AS, D15–D0, LDS, R/W, UDS
Current Dissipation*
f = 0 Hz
I
—
0.7
—
1.0
mA
D
f=10MHz
f=16 MHz
f= 20 MHz
—
—
—
—
10
15
—
—
—
—
15
25
mA
mA
mA
pF
20
30
Capacitance (Vin = 0 V, T = 25
A
°C, Frequency = 1 MHz)**
Cin
CL
20.0
20.0
Load Capacitance
HALT
—
70
—
70
pF
All Others
130
130
*During normal operation, instantaneous Vcc current requirements may be as high as 1.5A.
Currents listed are with no loading.
**Capacitance is periodically sampled rather than 100% tested.
10
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
6.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS — CLOCK
TIMING (See Figure 2)
Add the following table and Figure 8 to Section 10.9 on page 10-9.
10MHz
MAX
16MHz
20MHz
NUM.
CHARACTERISTIC
Frequency of Operation
Cycle time
SYMBOL
MIN
0
min
0
max
16.7
—
min
0
max
20.0
—
UNIT
MHz
ns
f
10.0
—
1
tcyc
100
60
50
2,3
Clock Pulse Width
t
45
45
—
—
27
27
—
—
21
21
—
—
ns
CL
t
CH
4,5
Clock Rise and Fall Times
t
t
—
—
10
10
—
—
5
5
—
—
4
4
ns
Cr
Cf
Applies to 3.3V and 5V.
1
3
2
2.0 V
0.8 V
4
5
NOTE: Timing measurements are referenced to and from a low voltage of 0.8 V and a
high voltage of 2.0 V, unless otherwise noted. The voltage swing through this
range should start outside and pass through the range such that the rise or
fall will be linear between 0.8 V and 2.0 V.
Figure 8. MC68SEC000 Clock Input Timing Diagram
11
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
7.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS — READ AND
WRITE CYCLES
Add the following table and Figures 9 and 10 to Section 10.16.
Applies to 3.3V and 5V.
(GND = 0 V; T = T to T ; see Figures 3 and 4)
A
L
H
10MHz
16MHz
20MHz
NUM
CHARACTERISTIC
UNIT
MIN
MAX
35
MIN
MAX
30
MIN
MAX
25
6
6A
7
Clock Low to Address Valid
Clock High to FC Valid
—
0
—
0
—
0
ns
ns
ns
35
30
25
Clock High to Address, Data Bus High Impedance (Maximum)
(Write)
—
55
—
50
—
42
8
Clock High to Address, FC Invalid (Minimum)
Clock High to AS, LDS, UDS Asserted
0
3
—
0
3
—
0
3
—
ns
ns
1
35
30
25
9
2
Address Valid to AS, LDS, UDS Asserted (Read)/ AS Asserted
(Write)
20
—
15
—
10
—
ns
11
2
FC Valid to AS, LDS, UDS Asserted (Read)/ AS Asserted (Write)
Clock Low to AS, LDS, UDS Negated
45
3
—
35
—
—
—
—
45
3
—
30
—
—
—
—
40
3
—
25
—
—
—
—
ns
ns
ns
ns
ns
ns
11A
1
12
2
AS, LDS, UDS Negated to Address, FC Invalid
AS (and LDS, UDS Read) Width Asserted
LDS, UDS Width Asserted (Write)
15
15
120
60
60
10
100
50
50
13
2
195
95
14
2
14A
2
AS, LDS, UDS Width Negated
105
15
16
Clock High to Control Bus High Impedance
AS, LDS, UDS Negated to R/W Invalid
—
55
—
—
50
—
—
42
—
ns
ns
2
15
15
10
17
1
Clock High to R/W High (Read)
Clock High to R/W Low (Write)
AS Asserted to R/W Low (Write)
Address Valid to R/W Low (Write)
FC Valid to R/W Low (Write)
0
0
35
35
10
—
—
—
0
0
30
30
10
—
—
—
0
0
25
25
10
—
—
—
ns
ns
ns
ns
ns
ns
18
1
20
2,6
—
0
—
0
—
0
20A
21
2
2
50
50
30
30
25
25
21A
2
R/W Low to DS Asserted (Write)
22
23
Clock Low to Data-Out Valid (Write)
—
35
—
—
30
—
—
25
—
ns
ns
2
AS, LDS, UDS Negated to Data-Out Invalid (Write)
30
15
10
25
26
27
28
2
5
2
Data-Out Valid to LDS, UDS Asserted (Write)
30
5
—
—
15
5
—
—
10
5
—
—
95
95
ns
ns
ns
ns
Data-In Valid to Clock Low (Setup Time on Read)
AS, LDS, UDS Negated to DTACK Negated (Asynchronous Hold)
0
110
110
0
110
110
0
28A Clock High to DTACK Negated
0
0
0
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M68000 USER’S MANUAL ADDENDUM
MOTOROLA
AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Continued)
10MHz
16MHz
20MHz
NUM
CHARACTERISTIC
UNIT
MIN
MAX
—
MIN
MAX
—
MIN
MAX
—
29
AS, LDS, UDS Negated to Data-In Invalid (Hold Time on Read)
0
—
0
0
—
0
0
—
0
ns
ns
ns
ns
29A AS, LDS, UDS Negated to Data-In High Impedance (Read)
150
—
90
75
30
AS, LDS, UDS Negated to BERR Negated
—
—
2,5
DTACK Asserted to Data-In Valid (Setup Time on Read)
—
65
—
50
—
42
31
32
33
34
35
HALT and RESET Input Transition Time
Clock High to BG Asserted
0
150
35
0
150
30
0
150
25
ns
ns
—
—
—
Clock High to BG Negated
—
35
—
30
—
25
ns
BR Asserted to BG Asserted
BR Negated to BG Negated
1.5
1.5
3.5
3.5
1.5
1.5
3.5
3.5
1.5
1.5
3.5
3.5
Clks
Clks
7
36
38
BG Asserted to Control, Address, Data Bus High Impedance (AS
Negated)
—
55
—
50
—
42
ns
39
44
BG Width Negated
1.5
0
—
55
—
1.5
0
—
50
—
1.5
0
—
42
—
Clks
ns
AS, LDS, UDS Negated to AVEC Negated
Asynchronous Input Setup Time
5
5
5
5
ns
47
2,3
BERR Asserted to DTACK Asserted
20
—
10
—
10
—
ns
48
52
53
55
Data-In Hold from Clock High
0
0
—
—
—
—
0
0
—
—
—
—
0
0
—
—
—
—
ns
ns
Data-Out Hold from Clock High (Write)
R/W Asserted to Data Bus Impedance Change (Write)
HALT, RESET Pulse Width
20
10
10
10
0
ns
4
10
Clks
56
58
7
BR Negated to AS, LDS, UDS, R/W Driven
BR Negated to FC Driven
1.5
1
—
—
1.5
1
—
—
1.5
1
—
—
Clks
Clks
7
58A
Applies to 3.3V and 5V.
NOTES: 1. For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns.
2.
3.
Actual value depends on clock period.
If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is an asynchronous input
using the asynchronous input setup time (#47).
4.
5.
For power-up, the MC68SEC000 must be held in the reset state for 100 ms to allow stabilization of on-chip circuitry. After the
system is powered up, #56 refers to the minimum pulse width required to reset the controller.
If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK asserted to data setup time (#31)
requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle.
6.
7.
When AS and R/W are equally loaded (
±20%), subtract 5 ns from the values given in these columns.
The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.
13
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
S0
S1
S2
S3
S4
S5
S6
S7
CLK
6A
FC2–FC0
8
6
A23–A0
AS
7
12
15
14
11
11A
13
17
LDS / UDS
R/W
9
18
28
47
DTACK
27
31
48
29
DATA IN
47
30
BERR / BR
(NOTE 2)
47
47
32
32
56
HALT / RESET
47
ASYNCHRONOUS
INPUTS
(NOTE 1)
NOTES:
1. Setup time for the asynchronous inputs IPL2–IPL0 and AVEC (#47) guarantees their recognition at the
next falling edge of the clock.
2. BR need fall at this time only to insure being recognized at the end of the bus cycle.
3. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V,
unless otherwise noted. The voltage swing through this range should start outside and pass through the
range such that the rise or fall is linear between 0.8 V and 2.0 V.
Figure 9. MC68SEC000 Read Cycle Timing Diagram
M68000 USER’S MANUAL ADDENDUM
14
MOTOROLA
S0
S1
S2
S3
S4
S5
S6
S7
CLK
6A
FC2–FC0
8
6
A23–A0
AS
7
12
15
14
9
13
11
9
11A
20A
20
22
14A
LDS / UDS
17
18
21
R/W
28
21A
55
47
DTACK
26
23
53
25
7
48
DATA OUT
47
30
BERR / BR
(NOTE 2)
47
47
32
32
56
HALT / RESET
47
ASYNCHRONOUS
INPUTS
(NOTE 1)
NOTES:
1. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V,
unless otherwise noted. The voltage swing through this range should start outside and pass through the
range such that the rise or fall is linear between 0.8 V and 2.0 V.
2. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge
of S2 (specification #20A).
Figure 10. MC68SEC000 Write Cycle Timing Diagram
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
15
8.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS — BUS
ARBITRATION
Add the following table and Figure 11 to Section 10.17.
(GND = 0 Vdc; T = T to T ; refer to Figure 13)
A
L
H
10MHz
16MHz
20MHz
NUM
CHARACTERISTICp
UNIT
MIN
MAX
55
MIN
MAX
50
MIN
MAX
42
7
Clock High to Address, Data Bus High Impedance (Maximum)
Clock High to Control Bus High Impedance
Clock High to BG Asserted
—
—
0
—
—
0
—
—
0
ns
ns
16
33
34
35
36
38
55
50
42
35
30
25
ns
Clock High to BG Negated
0
35
0
30
0
25
ns
BR Asserted to BG Asserted
1.5
1.5
—
3.5
3.5
55
1.5
1.5
—
3.5
3.5
50
1.5
1.5
—
3.5
3.5
42
Clks
Clks
ns
BR Negated to BG Negated
BG Asserted to Control, Address, Data Bus High Impedance (AS
Negated)
39
47
BG Width Negated
1.5
5
—
—
—
1.5
5
—
—
—
1.5
5
—
—
—
Clks
ns
Asynchronous Input Setup Time
BR Negated to AS, LDS, UDS, R/W Driven
1
1.5
1.5
1.5
Clks
58
1
BR Negated to FC Driven
1
—
1
—
1
—
Clks
58A
Applies to 3.3V and 5V.
1. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.
16
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
STROBES
AND R/W
36
BR
35
34
39
BG
33
38
CLK
NOTE: Setup time to the clock (#47) for the asynchronous inputs BERR, BR, DTACK, IPL2-IPL0, and VPA
guarantees their recognition at the next falling edge of the clock.
Figure 11. Bus Arbitration Timing
CLK
47
33
BR
BG
34
35
36
39
58
38
AS
LDS/UDS
R/W
58A
FC2–FC0
A23
9–A0
D15
7–D0
NOTE: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V.
Figure 12. MC68SEC000 Bus Arbitration Timing Diagram
MOTOROLA
M68000 USER’S MANUAL ADDENDUM
17
CLK
47
33
BR
BG
34
35
38
AS
DS
VMA
R/W
FC2-FC0
A23-A0
D15-D0
NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. This diagram also applies to the 68EC000.
Figure 13. Bus Arbitration Timing—Idle Bus Case
18
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
CLK
47
33
BR
BG
34
35
16
AS
DS
VMA
R/W
FC2-FC0
A23-A0
7
D15-D0
NOTE: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V.
This diagram also applies to the 68EC000.
Figure 14. Bus Arbitration Timing - Active Bus Case
MOTOROLA
M68000 USER’S MANUAL ADDENDUM
19
CLK
47
33
BR
BG
35
36
39
39
38
58
AS
DS
57A
VMA
R/W
FC2-FC0
A23-A0
D15-D0
NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V.
This diagram also applies to the 68EC000.
Figure 15. Bus Arbitration - Multiple Bus Request
20
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
9.0 MECHANICAL DATA
9.1 PIN ASSIGNMENTS
Add Figure 12 to Section 11.1.
The following defines the pin assignment and the package dimensions of the 64 lead QFP (FU package)
and 64 lead TQFP (PB package) for the MC68SEC000. Note that it is pin-to-pin compatible with the
MC68EC000.
64
49
48
R/W
DTACK
BG
1
D12
D13
D14
D15
A23
A22
A21
BR
V
CC
CLK
GND
V
MODE
HALT
RESET
AVEC
BERR
IPL2
CC
MC68SEC000FU/PB
A20
A19
A18
A17
A16
A15
A14
A13
IPL1
IPL0
16
17
33
32
FC2
Figure 16. 64-Lead Quad Flat Pack and 64-Lead Thin Quad Flat Pack
MOTOROLA
M68000 USER’S MANUAL ADDENDUM
21
10.0 PACKAGE DIMENSIONS - FU SUFFIX
This diagram replaces the one on Page 11-16
64 Lead Quad Flat Pack Case 840B-01
R
G
H
M
B
S
A
L
D
C
K
MILLIMETERS
INCHES
DIM
MIN
16.95
13.90
16.95
13.90
0.30
MAX
17.45
14.10
17.45
14.10
0.45
MIN
MAX
A
B
C
D
G
H
K
L
0.667
0.547
0.667
0.547
0.012
0.687
0.555
0.687
0.555
0.018
0.80 BSC
0.031 BSC
2.15
0.13
2.00
2.45
0.23
2.40
0.085
0.005
0.79
0.096
0.009
0.094
M
R
S
12.00 REF
12.00 REF
0.472 REF
0.472 REF
22
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
11.0 PACKAGE DIMENSIONS - PB SUFFIX
Add the following to Section 11.2.
64 Lead Thin Quad Flat Pack Case 840F-02
G
H
M
A1 B1
B
A
D1
C1
L
K
D
C
MILLIMETERS
MAX
INCHES
DIM
MIN
MIN
MAX
A
A1
B
12.00 BSC
6.00 BSC
10.00 BSC
5.00 BSC
12.00 BSC
6.00 BSC
10.00 BSC
5.00 BSC
0.472 BSC
0.236 BSC
0.394 BSC
0.197 BSC
0.472 BSC
0.236 BSC
0.394 BSC
0.197 BSC
B1
C
C1
D
D1
G
0.17
0.27
0.007
0.011
H
0.50 BSC
0.020 BSC
K
---
1.60
0.20
1.45
---
0.063
0.008
0.057
L
0.09
1.35
0.004
0.053
M
MOTOROLA
M68000 USER’S MANUAL ADDENDUM
23
12.0 PACKAGE/FREQUENCY AVAILABILITY
Replaces Section 11.1
The following tables identify the packages and operating frequencies available for the MC68HC000,
MC68HC001, MC68EC000, and the MC68SEC000.
VOLTAGE
MC68SEC000
PACKAGE
FREQUENCY
3.3 V
5 V
Quad Flat Pack (FU)
10 MHz
16 MHz
20MHz
✓
✓
✓
✓
✓
✓
10 MHz
16 MHz
20MHz
✓
✓
✓
✓
✓
✓
Thin Quad Flat Pack (PB)
MC68HC000
PACKAGE
VOLTAGE
5V
FREQUENCY
Plastic DIP
Plastic Quad Pack (PLCC)
Plastic Quad (Gull Wing)**
Pin Grid Array, Solder Lead Finish**
Pin Grid Array, Gold Lead Finish**
8,10,12,16,20 MHz
8,10,12,16,20 MHz
8,10,12,16,20 MHz
8,10,12,16,20 MHz
8,10,12,16,20 MHz
3
3
3
3
3
Plastic Quad Pack (PLCC)
MC68HC001**
PACKAGE
VOLTAGE
5V
FREQUENCY
Plastic Quad Pack (PLCC)
Plastic Quad (Gull Wing)
Pin Grid Array, Gold Lead Finish
8,10,12,16 MHz
8,10,12,16 MHz
8,10,12,16 MHz
8,10,12,16 MHz
✓
✓
✓
✓
MC68EC000
PACKAGE
VOLTAGE
5V
FREQUENCY
Plastic Quad Pack (PLCC)
Plastic Quad Flat Pack
8 MHz
10 MHz
12 MHz
16 MHz
20 MHz
✓
✓
✓
✓
✓
NOTE : ** not recommended for new designs
24
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
ORDERING INFORMATION
Add the following to Section 11.
The following tables contains the ordering information for the MC68SEC000.
MC68SEC000 Ordering Information
TEMPERATURE
RANGE
PACKAGE
QFP
BODY SIZE
LEAD SPACING
0.8mm
SPEED (IN MH Z)
VOLTAGE
SUFFIX
FU
CFU
PB
0C to +70C
-40C to +85C
0C to +70C
14.0 mm X 14.0mm
10.0mm x 10.0mm
10/16/20 MHz
3.3V or 5.0V
TQFP
0.5mm
CPB
-40C to +85C
MC68HC000 Ordering Information
TEMPERATURE
RANGE
PACKAGE
BODY SIZE
LEAD SPACING
SPEED(INMHZ)
VOLTAGE
SUFFIX
DIP
81.91mm X 20.57mm
2.54mm
8, 10, 12, 16
8, 10, 12, 16, 20
8, 10, 12, 16
P
0C to +70C
0C to +70C
-40C to +85C
5.0V
PLCC
FN
25.57mm X 25.27mm
1.27mm
CFN
MC68EC000 Ordering Information
TEMPERATURE
RANGE
PACKAGE
BODY SIZE
LEAD SPACING
SPEED(INMHZ)
VOLTAGE
SUFFIX
PLCC
PQFP
25.57mm X 25.27mm
14.1mm X 14.1mm
1.27mm
0.8mm
8, 10,12, 16, 20
8, 10,12, 16, 20
5.0V
FN
FU
0C to +70C
DOCUMENTATION
Add to Section 11.
The documents listed in the following table contain detailed information that pertain to the MC68SEC000
processor. You can obtain these documents from the Literature Distribution Centers listed on the last page
of this document.
MC68SEC000 Documentation
MC68SEC000 DOCUMENTATION
DOCUMENT NUMBER
M68000 Family
M68000PM/AD
Programmer’s Reference Manual
M68000 User’s Manual
M68000UM/AD
BR729/D
High Performance Embedded Systems
Source Catalog‘‘
MC68EC000 Product Brief
MC68SEC000 Product Brief
MC68EC000/D
MC68SEC000/D
MOTOROLA
M68000 USER’S MANUAL ADDENDUM
25
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
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