MC74F253JS [MOTOROLA]
暂无描述;
| 型号： | MC74F253JS |
| 厂家： | 
MOTOROLA |
| 描述： | 暂无描述 复用器 输出元件 输入元件 |
| 文件： | 总3页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC54/74F253
DUAL 4-INPUT MULTIPLEXER
WITH 3-STATE OUTPUTS
The MC54/74F253 is a Dual 4-Input Multiplexer with 3-State Outputs. It can
select two bits of data from four sources using common select inputs. The out-
puts may be individually switched to a high-impedance state with a HIGH on
the respective Output Enable (OE) inputs, allowing the outputs to interface di-
rectly with bus-oriented systems.
DUAL 4-INPUT MULTIPLEXER
WITH 3-STATE OUTPUTS
FAST SCHOTTKY TTL
J SUFFIX
CERAMIC
CASE 620-09
CONNECTION DIAGRAM DIP (TOP VIEW)
16
1
V
OE
S
I
I
I
I
Z
b
CC
16
b
0
3b
13
2b
12
1b
11
0b
10
15
14
9
N SUFFIX
PLASTIC
CASE 648-08
16
1
1
OE
2
3
4
5
6
7
8
S
I
I
I
I
Z
a
GND
a
1
3a
2a
1a
0a
D SUFFIX
SOIC
CASE 751B-03
16
1
ORDERING INFORMATION
MC54FXXXJ
Ceramic
MC74FXXXN Plastic
MC74FXXXD SOIC
GUARANTEED OPERATING RANGES
Symbol
Parameter
Supply Voltage
Min
Typ
Max
Unit
V
CC
54, 74
54
4.5
–55
0
5.0
25
25
5.5
125
70
V
T
A
Operating Ambient Temperature Range
°C
74
I
Output Current — High
Output Current — Low
54, 74
54, 74
–3.0
24
mA
mA
OH
I
OL
FAST AND LS TTL DATA
4-120
MC54/74F253
LOGIC DIAGRAM
OE
OE
1
1
1
1
S
S
1
1
1
1
0a
a
1
b
3b
2b
1b
0b
0
1
3a
2a
1a
15
13
12
11
10
14
2
3
4
5
6
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
Z
9
Z
7
b
a
FUNCTIONAL DESCRIPTION
The F253 contains two identical 4-input Multiplexers with
3-State Outputs. They select two bits from four sources se-
Z = OE • (I • S • S + I
• S • S +
a
a
0a
2a
1
0
1a 1 0
I
• S • S + 1 • S • S )
1 0 3a 1 0
lected by common Select Inputs (S , S ). The 4-input multi-
Z = OE • (I • S • S + I • S • S +
0
1
b
b
0b
2b
1
0
1b
1
0
plexers have individual Output Enable (OE , OE ) inputs
I
• S • S + I • S • S )
a
b
1
0
3b
1
0
which, when HIGH, force the outputs to a high impedance
(high Z) state.
If the outputs of 3-state devices are tied together, all but one
device must be in the high impedance state to avoid high cur-
rents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so that there is
no overlap.
The F253 is the logic implementation of a 2-pole, 4-position
switch, where the position of the switch is determined by the
logic levels supplied to the two select inputs. The logic equa-
tions for the outputs are shown below:
FUNCTION TABLE
Select
Inputs
Output
Enable
Data Inputs
Output
S
S
I
I
I
I
3
OE
H
L
Z
Z
L
0
1
0
1
2
X
X
X
L
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
X
X
L
L
L
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
H
X
X
X
X
X
X
L
H
L
H
H
L
L
L
Z = High Impedance (off)
Address inputs S and S
0
1
L
H
X
X
X
X
L
H
L
are common to both sections.
H
H
H
H
L
L
H
X
X
L
H
L
H
H
L
H
L
H
FAST AND LS TTL DATA
4-121
MC54/74F253
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Unit
V
Test Conditions
Guaranteed Input HIGH Voltage
Guaranteed Input LOW Voltage
V
IH
2.0
V
V
V
Input LOW Voltage
0.8
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–1.2
V
I
I
I
I
= –18 mA
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MIN
IK
IN
54, 74
74
2.4
2.7
V
= –3.0 mA
= –3.0 mA
= 24 mA
= 4.50 V
= 4.75 V
= MIN
OH
OH
OH
OL
V
V
Output LOW Voltage
0.5
50
V
OL
OZH
OZL
IH
I
I
I
Output Off Current — HIGH
Output Off Current — LOW
Input HIGH Current
µA
µA
µA
µA
mA
mA
V
V
V
V
V
V
= 2.7 V
= 0.5 V
= MAX
= MAX
= MAX
OUT
OUT
–50
20
= 2.7 V
IN
100
–0.6
–150
= 7.0 V
IN
I
I
Input LOW Current
= 0.5 V
V
V
= MAX
= MAX
IL
IN
CC
Output Short Circuit
Current (Note 2)
–60
= 0 V
OUT
OS
CC
Power Supply Current
Total, Output HIGH
Total, Output LOW
OE = GND
n
16
23
I
O
= 4.5 V; S , I – I = GND
n
1
3
I
mA
I , S , OE = GND
n n n
CC
V
CC
= MAX
Total at HIGH-Z
23
OE = 4.5 V, V
= MAX
n
CC
I , S = GND
n
n
AC CHARACTERISTICS
54/74F
54F
= -55°C to +125°C
74F
T
= +25°C
T
A
T = 0°C to +70°C
A
A
V
= +5.0 V
= 50 pF
Max
11.5
9.0
V
= 5.0 V ± 10%
V
CC
= 5.0 V ± 10%
CC
CC
C
C
= 50 pF
C = 50 pF
L
L
L
Symbol
Parameter
Propagation Delay
S to Z
n
Min
4.5
3.0
3.0
2.5
3.0
3.0
2.0
2.0
Min
3.5
2.5
2.5
2.5
2.5
2.5
2.0
2.0
Max
Min
4.5
3.0
3.0
2.5
3.0
3.0
2.0
2.0
Max
Unit
t
15
11
13.5
10
ns
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
t
t
t
t
t
t
t
n
Propagation Delay
to Z
7.0
9.0
8.0
10
8.0
7.0
9.0
9.0
6.0
7.0
ns
ns
ns
I
n
6.0
n
Output Enable Time
8.0
8.0
10
Output Disable Time
5.0
6.5
8.0
6.0
FAST AND LS TTL DATA
4-122
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