MC74HC390 [MOTOROLA]
Dual 4-Stage Binary Ripple Counter with ±2and ±5 Sections; 双4级二进制纹波计数器具有± 2AND ± 5节
| 型号： | MC74HC390 |
| 厂家： | 
MOTOROLA |
| 描述： | Dual 4-Stage Binary Ripple Counter with ±2and ±5 Sections |
| 文件： | 总8页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
÷
÷
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
High–Performance Silicon–Gate CMOS
16
1
The MC54/74HC390 is identical in pinout to the LS390. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
This device consists of two independent 4–bit counters, each composed
of a divide–by–two and a divide–by–five section. The divide–by–two and
divide–by–five counters have separate clock inputs, and can be cascaded to
implement various combinations of ÷ 2 and/or ÷ 5 up to a ÷ 100 counter.
Flip–flops internal to the counters are triggered by high–to–low transitions
of the clock input. A separate, asynchronous reset is provided for each 4–bit
counter. State changes of the Q outputs do not occur simultaneously
because of internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used as clocks or strobes
except when gated with the Clock of the HC390.
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
ORDERING INFORMATION
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No 7A
PIN ASSIGNMENT
•
Chip Complexity: 244 FETs or 61 Equivalent Gates
CLOCK A
1
2
16
15
V
CC
a
CLOCK A
RESET a
b
b
Q
3
4
5
6
7
8
14
13
12
11
10
9
RESET b
Aa
LOGIC DIAGRAM
CLOCK B
Q
Ab
a
Q
Q
CLOCK B
Ba
Q
÷
2
Ca
Da
Bb
3, 13
5, 11
1, 15
Q
Q
A
CLOCK A
COUNTER
Q
Q
Cb
Db
GND
Q
B
÷
5
6, 10
7, 9
4, 12
2, 14
FUNCTION TABLE
Q
Q
CLOCK B
RESET
C
D
COUNTER
Clock
A
B
Reset
Action
X
X
H
Reset
÷ 2 and ÷ 5
X
L
L
Increment
÷ 2
PIN 16 = V
CC
PIN 8 = GND
X
Increment
÷ 5
10/95
REV 6
Motorola, Inc. 1995
MC54/74HC390
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 1.5 to V
+ 1.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
I
DC Supply Current, V and GND Pins
CC
CC
range GND (V or V
)
V
CC
.
in out
P
D
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V ).
Unused outputs must be left open.
CC
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic or SOIC DIP)
L
260
300
(Ceramic DIP)
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
Symbol
Parameter
Test Conditions
25 C
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
IL
out
CC
|I
|
20 µA
out
V
|I
= V or V
IH IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
OH
Minimum High–Level Output
Voltage
in
out
|
20 µA
V
in
= V or V
|I
|I
|
|
4.0 mA
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
IH
IL out
out
V
|I
= V or V
IH
out
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
Maximum Low–Level Output
Voltage
V
in
IL
|
20 µA
V
= V or V
|I
|I
|
|
4.0 mA
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
in
in
IH IL out
out
I
Maximum Input Leakage Current
V
V
= V
= V
or GND
6.0
6.0
± 0.1
± 1.0
± 1.0
µA
µA
in
CC
I
Maximum Quiescent Supply
Current (per Package)
or GND
8
80
160
CC
in
CC
I
= 0 µA
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
MC54/74HC390
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
f
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
f
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)
2.0
4.5
6.0
5.4
27
32
4.4
22
26
3.6
18
21
MHz
max
t
t
t
t
t
,
Maximum Propagation Delay, Clock A to QA
(Figures 1 and 3)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
ns
ns
ns
ns
ns
ns
ns
pF
PLH
t
PHL
,
Maximum Propagation Delay, Clock A to QC
(QA connected to Clock B)
(Figures 1 and 3)
2.0
4.5
6.0
290
58
49
365
73
62
435
87
74
PLH
t
PHL
,
Maximum Propagation Delay, Clock B to QB
(Figures 1 and 3)
2.0
4.5
6.0
130
26
22
165
33
28
195
39
33
PLH
t
PHL
,
Maximum Propagation Delay, Clock B to QC
(Figures 1 and 3)
2.0
4.5
6.0
185
37
31
230
46
39
280
56
48
PLH
t
PHL
,
Maximum Propagation Delay, Clock B to QD
(Figures 1 and 3)
2.0
4.5
6.0
130
26
22
165
33
28
195
39
33
PLH
t
PHL
t
Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)
2.0
4.5
6.0
165
33
28
205
41
35
250
50
43
PHL
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
TLH
THL
C
Maximum Input Capacitance
—
10
10
10
in
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Counter)*
pF
35
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
TIMING REQUIREMENTS (Input t = t = 6 ns)
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
t
Minimum Recovery Time, Reset Inactive to Clock A or Clock B
(Figure 2)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
rec
t
t
Minimum Pulse Width, Clock A, Clock B
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
ns
ns
w
Minimum Pulse Width, Reset
(Figure 2)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
w
t , t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
f
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
3
MOTOROLA
MC54/74HC390
PIN DESCRIPTIONS
OUTPUTS
INPUTS
Clock A (Pins 1, 15) and Clock B (Pins 4, 15)
Q
(Pins 3, 13)
A
Clock A is the clock input to the ÷ 2 counter; Clock B is the
clock input to the ÷ 5 counter. The internal flip–flops are
toggled by high–to–low transitions of the clock input.
Output of the ÷ 2 counter.
Q , Q , Q (Pins 5, 6, 7, 9, 10, 11)
B
C
D
CONTROL INPUTS
Outputs of the ÷ 5 counter. Q is the most significant bit.
D
Reset (Pins 2, 14)
Q
is the least significant bit when the counter is connected
A
Asynchronous reset. A high at the Reset input prevents
counting, resets the internal flip–flops, and forces Q through
for BCD output as in Figure 4. Q is the least significant bit
B
when the counter is operating in the bi–quinary mode as in
Figure 5.
A
Q
low.
D
SWITCHING WAVEFORMS
t
t
f
r
t
w
V
90%
50%
10%
CC
V
CLOCK
CC
50%
RESET
10%
GND
GND
t
w
t
PHL
1/f
max
t
t
50%
PLH
PHL
Q
90%
50%
10%
Q
t
rec
V
CC
t
t
50%
TLH
THL
CLOCK
GND
Figure 1.
Figure 2.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
* Includes all probe and jig capacitance
Figure 3.
MOTOROLA
4
MC54/74HC390
EXPANDED LOGIC DIAGRAM
1, 15
Q
C
CLOCK A
CLOCK B
3, 13
5, 11
D
Q
Q
Q
A
R
4, 12
Q
Q
C
D
B
R
Q
Q
C
6, 10
Q
Q
2
D
C
R
C
7, 9
D
Q
D
R
2, 14
RESET
TIMING DIAGRAM
(Q Connected to Clock B)
A
0
1
2
3
4
5
6
7
8
9
0
1
3
4
5
6
CLOCK A
RESET
Q
A
Q
Q
B
C
Q
D
5
MOTOROLA
MC54/74HC390
APPLICATIONS INFORMATION
Each half of the MC54/74HC390 has independent ÷ 2 and
÷ 5 sections (except for the Reset function). The ÷ 2 and ÷ 5
counters can be connected to give BCD or bi–quinary (2–5)
To obtain a bi–quinary count sequence, the input signals
connected to the Clock B input, and output Q is connected
D
to the Clock A input (Figure 5). Q provides a 50% duty cycle
A
count sequences. If Output Q is connected to the Clock B
output. The bi–quinary count sequence function table is
given in Table 2.
A
input (Figure 4), a decade divider with BCD output is
obtained. The function table for the BCD count sequence is
given in Table 1.
Table 1. BCD Count Sequence*
Output
Table 2. Bi–Quinary Count Sequence**
Output
Count
Count
Q
Q
Q
Q
Q
Q
Q
Q
B
D
C
B
A
A
D
C
0
1
2
3
4
5
6
7
8
9
L
L
L
L
L
L
H
L
H
L
H
L
H
L
H
0
1
2
3
4
8
9
10
11
12
L
L
L
L
L
H
H
H
H
H
L
L
L
H
L
H
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
L
H
H
L
L
L
L
H
L
L
L
L
H
L
H
H
L
L
L
H
H
L
L
H
H
H
H
L
L
H
H
L
L
L
* Q connected to Clock B input.
A
**Q connected to Clock A input.
D
CONNECTION DIAGRAMS
1, 15
3, 13
1, 15
3, 13
5, 11
Q
Q
÷ 2
COUNTER
A
÷
2
A
CLOCK A
CLOCK A
COUNTER
5, 11
6, 10
7, 9
Q
Q
4, 12
2, 14
B
4, 12
2, 14
B
÷
5
CLOCK B
RESET
CLOCK B
RESET
6, 10
7, 9
÷
5
Q
Q
COUNTER
Q
Q
C
D
C
D
COUNTER
Figure 4. BCD Count
Figure 5. Bi-Quinary Count
MOTOROLA
6
MC54/74HC390
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
NOTES:
16
1
9
8
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
–B
–
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
—
0.39
1.27 BSC
MAX
19.93
7.49
5.08
0.50
0.750
0.240
—
0.015
0.050 BSC
–T
SEAT
–
ING
N
K
PLANE
F
G
J
K
L
M
N
0.055
0.100 BSC
0.008
0.125
0.065
1.40
2.54 BSC
0.21
3.18
1.65
E
M
0.015
0.170
0.38
4.31
J 16 PL
F
G
0.300 BSC
15
0.040
7.62 BSC
15
1.01
0.51
M
S
0.25 (0.010)
T
B
D 16 PL
°
°
0°
0°
M
S
0.25 (0.010)
T
A
0.020
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A
–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
9
B
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
1
8
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
MIN
MAX
0.770
0.270
0.175
0.021
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
F
C
L
0.740
0.250
0.145
0.015
0.040
S
0.070
1.77
SEATING
PLANE
–T
0.100 BSC
0.050 BSC
0.015
0.130
0.305
2.54 BSC
1.27 BSC
0.38
3.30
7.74
–
M
K
0.008
0.110
0.295
0.21
2.80
7.50
H
J
G
D 16 PL
M
S
0°
10°
0°
10°
M
M
0.25 (0.010)
T
A
0.020
0.040
0.51
1.01
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
8
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
1
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
MIN
MAX
0.393
0.157
0.068
0.019
0.049
0.386
0.150
0.054
0.014
0.016
0.050 BSC
0.008
0.004
F
K
R X 45°
C
1.25
1.27 BSC
–T
0.19
0.10
0.25
0.25
0.009
0.009
J
SEAT
–
ING
M
K
PLANE
D 16 PL
M
P
R
0
5.80
0.25
°
7
6.20
0.50
°
0
°
7°
0.244
0.019
0.229
0.010
M
S
S
0.25 (0.010)
T
B
A
7
MOTOROLA
MC54/74HC390
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintendedor unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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CODELINE
MC54/74HC390/D
◊
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