MC74HC393NS [MOTOROLA]
Binary Counter, Asynchronous, Up Direction, CMOS, PDIP14,;
| 型号： | MC74HC393NS |
| 厂家： | 
MOTOROLA |
| 描述： | Binary Counter, Asynchronous, Up Direction, CMOS, PDIP14, 计数器 触发器 逻辑集成电路 光电二极管 |
| 文件： | 总8页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
14
14
High–Performance Silicon–Gate CMOS
1
The MC54/74HC393A is identical in pinout to the LS393. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device consists of two independent 4–bit binary ripple counters with
parallel outputs from each counter stage. A ÷ 256 counter can be obtained
by cascading the two binary counters.
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
1
Internal flip–flops are triggered by high–to–low transitions of the clock
input. Reset for the counters is asynchronous and active–high. State
changes of the Q outputs do not occur simultaneously because of internal
ripple delays. Therefore, decoded output signals are subject to decoding
spikes and should not be used as clocks or as strobes except when gated
with the Clock of the HC393A.
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
14
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
1
ORDERING INFORMATION
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
MC54HCXXXAJ
Ceramic
Plastic
SOIC
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
TSSOP
•
Chip Complexity: 236 FETs or 59 Equivalent Gates
PIN ASSIGNMENT
LOGIC DIAGRAM
CLOCK a
RESET a
1
2
3
4
14
13
12
11
V
CC
CLOCK b
RESET b
3, 11
Q1
Q1
Q2
a
4, 10
Q2
Q3
Q4
1, 13
2, 12
Q1
b
BINARY
COUNTER
a
CLOCK
RESET
5, 9
6, 8
Q3
5
6
10
9
Q2
b
a
a
Q4
Q3
b
b
GND
7
8
Q4
PIN 14 = V
CC
PIN 7 = GND
FUNCTION TABLE
Inputs
Clock
Reset
Outputs
X
H
L
H
L
L
L
L
L
No Change
No Change
No Change
Advance to
Next State
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
10/95
REV 0
Motorola, Inc. 1995
MC54/74HC393A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 1.5 to V
+ 1.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
CC
and GND Pins
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
450
level (e.g., either GND or V ).
CC
TSSOP Package†
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
(Ceramic DIP)
L
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
V
CC
= 2.0 V
= 3.0 V
= 4.5 V
= 6.0 V
0
0
0
0
1000
600
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
V
V
IL
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
in
|I
|
20 µA
out
V
in
= V or V
IH
|I
|I
|I
|
|
|
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
IL out
out
out
MOTOROLA
2
MC54/74HC393A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
85 C
125 C
Unit
V
OL
Maximum Low–Level Output
Voltage
V
= V or V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH IL
|I
|
20 µA
out
V
in
= V or V
IH
|I
|I
|I
|
|
|
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
IL out
out
out
I
Maximum Input Leakage Current
V
V
= V
= V
or GND
6.0
6.0
± 0.1
± 1.0
± 1.0
µA
µA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
or GND
4
40
160
CC
in
CC
I
= 0 µA
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
f
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)
2.0
3.0
4.5
6.0
10
15
30
50
9
8
MHz
max
14
28
45
12
25
40
t
t
t
t
,
Maximum Propagation Delay, Clock to Q1
(Figures 1 and 3)
2.0
3.0
4.5
6.0
70
40
20
16
80
45
25
21
90
50
30
27
ns
ns
ns
ns
ns
ns
pF
PLH
t
PHL
,
Maximum Propagation Delay, Clock to Q2
(Figures 1 and 3)
2.0
3.0
4.5
6.0
90
56
32
25
105
70
38
180
100
45
PLH
t
PHL
31
40
,
Maximum Propagation Delay, Clock to Q3
(Figures 1 and 3)
2.0
3.0
4.5
6.0
60
40
30
25
75
55
40
35
90
65
50
42
PLH
t
PHL
,
Maximum Propagation Delay, Clock to Q4
(Figures 1 and 3)
2.0
3.0
4.5
6.0
200
160
35
250
185
45
300
210
60
PLH
t
PHL
30
40
50
t
Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)
2.0
3.0
4.5
6.0
80
48
28
21
95
65
32
25
110
75
40
PHL
30
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
TLH
THL
19
C
Maximum Input Capacitance
—
10
10
10
in
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Counter)*
pF
35
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
3
MOTOROLA
MC54/74HC393A
TIMING REQUIREMENTS (Input t = t = 6 ns)
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
t
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
25
15
5
30
20
6
40
30
10
7
ns
rec
5
5
t
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
ns
ns
ns
w
w
19
t
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
t , t
r f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
4
MC54/74HC393A
PIN DESCRIPTIONS
INPUTS
vided for each counter. A high at the Reset input prevents
counting and forces all four outputs low.
Clock (Pins 1, 13)
Clock input. The internal flip–flops are toggled and the
counter state advances on high–to–low transitions of the
clock input.
OUTPUTS
CONTROL INPUTS
Q1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)
Reset (Pins 2, 12)
Active–high, asynchronous reset. A separate reset is pro-
Parallel binary outputs Q4 is the most significant bit.
SWITCHING WAVEFORMS
t
t
r
f
t
w
V
CC
90%
V
CC
50%
RESET
50%
CLOCK
10%
GND
GND
t
t
w
PHL
1/f
PLH
max
t
t
PHL
50%
rec
Q
90%
50%
10%
t
Q
V
CC
50%
CLOCK
GND
t
t
THL
TLH
Figure 1.
Figure 2.
EXPANDED LOGIC DIAGRAM
TEST
POINT
1, 13
CLOCK
C
C
Q
Q
OUTPUT
3, 11
4, 10
DEVICE
UNDER
TEST
D
D
Q1
Q2
C *
L
Q
Q
* Includes all probe and jig capacitance
Figure 3. Test Circuit
C
C
Q
Q
5, 9
6, 8
Q3
Q4
D
D
Q
Q
2, 12
RESET
5
MOTOROLA
MC54/74HC393A
TIMING DIAGRAM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
CLOCK
RESET
Q1
Q2
Q3
Q4
COUNT SEQUENCE
Outputs
Count
Q4
Q3
Q2
Q1
0
1
2
3
4
5
6
7
8
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
L
L
L
L
H
H
H
H
L
H
H
L
9
L
10
11
12
13
14
15
H
H
L
L
H
H
MOTOROLA
6
MC54/74HC393A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE Y
14
1
8
7
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMESNION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
-B-
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.785
0.280
0.200
0.020
0.065
MIN
19.05
6.23
3.94
0.39
1.40
MAX
19.94
7.11
5.08
0.50
1.65
0.750
0.245
0.155
0.015
0.055
-T-
SEATING
PLANE
K
G
J
K
L
M
N
0.100 BSC
2.54 BSC
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
M
F
G
N
D 14 PL
0.25 (0.010)
J 14 PL
0.300 BSC
15
0.040
7.62 BSC
15
0.51 1.01
0°
°
0°
°
M
M
S
S
T
A
0.25 (0.010)
T
B
0.020
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
ISSUE L
14
1
8
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
B
7
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
C
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.095
0.015
0.135
1.32
0.20
2.92
2.41
0.38
3.43
J
N
0.300 BSC
7.62 BSC
SEATING
PLANE
K
0
10
0
10
0.015
0.039
0.39
1.01
H
G
D
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ISSUE F
–A–
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
P 7 PL
–B–
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
M
M
0.25 (0.010)
B
1
7
MILLIMETERS
INCHES
G
F
R X 45°
DIM
A
B
C
D
F
G
J
MIN
8.55
3.80
1.35
0.35
0.40
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
C
0.337
0.150
0.054
0.014
0.016
J
M
SEATING
PLANE
K
D 14 PL
0.25 (0.010)
1.27 BSC
0.050 BSC
0.19
0.10
0.25
0.25
0.008
0.004
0.009
0.009
M
S
S
T
B
A
K
M
P
R
0
5.80
0.25
°
7
6.20
0.50
°
0
°
7°
0.244
0.019
0.228
0.010
7
MOTOROLA
MC54/74HC393A
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
NOTES:
14X K REF
0.10 (0.004)
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
T
U
V
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
8
7
2X L/2
M
B
L
N
–U–
PIN 1
IDENT.
F
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
K
0.15 (0.006) T
U
A
MILLIMETERS
INCHES
K1
DIM
A
B
C
D
F
G
H
J
J1
K
MIN
4.90
4.30
–––
0.05
0.50
MAX
5.10
4.50
1.20
0.15
0.75
MIN
MAX
0.200
0.177
0.047
0.006
0.030
–V–
0.193
0.169
–––
0.002
0.020
J J1
SECTION N–N
0.65 BSC
0.026 BSC
0.50
0.09
0.09
0.19
0.19
0.60
0.20
0.16
0.30
0.25
0.020
0.004
0.004
0.007
0.007
0.024
0.008
0.006
0.012
0.010
–W–
C
K1
L
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
SEATING
PLANE
–T–
H
G
DETAIL E
D
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
CODELINE
MC54/74HC393A/D
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