MC74HCT174ANDS [MOTOROLA]
D Flip-Flop, 6-Func, Positive Edge Triggered, CMOS, PDIP16;
| 型号： | MC74HCT174ANDS |
| 厂家： | 
MOTOROLA |
| 描述： | D Flip-Flop, 6-Func, Positive Edge Triggered, CMOS, PDIP16 触发器 时钟 |
| 文件： | 总5页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
High–Performance Silicon–Gate CMOS
1
The MC74HCT174A is identical in pinout to the LS174. This device may
be used as a level converter for interfacing TTL or NMOS outputs to High
Speed CMOS inputs.
D SUFFIX
This device consists of six D flip–flops with common Clock and Reset
inputs. Each flip–flop is loaded with a low–to–high transition of the Clock
input. Reset is asynchronous and active–low.
16
SOIC PACKAGE
CASE 751B–05
1
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA
ORDERING INFORMATION
MC74HCXXXAN
MC74HCXXXAD
Plastic
SOIC
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
PIN ASSIGNMENT
•
Chip Complexity: 178 FETs or 44.5 Equivalent Gates
RESET
Q0
1
2
16
15
V
CC
Q5
LOGIC DIAGRAM
D0
D1
3
4
5
6
7
8
14
13
12
11
10
9
D5
D4
3
4
2
5
Q0
D0
D1
D2
D3
D4
D5
Q1
Q4
Q1
Q2
Q3
Q4
Q5
D2
D3
6
7
DATA
INPUTS
NONINVERTING
OUTPUTS
Q2
Q3
11
13
14
10
12
15
GND
CLOCK
FUNCTION TABLE
9
1
CLOCK
RESET
Inputs
Reset Clock
Output
D
Q
PIN 16 = V
PIN 8 = GND
CC
L
X
X
H
L
L
H
L
H
H
H
H
L
X
X
No Change
No Change
Design Criteria
Internal Gate Count*
Value
Units
ea.
ns
44.5
1.5
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
0.005
0.0075
µW
pJ
* Equivalent to a two–input NAND gate.
10/95
REV 6
Motorola, Inc. 1995
MC74HCT174A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 1.5 to V
+ 1.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
CC
and GND Pins
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
750
500
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
C
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
5.5
V , V
in out
DC Input Voltage, Output Voltage
(Referenced to GND)
V
CC
V
T
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
– 55 + 125
500
C
A
t , t
r f
0
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
85 C
125 C
Unit
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 or V
– 0.1 V
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 or V
– 0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
IL
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH IL
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
in
|I
|
20 µA
out
V
= V or V
IH
in
IL
IL
IL
|I
|
4.0 mA
4.5
3.98
3.84
3.70
out
V
OL
Maximum Low–Level Output
Voltage
V
= V or V
IH
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
in
|I
|
20 µA
out
V
= V or V
in
IH
4.0 mA
|I
|
4.5
5.5
5.5
0.26
± 0.1
4.0
0.33
± 1.0
40
0.4
± 1.0
160
out
I
Maximum Input Leakage Current
V
= V
or GND
or GND
µA
µA
in
in
CC
CC
I
Maximum Quiescent Supply
Current (per Package)
V
I
= V
= 0 µA
CC
in
out
∆I
CC
Additional Quiescent Supply
Current
V
V
l
= 2.4 V, Any One Input
≥ – 55 C
25 C to 125 C
in
in
out
= V
or GND, Other Inputs
CC
= 0 µA
5.5
2.9
2.4
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
MC74HCT174A
AC ELECTRICAL CHARACTERISTICS (V
CC
= 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)
L r f
Guaranteed Limit
– 55 to
25 C
Symbol
Parameter
Unit
MHz
ns
85 C
24
125 C
20
f
Maximum Clock Frequency (50% Duty Cycle)
30
24
MAX
t
t
,
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
30
36
PLH
PHL
t
Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)
23
15
10
28
19
10
35
22
10
ns
ns
pF
PHL
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
TLH
t
THL
C
Maximum Input Capacitance
in
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Enabled Output)*
pF
79
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V . For load considerations, see Chapter 2 of the
CC CC
PD CC
TIMING REQUIREMENTS (V
= 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)
CC
L
r
f
Guaranteed Limit
– 55 to 25 C
85 C
Max
125 C
Max
Symbol
Parameter
Fig.
3
Unit
ns
Min
10
Max
Min
13
Min
15
t
su
Minimum Setup Time, Data to Clock
Minimum Hold Time, Clock to Data
t
h
3
5.0
5.0
15
6.0
6.0
19
8.0
8.0
22
ns
t
Minimum Recovery Time, Reset Inactive to Clock
Minimum Pulse Width, Clock
2
ns
rec
t
t
1
ns
w
Minimum Pulse Width, Reset
2
15
19
22
ns
w
t , t
r f
Maximum Input Rise and Fall Times
1
500
500
500
ns
3
MOTOROLA
MC74HCT174A
SWITCHING WAVEFORMS
t
t
r
f
V
t
CC
w
2.7 V
3.0 V
GND
CLOCK
1.3 V
1.3 V
RESET
0.3 V
GND
t
w
t
PHL
1/f
max
1.3 V
t
t
PHL
Q
PLH
90%
1.3 V
10%
t
rec
3.0 V
GND
Q
CLOCK
1.3 V
t
t
THL
TLH
Figure 1.
Figure 2.
TEST POINT
VALID
OUTPUT
3.0 V
DEVICE
UNDER
TEST
1.3 V
DATA
C *
L
GND
3.0 V
t
t
h
su
CLOCK
1.3 V
* Includes all probe and jig capacitance
GND
Figure 3.
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
9
3
CLOCK
D0
C
2
5
Q
Q0
Q1
D
R
1
RESET
C
Q
4
D1
D
R
C
7
Q
Q2
Q3
Q4
Q5
6
D2
D3
D4
D5
D
R
C
Q
10
12
15
11
13
14
D
R
C
Q
D
R
C
Q
D
R
MOTOROLA
4
MC74HCT174A
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A
–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
MIN
MAX
0.770
0.270
0.175
0.021
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
F
C
L
0.740
0.250
0.145
0.015
0.040
S
0.070
1.77
SEATING
–T
–
PLANE
0.100 BSC
0.050 BSC
0.015
0.130
0.305
2.54 BSC
1.27 BSC
0.38
3.30
7.74
M
K
0.008
0.110
0.295
0.21
2.80
7.50
H
J
G
D 16 PL
M
S
0°
10°
0°
10°
M
M
0.25 (0.010)
T
A
0.020
0.040
0.51
1.01
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
MIN
MAX
0.393
0.157
0.068
0.019
0.049
0.386
0.150
0.054
0.014
0.016
F
K
R X 45°
C
1.25
1.27 BSC
0.050 BSC
–T
0.19
0.10
0.25
0.25
0.008
0.004
0.009
0.009
J
SEAT
–
ING
M
K
PLANE
D 16 PL
M
P
R
0
5.80
0.25
°
7
6.20
0.50
°
0
°
7°
0.244
0.019
0.229
0.010
M
S
S
0.25 (0.010)
T
B
A
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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CODELINE
MC74HCT174A/D
◊
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