MC74HCT541DWD [MOTOROLA]
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| 型号： | MC74HCT541DWD |
| 厂家： | 
MOTOROLA |
| 描述： | 暂无描述 驱动器 |
| 文件： | 总5页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
20
1
High–Performance Silicon–Gate CMOS
The MC74HCT541A is identical in pinout to the LS541. This device may
be used as a level converter for interfacing TTL or NMOS outputs to high
speed CMOS inputs.
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
1
The HCT541A is an octal non–inverting buffer/line driver/line receiver
designed to be used with 3–state memory address drivers, clock drivers, and
other bus–oriented systems. This device features inputs and outputs on
opposite sides of the package and two ANDed active–low output enables.
ORDERING INFORMATION
MC74HCTXXXAN
MC74HCTXXXADW
Plastic
SOIC
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS–Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5V
Low Input Current: 1µA
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
FUNCTION TABLE
Inputs
Output Y
OE1 OE2
A
L
L
L
L
L
H
X
X
L
H
Z
Z
H
X
X
H
LOGIC DIAGRAM
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
A8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Z = High Impedance
X = Don’t Care
Data
Inputs
Non–Inverting
Outputs
Pinout: 20–Lead Packages (Top View)
V
OE2
19
Y1
18
Y2
17
Y3
16
Y4
15
Y5
14
Y6
13
Y7
12
Y8
11
CC
1
Output
Enables
OE1
OE2
PIN 20 = V
CC
20
PIN 10 = GND
19
1
2
3
4
5
6
7
9
8
10
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
10/95
Motorola, Inc. 1995
REV 1
MC74HCT541A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 35
± 75
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
CC
and GND Pins
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
750
500
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature Range
– 65 to + 150
C
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP or SOIC Package
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature Range, All Package Types
Input Rise/Fall Time (Figure 1)
5.5
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
0
500
ns
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
Symbol
Parameter
Condition
–55 to 25°C ≤85°C ≤125°C
Unit
V
IH
Minimum High–Level Input Voltage
V
= 0.1V or V
– 0.1V
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
out
|I | ≤ 20µA
CC
out
V
Maximum Low–Level Input Voltage
V
= 0.1V or V
– 0.1V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
IL
out
|I | ≤ 20µA
CC
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
in
IH
|I | ≤ 20µA
IL
out
V
V
= V or V
IH
|I | ≤ 6.0mA
out
4.5
3.98
3.84
3.70
in
IL
V
OL
Maximum Low–Level Output
Voltage
= V or V
IH
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IL
|I | ≤ 20µA
out
V
= V or V
IH
|I | ≤ 6.0mA
out
4.5
5.5
5.5
0.26
±0.1
±0.5
0.33
±1.0
±5.0
0.40
±1.0
in
in
IL
I
Maximum Input Leakage Current
V
= V
CC
or GND
µA
µA
in
I
Maximum Three–State Leakage
Current
Output in High Impedance State
±10.0
OZ
V
= V or V
in
IL IH
V
out
= V or GND
CC
I
Maximum Quiescent Supply
Current (per Package)
V
= V
CC
= 0µA
or GND
5.5
4
40
160
µA
CC
in
I
out
∆I
CC
Additional Quiescent Supply Current
V
V
I
= 2.4V, Any One Input
in
in
out
≥ –55°C
25 to 125°C
= V
CC
or GND, Other Inputs
= 0µA
5.5
2.9
2.4
mA
1. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Total Supply Current = I
+ Σ∆I .
CC
CC
MOTOROLA
3–2
MC74HCT541A
AC CHARACTERISTICS (V
= 5.0V, C = 50 pF, Input t = t = 6 ns)
L r f
CC
Guaranteed Limit
Symbol
Parameter
–55 to 25°C
≤85°C
≤125°C
Unit
t
t
,
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
23
28
32
ns
PLH
PHL
t
t
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
30
30
12
34
34
15
38
38
18
ns
ns
ns
PLZ
PHZ
t
t
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
PZL
PZH
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
TLH
THL
C
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
Maximum Three–State Output Capacitance (Output in High Impedance
State)
out
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Buffer)*
pF
55
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V . For load considerations, see Chapter 2 of the
CC CC
PD CC
SWITCHING WAVEFORMS
3.0V
t
t
f
r
OE1 or OE2
3.0V
1.3V
1.3V
90%
1.3V
10%
GND
INPUT A
t
t
PZL PLZ
HIGH
IMPEDANCE
GND
OUTPUT Y
t
PHL
t
PLH
1.3V
10%
90%
V
OL
90%
t
t
PZH PHZ
1.3V
10%
OUTPUT Y
V
OH
OUTPUT Y
1.3V
t
t
THL
TLH
HIGH
IMPEDANCE
Figure 1.
Figure 2.
TEST CIRCUITS
TEST
POINT
TEST
POINT
CONNECT TO V
WHEN
CC
1k
Ω
OUTPUT
OUTPUT
TESTING t
CONNECT TO GND WHEN
TESTING t and t
AND t .
PLZ
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
.
PHZ PZH
C *
C *
L
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
3–3
MOTOROLA
MC74HCT541A
PIN DESCRIPTIONS
INPUTS
puts are enabled and the device functions as a non–inverting
buffer. When a high voltage is applied to either input, the out-
puts assume the high impedance state.
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8,
9) — Data input pins. Data on these pins appear in non–in-
verted form on the corresponding Y outputs, when the out-
puts are enabled.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11) — Device outputs. Depending upon the state of
the output enable pins, these outputs are either non–invert-
ing outputs or high–impedance outputs.
CONTROLS
OE1, OE2 (PINS 1, 19) — Output enables (active–low).
When a low voltage is applied to both of these pins, the out-
LOGIC DETAIL
To 7 Other
Buffers
V
CC
One of Eight
Buffers
INPUT A
OUTPUT Y
OE1
OE2
MOTOROLA
3–4
MC74HCT541A
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
10
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
1.070
0.260
0.180
0.022
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
1.010
0.240
0.150
0.015
–T–
SEATING
PLANE
K
E
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
F
G
J
K
L
N
E
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
0.25 (0.010)
M
M
0.25 (0.010)
T B
M
N
0
15
0
15
0.020
0.040
0.51
1.01
M
M
T
A
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
10X P
–B–
M
M
0.010 (0.25)
B
1
10
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
20X D
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
0.010 (0.25)
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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MC74HCT541A/D
◊
相关型号：
MC74HCT541ND
Bus Driver, HCT Series, 1-Func, 8-Bit, True Output, CMOS, PDIP20, PLASTIC, DIP-20
MOTOROLA
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