MC74HCT573ADTEL [ONSEMI]
IC,LATCH,SINGLE,8-BIT,HCT-CMOS,TSSOP,20PIN,PLASTIC;
| 型号： | MC74HCT573ADTEL |
| 厂家： | 
ONSEMI |
| 描述： | IC,LATCH,SINGLE,8-BIT,HCT-CMOS,TSSOP,20PIN,PLASTIC 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High–Performance Silicon–Gate CMOS
http://onsemi.com
The MC74HCT573A is identical in pinout to the LS573. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High–Speed CMOS inputs.
MARKING
DIAGRAMS
20
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold times becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
high–impedance state. Thus, data may be latched even when the
outputs are not enabled.
The HCT573A is identical in function to the HCT373A but has the
Data Inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
PDIP–20
N SUFFIX
CASE 738
MC74HCT573AN
AWLYYWW
20
1
1
20
SOIC WIDE–20
DW SUFFIX
CASE 751D
HCT573A
AWLYYWW
20
1
1
20
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS–Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 10 µA
HCT
573A
ALYW
TSSOP–20
DT SUFFIX
CASE 948G
20
1
1
A
= Assembly Location
WL = Wafer Lot
YY = Year
• In Compliance with the Requirements Defined by JEDEC Standard
WW = Work Week
No. 7A
• Chip Complexity: 234 FETs or 58.5 Equivalent Gates
— Improved Propagation Delays
ORDERING INFORMATION
— 50% Lower Quiescent Power
Device
Package
PDIP–20
Shipping
1440 / Box
38 / Rail
MC74HCT573AN
MC74HCT573ADW
SOIC–WIDE
MC74HCT573ADWR2 SOIC–WIDE 1000 / Reel
MC74HCT573ADT
TSSOP–20
75 / Rail
MC74HCT573ADTR2
TSSOP–20 2500 / Reel
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 8
MC74HCT573A/D
MC74HCT573A
LOGIC DIAGRAM
PIN ASSIGNMENT
OUTPUT
ENABLE
2
3
4
19
1
2
3
4
5
6
7
8
9
20
V
CC
D0
D1
D2
Q0
Q1
Q2
18
17
D0
D1
D2
D3
D4
D5
D6
D7
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
5
6
16
15
NONINVERTING
OUTPUTS
DATA
INPUTS
D3
D4
Q3
Q4
7
8
9
14
13
12
D5
D6
D7
Q5
Q6
Q7
11
1
LATCH ENABLE
PIN 20 = V
CC
PIN 10 = GND
LATCH
ENABLE
GND 10
11
OUTPUT ENABLE
FUNCTION TABLE
Inputs
Output
Output Latch
Enable Enable
D
Q
L
L
L
H
H
L
H
L
X
X
H
L
No Change
Z
H
X
X = Don’t Care
Z = High Impedance
Design Criteria
Value
Units
ea
Internal Gate Count*
58.5
1.5
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
ns
5.0
µW
0.0075
pJ
*Equivalent to a two–input NAND gate.
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2
MC74HCT573A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
CC
V
out
– 0.5 to V
+ 0.5
V
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
and GND Pins
CC
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, TSSOP or SOIC Package)
L
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: –10 mW/ C from 65 to 125 C
SOIC Package: –7 mW/ C from 65 to 125 C
TSSOP Package: –6.1 mW/°C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
5.5
V , V
in out
V
CC
V
T
A
– 55 + 125
500
C
t , t
r f
0
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
Symbol
Parameter
Test Conditions
25 C
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
IL
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
in
IL
IL
IL
IL
|I
|
20 µA
out
V
= V or V
IH
in
|I
|
6.0 mA
4.5
3.98
3.84
3.7
out
V
OL
Maximum Low–Level Output
Voltage
V
V
= V or V
IH
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
in
|I
|
20 µA
out
V
= V or V
in
IH
|I
|
6.0 mA
4.5
5.5
5.5
0.26
± 0.1
± 0.5
0.33
± 1.0
± 5.0
0.4
± 1.0
± 10
out
I
in
Maximum Input Leakage Current
V
in
= V
or GND
µA
µA
CC
I
Maximum Three–State
Leakage Current
Output in High–Impedance State
OZ
V
= V or V
in
IL
= V
IH
or GND
V
out
CC
I
Maximum Quiescent Supply
Current (per Package)
V
= V
or GND
5.5
4.0
40
160
µA
CC
in
CC
I
0 µA
out
∆I
CC
Additional Quiescent Supply
Current
V
V
l
= 2.4 V, Any One Input
in
in
out
≥ – 55 C
25 C to 125 C
= V
or GND, Other Inputs
CC
= 0 µA
2.9
2.4
5.5
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
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3
MC74HCT573A
AC ELECTRICAL CHARACTERISTICS (V
CC
= 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)
L r f
Guaranteed Limit
– 55 to
25 C
Symbol
Parameter
Unit
85 C
125 C
t
t
,
Maximum Propagation Delay, Input D to Output Q
(Figures 1 and 5)
30
30
28
28
12
38
45
ns
PLH
PHL
t
t
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
38
35
35
15
45
42
42
18
ns
ns
ns
ns
PLH
PHL
T
T
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
PLZ,
PHZ
t
t
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
TZL,
TZH
t
t
,
Maximum Output Transition Time, any Output
(Figures 1 and 5)
TLH
THL
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
out
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Enabled Output)*
pF
48
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
V
f + I
V . For load considerations, see Chapter 2 of the
CC CC
PD CC
TIMING REQUIREMENTS (V
= 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)
CC
L
r
f
Guaranteed Limit
– 55 to 25 C
85 C
Max
125 C
Max
Symbol
Parameter
Fig.
4
Unit
ns
Min
10
Max
Min
13
Min
15
t
su
Minimum Setup Time, Input D to Latch Enable
Minimum Hold Time, Latch Enable to Input D
Minimum Pulse Width, Latch Enable
t
h
4
5.0
15
5.0
19
5.0
22
ns
t
w
2
ns
t , t
r
Maximum Input Rise and Fall Times
1
500
500
500
ns
f
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4
MC74HCT573A
SWITCHING WAVEFORMS
3.0 V
GND
LATCH
ENABLE
t
t
f
1.3 V
t
r
3.0 V
2.7 V
1.3 V
INPUT D
Q
0.3 V
w
GND
t
t
PHL
PLH
90%
1.3 V
10%
t
t
PHL
PLH
1.3 V
t
t
TLH
THL
Q
Figure 1.
Figure 2.
OUTPUT
ENABLE
3.0 V
GND
VALID
1.3 V
3.0 V
GND
1.3 V
INPUT D
t
t
PLZ
PZL
HIGH
IMPEDANCE
Q
Q
1.3 V
t
t
h
SU
3.0 V
GND
10%
V
OL
t
t
1.3 V
PZH PHZ
LATCH
ENABLE
V
OH
90%
1.3 V
HIGH
IMPEDANCE
Figure 3.
Figure 4.
EXPANDED LOGIC DIAGRAM
TEST POINT
OUTPUT
2
D0
D
19
Q
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
DEVICE
UNDER
TEST
3
D1
D
C *
L
18
17
16
15
14
13
12
Q
LE
4
D2
D
Q
LE
*Includes all probe and jig capacitance
5
D3
D
Q
LE
Figure 5. Test Circuit
6
D4
D
Q
LE
7
D5
D
TEST POINT
Q
LE
CONNECT TO V WHEN
CC
8
1 kΩ
OUTPUT
D6
D
TESTING t
AND t
.
PLZ
PZL
Q
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
LE
.
PHZ PZH
9
C *
L
D7
D
Q
LE
11
LATCH ENABLE
*Includes all probe and jig capacitance
1
OUTPUT ENABLE
Figure 6. Test Circuit
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5
MC74HCT573A
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
10
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
INCHES
DIM MIN MAX
1.070 25.66 27.17
MILLIMETERS
MIN MAX
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.050 BSC
0.050
0.260
0.180
0.022
6.10
3.81
0.39
1.27 BSC
1.27
6.60
4.57
0.55
–T–
SEATING
PLANE
K
M
0.070
1.77
N
E
G
0.100 BSC
2.54 BSC
J
0.008
0.110
0.300 BSC
0.015
0.140
0.21
2.80
7.62 BSC
0
0.51
0.38
3.55
G
F
K
L
M
N
J 20 PL
D 20 PL
M
M
0.25 (0.010)
T B
0
15
0.040
15
1.01
0.020
M
M
0.25 (0.010)
T A
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
B
20X B
A
A1
B
C
D
E
e
H
h
2.35
0.10
0.35
0.23
12.65 12.95
7.40 7.60
1.27 BSC
10.05 10.55
M
S
S
T
0.25
A
B
A
0.25
0.50
0
0.75
0.90
7
L
SEATING
PLANE
18X e
A1
C
T
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6
MC74HCT573A
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
CASE 948E–02
ISSUE A
20X K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
M
S
S
0.10 (0.004)
T U
V
S
Y14.5M, 1982.
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
S
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
0.15 (0.006) T U
M
A
–V–
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
C
6.40
4.30
–––
6.60 0.252
4.50 0.169
1.20
N
–––
D
F
0.05
0.50
0.15 0.002
0.75 0.020
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
–W–
C
6.40 BSC
0.252 BSC
G
D
M
0
8
0
8
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
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7
MC74HCT573A
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLCproductsarenotdesigned, intended, orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody, orotherapplications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment:
CENTRAL/SOUTH AMERICA:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
Email: ONlit–spanish@hibbertco.com
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
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Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
Toll Free from Hong Kong & Singapore:
Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada
001–800–4422–3781
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
Email: ONlit–asia@hibbertco.com
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German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)
Email: ONlit–german@hibbertco.com
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549
Phone: 81–3–5740–2745
French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time)
Email: ONlit–french@hibbertco.com
English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)
Email: ONlit@hibbertco.com
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
For additional information, please contact your local
Sales Representative.
*Available from Germany, France, Italy, England, Ireland
MC74HCT573A/D
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