MC74HCT573ADW [MOTOROLA]
Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs; 八路三态同相透明锁存器与LSTTL兼容输入型号: | MC74HCT573ADW |
厂家: | MOTOROLA |
描述: | Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs |
文件: | 总6页 (文件大小:206K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
20
High–Performance Silicon–Gate CMOS
1
The MC74HCT573A is identical in pinout to the LS573. This device may
be used as a level converter for interfacing TTL or NMOS outputs to
High–Speed CMOS inputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes low,
data meeting the setup and hold times becomes latched.
The Output Enable input does not affect the state of the latches, but when
Output Enable is high, all device outputs are forced to the high–impedance
state. Thus, data may be latched even when the outputs are not enabled.
The HCT573A is identical in function to the HCT373A but has the Data
Inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
1
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
20
1
ORDERING INFORMATION
MC74HCTXXXAN Plastic
MC74HCTXXXADW SOIC
MC74HCTXXXADT TSSOP
The HCT573A is the noninverting version of the HC563A.
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS–Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 10 µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 234 FETs or 58.5 Equivalent Gates
PIN ASSIGNMENT
OUTPUT
ENABLE
1
20
V
CC
D0
2
3
4
19
18
17
Q0
Q1
Q2
D1
D2
•
— Improved Propagation Delays
— 50% Lower Quiescent Power
D3
D4
D5
D6
5
6
7
8
16
15
14
13
Q3
Q4
Q5
Q6
LOGIC DIAGRAM
2
3
4
19
18
17
D7
9
12
11
Q7
D0
D1
D2
Q0
Q1
Q2
LATCH
ENABLE
GND
10
5
6
16
15
NONINVERTING
OUTPUTS
DATA
INPUTS
D3
D4
Q3
Q4
FUNCTION TABLE
7
8
14
13
D5
D6
D7
Q5
Q6
Q7
Inputs
Output
9
12
Output Latch
Enable Enable
D
Q
11
1
L
L
L
H
H
L
H
L
X
X
H
LATCH ENABLE
L
No Change
Z
PIN 20 = V
PIN 10 = GND
CC
OUTPUT ENABLE
H
X
X = Don’t Care
Z = High Impedance
Design Criteria
Internal Gate Count*
Value
58.5
1.5
Units
ea
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
ns
5.0
µW
pJ
0.0075
* Equivalent to a two–input NAND gate.
10/96
REV 7
Motorola, Inc. 1996
MC74HCT573A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
range GND (V or V
)
V
.
DC Supply Current, V
and GND Pins
CC
in out
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, TSSOP or SOIC Package)
L
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: –10 mW/ C from 65 to 125 C
SOIC Package: –7 mW/ C from 65 to 125 C
TSSOP Package: –6.1 mW/°C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
5.5
V , V
in out
V
CC
V
T
A
– 55 + 125
500
C
t , t
r f
0
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
Symbol
Parameter
Test Conditions
25 C
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
IL
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
in
IL
IL
IL
IL
|I
|
20 µA
out
V
= V or V
IH
in
|I
|
6.0 mA
4.5
3.98
3.84
3.7
out
V
OL
Maximum Low–Level Output
Voltage
V
V
= V or V
IH
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
in
|I
|
20 µA
out
V
= V or V
in
IH
|I
|
6.0 mA
4.5
5.5
5.5
0.26
± 0.1
± 0.5
0.33
± 1.0
± 5.0
0.4
± 1.0
± 10
out
I
in
Maximum Input Leakage Current
V
in
= V
or GND
µA
µA
CC
I
Maximum Three–State
Leakage Current
Output in High–Impedance State
OZ
V
= V or V
in
IL
= V
IH
or GND
V
out
CC
I
Maximum Quiescent Supply
Current (per Package)
V
= V
or GND
5.5
4.0
40
160
µA
CC
in
CC
I
0 µA
out
∆I
CC
Additional Quiescent Supply
Current
V
V
l
= 2.4 V, Any One Input
in
in
out
≥ – 55 C
25 C to 125 C
= V
or GND, Other Inputs
CC
= 0 µA
2.9
2.4
5.5
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
MC74HCT573A
AC ELECTRICAL CHARACTERISTICS (V
CC
= 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)
L r f
Guaranteed Limit
– 55 to
25 C
Symbol
Parameter
Unit
85 C
125 C
t
t
,
Maximum Propagation Delay, Input D to Output Q
(Figures 1 and 5)
30
30
28
28
12
38
45
ns
PLH
PHL
t
t
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
38
35
35
15
45
42
42
18
ns
ns
ns
ns
PLH
PHL
T
T
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
PLZ,
PHZ
t
t
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
TZL,
TZH
t
t
,
Maximum Output Transition Time, any Output
(Figures 1 and 5)
TLH
THL
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
out
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Enabled Output)*
pF
48
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V . For load considerations, see Chapter 2 of the
CC CC
PD CC
TIMING REQUIREMENTS (V
= 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)
L r f
CC
Guaranteed Limit
– 55 to 25 C
85 C
Max
125 C
Max
Symbol
Parameter
Fig.
4
Unit
ns
Min
10
Max
Min
13
Min
15
t
su
Minimum Setup Time, Input D to Latch Enable
Minimum Hold Time, Latch Enable to Input D
Minimum Pulse Width, Latch Enable
t
h
4
5.0
15
5.0
19
5.0
22
ns
t
w
2
ns
t , t
r
Maximum Input Rise and Fall Times
1
500
500
500
ns
f
3
MOTOROLA
MC74HCT573A
SWITCHING WAVEFORMS
3.0 V
GND
LATCH
ENABLE
t
t
f
1.3 V
t
r
3.0 V
2.7 V
1.3 V
0.3 V
INPUT D
w
GND
t
t
PHL
PLH
90%
1.3 V
10%
t
t
PHL
PLH
Q
1.3 V
t
t
TLH
THL
Q
Figure 1.
Figure 2.
OUTPUT
ENABLE
3.0 V
GND
VALID
1.3 V
3.0 V
GND
1.3 V
INPUT D
t
t
PLZ
PZL
HIGH
IMPEDANCE
Q
1.3 V
t
t
h
SU
3.0 V
GND
10%
V
V
OL
t
t
1.3 V
PZH
PHZ
LATCH
ENABLE
90%
OH
Q
1.3 V
HIGH
IMPEDANCE
Figure 3.
Figure 4.
EXPANDED LOGIC DIAGRAM
TEST POINT
2
D0
D
19
OUTPUT
Q
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
DEVICE
UNDER
TEST
3
D1
D
C *
18
17
16
15
14
13
12
L
Q
LE
4
D2
D
Q
LE
* Includes all probe and jig capacitance
5
D3
D
Q
LE
Figure 5. Test Circuit
6
D4
D
Q
LE
7
D5
D
TEST POINT
Q
LE
CONNECT TO V
WHEN
.
PZL
CC
AND t
8
1 k
Ω
OUTPUT
D6
D
TESTING t
PLZ
CONNECT TO GND WHEN
TESTING t AND t
Q
DEVICE
UNDER
TEST
LE
.
PZH
PHZ
9
C *
L
D7
D
Q
LE
11
LATCH ENABLE
* Includes all probe and jig capacitance
1
OUTPUT ENABLE
Figure 6. Test Circuit
MOTOROLA
4
MC74HCT573A
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
10
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
1.070
0.260
0.180
0.022
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
1.010
0.240
0.150
0.015
–T–
SEATING
PLANE
K
E
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
F
G
J
K
L
N
E
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
0.25 (0.010)
M
M
0.25 (0.010)
T B
M
N
0
15
0
15
0.020
0.040
0.51
1.01
M
M
T
A
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
10X P
–B–
M
M
0.010 (0.25)
B
1
10
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
20X D
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
0.010 (0.25)
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
5
MOTOROLA
MC74HCT573A
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X K REF
0.10 (0.004)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
M
S
S
T
U
V
S
Y14.5M, 1982.
0.15 (0.006)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
N
S
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
0.15 (0.006)
T U
M
A
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
6.40
4.30
–––
0.05
0.50
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
0.047
0.006
0.030
–V–
0.252
0.169
–––
0.002
0.020
N
F
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
G
D
M
0
8
0
8
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
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51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MC74HCT573A/D
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