MC74LVX541M [MOTOROLA]
Bus Driver, LV/LV-A/LVX/H Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, EIAJ, PLASTIC, SOIC-20;
| 型号： | MC74LVX541M |
| 厂家： | 
MOTOROLA |
| 描述： | Bus Driver, LV/LV-A/LVX/H Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, EIAJ, PLASTIC, SOIC-20 光电二极管 |
| 文件： | 总8页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC74LVX541 is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74LVX541 is a noninverting type. When either OE1 or OE2
are high, the terminal outputs are in the high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
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MARKING
DIAGRAMS
20
SOIC–20
DW SUFFIX
CASE 751D
LVX541
AWLYYWW
• High Speed: t
= 5.0ns (Typ) at V
= 3.3V
PD
• Low Power Dissipation: I
CC
= 4µA (Max) at T = 25°C
CC
A
• High Noise Immunity: V
= V
= 28% V
NIL CC
1
NIH
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 3.6V Operating Range
20
TSSOP–20
DT SUFFIX
CASE 948E
LVX541
AWLYWW
• Low Noise: V
= 1.2V (Max)
OLP
1
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 134 FETs or 33.5 Equivalent Gates
20
SOIC EIAJ–20
M SUFFIX
CASE 967
LVX541
ALYW
1
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
A
= Assembly Location
WL = Wafer Lot
= Year
WW = Work Week
Y
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
38 Units/Rail
MC74LVX541DW
MC74LVX541DWR2
MC74LVX541DT
SOIC–20
SOIC–20 1000 Units/Reel
TSSOP–20 75 Units/Rail
MC74LVX541DTR2 TSSOP–20 2500 Units/Reel
MC74LVX541M
SOIC
40 Units/Rail
EIAJ–20
MC74LVX541MEL
SOIC
2000 Units/Reel
EIAJ–20
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
June, 2000 – Rev. 0
MC74LVX541/D
MC74LVX541
LOGIC DIAGRAM
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
DATA
INPUTS
NONINVERTING
OUTPUTS
A8
1
OE1
OUTPUT
ENABLES
19
OE2
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
OE1
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
20
V
CC
19 OE2
18 Y1
17 Y2
16 Y3
15 Y4
14 Y5
13 Y6
12 Y7
11 Y8
Output Y
OE1 OE2
A
L
L
L
L
L
H
X
X
L
H
Z
Z
H
X
X
H
GND 10
IEC LOGIC DIAGRAM
&
1
QE1
EN
19
QE2
18
2
3
4
5
6
7
8
9
A1
A2
A3
A4
1
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
17
16
15
14
13
12
11
A5
A6
A7
A8
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MC74LVX541
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage
DC Input Voltage
– 0.5 to + 7.0
– 0.5 to + 7.0
CC
V
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
– 0.5 to V
CC
+ 0.5
V
out
I
IK
– 20
mA
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
± 20
± 25
± 50
OK
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
I
DC Output Current, per Pin
DC Supply Current, V and GND Pins
in out
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
I
CC
level (e.g., either GND or V
).
P
D
Power Dissipation in Still Air,
SOIC Packages†
TSSOP Package†
500
450
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
C
* Absolutemaximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolute–maximum–rated
conditions is not implied.
†Derating — SOIC Packages: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
3.6
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
in
5.5
V
V
out
0
V
CC
V
T
Operating Temperature, All Package Types
Input Rise and Fall Time = 3.3V ±0.3V
– 40
0
+ 85
100
C
A
t , t
r f
V
CC
ns/V
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = – 40 to 85°C
A
V
CC
V
Symbol
Parameter
Test Conditions
Unit
Min
Typ
Max
Min
Max
V
IH
Minimum High–Level
Input Voltage
2.0
3.0
3.6
1.50
2.0
2.4
1.50
2.0
2.4
V
V
Maximum Low–Level
Input Voltage
2.0
3.0
3.6
0.50
0.80
0.80
0.50
0.80
0.80
V
V
V
IL
V
OH
Minimum High–Level
Output Voltage
I
I
I
= – 50µA
= – 50µA
= – 4mA
2.0
3.0
3.0
1.9
2.9
2.58
2.0
3.0
1.9
2.9
2.48
OH
OH
OH
V
in
= V or V
IH
IL
V
OL
Maximum Low–Level
Output Voltage
I
I
I
= 50µA
= 50µA
= 4mA
2.0
3.0
3.0
0.0
0.0
0.1
0.1
0.36
0.1
0.1
0.44
OL
OL
OL
V
in
= V or V
IH
IL
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3
MC74LVX541
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = – 40 to 85°C
A
V
CC
V
Symbol
Parameter
Test Conditions
Min
Typ
Max
Min
Max
Unit
I
Maximum Input
Leakage Current
V
V
= 5.5V or GND
0 to 3.6
± 0.1
± 1.0
µA
in
in
I
Maximum Three–State
Leakage Current
= V or V
IL
3.6
± 0.25
± 2.5
µA
µA
OZ
CC
in
IH
or GND
V
out
= V
CC
or GND
CC
I
Maximum Quiescent
Supply Current
V
in
= V
3.6
4.0
40.0
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T
A
= – 40 to 85°C
Symbol
Parameter
Test Conditions
Unit
Min
Typ
Max
Min
1.0
Max
t
t
,
Maximum Propagation Delay,
A to Y
V
V
V
= 2.7V
C
C
= 15pF
= 50pF
5.0
7.5
7.0
10.5
8.5
12.0
ns
PLH
CC
CC
CC
L
L
1.0
PHL
= 3.3 ± 0.3V
C
C
= 15pF
= 50pF
3.5
5.0
5.0
7.0
1.0
1.0
6.0
8.0
L
L
t
t
,
Output Enable TIme,
OE to Y
= 2.7V
= 1kΩ
C
C
= 15pF
= 50pF
6.8
9.3
10.5
14.0
1.0
1.0
12.5
16.0
ns
ns
PZL
L
L
R
PZH
L
V
R
= 3.3 ± 0.3V
= 1kΩ
C
C
= 15pF
= 50pF
4.7
6.2
7.2
9.2
1.0
1.0
8.5
10.5
CC
L
L
L
t
t
,
Output Disable Time,
OE to Y
V
R
= 2.7V
= 1kΩ
C
C
C
C
= 50pF
= 50pF
= 50pF
= 50pF
11.2
15.4
8.8
1.5
1.0
10
1.0
17.5
10.0
1.5
PLZ
CC
L
L
L
L
PHZ
L
V
R
= 3.3 ± 0.3V
= 1kΩ
6.0
1.0
CC
L
t
t
,
Output to Output Skew
V
CC
= 2.7V
(Note 1.)
ns
ns
OSLH
OSHL
V
= 3.3 ± 0.3V
CC
(Note 1.)
1.0
C
Maximum Input Capacitance
4
6
10
pF
pF
in
C
Maximum Three–State Output
Capacitance (Output in High
Impedance State)
out
Typical @ 25°C, V
= 5.0V
CC
C
Power Dissipation Capacitance (Note 2.)
pF
18
PD
1. Parameter guaranteed by design. t = |t – t
|, t
= |t
– t
|.
OSLH PLHm PLHn OSHL
PHLm PHLn
2. C
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Averageoperatingcurrentcanbeobtainedbytheequation:I
=C
.
V
f
+I
/8(perbit).C isusedtodeterminetheno–load
PD
CC(OPR)
PD CC in CC
2
dynamic power consumption; P = C
V
CC
f
+ I
V
D
PD
in CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V
= 3.3V)
r
f
L
CC
T
A
= 25°C
Symbol
Parameter
Unit
V
Typ
Max
V
OLP
Quiet Output Maximum Dynamic V
0.5
0.8
–0.8
2.0
OL
V
OLV
Quiet Output Minimum Dynamic V
– 0.5
V
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
0.8
V
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4
MC74LVX541
SWITCHING WAVEFORMS
V
CC
OE1 or OE2
50%
50%
V
CC
GND
A
50%
t
t
PZL PLZ
HIGH
IMPEDANCE
GND
t
t
PHL
PLH
50% V
CC
Y
Y
V
+0.3V
–0.3V
OL
t
t
50% V
CC
PZH PHZ
Y
V
OH
50% V
CC
HIGH
IMPEDANCE
Figure 1.
Figure 2.
TEST CIRCUITS
TEST
TEST
POINT
POINT
CONNECT TO V WHEN
CC
1kΩ
OUTPUT
OUTPUT
TESTING t
CONNECT TO GND WHEN
TESTING t AND t
AND t .
PZL
PLZ
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
.
PHZ PZH
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
INPUT EQUIVALENT CIRCUIT
INPUT
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5
MC74LVX541
PACKAGE DIMENSIONS
SOIC–20
DW SUFFIX
PLASTIC SOIC WIDE PACKAGE
CASE 751D–05
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ISSUE F
–A–
ANSI Y14.5M, 1982.
20
11
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
10X P
–B–
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
M
M
0.010 (0.25)
B
1
10
MILLIMETERS
DIM MIN MAX
INCHES
20X D
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
A
B
C
D
F
12.65
7.40
2.35
0.35
0.50
12.95 0.499
7.60 0.292
2.65 0.093
0.49 0.014
0.90 0.020
M
S
S
0.010 (0.25) T A
B
F
G
J
K
M
P
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32 0.010
0.25 0.004
0.012
0.009
7
R X 45
7
0
10.05
0.25
10.55 0.395
0.75 0.010
0.415
0.029
C
R
SEATING
PLANE
–T–
M
18X G
K
TSSOP–20
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
0.10 (0.004)
T U
V
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
S
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
0.15 (0.006) T U
M
A
–V–
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
C
6.40
4.30
–––
6.60 0.252
4.50 0.169
1.20
N
–––
D
F
0.05
0.50
0.15 0.002
0.75 0.020
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
–W–
C
6.40 BSC
0.252 BSC
G
D
M
0
8
0
8
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
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6
MC74LVX541
PACKAGE DIMENSIONS
SOIC EIAJ–20
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 967–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
20
11
Q
1
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
E
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN MAX
––– 0.081
e
A
DIM MIN
MAX
c
A
A
–––
0.05
0.35
0.18
2.05
0.20 0.002 0.008
0.50 0.014 0.020
0.27 0.007
1
b
c
0.011
D
E
e
12.35 12.80 0.486 0.504
A
b
1
5.10
5.45 0.201 0.215
1.27 BSC
0.050 BSC
8.20 0.291 0.323
0.85 0.020 0.033
1.50 0.043 0.059
M
0.10 (0.004)
0.13 (0.005)
H
7.40
0.50
1.10
0
0.70
–––
E
L
L
E
M
Q
10
0.90 0.028 0.035
0.81 ––– 0.032
10
0
1
Z
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7
MC74LVX541
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLCproductsarenotdesigned, intended, orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody, orotherapplications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
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attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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MC74LVX541/D
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