MC74VHC373DT [MOTOROLA]
Octal D-Type Latch with 3-State Output; 八D型锁存器具有三态输出
| 型号： | MC74VHC373DT |
| 厂家： | 
MOTOROLA |
| 描述： | Octal D-Type Latch with 3-State Output |
| 文件： | 总7页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The MC74VHC373 is an advanced high speed CMOS octal latch with
3–state output fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
This 8–bit D–type latch is controlled by a latch enable input and an output
enable input. When the output enable input is high, the eight outputs are in a
high impedance state.
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
•
•
•
•
•
•
•
•
•
•
•
High Speed: t
= 5.0ns (Typ) at V
= 5V
PD
Low Power Dissipation: I
CC
= 4µA (Max) at T = 25°C
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
CC
A
High Noise Immunity: V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
= V
= 28% V
NIH
NIL CC
Designed for 2V to 5.5V Operating Range
Low Noise: V
= 0.9V (Max)
OLP
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 186 FETs or 46.5 Equivalent Gates
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
ORDERING INFORMATION
MC74VHCXXXDW
MC74VHCXXXDT
MC74VHCXXXM
SOIC
TSSOP
SOIC EIAJ
LOGIC DIAGRAM
2
5
3
D0
D1
D2
D3
D4
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
PIN ASSIGNMENT
6
7
1
20
V
OE
Q0
D0
D1
CC
8
9
DATA
INPUTS
NONINVERTING
OUTPUTS
2
3
4
19
18
17
Q7
D7
D6
13
12
15
16
19
14
17
18
D5
D6
D7
Q1
Q2
5
16
15
14
13
12
11
Q6
Q5
D5
D4
Q4
6
D2
7
11
1
D3
8
LE
OE
Q3
9
GND
10
LE
FUNCTION TABLE
INPUTS
OUTPUT
Q
OE
LE
D
L
L
L
H
H
L
H
L
X
X
H
L
No Change
Z
H
X
6/97
REV 1
Motorola, Inc. 1997
MC74VHC373
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage
DC Input Voltage
– 0.5 to + 7.0
– 0.5 to + 7.0
CC
V
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
– 0.5 to V
CC
+ 0.5
V
out
I
IK
– 20
mA
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
± 20
± 25
± 75
OK
V
should be constrained to the
out
range GND (V or V
)
V
.
I
DC Output Current, per Pin
DC Supply Current, V and GND Pins
in out
CC
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
I
CC
level (e.g., either GND or V
).
P
D
Power Dissipation in Still Air,
SOIC Packages†
TSSOP Package†
500
450
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
C
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may adversely
affect device reliability. Functional operation under absolute–maximum–rated conditions is not
implied.
†Derating — SOIC Packages: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
in
5.5
V
V
out
0
V
CC
V
T
Operating Temperature
Input Rise and Fall Time
– 40
+ 85
C
A
t , t
r f
V
CC
V
CC
= 3.3V
= 5.0V
0
0
100
20
ns/V
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = – 40 to 85°C
A
V
CC
V
Symbol
Parameter
Test Conditions
Unit
Min
1.50
Typ
Max
Min
Max
V
IH
Minimum High–Level
Input Voltage
2.0
3.0 to
5.5
1.50
V
V
x 0.7
V
x 0.7
CC
CC
V
Maximum Low–Level
Input Voltage
2.0
3.0 to
5.5
0.50
0.50
V
V
IL
V
x 0.3
V
x 0.3
CC
CC
V
OH
Minimum High–Level
Output Voltage
V
= V or V
IH
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
in
IL
IL
I
= – 50µ
OH
V
in
= V or V
IH
I
I
= – 4mA
3.0
4.5
2.58
3.94
2.48
3.80
OH
OH
= – mA8
V
OL
Maximum Low–Level
Output Voltage
V
= V or V
IH IL
= 50µA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
in
I
OL
V
= V or V
in
in
IH
IL
I
I
= 4mA
= 8mA
3.0
4.5
0.36
0.36
0.44
0.44
OL
OL
I
in
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to 5.5
± 0.1
± 1.0
µA
MOTOROLA
2
MC74VHC373
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = – 40 to 85°C
A
V
CC
V
Symbol
Parameter
Test Conditions
Min
Typ
Max
Min
Max
Unit
I
Maximum Three–State
Leakage Current
V
= V or V
5.5
± 0.25
± 2.5
µA
OZ
in
IL
= V
IH
or GND
V
out
CC
or GND
I
Maximum Quiescent
Supply Current
V
in
= V
5.5
4.0
40.0
µA
CC
CC
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T
A
= – 40 to 85°C
Symbol
Parameter
Test Conditions
Unit
Min
Typ
Max
Min
1.0
Max
t
t
t
,
Maximum Propagation Delay,
D to Q
V
V
V
V
V
= 3.3 ± 0.3V
= 5.0 ± 0.5V
= 3.3 ± 0.3V
= 5.0 ± 0.5V
= 3.3 ± 0.3V
C
C
= 15pF
= 50pF
7.0
9.5
11.0
14.5
13.0
16.5
ns
PLH
CC
CC
CC
CC
CC
L
L
t
1.0
PHL
C
C
= 15pF
= 50pF
4.9
6.4
7.2
9.2
1.0
1.0
8.5
10.5
L
L
,
Maximum Propagation Delay,
LE to Q
C
C
= 15pF
= 50pF
7.3
9.8
11.4
14.9
1.0
1.0
13.5
17.0
ns
ns
ns
PLH
t
L
L
PHL
C
C
= 15pF
= 50pF
5.0
6.5
7.2
9.2
1.0
1.0
8.5
10.5
L
L
,
Output Enable Time,
OE to Q
C
C
= 15pF
= 50pF
7.3
9.8
11.4
14.9
1.0
1.0
13.5
17.0
PZL
L
L
t
R
= 1kΩ
PZH
L
V
R
= 5.0 ± 0.5V
= 1kΩ
C
L
C
L
= 15pF
= 50pF
5.5
7.0
8.1
10.1
1.0
1.0
9.5
11.5
CC
L
t
t
,
Output Disable Time,
OE to Q
V
R
= 3.3 ± 0.3V
= 1kΩ
C
C
C
C
= 50pF
= 50pF
= 50pF
= 50pF
9.5
13.2
9.2
1.5
1.0
10
1.0
15.0
10.5
1.5
PLZ
CC
L
L
L
L
PHZ
L
V
R
= 5.0 ± 0.5V
= 1kΩ
6.5
1.0
CC
L
t
t
,
Output to Output Skew
V
CC
= 3.3 ± 0.3V
(Note 1.)
ns
ns
OSLH
OSHL
V
= 5.5 ± 0.5V
CC
(Note 1.)
1.0
C
Maximum Input Capacitance
4
6
10
pF
pF
in
C
Maximum Three–State Output
Capacitance (Output in
out
High–Impedance State)
Typical @ 25°C, V
= 5.0V
CC
C
Power Dissipation Capacitance (Note 2.)
pF
27
PD
1. Parameter guaranteed by design. t = |t – t
|, t
= |t
– t |.
PHLm PHLn
OSLH
PLHm PLHn OSHL
2. C
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Averageoperatingcurrentcanbeobtainedbytheequation:I
=C
.
V
f
+I
/8(perlatch).C isusedtodeterminetheno–load
PD
CC(OPR)
PD CC in CC
2
dynamic power consumption; P = C
V
f
+ I
in CC
V
D
PD
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50 pF, V
= 5.0V)
r
f
L
CC
T
A
= 25°C
Symbol
Parameter
Unit
V
Typ
Max
V
OLP
Quiet Output Maximum Dynamic V
0.6
0.9
– 0.9
3.5
OL
V
OLV
Quiet Output Minimum Dynamic V
– 0.6
V
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
1.5
V
3
MOTOROLA
MC74VHC373
TIMING REQUIREMENTS (Input t = t = 3.0ns)
r
f
T
= – 40
A
to 85°C
T
A
= 25°C
Symbol
Parameter
Minimum Pulse Width, LE
Test Conditions
Unit
Typ
Limit
Limit
t
V
V
= 3.3 ± 0.3V
= 5.0 ±0.5V
5.0
5.0
5.0
5.0
ns
w(h)
CC
CC
t
Minimum Setup Time, D to LE
Minimum Hold Time, D to LE
V
V
= 3.3 ± 0.3V
= 5.0 ± 0.5V
4.0
4.0
4.0
4.0
ns
ns
su
CC
CC
t
V
CC
V
CC
= 3.3 ± 0.3V
= 5.0 ± 0.5V
1.0
1.0
1.0
1.0
h
SWITCHING WAVEFORMS
t
w
V
V
CC
CC
LE
50%
D
Q
50%
GND
GND
t
t
PHL
PLH
t
t
PLH
PHL
50% VCC
Q
50% VCC
Figure 1.
Figure 2.
V
CC
OE
50%
GND
VALID
t
t
PLZ
PZL
V
CC
HIGH
IMPEDANCE
D
50%
50% VCC
GND
Q
Q
t
t
VOL +0.3V
su
h
t
t
PHZ
V
PZH
CC
LE
50%
VOL –0.3V
GND
50% VCC
HIGH
IMPEDANCE
Figure 3.
Figure 4.
MOTOROLA
4
MC74VHC373
TEST CIRCUITS
TEST POINT
TEST POINT
1 k
CONNECT TO V
WHEN
.
PZL
CC
AND t
OUTPUT
Ω
OUTPUT
TESTING t
PLZ
CONNECT TO GND WHEN
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
TESTING t
AND t
.
PZH
C *
PHZ
L
C *
L
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 5.
Figure 6.
EXPANDED LOGIC DIAGRAM
D0
D1
D2
D3
D4
13
D5
14
D6
17
D7
18
3
4
7
8
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LE
LE
LE
LE
LE
LE
LE
LE
11
1
LE
OE
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
INPUT EQUIVALENT CIRCUIT
INPUT
5
MOTOROLA
MC74VHC373
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
–A–
ANSI Y14.5M, 1982.
20
11
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
10X P
–B–
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
M
M
0.010 (0.25)
B
1
10
MILLIMETERS
INCHES
20X D
0.010 (0.25)
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X K REF
0.10 (0.004)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
T
U
V
S
0.15 (0.006)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
N
S
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
0.15 (0.006)
T U
M
A
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
6.40
4.30
–––
0.05
0.50
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
0.047
0.006
0.030
–V–
0.252
0.169
–––
0.002
0.020
N
F
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
G
D
M
0
8
0
8
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
MOTOROLA
6
MC74VHC373
OUTLINE DIMENSIONS
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 967–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
E
20
11
Q
1
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
E
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
e
A
DIM
A
1
b
c
D
E
e
MIN
–––
MAX
2.05
0.20
0.50
0.27
12.80
5.45
MIN
MAX
0.081
0.008
0.020
0.011
0.504
0.215
c
–––
0.002
0.014
0.007
0.486
0.201
A
0.05
0.35
0.18
12.35
5.10
A
b
1
1.27 BSC
0.050 BSC
M
0.10 (0.004)
0.13 (0.005)
H
7.40
0.50
1.10
0
8.20
0.85
1.50
10
0.291
0.020
0.043
0
0.323
0.033
0.059
10
E
L
L
M
E
Q
Z
0.70
–––
0.90
0.81
0.028
–––
0.035
0.032
1
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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MC74VHC373/D
◊
相关型号：
MC74VHC373DWR2
Bus Driver, AHC/VHC Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, PLASTIC, SOIC-20
MOTOROLA
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