MC74VHC373MEL [ONSEMI]
Octal D-Type Latch with 3-State Output; 八D型锁存器具有三态输出
| 型号： | MC74VHC373MEL |
| 厂家： | 
ONSEMI |
| 描述： | Octal D-Type Latch with 3-State Output |
| 文件： | 总8页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC373
Octal D−Type Latch
with 3−State Output
The MC74VHC373 is an advanced high speed CMOS octal latch
with 3−state output fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
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This 8−bit D−type latch is controlled by a latch enable input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
MARKING
DIAGRAMS
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
20
1
SOIC−20 WIDE
DW SUFFIX
CASE 751D
VHC373
AWLYYWW
20
1
Features
20
• High Speed: t = 5.0 ns (Typ) at V = 5.0 V
PD
CC
• Low Power Dissipation: I = 4.0 mA (Max) at T = 25°C
CC
A
VHC
373
ALYW
TSSOP−20
DT SUFFIX
CASE 948E
20
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
1
1
20
• Designed for 2.0 V to 5.5 V Operating Range
SOEIAJ−20
M SUFFIX
CASE 967
• Low Noise: V
= 0.9 V (Max)
OLP
74VHC373
AWLYYWW
20
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
1
1
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 186 FETs or 46.5 Equivalent Gates
• Pb−Free Packages are Available*
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
20
V
CC
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
GND 10
11
LE
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
January, 2005 − Rev. 6
MC74VHC373/D
MC74VHC373
2
5
3
D0
D1
D2
D3
D4
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
6
7
FUNCTION TABLE
8
9
DATA
INPUTS
LE
OUTPUT
NONINVERTING
OUTPUTS
INPUTS
13
12
15
16
19
OE
D
Q
14
17
18
L
L
L
H
H
L
H
L
X
X
H
D5
D6
D7
L
No Change
Z
H
X
11
1
LE
OE
Figure 1. Logic Diagram
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage
DC Input Voltage
– 0.5 to + 7.0
– 0.5 to + 7.0
CC
V
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
– 0.5 to V + 0.5
V
out
IK
CC
I
− 20
± 20
± 25
± 75
mA
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
OK
V
out
should be constrained to the
range GND v (V or V ) v V
.
I
DC Output Current, per Pin
DC Supply Current, V and GND Pins
in
out
CC
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
I
CC
level (e.g., either GND or V ).
P
D
Power Dissipation in Still Air,
SOIC Packages†
TSSOP Package†
500
450
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
_C
stg
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
V
in
5.5
V
V
DC Output Voltage
Operating Temperature
Input Rise and Fall Time
0
V
V
out
CC
T
− 40
+ 85
_C
ns/V
A
t , t
r
V
CC
V
CC
= 3.3 V
= 5.0 V
0
0
100
20
f
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2
MC74VHC373
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = − 40 to 85°C
A
V
CC
Min
Typ
Max
Min
Max
V
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0 to
5.5
1.50
1.50
V
V
x 0.7
V
x 0.7
CC
CC
V
Maximum Low−Level
Input Voltage
2.0
3.0 to
5.5
0.50
0.50
V
V
IL
V
x 0.3
V
x 0.3
CC
CC
V
OH
Minimum High−Level
Output Voltage
V
= V or V
= − 50 mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
in
IH
IL
I
OH
V
in
= V or V
IH
IL
I
I
= − 4 mA
= − 8 mA
3.0
4.5
2.58
3.94
2.48
3.80
OH
OH
V
OL
Maximum Low−Level
Output Voltage
V
= V or V
= 50 mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
IL
I
OL
V
in
= V or V
IH
IL
I
OL
I
OL
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
I
Maximum Input
Leakage Current
V
V
= 5.5 V or GND
0 to 5.5
± 0.1
± 1.0
mA
mA
in
in
I
Maximum
= V or V
IH
5.5
± 0.25
± 2.5
OZ
in
IL
Three−State Leakage
Current
V
= V or GND
out CC
I
Maximum Quiescent
Supply Current
V
in
= V or GND
5.5
4.0
40.0
mA
CC
CC
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T = − 40 to 85°C
A
Min
Typ
Max
Min
1.0
Max
Symbol
Parameter
Test Conditions
= 3.3 ± 0.3 V C = 15 pF
Unit
t
t
t
t
,
Maximum Propagation Delay,
D to Q
V
V
V
V
V
7.3
9.8
11.4
14.9
13.5
17.0
ns
PLH
t
CC
CC
CC
CC
CC
L
C = 50 pF
L
1.0
PHL
= 5.0 ± 0.5 V C = 15 pF
4.9
6.4
7.2
9.2
1.0
1.0
8.5
10.5
L
C = 50 pF
L
,
Maximum Propagation Delay,
LE to Q
= 3.3 ± 0.3 V C = 15 pF
7.0
9.5
11.0
14.5
1.0
1.0
13.0
16.5
ns
ns
ns
PLH
t
L
C = 50 pF
L
PHL
= 5.0 ± 0.5 V C = 15 pF
5.0
6.5
7.2
9.2
1.0
1.0
8.5
10.5
L
C = 50 pF
L
,
Output Enable Time,
OE to Q
= 3.3 ± 0.3 V C = 15 pF
7.3
9.8
11.4
14.9
1.0
1.0
13.5
17.0
PZL
t
L
R = 1 kW
C = 50 pF
L
PZH
L
V
CC
= 5.0 ± 0.5 V C = 15 pF
5.5
7.0
8.1
10.1
1.0
1.0
9.5
11.5
L
R = 1 kW
C = 50 pF
L
L
,
Output Disable Time,
OE to Q
V
CC
= 3.3 ± 0.3 V C = 50 pF
9.5
13.2
9.2
1.5
1.0
1.0
15.0
10.5
1.5
PLZ
L
t
R = 1 kW
L
PHZ
V
CC
= 5.0 ± 0.5V C = 50 pF
L
R = 1 kW
6.5
1.0
L
t
,
Output to Output Skew
V
CC
= 3.3 ± 0.3 V C = 50 pF
ns
ns
OSLH
L
t
(Note 1)
OSHL
V
CC
= 5.5 ± 0.5 V C = 50 pF
1.0
L
(Note 1)
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3
MC74VHC373
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T = − 40 to 85°C
A
Min
Typ
4
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
pF
C
Maximum Input Capacitance
10
10
in
C
Maximum Three−State Output
Capacitance (Output in
6
pF
out
High−Impedance State)
Typical @ 25°C, V = 5.0 V
CC
27
C
Power Dissipation Capacitance (Note 2)
pF
PD
1. Parameter guaranteed by design. t
= |t
− t
|, t
= |t
− t
PHLn
|.
OSLH
PLHm
PLHn OSHL
PHLm
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
no−load dynamic power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I /8 (per latch). C is used to determine the
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50 pF, V = 5.0V)
r
f
L
CC
T
A
= 25°C
Typ
Max
Symbol
Parameter
Unit
V
V
V
Quiet Output Maximum Dynamic V
0.6
0.9
− 0.9
3.5
OLP
OL
Quiet Output Minimum Dynamic V
− 0.6
V
OLV
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
1.5
V
TIMING REQUIREMENTS (Input t = t = 3.0 ns)
r
f
T
A
= − 40
to 85°C
T
A
= 25°C
Typ
Limit
Limit
Symbol
Parameter
Test Conditions
Unit
t
Minimum Pulse Width, LE
V
CC
V
CC
= 3.3 ± 0.3 V
= 5.0 ±0.5 V
5.0
5.0
5.0
5.0
ns
w(h)
t
Minimum Setup Time, D to LE
Minimum Hold Time, D to LE
V
V
= 3.3 ± 0.3 V
= 5.0 ± 0.5 V
4.0
4.0
4.0
4.0
ns
ns
su
CC
CC
t
V
CC
V
CC
= 3.3 ± 0.3 V
= 5.0 ± 0.5 V
1.0
1.0
1.0
1.0
h
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHC373DWR2
MC74VHC373DWR2G
SOIC−20
1000 Tape & Reel
1000 Tape & Reel
SOIC−20
(Pb−Free)
MC74VHC373DTR2
MC74VHC373MEL
MC74VHC373MELG
TSSOP−20*
SOEIAJ−20
2500 Tape & Reel
2000 Tape & Reel
2000 Tape & Reel
SOEIAJ−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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4
MC74VHC373
SWITCHING WAVEFORMS
t
w
V
CC
V
CC
LE
50%
D
Q
50%
GND
GND
t
t
PHL
PLH
t
t
PHL
PLH
50% VCC
Q
50% VCC
Figure 2.
Figure 3.
V
CC
OE
50%
GND
VALID
t
t
PLZ
PZL
V
CC
HIGH
D
50%
IMPEDANCE
50% VCC
GND
Q
Q
t
su
t
VOL +0.3V
h
t
t
PHZ
V
PZH
CC
LE
50%
VOL −0.3V
GND
50% VCC
HIGH
IMPEDANCE
Figure 4.
Figure 5.
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
1 kW
CONNECT TO V WHEN
CC
OUTPUT
TESTING t AND t
PLZ
.
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
C *
L
PHZ
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6.
Figure 7.
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5
MC74VHC373
D0
D1
D2
D3
D4
13
D5
14
D6
17
D7
18
3
4
7
8
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LE
LE
LE
LE
LE
LE
LE
LE
11
1
LE
OE
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q7
Q0
Q1
Q2
Q3
Figure 8. EXPANDED LOGIC DIAGRAM
INPUT
Figure 9. INPUT EQUIVALENT CIRCUIT
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6
MC74VHC373
OUTLINE DIMENSIONS
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
20X B
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
B
T
0.25
A
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
L
18X e
q
_
_
A1
C
T
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE B
20X K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
20
11
2X L/2
J J1
B
L
−U−
PIN 1
IDENT
SECTION N−N
1
10
0.25 (0.010)
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
S
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
0.15 (0.006) T U
M
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
6.40
4.30
−−−
6.60 0.252
4.50 0.169
N
C
1.20
−−−
D
0.05
0.50
0.15 0.002
0.75 0.020
F
F
G
H
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
J
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
−W−
J1
K
C
K1
L
6.40 BSC
0 8 0 8
0.252 BSC
G
D
M
_
_
_
_
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
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7
MC74VHC373
OUTLINE DIMENSIONS
SOEIAJ−20
M SUFFIX
CASE 967−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
E
20
11
Q
1
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN
e
A
DIM MIN
MAX
2.05
0.20
0.50
0.27
12.80
5.45
MAX
0.081
0.008
0.020
0.011
0.504
0.215
c
A
−−−
0.05
0.35
0.18
12.35
5.10
−−−
0.002
0.014
0.007
0.486
0.201
A
1
b
c
D
E
e
A
b
1
1.27 BSC
0.050 BSC
M
0.10 (0.004)
0.13 (0.005)
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0
10
_
0.035
0.032
_
_
_
0.70
−−−
0.90
0.81
0.028
−−−
1
Z
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MC74VHC373/D
相关型号：
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