MC88915FN70R2_技术文档

SEMICONDUCTOR TECHNICAL DATA

Features

The MC88915 Clock Driver utilizes phase–locked loop

technology to lock its low skew outputs’ frequency and phase

onto an input reference clock. It is designed to provide clock

distribution for high performance PC’s and workstations.

• Five Outputs (QO–Q4) with Output–Output Skew < 500

ps each being phase and frequency locked to the SYNC

input

The PLL allows the high current, low skew outputs to lock

onto a single clock input and distribute it with essentially zero

delay to multiple components on a board. The PLL also allows

the MC88915 to multiply a low frequency input clock and

distribute it locally at a higher (2X) system frequency. Multiple

88915’s can lock onto a single reference clock, which is ideal

for applications when a central system clock must be

distributed synchronously to multiple boards (see Figure 7).

• The phase variation from part–to–part between the SYNC

and FEEDBACK inputs is less than 550 ps (derived from

the t

PD

skew)

specification, which defines the part–to–part

• Input/Output phase–locked frequency ratios of 1:2, 1:1,

and 2:1 are available

• Input frequency range from 5MHz – 2X_Q FMAX spec

• Additional outputs available at 2X and +2 the system “Q”

frequency. Also a Q (180° phase shift) output available

Five “Q” outputs (QO–Q4) are provided with less than 500

ps skew between their rising edges. The Q5 output is inverted

(180° phase shift) from the “Q” outputs. The 2X_Q output runs

at twice the “Q” output frequency, while the Q/2 runs at 1/2 the

“Q” frequency.

• All outputs have ±36 mA drive (equal high and low) at

CMOS levels, and can drive either CMOS or TTL inputs.

All inputs are TTL–level compatible

• Test Mode pin (PLL_EN) provided for low frequency

testing. Two selectable CLOCK inputs for test or

redundancy purposes

The VCO is designed to run optimally between 20 MHz and

the 2X_Q Fmax specification. The wiring diagrams in Figure 5

detail the different feedback configurations which create

specific input/output frequency relationships. Possible

frequency ratios of the “Q” outputs to the SYNC input are 2:1,

1:1, and 1:2.

RST

4

V

Q5

2

GND Q4

V

2X_Q

26

CC

3

1

28

27

FEEDBACK

REF_SEL

SYNC[0]

5

25

Q/2

GND

Q3

The FREQ_SEL pin provides one bit programmable

divide–by in the feedback path of the PLL. It selects between

divide–by–1 and divide–by–2 of the VCO before its signal

reaches the internal clock distribution section of the chip (see

the block diagram on page 2). In most applications

FREQ_SEL should be held high (÷1). If a low frequency

reference clock input is used, holding FREQ_SEL low (÷2) will

allow the VCO to run in its optimal range (>20 MHz).

6

24

23

22

21

20

19

7

V

(AN)

RC1

8

V

CC

9

Q2

GND(AN)

SYNC[1]

10

11

GND

LOCK

In normal phase–locked operation the PLL_EN pin is held

high. Pulling the PLL_EN pin low disables the VCO and puts

the 88915 in a static “test mode”. In this mode there is no

frequency limitation on the input clock, which is necessary for

a low frequency board test environment. The second SYNC

input can be used as a test clock input to further simplify

board–level testing (see detailed description on page 11).

12

13

14

15

V

16

17

18

PLL_EN

GND Q0

Q1 GND

FREQ_SEL

CC

28–Lead Pinout (Top View)

A lock indicator output (LOCK) will go high when the loop is

in steady–state phase and frequency lock. The LOCK output

will go low if phase–lock is lost or when the PLL_EN pin is low.

Under certain conditions the lock output may remain low, even

though the part is phase–locked. Therefore the LOCK output

signal should not be used to drive any active circuitry; it should

be used for passive monitoring or evaluation purposes only.

FN SUFFIX

PLASTIC PLCC

CASE 776–02

ORDERING INFORMATION

MC88915FN55 PLCC

MC88915FN70 PLCC

Yield Surface Modeling and YSM are trademarks of Motorola, Inc.

1/97

REV 4

1

Motorola, Inc. 1997

MC88915

LOCK

FEEDBACK

SYNC (0)

VOLTAGE

0

1

PHASE/FREQ.

DETECTOR

CHARGE PUMP/LOOP

FILTER

CONTROLLED

M

U

X

OSCILLATOR

SYNC (1)

EXTERNAL REC NETWORK

(RC1 Pin)

REF_SEL

2x_Q

Q0

1

0

PLL_EN

MUX

D

Q

(

÷

1)

2)

CP

1

R

M

U

X

(÷

DIVIDE

BY TWO

0

Q1

Q2

Q3

D

Q

CP

FREQ_SEL

RST

D

Q

CP

PIN SUMMARY

Pin Name

Num

I/O

Function

1

5

1

11

SYNC[0]

SYNC[1]

REF_SEL

FREQ_SEL

FEEDBACK

RC1

Q(0–4)

Q5

2x_Q

Q/2

LOCK

RST

PLL_EN

Input

Reference clock input

D

CP

Chooses reference between sync[0] & Sync[1]

Selects Q output frequency

Feedback input to phase detector

Input for external RC network

Clock output (locked to sync)

Inverse of clock output

R

Input

Output

Input

Q4

Q5

D

Q

2 x clock output (Q) frequency (synchronous)

Clock output(Q) frequency ÷ 2 (synchronous)

CP

Indicates phase lock has been achieved (high when locked)

Asynchronous reset (active low)

Disables phase–lock for low freq. testing

Power and ground pins (note pins 8, 10 are

“quiet” supply pins for internal logic only)

Input

D

V

,GND

CC

CP

Q/2

D

CP

R

MC88915 Block Diagram

MOTOROLA

2

TIMING SOLUTIONS

BR1333 — Rev 6

MC88915

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND; T =0° C to + 70° C, V

CC

= 5.0V ± 5%)

A

Symbol

Parameter

Test Conditions

V

Guaranteed Limit

Unit

V

CC

V

IH

Minimum High–Level Input

Voltage

V

= 0.1 V or V

– 0.1 V

4.75

5.25

2.0

out

CC

V

IL

Maximum Low–Level Input

Voltage

V

out

= 0.1 V or V

– 0.1 V

4.75

5.25

0.8

V

OH

Minimum High–Level Output

Voltage

V

= V or V

IH IL

4.75

5.25

4.01

4.51

V

in

1

= –36 mA

I

OH

V

OL

Maximum Low–Level Output

Voltage

V

= V or V

IH IL

4.75

5.25

0.44

V

in

1

= 36 mA

I

OL

I

Maximum Input Leakage Current

V = V

or GND

– 2.1 V

5.25

±1.0

µA

mA

in

I

CC

2

I

Maximum I /Input

CC

V = V

I

CCT

OLD

1.5

3

I

Minimum Dynamic Output Current

V

OLD

V

OHD

= 1.0V Max

88

–88

1.0

I

= 3.85 V Max

OHD

I

Maximum Quiescent Supply

Current (per Package)

V = V

I

or GND

CC

1. I

and I are 12mA and –12mA respectively for the LOCK output.

OH

OL

2. The PLL_EN input pin is not guaranteed to meet this specification.

3. Maximum test duration is 2.0ms, one output loaded at a time.

CAPACITANCE AND POWER SPECIFICATIONS

Symbol

Parameter

Typical Values

Unit

pF

Conditions

C

Input Capacitance

4.5

40

V

CC

V

CC

V

CC

= 5.0 V

IN

C

Power Dissipation Capacitance

pF

= 5.0 V

PD

Power Dissipation @ 33MHz with 50Ω Thevenin Termination

15 mW/Output

120 mW/Device

mW

1

T = 25°C

PD

Power Dissipation @ 33MHz with 50Ω Parallel Termination to GND

37.5 mW/Output

300 mW/Device

mW

V

= 5.0 V

T = 25° C

2

CC

SYNC INPUT TIMING REQUIREMENTS

Symbol

Parameter

Min

Max

Unit

t

, t

Maximum Rise and Fall times, (SYNC Inputs: From 0.8V – 2.0V)

–

3.0

ns

RISE FALL

FN55

36

FN70

28.5

1

200

t

Input Clock Period (SYNC Inputs)

ns

CYCLE

Duty Cycle

Input Duty Cycle (SYNC Inputs)

50% ±25%

1. Information in Fig. 5 and in the “General AC Specification Notes”, Note #3 describes this specification and its actual limits depending on the

application.

FREQUENCY SPECIFICATIONS (T =0° C to + 70° C, V

CC

= 5.0V ±5%, C = 50pF)

L

A

Guaranteed Minimum

Symbol

Parameter

MC88915FN55

55

27.5

1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded at 50 pF.

MC88915FN70

70

35

Unit

MHz

1

f

Maximum Operating Frequency

(2X_Q Output)

Maximum Operating Frequency (Q0–Q4,Q5 Output)

max

TIMING SOLUTIONS

BR1333 — Rev 6

3

MOTOROLA

MC88915

AC ELECTRICAL CHARACTERISTICS (T =0° C to +70° C, V

CC

= 5.0V ±5%, C = 50pF)

A

L

Symbol

Parameter

Min

Max

Unit

t

, t

Rise and Fall Times, all Outputs Into a 50 pF, 500 Ω Load

1.0

2.5

ns

RISE FALL

(Outputs)

(Between 0.2V and 0.8V

)

CC

3

t

, t

Rise and Fall Time, 2X_Q Output Into a 20 pF Load With Termina-

tion specified in note 2 (Between 0.8 V and 2.0 V)

0.5

1.6

ns

RISE FALL

(2X_Q Output)

3

t

Output Pulse Width (Q0, Q1, Q3, Q4, Q5, Q/2 @V /2)

CC

0.5t

– 0.5

0.5t

+ 0.5

Pulse Width

CYCLE

(Q0,Q1,Q3,Q4,

Q5,Q/2)

t

= 1/Freq. at which the “Q”

CYCLE

Outputs are running

ns

3

t

Output Pulse Width (Q2 Output @ V /2)

CC

0.5t

– 0.6

– 0.5

– 1.0

0.5t

+ 0.6

+ 0.5

+ 1.0

Pulse Width

(Q2 only)

CYCLE

Output Pulse Width (2X_Q Output @ 1.5 V) (See AC Note 2)

ns

Pulse Width

(2X_Q Output)

3

t

Output Pulse Width (2X_Q Output @ V /2)

CC

Pulse Width

(2X_Q Output)

3

t

(470kΩ From RC1 to An.V

)

PD

(Sync–Feedback) SYNC input to feedback delay

(meas. @ SYNC0 or 1 and FEEDBACK input pins)

CC

–0.50

(470kΩ From RC1 to An.GND)

–1.05

ns

(See General AC Specification note 4 and Fig. 2 for explanation)

+1.25

–

+3.25

500

1,3

t

Output–to–Output Skew Between Outputs Q0 – Q4, Q/2

(Rising Edges Only)

ps

ms

ns

SKEWr

(Rising)

1,3

Output–to–Output Skew Between Outputs Q0 – Q4

(Falling Edges Only)

–

750

10

SKEWf

(Falling)

1,3

t

Output–to–Output Skew Between Outputs 2X_Q, Q/2, Q0 – Q4

Rising, Q5 Falling

SKEWall

2

t

Time Required to acquire Phase–Lock from time SYNC Input Sig-

1

LOCK

nal is Received.

t

Propagation Delay, RST to Any Output (High–Low)

1.5

13.5

PHL

(Reset – Q)

1. Under equally loaded conditions, C ≤50pF (±2pF), and at a fixed temperature and voltage.

L

2. With V

fully powered–on and an output properly connected to the FEEDBACK pin. t

Max. is with C1 = 0.1µF, t Min is with

LOCK

CC

C1 = 0.01µF.

LOCK

3. These specifications are not tested, they are guaranteed by statistical characterization. See General AC Specification note 1.

1

RESET TIMING REQUIREMENTS

Symbol

, RST

Parameter

Minimum

Unit

t

Reset Recovery Time rising RST

edge to falling SYNC edge

9.0

ns

REC

to SYNC

t

, RST

LOW

Minimum Pulse Width,

RST input LOW

5.0

ns

W

1. These reset specs are valid only when PLL_EN is LOW and the part is in Test mode (not in phase–lock)

MOTOROLA

4

TIMING SOLUTIONS

BR1333 — Rev 6

MC88915

General AC Specification Notes

statistical characterization. In this way all units passing

the ATE test will meet or exceed the non–tested

specifications limits.

1. Several specifications can only be measured when the

MC88915 is in phase–locked operation. It is not possible

to have the part in phase–lock on ATE (automated test

equipment). Statistical characterization techniques were

used to guarantee those specifications which cannot be

measured on the ATE. MC88915 units were fabricated

with key transistor properties intentionally varied to

create a 14 cell designed experimental matrix. IC

performancewas characterized over a range of transistor

properties (represented by the 14 cells) in excess of the

expected process variation of the wafer fabrication area.

Response Surface Modeling (RSM) techniques were

used to relate IC performance to the CMOS transistor

properties over operation voltage and temperature. IC

Performance to each specification and fab variation were

used in conjunction with Yield Surface Modeling (YSM

) methodology to set performance limits of ATE testable

specifications within those which are to be guaranteed by

2. These two specs (t

RlSE/FALL

and t

Width 2X_Q

PULSE

output) guarantee that the MC88915 meets the 25 MHz

68040 P–Clock input specification (at 50 MHz). For these

two specs to be guaranteed by Motorola, the termination

scheme shown below in Figure 1 must be used.

3. The wiring Diagrams and written explanations in Figure 5

demonstratethe input and output frequencyrelationships

for three possible feedback configurations. The allowable

SYNC input range for each case is also indicated. There

are two allowable SYNC frequency ranges, depending

whether FREQ_SEL is high or low. Although not shown, it

is possible to feed back the Q5 output, thus creating a

180° phase shift between the SYNC input and the “Q”

outputs. Table 1 below summarizes the allowable SYNC

frequency range for each possible configuration.

Z

O

(CLOCK TRACE)

R

s

88915

2X_Q

Output

68040

P–Clock

Input

R

p

R = Z – 7

Ω

s

o

R = 1.5 Z

p

o

Figure 1. MC68040 P–Clock Input Termination Scheme

FREQ_SEL

Level

Feedback

Output

Allowable SYNC Input

Frequency Range (MHZ)

Corresponding VCO

Frequency Range

Phase Relationships

of the “Q” Outputs

to Rising SYNC Edge

HIGH

LOW

Q/2

5 to (2X_Q FMAX Spec)/4

20 to (2X_Q FMAX Spec)

0°

Any “Q” (Q0–Q4) 10 to (2X_Q FMAX Spec)/2

Q5

2X_Q

Q/2

10 to (2X_Q FMAX Spec)/2

20 to (2X_Q FMAX Spec)

180°

0°

2.5 to (2X_Q FMAX Spec)/8 20 to (2X_Q FMAX Spec)

0°

Any “Q” (Q0–Q4) 5 to (2X_Q FMAX Spec)/4

20 to (2X_Q FMAX Spec)

20 to (2X_Q FMAXSpec)

0°

Q5

5 to (2X_Q FMAX Spec)/4

10 to (2X_Q FMAX Spec)/2

180°

0°

2X_Q

Table 1. Allowable SYNC Input Frequency Ranges for Different Feedback Configurations.

4. A 1 MΩ resistor tied to either Analog V

CC

or Analog GND

lots described in note 1 while the part was in

phase–lockedoperation. Theactualmeasurementswere

made with a 10 MHz SYNC input (1.0 ns edge rate from

0.8 V – 2.0 V) with the Q/2 output fed back. The phase

measurements were made at 1.5 V. The Q/2 output was

as shown in Figure 2 is required to ensure no jitter is

present on the MC88915 outputs. This technique causes

a phase offset between the SYNC input and the output

connected to the FEEDBACK input, measured at the

input pins. The t

with process, temperature, and voltage. The specs were

arrived at by measuring the phase relationship for the 14

spec describes how this offset varies

terminatedattheFEEDBACKinputwith100ΩtoV

100 Ω to ground.

and

PD

CC

TIMING SOLUTIONS

BR1333 — Rev 6

5

MOTOROLA

MC88915

ANALOG VCC

RC1

EXTERNAL LOOP FILTER

470K

Ω

REFERENCE

RESISTOR

RC1

R2

330

Ω

R2

C1

330

Ω

470K

REFERENCE

RESISTOR

Ω

0.1

µ

F

0.1µF

C1

ANALOG GND

With the 470K

measured at the input pins is:

Ω

resistor tied in this fashion, the t specification

PD

With the 470K

measured at the input pins is:

Ω

resistor tied in this fashion, the t

PD

specification

t

= 2.25ns

±

1.0ns

t

= –0.775ns ± 0.275ns

PD

3.0V

SYNC INPUT

–0.775ns OFFSET

2.25ns OFFSET

5.0V

FEEDBACK OUTPUT

Figure 2. Depiction of the Fixed SYNC to Feedback Offset (tPD) Which is

Present When a 470KΩ Resistor is Tied to VCC or Ground

5. Thet

specificationguaranteesthattherisingedges

distributionof these outputs are provided in table 2. When

taking the skew data, Q0 was used as a reference, so all

measurements are relative to thisoutput. Theinformation

in Table 2 is derived from measurements taken from the

14 process lots described in Note 1, over the temperature

and voltage range.

SKEWr

of outputs Q/2, Q0, Q1, Q2, Q3, and Q4 will always fall

within a 500ps window within one part. However, if the

relative position of each output within this window is not

specified, the 500 ps window must be added to each side

of the tPD specification limits to calculate the total

part–to–part skew. For this reason the absolute

–

(ps)

+

(ps)

Output

Q0

0

Q1

–72

–44

–40

–274

–16

–633

40

Q2

276

255

–34

250

–35

Q3

Q4

Q/2

2X_Q

Table 2. Relative Positions of Outputs Q/2, Q0–Q4, 2X_Q, Within the 500ps t

SKEWr

Spec Window

MOTOROLA

6

TIMING SOLUTIONS

BR1333 — Rev 6

MC88915

6. Calculation of Total Output–to–Skew between multiple

parts (Part–to–Part skew)

– 0.32ns] = –1.37ns is the lower t

PD

limit, and [–0.5ns +

0.32ns] = –0.18ns is the upper limit. Therefore the worst

case skew of output Q2 between any number of parts is

|(–1.37) – (–0.18)| = 1.19ns. Q2 has the worst case skew

distribution of any output, so 1.2ns is the absolute worst

case output–to–output skew between multiple parts.

By combining the t

specification and the information in

PD

Note 5, the worst case output–to–output skew between

multiple 88915’s connected in parallel can be calculated.

This calculation assumes that all parts have a common

SYNC input clock with equal delay of that input signal to

each part. This skew value is valid at the 88915 output

pins only (equally loaded), it does not include PCB trace

delays due to varying loads.

7. Note 4 explains that the t

PD

specification was measured

and is guaranteed for the configuration of the Q/2 output

connected to the FEEDBACK pin and the SYNC input

running at 10MHz. The fixed offset (t ) as described

PD

With a 1MΩ resistor tied to analog V

as shown in note

above has some dependence on the input frequency and

at what frequency the VCO is running. The graphs of

Figure 3 demonstrate this dependence.

CC

spec. limits between SYNC and the Q/2 output

4, the t

PD

(connected to the FEEDBACK pin) are –1.05ns and

–0.5ns. To calculate the skew of any given output

between two or more parts, the absolute value of the

distribution of that output given in table 2 must be

The data presented in Figure 3 is from devices

representing process extremes, and the measurements

subtracted and added to the lower and upper t

limits respectively. ForoutputQ2, [276–(–44)]=320psis

the absolute value of the distribution. Therefore [–1.05ns

spec

were also taken at the voltage extremes (V = 5.25V

PD

CC

and 4.75V). Therefore the data in Figure 3 is a realistic

representation of the variation of t

.

PD

–0.50

–0.5

–0.75

–1.0

tPD

SYNC to

FEEDBACK

(ns)

SYNC to

FEEDBACK

(ns)

–1.00

–1.25

–1.50

–1.5

–2.0

2.5

5.0

7.5

10.0

12.5

15.0

17.5

2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5

SYNC INPUT FREQUENCY (MHz)

Figure 3a.

Figure 3b.

t

versus Frequency Variation for Q/2 Output Fed

t

versus Frequency Variation for Q4 Output Fed

PD

Back, Including Process and Voltage Variation @ 25

°

C

Back, Including Process and Voltage Variation @ 25

°

C

(With 1M

Ω

Resistor Tied to Analog V

)

(With 1M

Ω

Resistor Tied to Analog V

)

CC

3.5

3.0

2.5

2.0

1.5

1.0

0.5

3.5

3.0

2.5

tPD

SYNC to

FEEDBACK

(ns)

tPD

SYNC to

FEEDBACK

(ns)

2.0

1.5

1.0

0.5

2.5

5.0

7.5

10.0

12.5

15.0

17.5

0

5

10

15

20

25

SYNC INPUT FREQUENCY (MHz)

Figure 3c.

Figure 3d.

t

versus Frequency Variation for Q/2 Output Fed

t

versus Frequency Variation for Q4 Output Fed

PD

Back, Including Process and Voltage Variation @ 25

(With 1M Resistor Tied to Analog GND)

PD

°

C

Back, Including Process and Voltage Variation @ 25

°

C

Ω

(With 1MΩ Resistor Tied to Analog GND)

TIMING SOLUTIONS

BR1333 — Rev 6

7

MOTOROLA

MC88915

SYNC INPUT

(SYNC[1] or

SYNC[0])

t

SYNC INPUT

CYCLE

t

PD

FEEDBACK

INPUT

Q/2 OUTPUT

t

SKEWf

SKEWr

t

SKEWR

SKEWALL

Q0 – Q4

OUTPUTS

t

CYCLE “Q” OUTPUTS

Q5 OUTPUT

2X_Q OUTPUT

Figure 4. Output / Input Switching Waveforms and Timing Diagrams

(These waveforms represent the hook–up configuration of Figure 5a on page 9)

Timing Notes:

• The MC88915 aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does

not require a 50% duty cycle.

• All skew specs are measured between the V /2 crossing point of the appropriate output edges.All skews

CC

are specified as ‘windows’, not as a ± deviation around a center point.

• If a “Q” output is connected to the FEEDBACK input (this situation is not shown), the “Q” output frequency

would match the SYNC input frequency, the 2X_Q output would run at twice the SYNC frequency, and the

Q/2 output would run at half the SYNC frequency.

MOTOROLA

8

TIMING SOLUTIONS

BR1333 — Rev 6

MC88915

50 MHz SIGNAL

12.5 MHz FEEDBACK SIGNAL

HIGH

1:2 Input to “Q” Output Frequency Relationship

RST

Q4

2X_Q

Q5

FEEDBACK

REF_SEL

SYNC[0]

Q/2

Q3

Q2

In this application, the Q/2 output is connected to

the FEEDBACK input. The internal PLL will line up

the positive edges of Q/2 and SYNC, thus the Q/2

frequency will equal the SYNC frequency. The “Q”

outputs (Q0–Q4, Q5) will always run at 2X the Q/2

frequency, and the 2X_Q output will run at 4X the

Q/2 frequency.

LOW

12.5 MHz INPUT

CRYSTAL

OSCILLATOR

MC88915

25MHz

“Q”

CLOCK

OUTPUTS

ANALOG V

CC

EXTERNAL

LOOP

FILTER

RC1

ANALOG GND

PLL_EN

Q1

Allowable Input Frequency Range:

FQ_SEL

HIGH

Q0

5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL HIGH)

2.5MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW)

HIGH

Figure 5a. Wiring Diagram and Frequency Relationships With Q/2 Output Feed Back

50 MHz SIGNAL

25 MHz FEEDBACK SIGNAL

HIGH

1:1 Input to “Q” Output Frequency Relationship

RST

Q5

Q4

2X_Q

12.5 MHz

SIGNAL

FEEDBACK

REF_SEL

SYNC[0]

Q/2

Q3

Q2

In this application, the Q4 output is connected to

the FEEDBACK input. The internal PLL will line up

the positive edges of Q4 and SYNC, thus the Q4

frequency (and the rest of the “Q” outputs) will

equal the SYNC frequency. The Q/2 output will al-

LOW

25 MHZ INPUT

CRYSTAL

25MHz

“Q”

CLOCK

MC88915

OSCILLATOR

ANALOG V

CC

EXTERNAL

LOOP

FILTER

RC1

OUTPUTS ways run at 1/2 the “Q” frequency, and the 2X_Q

output will run at 2X the “Q” frequency.

ANALOG GND

PLL_EN

FQ_SEL

HIGH

Q0

Q1

Allowable Input Frequency Range:

10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL HIGH)

5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL LOW)

HIGH

Figure 5b. Wiring Diagram and Frequency Relationships With Q4 Output Feed Back

50 MHz FEEDBACK SIGNAL

HIGH

RST

Q4

2X_Q

Q/2

Q5

2:1 Input to “Q” Output Frequency Relationship

12.5 MHz

SIGNAL

FEEDBACK

REF_SEL

SYNC[0]

LOW

In this application, the 2X_Q output is connected

to the FEEDBACK input. The internal PLL will line

up the positive edges of 2X_Q and SYNC, thus the

2X_Q frequency will equal the SYNC frequency.

The Q/2 output will always run at 1/4 the 2X_Q fre-

quency, and the “Q” outputs will run at 1/2 the

2X_Q frequency.

50 MHz INPUT

MC88915

CRYSTAL

Q3

Q2

25MHz

“Q”

CLOCK

OUTPUTS

OSCILLATOR

ANALOG V

CC

EXTERNAL

LOOP

FILTER

RC1

ANALOG GND

PLL_EN

Q1

FQ_SEL

HIGH

Q0

Allowable Input Frequency Range:

HIGH

20MHz to (2X_Q FMAX Spec) (for FREQ_SEL HIGH)

10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW)

Figure 5c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feed Back

TIMING SOLUTIONS

BR1333 — Rev 6

9

MOTOROLA

MC88915

BOARD V

CC

47Ω

8

9

ANALOG V

CC

470KΩ

330

Ω

ANALOG LOOP FILTER/VCO

SECTION OF THE MC88915

28–PIN PLCC PACKAGE (NOT

DRAWN TO SCALE)

0.1

µ

F HIGH

FREQ

10

µF LOW

RC1

FREQ BYPASS

BYPASS

0.1µF (LOOP

FILTER CAP)

10 ANALOG GND

47Ω

A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND

SHOULDNOTBEUSED. FOLLOWINGTHESEPRESCRIBEDGUIDELINES

ISALLTHATISNECESSARYTOUSETHEMC88915INANORMALDIGITAL

ENVIRONMENT.

BOARD GND

Figure 6. Recommended Loop Filter and Analog Isolation Scheme for the MC88915

Notes Concerning Loop Filter and Board Layout Issues

1. Figure 6 shows a loop filter and analog isolation scheme

which will be effective in most applications. The following

guidelines should be followed to ensure stable and

jitter–free operation:

is to give the 88915 additional protection from the power

supply and ground plane transients that can occur in a

high frequency, high speed digital system.

1c.There are no special requirements set forth for the loop

filter resistors (470K and 330Ω). The loop filter capacitor

(0.1µF) can be a ceramic chip capacitior, the same as a

standard bypass capacitor.

1a.All loop filter and analog isolation components should be

tied as close to the package as possible. Stray current

passing through the parasitics of long traces can cause

undesirable voltage transients at the RC1 pin.

1d.The 470K reference resistor injects current into the

internal charge pump of the PLL, causing a fixed offset

between the outputs and the SYNC input. This also

prevents excessive jitter caused by inherent PLL

dead–band. If the VCO (2X_Q output) is running above

40MHz, the 470K resistor provides the correct amount of

current injection into the charge pump (2–3µA). If the

VCO is running below 40MHz, a 1MΩ reference resistor

should be used (instead of 470K).

1b.The 47Ω resistors, the 10µF low frequency bypass

capacitor, andthe0.1µF high frequency bypass capacitor

form a wide bandwidth filter that will minimize the 88915’s

sensitivity to voltage transients from the system digital

V

supply and ground planes. This filter will typically

CC

ensure that a 100mV step deviation on the digital V

CC

supply will cause no more than a 100pS phase deviation

on the 88915 outputs. A 250mV step deviation on V

CC

using the recommended filter values should cause no

more than a 250pS phase deviation; if a 25µF bypass

2. In addition to the bypass capacitors used in the analog

capacitor is used (instead of 10µF) a 250mV V

should cause no more than a 100pS phase deviation.

step

CC

filter of Figure 6, there should be a 0.1µF bypass

capacitorbetweeneachoftheother(digital)fourV

pins

CC

If good bypass techniques are used on a board design

and the board ground plane. This will reduce output

switching noise caused by the 88915 outputs, in addition

toreducingpotentialfornoiseinthe‘analog’sectionofthe

chip. These bypass capacitors should also be tied as

close to the 88915 package as possible.

near components which may cause digital V

and

step deviations

CC

ground noise, the above described V

CC

should not occur at the 88915’s digital V

supply. The

purpose of the bypass filtering scheme shown in Figure 6

CC

MOTOROLA

10

TIMING SOLUTIONS

BR1333 — Rev 6

MC88915

CPU

CMMU

CPU

CMMU

CARD

MC88915

PLL

2f

CLOCK

@ f

CMMU

SYSTEM

CLOCK

SOURCE

CPU

CMMU

CARD

CMMU

CPU

MC88915

PLL

2f

DISTRIBUTE

CLOCK @ f

CMMU

CLOCK @ 2f

AT POINT OF USE

PLL

MEMORY

CONTROL

2f

MEMORY

CARDS

CLOCK @ 2f

AT POINT OF USE

Figure 7. Representation of a Potential Multi–Processing Application Utilizing the MC88915

for Frequency Multiplication and Low Board–to–Board Skew

MC88915 System Level Testing Functionality

When the PLL_EN pin is low, the VCO is disabled and the 88915 is in low frequency “test mode”. In test mode (with FREQ_SEL

high), the 2X_Q output is inverted from the selected SYNC input, and the “Q” outputs are divide–by–2 (negative edge triggered)

of the SYNC input, and the Q/2 output is divide–by–4. With FREQ_SEL low the 2X_Q output is divide–by–2 of the SYNC, the “Q”

outputs divide–by–4, and the Q/2 output divide–by–8. These relationships can be seen on the block diagram. A recommended

test configuration would be to use SYNC0 as the test clock input, and tie PLL_EN and REF_SEL together and connect them to

the test select logic. When these inputs are low, the 88915 is in test mode and the SYNC0 input is selected.

Thisfunctionalityisneededsincemostboard–leveltestersrunat1MHzorbelow, andthe88915cannotlockontothatlowofan

input frequency. In the test mode described above, any frequency test signal can be used.

TIMING SOLUTIONS

BR1333 — Rev 6

11

MOTOROLA

MC88915

OUTLINE DIMENSIONS

FN SUFFIX

PLASTIC PACKAGE

CASE 776–02

ISSUE D

M

S

0.007 (0.180)

T

L–M

N

B

Y BRK

D

–N–

M

S

0.007 (0.180)

T

L–M

N

U

Z

–M–

–L–

W

D

S

0.010 (0.250)

T

L–M

N

X

G1

V

28

1

VIEW D–D

M

S

A

0.007 (0.180)

T

L–M

N

M

S

0.007 (0.180)

T

L–M

N

H

Z

M

S

T

N

R

K1

C

E

0.004 (0.100)

SEATING

PLANE

G

K

–T–

VIEW S

J

M

S

0.007 (0.180)

T

L–M

N

F

G1

S

0.010 (0.250)

T

L–M

N

VIEW S

NOTES:

INCHES

MILLIMETERS

1. DATUMS –L–, –M–, AND –N– DETERMINED

WHERE TOP OF LEAD SHOULDER EXITS

PLASTIC BODY AT MOLD PARTING LINE.

2. DIMENSION G1, TRUE POSITION TO BE

MEASURED AT DATUM –T–, SEATING PLANE.

3. DIMENSIONS R AND U DO NOT INCLUDE

MOLD FLASH. ALLOWABLE MOLD FLASH IS

0.010 (0.250) PER SIDE.

DIM

A

B

C

E

F

G

H

J

K

R

U

V

W

X

Y

Z

G1

K1

MIN

MAX

0.495

0.180

0.110

0.019

MIN

12.32

4.20

MAX

12.57

4.57

0.485

0.165

0.090

0.013

2.29

2.79

0.33

0.48

0.050 BSC

1.27 BSC

4. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

0.026

0.020

0.025

0.450

0.042

–––

0.032

–––

0.456

0.048

0.056

0.020

10

0.66

0.51

0.64

11.43

1.07

–––

0.81

–––

11.58

1.21

1.42

0.50

10

5. CONTROLLING DIMENSION: INCH.

6. THE PACKAGE TOP MAY BE SMALLER THAN

THE PACKAGE BOTTOM BY UP TO 0.012

(0.300). DIMENSIONS R AND U ARE

DETERMINED AT THE OUTERMOST

EXTREMES OF THE PLASTIC BODY

EXCLUSIVE OF MOLD FLASH, TIE BAR

BURRS, GATE BURRS AND INTERLEAD

FLASH, BUT INCLUDING ANY MISMATCH

BETWEEN THE TOP AND BOTTOM OF THE

PLASTIC BODY.

2

0.410

0.040

0.430

–––

10.42

1.02

10.92

–––

7. DIMENSION H DOES NOT INCLUDE DAMBAR

PROTRUSION OR INTRUSION. THE DAMBAR

PROTRUSION(S) SHALL NOT CAUSE THE H

DIMENSION TO BE GREATER THAN 0.037

(0.940). THE DAMBAR INTRUSION(S) SHALL

NOT CAUSE THE H DIMENSION TO BE

SMALLER THAN 0.025 (0.635).

MOTOROLA

12

TIMING SOLUTIONS

BR1333 — Rev 6

MC88915

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola

datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”

must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of

others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury

ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

Motorola was negligent regarding the design or manufacture of the part. Motorola and

Opportunity/Affirmative Action Employer.

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal

How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;

P.O. Box 5405; Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447

JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,

3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

MC88915/D

MOTOROLA

◊

TIMING SOLUTIONS

BR1333 — Rev 6

13


型号：	MC88915FN70R2
厂家：	MOTOROLA
描述：	88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLASTIC, LCC-28 驱动输出元件
文件：	总13页 (文件大小：148K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC88915FN70R2 [MOTOROLA]

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