MCM67H618AFN9 [MOTOROLA]
64K x 18 Bit BurstRAM Synchronous Fast Static RAM; 64K ×18位BurstRAM同步快速静态RAM
| 型号： | MCM67H618AFN9 |
| 厂家： | 
MOTOROLA |
| 描述： | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| 文件： | 总12页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MCM67H618A/D
SEMICONDUCTOR TECHNICAL DATA
MCM67H618A
Product Preview
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Self–Timed Write
The MCM67H618A is a 1,179,648 bit synchronous fast static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486 and Pentium microprocessors. It is organized as 65,536 words
of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS
technology. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive capability outputs onto a single monolithic circuit for
reduced parts count implementation of cache data RAM applications. Syn-
chronous design allows precise cycle control with the use of an external clock
(K). BiCMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability.
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENT
7
6
5
4
3
2
1 52 51 50 49 48 47
46
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals except
output enable (G) are clock (K) controlled through positive–edge–triggered
noninverting registers.
8
9
DQ9
DQ10
DQ8
DQ7
DQ6
45
44
43
42
41
V
V
10
CC
SS
Bursts canbeinitiatedwitheitheraddressstatusprocessor(ADSP) or address
status cache controller (ADSC) input pins. Subsequent burst addresses can be
generated internally by the MCM67H618A (burst sequence imitates that of the
i486 and Pentium) and controlled by the burst address advance (ADV) input pin.
The following pages provide more detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased flexibility for incoming signals.
11
12
13
14
15
V
CC
DQ11
DQ12
DQ13
DQ14
V
SS
DQ5
40 DQ4
39 DQ3
38 DQ2
V
16
17
SS
V
37
V
V
CC
SS
CC
DQ15
18
36
Dual write enables (LW and UW) are provided to allow individually writeable DQ16 19
35 DQ1
34 DQ0
DQ17
20
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17
(the upper bits).
21 22 23 24 25 26 27 28 29 30 31 32 33
This device is ideally suited for systems that require wide data bus widths and
cache memory. See Figure 2 for applications information.
•
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 5% Power Supply
Fast Access Times: 9/10/12 ns Max
Byte Writeable via Dual Write Enables
Internal Input Registers (Address, Data, Control)
Internally Self–Timed Write Cycle
ADSP, ADSC, and ADV Burst Control Pins
Asynchronous Output Enable Controlled Three–State Outputs
Common Data Inputs and Data Outputs
3.3 V I/O Compatible
High Board Density 52–Lead PLCC Package
ADSP Disabled with Chip Enable (E) – Supports Address Pipelining
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
ADV . . . . . . . . . . . . Burst Address Advance
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Upper Byte Write Enable
ADSC . . . . . . . . . Controller Address Status
ADSP . . . . . . . . . Processor Address Status
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . Data Input/Output
V
CC
V
SS
. . . . . . . . . . . . . . . . + 5 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground
All power supply and ground pins must be
connectedforproperoperationofthedevice.
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
5/95
Motorola, Inc. 1994
BLOCK DIAGRAM (See Note)
ADV
BURST LOGIC
INTERNAL
ADDRESS
A0
′
′
Q0
Q1
K
A0
64K x 18
MEMORY
ARRAY
16
A1
CLR
A1
ADSC
ADSP
2
A1 – A0
ADDRESS
REGISTER
A2 – A15
A0 – A15
18
9
9
16
WRITE
REGISTER
DATA–IN
REGISTERS
UW
LW
ENABLE
REGISTER
OUTPUT
BUFFER
E
9
9
G
9
9
DQ0 – DQ8
DQ9 – DQ17
NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP and E are sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC)
is performed using the new external address. Alternatively, an ADSP–initiated two cycle WRITE can be performed by as-
serting ADSP, E, and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW
with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram). Note that when E and
ADSC are high, ADSP is ignored – the external address is not registered in this case.
When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent
on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded.
After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address
is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait
state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See
BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).
BURST SEQUENCE TABLE (See Note)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A15 – A2
A15 – A2
A15 – A2
A15 – A2
A1
A1
A1
A1
A0
A0
A0
A0
NOTE: The burst wraps around to its initial state upon completion.
MCM67H618A
2
MOTOROLA FAST SRAM
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
E
H
L
ADSP
ADSC
ADV
X
UW or LW
K
Address Used
N/A
Operation
X
L
L
X
L
X
X
L
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
Deselected
X
External Address
External Address
External Address
Next Address
Next Address
Current Address
Current Address
Next Address
Next Address
Current Address
Current Address
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Suspend Burst
Read Cycle, Suspend Burst
L
H
H
H
H
H
H
X
X
X
X
X
L
L
X
H
L
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
L
H
L
L
H
L
H
H
H
H
NOTES:
1. X means Don’t Care.
2. All inputs except G must meet setup and hold times for the low–to–high transition of clock (K).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation
Read
G
L
I/O Status
Data Out
Read
H
X
X
High–Z
Write
High–Z — Data In
High–Z
Deselected
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, G must be high before the input data
required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
SS
= 0 V)
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
Rating
Power Supply Voltage
Voltage Relative to V
Symbol
Value
Unit
V
V
CC
– 0.5 to + 7.0
for Any
V , V
in out
– 0.5 to V
CC
+ 0.5
V
SS
Pin Except V
CC
Output Current (per I/O)
Power Dissipation
I
± 30
mA
W
out
P
D
1.6
Temperature Under Bias
Operating Temperature
Storage Temperature
T
bias
– 10 to + 85
0 to +70
°C
°C
°C
T
A
This devicecontainscircuitrythatwillensure
the output devices are in High–Z at power up.
T
stg
– 55 to + 125
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
MCM67H618A
3
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 5%, T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to V
= 0 V)
SS
Parameter
Supply Voltage (Operating Voltage Range)
Input High Voltage
Symbol
Min
4.75
2.2
Max
Unit
V
V
CC
5.25
V
IH
V
+ 0.3**
V
CC
Input Low Voltage
V
IL
– 0.5*
0.8
V
*V (min) = – 0.5 V dc; V (min) = – 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.
IL IL
**V (max) = V
+ 0.3 V dc; V (max) = V
+ 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.
IH CC IH CC
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Max
± 1.0
± 1.0
Unit
µA
Input Leakage Current (All Inputs, V = 0 to V
in CC
)
I
—
—
lkg(I)
Output Leakage Current (G = V
IH
)
I
µA
lkg(O)
AC Supply Current (G = V , E = V , I
= 0 mA, All Inputs = V or V , V = 0.0 V and
IL IH IL
I
I
I
—
—
—
275
265
250
mA
IH
IL out
min)
KHKH
CCA9
CCA10
CCA12
V
IH
≥ 3.0 V, Cycle Time ≥ t
AC Standby Current (E = V , I
= 0 mA, All Inputs = V and V
min)
V
= 0.0 V and
I
—
95
mA
IH out
IL IH, IL
SB1
V
IH
≥ 3.0 V, Cycle Time ≥ t
KHKH
Output Low Voltage (I
= + 8.0 mA)
V
—
0.4
3.3
V
V
OL
OL
Output High Voltage (I
= – 4.0 mA)
V
OH
2.4
OH
NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible i486 and Pentium
bus cycles.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Input Capacitance (All Pins Except DQ0 – DQ17)
Input/Output Capacitance (DQ0 – DQ17)
Symbol
Typ
4
Max
5
Unit
pF
C
in
C
6
8
pF
I/O
MCM67H618A
4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 5%, T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM67H618A–9
MCM67H618A–10
MCM67H618A–12
Parameter
Cycle Time
Symbol
Min
15
—
—
6
Max
—
9
Min
16.6
—
—
6
Max
—
10
5
Min
20
—
—
6
Max
—
12
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
t
KHKH
Clock Access Time
t
5
KHQV
Output Enable to Output Valid
Clock High to Output Active
Clock High to Output Change
Output Enable to Output Active
Output Disable to Q High–Z
Clock High to Q High–Z
t
5
GLQV
t
t
—
—
—
6
—
—
—
7
—
—
—
7
KHQX1
KHQX2
3
3
3
t
0
0
0
GLQX
GHQZ
t
—
3
—
3
—
3
6
7
t
6
7
7
KHQZ
Clock High Pulse Width
t
5
—
—
—
5
—
—
—
6
—
—
—
KHKL
KLKH
AVKH
Clock Low Pulse Width
t
5
5
6
Setup Times:
Address
Address Status
Data In
t
2.5
2.5
2.5
t
t
ADSVKH
t
t
DVKH
Write
WVKH
ADVVKH
Address Advance
Chip Enable
t
EVKH
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
t
0.5
—
0.5
—
0.5
—
ns
7
KHAX
t
t
KHADSX
t
t
KHDX
KHWX
KHADVX
t
KHEX
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW.
2. A read cycle is defined by UW and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and ADSP
high for the setup and hold times.
3. All read and write cycle timings are referenced from K or G.
4. G is a don’t care when UW or LW is sampled low.
5. Maximum access times are guaranteed for all possible i486 and Pentium external bus cycles.
6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested.
At any given voltage and temperature, t
max is less than t min for a given device and from device to device.
KHQZ
KHQZ1
7. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of K whenever ADSP or
ADSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of
K when the chip is enabled. Chip enable must be asserted at each rising edge of clock for the device (when ADSC is low) to remain enabled.
+ 5 V
AC TEST LOADS
480
Ω
OUTPUT
OUTPUT
255 Ω
R
= 50 Ω
Z
= 50
Ω
L
0
5 pF
V
= 1.5 V
L
Figure 1A
Figure 1B
MCM67H618A
5
MOTOROLA FAST SRAM
MCM67H618A
6
MOTOROLA FAST SRAM
MCM67H618A
7
MOTOROLA FAST SRAM
COMBINATION READ/WRITE CYCLE (E low, ADSC high)
t
KHKH
K
t
t
KLKH
KHKL
t
t
KHADSX
ADSVKH
ADSP
t
t
KHAX
AVKH
ADDRESS
A1
A2
A3
t
t
t
WVKH
KHWX
LW, UW
t
ADVVKH
KHADVX
ADV
G
t
t
t
GLQV
DVKH
KHDX
t
KHQV
DATA IN
D(A2)
t
t
t
t
KHQX2
KHQX1
GHQZ
GLQX
DATA OUT
Q(A3)
Q(A3 + 1)
Q(A3 + 2)
Q(A1)
READ
WRITE
BURST READ
MCM67H618A
8
MOTOROLA FAST SRAM
APPLICATION EXAMPLE
DATA BUS
DATA
ADDRESS BUS
ADDRESS
72
16
CLOCK
Pentium
ADDR
ADDR
DATA
K
CLK
NA
K
ADSC
W
CACHE
CONTROL
LOGIC
MCM67H618AFN9
G
E
ADV
ADSP
ADS
CONTROL
512K Byte Burstable, Secondary Cache
Using Four MCM67H618AFN9s with a 66 MHz Pentium
Figure 2
MCM67H618A
9
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM
67H618A XX XX
Speed (9 = 9 ns, 10 = 10 ns, 12 = 12 ns)
Package (FN = PLCC)
Motorola Memory Prefix
Part Number
Full Part Numbers — MCM67H618AFN9
MCM67H618AFN10 MCM67H618AFN12
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintendedor unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MCM67H618A
10
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
FN PACKAGE
52–LEAD PLCC
CASE 778–02
M
S
S
B
0.007 (0.180)
T
L –M
N
Y BRK
-N-
M
S
S
0.007 (0.180)
T
L –M
N
U
D
D
-L-
-M-
52
LEADS
ACTUAL
Z
W
(NOTE 1)
52
1
G1
X
S
S
S
0.010 (0.250)
0.007 (0.180)
T
L –M
L –M
N
V
VIEW D-D
M
S
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T
T
L –M
L –M
N
N
Z
M
R
M
S
S
H
T
N
C
K1
E
K
0.004 (0.100)
(NOTE 1)
52
SEATING
-T-
G
J
PLANE
M
S
S
F
0.007 (0.180)
T
L –M
N
VIEW S
VIEW S
G1
S
S
S
0.010 (0.250)
T
L –M
N
NOTES:
1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE
REPRESENTED BY A GENERAL (SMALLER) CASE
OUTLINE DRAWING RATHER THAN SHOWING ALL 52
LEADS.
2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF
LEAD SHOULDER EXITS PLASTIC BODY AT MOLD
PARTING LINE.
3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-,
SEATING PLANE.
4. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
1982.
INCHES
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
20.19
20.19
4.57
A
B
C
E
0.785
0.785
0.165
0.090
0.013
0.795
0.795
0.180
0.110
0.019
19.94
19.94
4.20
2.29
2.79
F
0.33
0.48
G
H
J
K
R
U
V
W
X
Y
0.050 BSC
1.27 BSC
0.026
0.032
—
—
0.756
0.756
0.048
0.048
0.056
0.020
0.66
0.51
0.64
19.05
19.05
1.07
1.07
1.07
—
0.81
—
—
19.20
19.20
1.21
1.21
1.42
0.50
0.020
0.025
0.750
0.750
0.042
0.042
0.042
—
6. CONTROLLING DIMENSION: INCH.
7. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS
R AND U ARE DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
8. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION
TO BE GREATER THAN 0.037 (0.940). THE DAMBAR
INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO
BE SMALLER THAN 0.025 (0.635).
Z
G1
K1
2°
10
°
2°
10°
0.710
0.040
0.730
—
18.04
1.02
18.54
—
MCM67H618A
11
MOTOROLA FAST SRAM
Literature Distribution Centers:
USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
CODELINE TO BE PLACED HERE
MCM67H618A/D
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