MLP1N06 [MOTOROLA]

VOLTAGE CLAMPED CURRENT LIMITING MOSFET; 电压固支限流MOSFET


型号：	MLP1N06
厂家：	MOTOROLA
描述：	VOLTAGE CLAMPED CURRENT LIMITING MOSFET 电压固支限流MOSFET
文件：	总6页 (文件大小：140K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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by MLP1N06CL/D

SEMICONDUCTOR TECHNICAL DATA

SMARTDISCRETES

Internally Clamped, Current Limited

N–Channel Logic Level Power MOSFET

Motorola Preferred Device

These SMARTDISCRETES devices feature current limiting for short circuit

protection, an integral gate–to–source clamp for ESD protection and gate–to–drain

clamp for over–voltage protection. No additional gate series resistance is required

when interfacing to the output of a MCU, but a 40 kΩ gate pulldown resistor is

recommended to avoid a floating gate condition.

The internal gate–to–source and gate–to–drain clamps allow the devices to be

applied without use of external transient suppression components. The gate–to–

source clamp protects the MOSFET input from electrostatic gate voltage stresses

up to 2.0 kV. The gate–to–drain clamp protects the MOSFET drain from drain

avalanche stresses that occur with inductive loads. This unique design provides

voltage clamping that is essentially independent of operating temperature.

The MLP1N06CL is fabricated using Motorola’s SMARTDISCRETES technolo-

gy which combines the advantages of a power MOSFET output device with

on–chip protective circuitry. This approach offers an economical means for

providing additional functions that protect a power MOSFET in harsh automotive

and industrial environments. SMARTDISCRETES devices are specified over a

wide temperature range from –50°C to 150°C.

VOLTAGE CLAMPED

CURRENT LIMITING

MOSFET

62 VOLTS (CLAMPED)

= 0.75 OHMS

DS(on)

•

Temperature Compensated Gate–to–Drain Clamp Limits Voltage Stress

Applied to the Device and Protects the Load From Overvoltage

Integrated ESD Diode Protection

•

Controlled Switching Minimizes RFI

•

Low Threshold Voltage Enables Interfacing Power Loads to Microprocessors

MAXIMUM RATINGS (T = 25°C unless otherwise noted)

Rating

Symbol

Value

Clamped

±10

Unit

Vdc

Adc

Drain–to–Source Voltage

DSS

Drain–to–Gate Voltage (R

= 1.0 MΩ)

DGR

Gate–to–Source Voltage — Continuous

Drain Current — Continuous

Drain Current — Single Pulse

Self–limited

1.8

Total Power Dissipation

2.0

Watts

Electrostatic Discharge Voltage (Human Body Model)

Operating and Storage Junction Temperature Range

ESD

T , T

–50 to 150

°C

stg

THERMAL CHARACTERISTICS

Thermal Resistance, Junction to Case

Thermal Resistance, Junction to Ambient

3.12

62.5

°C/W

°C

Maximum Lead Temperature for Soldering Purposes,

1/8″ from case

260

CASE 221A–06, Style 5

TO–220AB

UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS

Single Pulse Drain–to–Source Avalanche Energy

(Starting T = 25°C, I = 2.0 A, L = 40 mH) (Figure 6)

SMARTDISCRETES is a trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola TMOS Power MOSFET Transistor Device Data

Motorola, Inc. 1996

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)

Characteristic

OFF CHARACTERISTICS

Drain–to–Source Sustaining Voltage (Internally Clamped)

Symbol

Min

Typ

Max

Unit

Vdc

(BR)DSS

(I = 20 mA, V

= 0)

= 0, T = 150°C)

Zero Gate Voltage Drain Current

µAdc

DSS

= 45 V, V

= 0)

—

0.6

6.0

5.0

= 0, T = 150°C)

Gate–Body Leakage Current

GSS

(V = 5.0 V, V

= 0)

—

0.5

1.0

5.0

= 0, T = 150°C)

ON CHARACTERISTICS*

Gate Threshold Voltage

Vdc

GS(th)

(I = 250 µA, V

= V

)

1.0

0.6

1.5

—

2.0

1.6

(I = 250 µA, V

= V , T = 150°C)

Static Drain–to–Source On–Resistance

Ohms

DS(on)

(I = 1.0 A, V

= 4.0 V)

= 5.0 V)

= 4.0 V, T = 150°C)

= 5.0 V, T = 150°C)

—

0.63

0.59

1.1

0.75

1.9

(I = 1.0 A, V

1.0

1.8

Forward Transconductance (I = 1.0 A, V

= 10 V)

1.0

—

1.4

1.1

—

mhos

Vdc

Static Source–to–Drain Diode Voltage (I = 1.0 A, V

= 0)

1.5

Static Drain Current Limit

D(lim)

= 5.0 V, V

= 10 V)

= 10 V, T = 150°C)

2.0

1.1

2.3

1.3

2.75

1.8

RESISTIVE SWITCHING CHARACTERISTICS*

Turn–On Delay Time

—

1.2

4.0

3.0

2.0

6.0

5.0

µs

d(on)

Rise Time

(V = 25 V, I = 1.0 A,

DD D

= 5.0 V, R = 50 Ohms)

Turn–Off Delay Time

Fall Time

d(off)

* Indicates Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.

= 25°C

≥

7.5 V

–50°C

10 V

6 V

8 V

4 V

25°C

= 150°C

= 3 V

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. Output Characteristics

Figure 2. Transfer Function

Motorola TMOS Power MOSFET Transistor Device Data

THE SMARTDISCRETES CONCEPT

From a standard power MOSFET process, several active

and passive elements can be obtained that provide on–chip

protection to the basic power device. Such elements require

only a small increase in silicon area and/or the addition of one

masking layer to the process. The resulting device exhibits

significant improvements in ruggedness and reliability as well

as system cost reduction. The SMARTDISCRETES device

functions can now provide an economical alternative to smart

power ICs for power applications requiring low on–resistance,

high voltage and high current.

These devices are designed for applications that require a

rugged power switching device with short circuit protection

that can be directly interfaced to a microcontroller unit

(MCU). Ideal applications include automotive fuel injector

driver, incandescent lamp driver or other applications where

a high in–rush current or a shorted load condition could occur.

= 5 V

= 7.5 V

–50

100

150

T , JUNCTION TEMPERATURE (

OPERATION IN THE CURRENT LIMIT MODE

Figure 3. I

Variation With Temperature

D(lim)

The amount of time that an unprotected device can with-

stand the current stress resulting from a shorted load before

its maximum junction temperature is exceeded is dependent

upon a number of factors that include the amount

of heatsinking that is provided, the size or rating of the de-

vice, its initial junction temperature, and the supply voltage.

Without some form of current limiting, a shorted load can

raise a device’s junction temperature beyond the maximum

rated operating temperature in only a few milliseconds.

Even with no heatsink, the MLP1N06CL can withstand a

shorted load powered by an automotive battery (10 to 14

Volts) for almost a second if its initial operating temperature

is under 100°C. For longer periods of operation in the cur-

rent–limited mode, device heatsinking can extend operation

from several seconds to indefinitely depending on the

amount of heatsinking provided.

= 1 A

150°C

= –50°C

25°C

SHORT CIRCUIT PROTECTION AND THE EFFECT OF

TEMPERATURE

The on–chip circuitry of the MLP1N06CL offers an inte-

grated means of protecting the MOSFET component from

high in–rush current or a shorted load. As shown in the sche-

matic diagram, the current limiting feature is provided by an

NPN transistor and integral resistors R1 and R2. R2 senses

the current through the MOSFET and forward biases the

NPN transistor’s base as the current increases. As the NPN

turns on, it begins to pull gate drive current through R1, drop-

ping the gate drive voltage across it, and thus lowering the

voltage across the gate–to–source of the power MOSFET

and limiting the current. The current limit is temperature de-

pendent as shown in Figure 3, and decreases from about 2.3

Amps at 25°C to about 1.3 Amps at 150°C.

, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 4. R

Variation With

Gate–To–Source Voltage

DS(on)

1.25

= 1 A

Since the MLP1N06CL continues to conduct current and

dissipate power during a shorted load condition, it is impor-

tant to provide sufficient heatsinking to limit the device junc-

tion temperature to a maximum of 150°C.

= 4 V

0.75

= 5 V

The metal current sense resistor R2 adds about 0.4 ohms

to the power MOSFET’s on–resistance, but the effect of tem-

perature on the combination is less than on a standard

MOSFET due to the lower temperature coefficient of R2. The

on–resistance variation with temperature for gate voltages of

4 and 5 Volts is shown in Figure 5.

0.5

0.25

–50

100

150

T , JUNCTION TEMPERATURE (

Back–to–back polysilicon diodes between gate and source

provide ESD protection to greater than 2 kV, HBM. This on–

chip protection feature eliminates the need for an external

Zener diode for systems with potentially heavy line transients.

Figure 5. On–Resistance Variation With

Temperature

Motorola TMOS Power MOSFET Transistor Device Data

100

–50

100

150

100

125

150

T , JUNCTION TEMPERATURE (

°C)

Figure 6. Single Pulse Avalanche Energy

versus Junction Temperature

Figure 7. Drain–Source Sustaining

Voltage Variation With Temperature

FORWARD BIASED SAFE OPERATING AREA

DUTY CYCLE OPERATION

When operating in the duty cycle mode, the maximum

drain voltage can be increased. The maximum operating

temperature is related to the duty cycle (DC) by the following

equation:

The FBSOA curves define the maximum drain–to–source

voltage and drain current that a device can safely handle

when it is forward biased, or when it is on, or being turned on.

Because these curves include the limitations of simultaneous

high voltage and high current, up to the rating of the device,

they are especially useful to designers of linear systems. The

curves are based on a case temperature of 25°C and a maxi-

mum junction temperature of 150°C. Limitations for repetitive

pulses at various case temperatures can be determined by

using the thermal response curves. Motorola Application

Note, AN569, “Transient Thermal Resistance — General

Data and Its Use” provides detailed instructions.

= (V

x I x DC x R ) + T

D θCA A

The maximum value of V

applied when operating in a

duty cycle mode can be approximated by:

150 – T

x DC x R

D(lim)

θJC

– MAX

– MIN

D(lim)

1 ms

MAXIMUM DC VOLTAGE CONSIDERATIONS

1.5

The maximum drain–to–source voltage that can be contin-

uously applied across the MLP1N06CL when it is in current

limit is a function of the power that must be dissipated. This

power is determined by the maximum current limit at maxi-

mum rated operating temperature (1.8 A at 150°C) and not

D(lim)

5 ms

0.6

DEVICE/POWER LIMITED

LIMITED

DS(on)

0.3

0.2

= 5 V

the R

. The maximum voltage can be calculated by the

following equation:

DS(on)

SINGLE PULSE

= 25

°C

0.1

100

(150 – T )

supply

+ R

)

θCA

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

D(lim) θJC

Figure 8. Maximum Rated Forward Bias

Safe Operating Area (MLP1N06CL)

where the value of R

is determined by the heatsink that is

being used in the application.

θCA

Motorola TMOS Power MOSFET Transistor Device Data

1.0

0.7

D = 0.5

(t) = r(t) R

0.5

(t) = 3.12°C/W Max

D Curves Apply for Power

Pulse Train Shown

0.3

0.2

0.1

Read Time at t

– T = P

C (pk)

(t)

J(pk)

θJC

0.1

0.07

0.05

0.02

(pk)

0.03

0.02

0.01

SINGLE PULSE

DUTY CYCLE, D =t /t

1 2

0.01

0.02 0.03 0.05

0.1

0.2 0.3

0.5

1.0

2.0 3.0

5.0

100

200 300 500

1000

t, TIME (ms)

Figure 9. Thermal Response (MLP1N06CL)

off

d(off)

d(on)

out

90%

DUT

PULSE GENERATOR

OUTPUT, V

INVERTED

out

z = 50

Ω

10%

gen

50Ω

90%

50%

Ω

50%

10%

PULSE WIDTH

INPUT, V

Figure 10. Switching Test Circuit

Figure 11. Switching Waveforms

ACTIVE CLAMPING

SMARTDISCRETES technology can provide on–chip real-

ization of the popular gate–to–source and gate–to–drain

Zener diode clamp elements. Until recently, such features

have been implemented only with discrete components

which consume board space and add system cost. The

SMARTDISCRETES technology approach economically

melds these features and the power chip with only a slight

increase in chip area.

In practice, back–to–back diode elements are formed in a

polysilicon region monolithicly integrated with, but electrically

isolated from, the main device structure. Each back–to–back

diode element provides a temperature compensated voltage

element of about 7.2 volts. As the polysilicon region is

formed on top of silicon dioxide, the diode elements are free

from direct interaction with the conduction regions of the

power device, thus eliminating parasitic electrical effects

while maintaining excellent thermal coupling.

elements provide greater than 2.0 kV electrostatic voltage

protection.

The avalanche voltage of the gate–to–drain voltage clamp

is set less than that of the power MOSFET device. As soon

as the drain–to–source voltage exceeds this avalanche volt-

age, the resulting gate–to–drain Zener current builds a gate

voltage across the gate–to–source impedance, turning on

the power device which then conducts the current. Since vir-

tually all of the current is carried by the power device, the

gate–to–drain voltage clamp element may be small in size.

This technique of establishing a temperature compensated

drain–to–source sustaining voltage (Figure 7) effectively re-

moves the possibility of drain–to–source avalanche in the

power device.

The gate–to–drain voltage clamp technique is particularly

useful for snubbing loads where the inductive energy would

otherwise avalanche the power device. An improvement in

ruggedness of at least four times has been observed when

inductive energy is dissipated in the gate–to–drain clamped

conduction mode rather than in the more stressful gate–to–

source avalanche mode.

To achieve high gate–to–drain clamp voltages, several

voltage elements are strung together; the MLP1N06CL uses

8 such elements. Customarily, two voltage elements are

used to provide a 14.4 volt gate–to–source voltage clamp.

For the MLP1N06CL, the integrated gate–to–source voltage

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS

The MLP1N06CL has been designed to allow direct inter-

BAT

face to the output of a microcontrol unit to control an isolated

load. No additional series gate resistance is required, but a

40 kΩ gate pulldown resistor is recommended to avoid a

floating gate condition in the event of an MCU failure. The in-

ternal clamps allow the device to be used without any exter-

nal transistent suppressing components.

MCU

MLP1N06CL

PACKAGE DIMENSIONS

NOTES:

SEATING

PLANE

STYLE 5:

PIN 1. GATE

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

–T–

2. DRAIN

3. SOURCE

4. DRAIN

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL

BODY AND LEAD IRREGULARITIES ARE

ALLOWED.

INCHES

MIN

MILLIMETERS

DIM

MAX

0.620

0.405

0.190

0.035

0.147

0.105

0.155

0.025

0.562

0.060

0.210

0.120

0.110

0.055

0.255

0.050

–––

MIN

14.48

9.66

4.07

0.64

3.61

2.42

2.80

0.46

12.70

1.15

4.83

2.54

2.04

1.15

5.97

0.00

1.15

–––

MAX

15.75

10.28

4.82

0.88

3.73

2.66

3.93

0.64

14.27

1.52

5.33

3.04

2.79

1.39

6.47

1.27

–––

0.570

0.380

0.160

0.025

0.142

0.095

0.110

0.018

0.500

0.045

0.190

0.100

0.080

0.045

0.235

0.000

0.045

–––

0.080

2.04

CASE 221A–06

ISSUE Y

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

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Motorola TMOS Power MOSFET Transistor Device Data

MLP1N06CL/D

◊

MLP1N06 [MOTOROLA]

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