MPC755BPX400TD [MOTOROLA]
32-BIT, 400MHz, RISC PROCESSOR, PBGA360, PLASTIC, BGA-360;
| 型号： | MPC755BPX400TD |
| 厂家： | 
MOTOROLA |
| 描述： | 32-BIT, 400MHz, RISC PROCESSOR, PBGA360, PLASTIC, BGA-360 |
| 文件： | 总2页 (文件大小：511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC755FACT/D
REV. 0
F a c t S h e e t
MO T O R O L A MPC755 A N D MPC745
™
PO W E R PC MI C R O P R O C E S S O R S
MPC755 and MPC745 PowerPC microprocessors are high-performance, low-power, 32-bit implementations of
the PowerPC Reduced Instruction Set Computer (RISC) architecture, specially enhanced for embedded applications.
MPC755 and MPC745 microprocessors differ only in that the MPC755 features an enhanced, dedicated L2 cache
interface with on-chip L2 tags. The MPC755 is a drop-in replacement for the award winning PowerPC 750™
microprocessor and is footprint and user software code compatible with the MPC7400 microprocessor with AltiVec
™ technology. The MPC745 is a drop-in replacement for the PowerPC 740™ microprocessor and is also footprint
and user software code compatible with the PowerPC 603e™
microprocessor. MPC755/745 microprocessors provide on-chip
debug support and are fully JTAG-compliant.
Motorola MPC755
PowerPC Microprocessor
Superscalar Microprocessor
MPC755 and MPC745 microprocessors are superscalar, capable
of issuing three instructions per clock cycle (two instructions
+ branch) into six independent execution units:
ꢀ
Two integer units
ꢀ
Load/store unit
ꢀ
Double-precision floating-point unit
ꢀ
System register unit
ꢀ
Branch processing unit
The ability to execute multiple instructions in parallel, to
MPC755/745 Microprocessor
Block Diagram
pipeline instructions, and the use of simple instructions
with rapid execution times yields maximum efficiency and
throughput for MPC755 and MPC745 systems.
Completion
Unit
Branch
Unit
Dispatch
Unit
Power Management
The MPC755 and MPC745 microprocessors feature a
low-power 2.0-volt design with three power-saving user-
programmable modes — doze, nap and sleep — which
progressively reduce the power drawn by the processor.
Load/
Store
Unit
Floating
Point
Unit
Gen
Reg
File
FPU
Reg
File
D MMU
I MMU
Data Cache
Inst. Cache
These low-power microprocessors offer dynamic power
management to selectively activate functional units as they
are needed by the executing instructions. Both
microprocessors also provide a thermal assist unit and
instruction cache throttling for software-controllable
thermal management.
Bus Interface Unit
L2 Tags
L2 Cache
Port (755 only)
32b Address
32b/64b Data
System Bus
FSRAM
Cache and MMU Support
The MPC755/745 microprocessors have separate 32-Kbyte, physically-addressed instruction and data caches.
Both caches can be locked in part or whole to provide storage of critical data, key performance algorithms, or
code loops for fast response time. The MPC755 microprocessor’s dedicated L2 cache interface with on-chip L2
tags (up to 1MB) features support for direct-mapped SRAM mode, physically-mapped SRAM mode, a fast
(typically 1/2 core speed) interface to memory, instruction-only or data-only modes, and parity checking on both
L2 address and data.
MPC755/745 microprocessors contain separate memory management units (MMUs) for instructions and data,
52
32
supporting 4 Petabytes (2 ) of virtual memory and 4 Gigabytes (2 ) of physical memory. Both feature eight
instruction block address translation (iBAT) and eight data block address translation (dBAT) registers. Access
privileges and memory protection are controlled on block or page granularities. Large, 128-entry translation
lookaside buffers (TLBs) provide efficient physical address translation and support for virtual-memory
management on both page- and variable-sized blocks. Both hardware and software tablewalks are provided for
the TLBs.
PowerPC 755/745 CPU Summary
Flexible Bus Interface
PowerPC 745
PowerPC 755
300-350 MHz
300-400 MHz
MPC755/745 microprocessors have a
64-bit data bus with 32-bit mode and a
32-bit address bus. Support is included
for burst, split and pipelined
transactions. The interface provides
snooping for data cache coherency.
Both microprocessors maintain MEI
coherency protocol in hardware,
allowing access to system memory for
additional caching bus masters, such as
DMA devices.
300 and 350 MHz
300, 350 and 400 MHz
CPU Speeds – Internal
x3, x3.5, x4, x4.5, x5, x5.5,
x6, x6.5, x7, x7.5, x8, x10
x3, x3.5, x4, x4.5, x5, x5.5,
x6, x6.5, x7, x7.5, x8, x10
CPU Bus Dividers
Bus Interface
32-bit/64-bit
32-bit/64-bit
3 (2 + Branch)
3 (2 + Branch)
Instructions per Clock
32 Kbyte instruction
32 Kbyte data
32-Kbyte instruction
32-Kbyte data
L1 Cache
256, 512 Kbyte
1 Mbyte
—
L2 Cache
Core-to-L2 Frequency
—
1:1,1.5:1, 2:1, 2.5:1, 3:1
TBD
Typical/Maximum
Power Dissipation
TBD
2
2
51 mm
51 mm
Die Size
Package
255 PBGA
0.22µ 5LM
360 PBGA
0.22µ 5LM
Process
1.8/3.3V i/o, 2.0V internal
15.7 @ 350 MHz
11.6 @ 350 MHz
1.8/3.3V i/o, 2.0V internal
18.1 @ 400 MHz
Voltage
Contact Information
SPECint95 (estimated)
SPECfp95 (estimated)
Other Performance
12.3 @ 400 MHz
733 MIPS @ 400 MHz
Motorola offers user’s manuals,
application notes and sample code
for all of its processors. In addition,
local support for these products is
also provided. This information can
be found at:
641 MIPS @ 350 MHz
Integer(2), Floating-Point, Branch,
Load/Store, System Register
Integer(2), Floating-Point, Branch,
Load/Store, System Register
Execution Units
PowerPC 1xx, 6xx and 7xx Part Number Key
http://motorola.com/PowerPC/
XPC
755
B
PX
400
L
D
Frequency
Revision
100, 600, or 700
Series Device Number
(106,107, 603, 740, 745,
750, 755)
2-3 digits
For all other inquiries about Motorola
products, please contact the Motorola
Customer Response Center at:
Package
FE CQFP
Application Modifier
RX CBGA w/o lid
PX PBGA w/o lid
ZT PBGA w/ lid
Bus Ratio
Product Code
PPC Sample
C
D
L
2:1 (106 only)
5:2 (106 only)
Full spec all modes
-or-
XPC XC qualified
MPC Qualified
Part/Module Modifier
A
B
E
P
R
Alpha (original)
DGO process
Application Relief
Phone: 800-521-6274 or
http://motorola.com/semiconductors
603 Enhanced Performance
Enhanced & Lower Voltage
603e in HiP3 process
R
T
105°
ext. temp. (-40° to 105°)
©2000 Motorola, Inc. All rights reserved. Printed in the U.S.A. Motorola and the
are registered trademarks and AltiVec is a trademark of of Motorola, Inc. PowerPC, the PowerPC logo, PowerPC 603e, PowerPC 740 and PowerPC 750 are
trademarks of International Business Machines Corporation, used under license therefrom. This document contains information on a new product under development. Specifications and information herein are subject to change without notice.
1ATX45747-0 Printed in USA 5/00 Hibbert LITRISC-UCCJ
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