MPC93R51FA [MOTOROLA]

PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC, LQFP-32;


型号：	MPC93R51FA
厂家：	MOTOROLA
描述：	PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC, LQFP-32 驱动输出元件逻辑集成电路
文件：	总9页 (文件大小：155K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC93R51/D

Rev 1, 05/2003

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The MPC93R51 is a 3.3V compatible, PLL based clock generator tar-

geted for high performance clock distribution systems. With output fre-

quencies of up to 240 MHz and a maximum output skew of 150 ps the

MPC93R51 is an ideal solution for the most demanding clock tree de-

signs. The device offers 9 low skew clock outputs, each is configurable to

support the clocking needs of the various high-performance microproces-

sors including the PowerQuicc II integrated communication microproces-

sor. The devices employs a fully differential PLL design to minimize cycle-

to-cycle and long-term jitter.

LOW VOLTAGE 3.3V

PLL CLOCK GENERATOR

Features

• 9 outputs LVCMOS PLL clock generator

• 25 - 240 MHz output frequency range

• Fully integrated PLL

• Compatible to various microprocessors such as PowerQuicc II

• Supports networking, telecommunications and computer applications

• Configurable outputs: divide-by-2, 4 and 8 of VCO frequency

• LVPECL and LVCMOS compatible inputs

• External feedback enables zero-delay configurations

• Output enable/disable and static test mode (PLL enable/disable)

• Low skew characteristics: maximum 150 ps output-to-output

• Cycle-to-cycle jitter max. 22 ps RMS

FA SUFFIX

LQFP PACKAGE

CASE 873A

• 32 lead LQFP package

• Ambient Temperature Range 0°C to +70°C

• Pin & Function Compatible with the MPC951

Functional Description

The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal

operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback

path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be

selected to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8 the internal VCO of the

MPC93R51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is

either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the

FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and

1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input (TCLK).

The MPC93R51 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the

selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system

diagnostics, test and debug purpose. This test mode is fully static and the minimum clock frequency specification does not apply.

The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes the PLL to loose

lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase locked loop, also

enabling the PLL to recover to normal operation. The MPC93R51 is 3.3V compatible and requires no external loop filter compo-

nents. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the

capability to drive terminated 50 W transmission lines. For series terminated transmission lines, each of the MPC93R51 outputs

can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm²32-lead LQFP

package.

Application Information

The fully integrated PLL of the MPC93R51 allows the low skew outputs to lock onto a clock input and distribute it with

essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase

offset between the outputs and the reference signal.

130

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

MPC93R51

(pullup)

PCLK

÷2

÷4

÷8

PLL

Ref

(pulldown)

TCLK

(pulldown)

REF_SEL

EXT_FB

200 - 480 MHz

(pullup)

PLL_EN

QC0

QC1

(pulldown)

FSELA

FSELB

QD0

FSELC

FSELD

(pulldown)

QD1

QD2

QD3

QD4

(pulldown)

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Figure 1. MPC93R51 Logic Diagram

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MPC93R51

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Figure 2. Pinout: 32–Lead LQFP Package Pinout (Top View)

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

131

MPC93R51

PIN CONFIGURATION

I/O

Type

LVPECL

Function

PCLK, PCLK

Input

Differential clock reference

Low voltage positive ECL input

TCLK

Input

LVCMOS

Single ended reference clock signal or test clock

Feedback signal input, connect to a QA, QB, QC, QD output

Selects input reference clock

EXT_FB

REF_SEL

FSELA

FSELB

FSELC

FSELD

Output A divider selection

Output B divider selection

Outputs C divider selection

Outputs D divider selection

Input

LVCMOS

VCC

Output enable/disable

Output

Supply

Bank A clock output

Bank B clock output

QC0, QC1

QD0 - QD4

VCCA

VCC

Bank C clock outputs

Bank D clock outputs

Positive power supply for the PLL

Positive power supply for I/O and core

Negative power supply

VCC

GND

Ground

FUNCTION TABLE

Control

Default

REF_SEL

Selects PCLK as reference clock

Selects TCLK as reference clock

PLL_EN

Test mode with PLL disabled. The input clock is

directly routed to the output dividers

PLL enabled. The VCO output is routed to the

output dividers

Outputs enabled

Outputs disabled, PLL loop is open

VCO is forced to its minimum frequency

FSELA

FSELB

FSELC

FSELD

QA = VCO ÷ 2

QB = VCO ÷ 4

QC = VCO ÷ 4

QD = VCO ÷ 4

QA = VCO ÷ 4

QB = VCO ÷ 8

QC = VCO ÷ 8

QD = VCO ÷ 8

ABSOLUTE MAXIMUM RATINGS^a

Symbol

Characteristics

Min

-0.3

Max

Unit

Condition

Supply Voltage

3.9

DC Input Voltage

DC Output Voltage

DC Input Current

DC Output Current

Storage Temperature

+0.3

OUT

+0.3

°C

OUT

-55

150

a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions

or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not

implied.

GENERAL SPECIFICATIONS

Symbol

Characteristics

Output Termination Voltage

ESD (Machine Model)

ESD (Human Body Model)

Latch–Up

Min

Typ

V B 2

Max

Unit

Condition

HBM

200

2000

200

Power Dissipation Capacitance

Per output

Inputs

4.0

132

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

MPC93R51

DC CHARACTERISTICS (V_CC= 3.3V 5%, T_A= 0° to 70°C)

Sym-

bol

Characteristics

Min

Typ

Max

+ 0.3

Unit

Condition

Input High Voltage

2.0

LVCMOS

Input Low Voltage

0.8

LVCMOS

LVPECL

Peak-to-Peak Input Voltage

PCLK, PCLK

250

CMR

Common Mode Range

Output High Voltage

Output Low Voltage

1.0

2.4

-0.6

=-24 mA

0.55

0.30

= 24 mA

= 12 mA

OUT

Output Impedance

14 - 17

Input Leakage Current

Maximum PLL Supply Current

200

5.0

µA

= V or GND

3.0

7.0

CCA

CCQ

Maximum Quiescent Supply Current

All V Pins

a. V

(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V

range

CMR

and the input swing lies within the V (DC) specification.

b. The MPC93R51 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated trans-

mission line to a termination voltage of V . Alternatively, the device drives up to two 50Ω series terminated transmission lines.

AC CHARACTERISTICS (V_CC= 3.3V 5%, T_A= 0° to 70°C)^a

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

ref

Input Frequency

÷ 4 feedback

÷ 8 feedback

Static test mode

120

300

MHz

PLL_EN = 1

PLL_EN = 0

VCO Frequency

200

480

MHz

VCO

Maximum Output Frequency

÷ 2 output

÷ 4 output

÷ 8 output

100

240

120

MHz

MAX

Reference Input Duty Cycle

500

1.2

refDC

Peak-to-Peak Input Voltage PCLK, PCLK

1000

LVPECL

Common Mode Range

PCLK, PCLK

-0.9

LVPECL

CMR

tr, tf

TCLK Input Rise/Fall Time

1.0

0.8 to 2.0V

∅

(

Propagation Delay (static phase offset)

TCLK to EXT_FB

)

–50

+25

+150

+325

PLL locked

PCLK to EXT_FB

Output-to-Output Skew

150

sk(o)

Output Duty Cycle

100 – 240 MHz

50 – 120 MHz

25 – 60 MHz

47.5

48.75

52.5

51.75

t , t

Output Rise/Fall Time

Output Disable Time

Output Enable Time

0.1

1.0

0.55 to 2.4V

7.0

PLZ, HZ

6.0

PZL, ZH

PLL closed loop bandwidth ÷ 4 feedback

÷ 8 feedback

3.0 – 9.5

1.2 – 2.1

MHz

–3 db point of

PLL transfer

characteristic

Cycle-to-cycle jitter

Single Output Frequency Configuration

÷ 4 feedback

8.0

RMS value

JIT(CC)

Period Jitter

Single Output Frequency Configuration

÷ 4 feedback

JIT(PER)

I/O Phase Jitter

4.0 – 17

∅

JIT(

)

Maximum PLL Lock Time

1.0

LOCK

a. AC characteristics apply for parallel output termination of 50Ω to V

b. The PLL will be unstable with a divide by 2 feedback ratio.

c. V

(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V

range

CMR

and the input swing lies within the V (AC) specification. Violation of V

or V impacts static phase offset t

∅

)

CMR

(

d. The MPC93R51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t , can only be guaranteed if tr/tf

∅

(

)

are within the specified range.

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

133

MPC93R51

APPLICATIONS INFORMATION

Programming the MPC93R51

the various output configurations, the table describes the out-

puts using the input clock frequency CLK as a reference.

The MPC93R51 clock driver outputs can be configured into

several divider modes, in addition the external feedback of the

device allows for flexibility in establishing various input to out-

put frequency relationships. The output divider of the four out-

put groups allows the user to configure the outputs into 1:1,

2:1, 4:1 and 4:2:1 frequency ratios. The use of even dividers

ensure that the output duty cycle is always 50%. “Output Fre-

The output division settings establish the output relation-

ship, in addition, it must be ensured that the VCO will be stable

given the frequency of the outputs desired. The feedback fre-

quency should be used to situate the VCO into a frequency

range in which the PLL will be stable. The design of the PLL

supports output frequencies from 25 MHz to 240 MHz while the

VCO frequency range is specified from 200 MHz to 480 MHz

quency Relationship for an Example Configuration” illustrates and should not be exceeded for stable operation.

Output Frequency Relationship^afor an Example Configuration

Inputs

Outputs

FSELA

FSELB

FSELC

FSELD

CLK

2 * CLK

4 * CLK

2 * CLK

4 * CLK

CLK

CLK ÷ 2

2* CLK

CLK

2 * CLK

CLK ÷ 2

CLK

CLK ÷ 2

2 * CLK

CLK

CLK ÷ 2

2 * CLK

CLK

2 * CLK

CLK

2 * CLK

CLK ÷ 2

CLK

CLK ÷ 2

2 * CLK

CLK

2 * CLK

CLK

a. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB.

Using the MPC93R51 in zero–delay applications

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Nested clock trees are typical applications for the

MPC93R51. For these applications the MPC93R51 offers a

differential LVPECL clock input pair as a PLL reference. This

allows for the use of differential LVPECL primary clock distribu-

tion devices such as the Motorola MC100EP111 or

MC10EP222, taking advantage of its superior low-skew perfor-

mance. Clock trees using LVPECL for clock distribution and

the MPC93R51 as LVCMOS PLL fanout buffer with zero inser-

tion delay will show significantly lower clock skew than clock

distributions developed from CMOS fanout buffers.

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The external feedback option of the MPC93R51 PLL allows

for its use as a zero delay buffer. The PLL aligns the feedback

clock output edge with the clock input reference edge and

virtually eliminates the propagation delay through the device.

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MPC93R51 zero–delay configuration (feedback of QD4)

The remaining insertion delay (skew error) of the

MPC93R51 in zero-delay applications is measured between

the reference clock input and any output. This effective delay

Calculation of part-to-part skew

The MPC93R51 zero delay buffer supports applications

consists of the static phase offset (SPO or t₍∅₎), I/O jitter where critical clock signal timing can be maintained across

(t_JIT(_∅, phase or long-term jitter), feedback path delay and the several devices. If the reference clock inputs (TCLK or PCLK)

)

output-to-output skew (t_SK(O)relative to the feedback output. of two or more MPC93R51 are connected together, the maxi-

134

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

MPC93R51

mum overall timing uncertainty from the common TCLK input

to any output is:

Above equation uses the maximum I/O jitter number shown

in the AC characteristic table for V_CC=3.3V (17 ps RMS). I/O

jitter is frequency dependant with a maximum at the lowest

VCO frequency (200 MHz for the MPC93R51). Applications

using a higher VCO frequency exhibit less I/O jitter than the AC

characteristic limit. The I/O jitter characteristics in Figure 4 can

be used to derive a smaller I/O jitter number at the specific

VCO frequency, resulting in tighter timing limits in zero-delay

t_SK(PP)= t _∅+ t_SK(O)+ t_{PD, LINE(FB)}+ t_JIT(ꢀ CF

∅

)

(

)

This maximum timing uncertainty consist of 4 components:

static phase offset, output skew, feedback board trace delay

and I/O (phase) jitter:

mode and for part-to-part skew t_SK(PP)

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Figure 4. Max. I/O Jitter (RMS) versus frequency for

_CC=3.3V

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Power Supply Filtering

Figure 3. MPC93R51 max. device-to-device skew

The MPC93R51 is a mixed analog/digital product. Its analog

circuitry is naturally susceptible to random noise, especially if

this noise is seen on the power supply pins. Noise on the V_CCA

(PLL) power supply impacts the device characteristics, for

instance I/O jitter. The MPC93R51 provides separate power

supplies for the output buffers (V_CC) and the phase-locked

loop (V_CCA) of the device.The purpose of this design technique

is to isolate the high switching noise digital outputs from the

relatively sensitive internal analog phase-locked loop. In a digi-

tal system environment where it is more difficult to minimize

noise on the power supplies a second level of isolation may be

required. The simple but effective form of isolation is a power

supply filter on the V_CCApin for the MPC93R51.

Due to the statistical nature of I/O jitter a RMS value (1 s) is

specified. I/O jitter numbers for other confidence factors (CF)

can be derived from Table 8.

Table 8: Confidence Facter CF

Probability of clock edge within the distribution

0.68268948

0.95449988

0.99730007

0.99993663

0.99999943

0.99999999

Figure 5 illustrates a typical power supply filter scheme. The

MPC93R51 frequency and phase stability is most susceptible

to noise with spectral content in the 100kHz to 20MHz range.

Therefore the filter should be designed to target this range.

The key parameter that needs to be met in the final filter design

is the DC voltage drop across the series filter resistor R_F. From

the data sheet the I_CCAcurrent (the current sourced through

the V_CCApin) is typically 3 mA (5 mA maximum), assuming

that a minimum of 3.0V must be maintained on the V_CCApin.

The resistor R_Fshown in Figure 5 “V_CCAPower Supply Filter”

must have a resistance of 5–15W to meet the voltage drop

criteria.

The feedback trace delay is determined by the board layout

and can be used to fine-tune the effective delay through each

device. In the following example calculation a I/O jitter confi-

dence factor of 99.7% ( 3s) is assumed, resulting in a worst

case timing uncertainty from input to any output of -251 ps to

351 ps relative to TCLK (V_CC=3.3V and f_VCO= 400 MHz):

t_SK(PP)

[–50ps...150ps] + [–150ps...150ps] +

[(17ps @ –3)...(17ps @ 3)] + t_{PD, LINE(FB)}

[–251ps...351ps] + t_{PD, LINE(FB)}

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

135

MPC93R51

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Figure 5. V_CCAPower Supply Filter

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Ω

As the noise frequency crosses the series resonant point of

an individual capacitor its overall impedance begins to look

inductive and thus increases with increasing frequency. The

parallel capacitor combination shown ensures that a low im-

pedance path to ground exists for frequencies well above the

bandwidth of the PLL. Although the MPC93R51 has several

design features to minimize the susceptibility to power supply

noise (isolated power and grounds and fully differential PLL)

there still may be applications in which overall performance is

being degraded due to system power supply noise. The power

supply filter schemes discussed in this section should be ade-

quate to eliminate power supply noise related problems in

most designs.

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Figure 6. Single versus Dual Transmission Lines

The waveform plots in Figure 7 “Single versus Dual Line

Termination Waveforms” show the simulation results of an out-

put driving a single line versus two lines. In both cases the

drive capability of the MPC93R51 output buffer is more than

sufficient to drive 50Ω transmission lines on the incident edge.

Note from the delay measurements in the simulations a delta

of only 43ps exists between the two differently loaded outputs.

This suggests that the dual line driving need not be used exclu-

sively to maintain the tight output-to-output skew of the

MPC93R51. The output waveform in Figure 7 “Single versus

Dual Line Termination Waveforms” shows a step in the wave-

form, this step is caused by the impedance mismatch seen

looking into the driver. The parallel combination of the 36Ω se-

ries resistor plus the output impedance does not match the

parallel combination of the line impedances. The voltage wave

launched down the two lines will equal:

Driving Transmission Lines

The MPC93R51 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output drivers

were designed to exhibit the lowest impedance possible. With

an output impedance of less than 20Ω the drivers can drive

either parallel or series terminated transmission lines. For

more information on transmission lines the reader is referred to

Motorola application note AN1091. In most high performance

clock networks point-to-point distribution of signals is the meth-

od of choice. In a point-to-point scheme either series termi-

nated or parallel terminated transmission lines can be used.

The parallel technique terminates the signal at the end of the

line with a 50Ω resistance to V_CC÷2.

V_L= V_S( Z₀÷ (R_S+R₀+Z₀))

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each output

of the MPC93R51 clock driver. For the series terminated case

however there is no DC current draw, thus the outputs can

drive multiple series terminated lines. Figure 6 “Single versus

Dual Transmission Lines” illustrates an output driving a single

series terminated line versus two series terminated lines in

Z₀= 50Ω || 50Ω

R_S= 36Ω || 36Ω

R₀= 14Ω

V_L= 3.0 ( 25 ÷ (18+17+25)

= 1.31V

At the load end the voltage will double, due to the near unity

parallel. When taken to its extreme the fanout of the reflection coefficient, to 2.6V. It will then increment towards the

MPC93R51 clock driver is effectively doubled due to its capa- quiescent 3.0V in steps separated by one round trip delay (in

bility to drive multiple lines.

this case 4.0ns).

136

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

MPC93R51

ꢐ

ꢏ

ꢓ

ꢒ

ꢰ ꢒ

ꢰ ꢗ

ꢰ ꢒ

ꢰ ꢗ

ꢰ ꢒ

ꢰ ꢗ

ꢒ

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the situation

in Figure 8 “Optimized Dual Line Termination” should be used.

In this case the series terminating resistors are reduced such

that when the parallel combination is added to the output buffer

impedance the line impedance is perfectly matched.

ꢇ ꢢꢨ ꢈ

ꢳ ꢐ ꢰꢚ ꢛꢗ ꢘ

ꢇ ꢢꢨ ꢄ

ꢳ ꢐꢰ ꢛꢐ ꢚꢘ

ꢨ

ꢂ

ꢨ

ꢂ

ꢻ

ꢦ

ꢟꢌ ꢆꢛ ꢐ ꢜꢗ ꢓ

ꢇ ꣁꢉꢌ ꣁꢉ

ꢄ ꣁꢕꢕꢎ ꢜ

ꣂ

ꢳ

ꢗ

ꢒΩ

ꢇ

ꢜ

ꢳ

ꢏ

ꢏΩ

ꢖ

ꢓꢑΩ

ꢜ

14Ω + 22Ω ꢁ 22Ω = 50Ω ꢁ 50Ω

25Ω = 25Ω

ꢏ

ꢑ

ꢘ

ꢚ

ꢓ

ꢒ

ꢓ

ꢏ

ꢓ

ꢑ

ꢉꢻ ꢟ ꢎ ꢶꢦ ꢖꢹ

Figure 8. Optimized Dual Line Termination

Figure 7. Single versus Dual Waveforms

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

ꢟ

ꢌ ꢆꢛ ꢐ ꢜꢗ ꢓ ꢂꣁ ꢉ

ꢌ ꢢꢩꢤꢞ

ꢀ ꢞꢦꢞ ꢠꢥ ꢨꢫꢠ

ꣂ

ꢳ

ꢗ

ꢒ

Ω

ꣂ ꢳ ꢗ ꢒΩ

ꢇ

ꣂ

ꢳ

ꢗ

ꢒ

ꢜ

ꢉ

ꢳ

ꢗ

ꢒΩ

ꢜ ꢳ ꢗ ꢒΩ

ꢉ

ꢅ

ꢉ

ꢅ

ꢉ ꢉ

ꢉ

Figure 9. TCLK MPC93R51 AC test reference for V_cc= 3.3V

ꢟ

ꢌ

ꢆ

ꢛ

ꢐ

ꢜ

ꢗ

ꢓ

ꢂ

ꣁ

ꢉ

ꣂ

ꢳ

ꢗ

ꢒ

Ω

ꢇ

ꢂꢣ ꢪꢪ ꢞꢠꢞ ꢦꢨ ꢣꢥꢩ

ꢌ ꢢꢩꢤꢞ ꢀ ꢞꢦꢞ ꢠꢥ ꢨꢫꢠ

ꣂ

ꢳ

ꢗ

ꢒ

Ω

ꢇ

ꣂ ꢳ ꢗꢒ W

ꢜ

ꢉ

ꢳ ꢗ ꢒΩ

ꢜ

ꢉ

ꢳ ꢗ ꢒΩ

ꢅ

ꢉ

ꢅ

ꢉ

Figure 10. PCLK MPC93R51 AC test reference

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

137

MPC93R51

ꢅ

ꢌ

ꢆ

ꢊ

ꢋ

ꢆ

ꢉ

ꢆ

ꢊ

ꢋ

ꢏ

ꢆ

ꢅ

ꢆ

ꢟ

ꢜ

ꢅ

ꢆ ꢟ ꢜ

ꢀ

ꢁ

ꢂ

ꢅ

ꢆ

ꢏ

ꢎ ꢧꢨ ꢍꢕꢄ

ꢆ

ꢎ

ꢧꢨ ꢍꢕ ꢄ

ꢀ

ꢁ

ꢂ

ꢀ ꢁꢂ

ꢨ

∅

ꢶ

ꢹ

ꢨ

∅

ꢶ

ꢹ

Figure 11. Propagation delay (t_PD, static phase

offset) test reference

Figure 12. Propagation delay (t_PD) test reference

ꢅ

ꢆ

ꢅ

ꢆ

Bꢏ

ꢆ

ꢏ

ꢆ

ꢀ ꢁꢂ

ꢀ

ꢁ

ꢂ

ꢨ

ꢌ

ꢅ

ꢆ

ꢉ

ꢒ

ꢀ ꢁꢂ

ꢀꢁ ꢂ ꢃ ꢅ ꢆ ꢧ ꢈꢇ ꢇꢉ

ꢄ

ꢇ

ꢨ

ꢖ

ꢋ

ꢶ

ꢇ

ꢹ

ꢉ

ꢝ

ꢬ

ꢭ

ꢞ

ꢠ

ꢨ

ꢺ

ꢞ

ꢣ

ꢿ

ꢲ

ꢞ

ꢪ

ꢠ

ꢫ

ꢞ

ꢥ

ꢿ

ꢲ

ꢤ

ꢨ

ꢷ

ꢥ

ꢝ

ꢯ

ꢭ

ꢞ

ꢨ

ꢞ

ꢌ

ꢊ

ꢨ

ꢞ

ꢊ

ꢱ

ꢞ

ꢫ

ꢦ

ꢷ

ꢞ

ꢨ

ꢞ

ꢠ

ꢫ

ꢩ

ꢞ

ꢲ

ꢞ

ꢦ

ꢲ

ꢌ

ꢬ

ꢊ

ꢞ

ꢊ

ꢨ

ꢱ

ꢫ

ꢨ

ꢦ

ꢝ

ꢨ

ꢞ

ꢦ

ꢫ

ꢞ

ꢦ

ꢲ

ꢱ

ꢞ

ꢫ

ꢲ

ꢦ

ꢬ

ꢨ

ꢞ

ꢠ

ꢫ

ꢤ

ꢩ

ꢺ

ꢩ

ꢞ

ꢲ

ꢉ

ꢝ

ꢫ

ꢞ

ꢭ

ꢥ

ꢣ

ꢬ

ꢦ

ꢥ

꣄

ꢨ

ꢣ

ꢫ

꣄

ꢦ

ꢭ

ꢲ

ꢣ

ꢦ

ꢞ

ꢤ

ꢸ

ꢯ

ꢞ

ꢷ

ꢮ

ꢞ

ꢣ

ꢤ

ꢲ

ꢞ

ꢦ

ꢪ

ꢣ

ꢦ

ꢥ

ꢞ

ꢦ

ꢲ

ꢯ

ꢥ

ꢤ

ꢨ

ꢝ

ꢞ

ꢥ

ꢮ

ꢫ

ꢞ

ꢠ

ꢩ

ꢤ

ꢥ

ꢨ

ꢯ

ꢱ

ꢭ

ꢥ

ꢤ

ꢨ

ꢞ

ꢝ

ꢲ

ꢮ

ꢣ

ꢪ

ꢣ

ꢪ

ꢨ

ꢞ

ꢝ

ꢠ

ꢞ

ꢦ

ꢥ

ꢱ

ꢞ

ꢣ

ꢦ

ꢞ

ꢲ

ꢣ

ꣀ

ꢣ

ꢲ

ꢝ

ꢞ

ꢣ

ꢿ

ꢨꢮ

ꢠ

ꢫ

ꢩ

ꢭ

ꢠ

ꢩ

ꢥ

ꢨ

ꢮ

ꢞ

ꢣ

ꢿ

ꢣ

ꢩ

ꢠ

ꢲ

ꢣ

ꢦ

ꢞ

ꢧ

ꢤ

ꢞ

ꢲ

ꢠ

ꢱ

ꢦ

ꢨ

ꢥ

ꢬ

ꢤꢣꢦ ꢬꢩꢞ ꢲ ꢞꣀꢣꢱꢞ

Figure 13. Output Duty Cycle (DC)

Figure 14. Output–to–output Skew t_SK(O)

ꢆ

ꢂ

꣆ꢆ ꢏ ꢆ

꣆

ꢆ

ꢊ ꢋ ꢆ ꢌ ꢄ ꢍ

ꢂ

꣆ꢆ ꢏ ꢈ ꣇ꢑ

꣆

ꢊ ꢋ ꢆ ꢌ ꢁ ꢁ ꢍ

ꢎ

ꢎ ꢐ ꢈ

ꢎ

ꢇ

ꢉ

ꢁ ꢽ ꢓ

ꢉ

ꢁ

ꢒ

ꢉ

ꢝ

ꢦ

ꢞ

ꢲ

ꣀ

ꢫ

ꢥ

ꢿ

ꢠ

ꢣ

ꢥ

ꢤ

ꢨ

ꢥ

ꢣ

ꢫ

ꢿ

ꢦ

ꢭ

ꢣ

ꢩ

ꢦ

ꢞ

ꢱ

ꢫ

ꢯ

ꢪ

ꢱ

ꢥ

ꢩ

ꢲ

ꢞ

ꣅ

ꢨ

ꢥ

ꢣ

ꢿ

ꢞ

ꢦ

ꢫ

ꢪ

ꢥ

ꢤ

ꢣ

ꢬ

ꢭ

ꢦ

ꢥ

ꢣ

ꢩ

ꢠ

ꢷ

ꢤ

ꢞ

ꢨ

ꢮ

ꢞ

ꢦ

ꢥ

ꢲ

ꣅ

ꢥ

ꢱ

ꢞ

ꢦ

ꢨ

ꢱ

ꢯ

ꢱ

ꢩ

ꢞ

ꢤ

ꢺ

ꢫ

ꣀ

ꢞ

ꢠ

ꢥ

ꢉ

ꢥ

ꢝ

ꢠ

ꢞ

ꢥ

ꢲ

ꢞ

ꢫ

ꣀ

ꢿ

ꢣ

ꢥ

ꢨ

ꢤ

ꢣ

ꢫ

ꢥ

ꢦ

ꢿ

ꢣ

ꢭ

ꢦ

ꢩ

ꢱ

ꢞ

ꢯ

ꢫ

ꢱ

ꢪ

ꢩ

ꢞ

ꢱ

ꢨ

ꢣ

ꢿ

ꢞ

ꢤ

ꢫ

ꢪ

ꢥ

ꢤ

ꢣ

ꢬ

ꢦꢥ

ꢩ

ꢮ

ꢣ

ꢨ

ꢝ

ꢠ

ꢞ

ꢤ

ꢭ

ꢞꢱ

ꢨ

ꢫ

ꢨ

ꢝꢞ

ꢣ

ꢲ

ꢞ

ꢥ

ꢩ

ꢭ

ꢞꢠ

ꢣ

ꢫ

ꢲ

ꢫ

ꣀꢞ

ꢠ

ꢥ

ꢱ

ꢞ

ꢨ

ꢱ

ꢯ

ꢱ

ꢩ

ꢞ

ꢦ

ꢲ

ꢯ

ꢱ

ꢩ

ꢞ

Figure 15. Cycle–to–cycle Jitter

Figure 16. Period Jitter

ꢉ ꢆ ꢊꢋ

ꢶ ꢌꢆ ꢊꢋꢹ

ꢅ

ꢆ

ꢳ ꢐ ꢰꢐ ꢅ

ꢆ

ꢏ ꢰ ꢑ

ꢎꢧꢨ ꢍꢕ ꢄ

ꢒ

ꢰ

ꢗ

ꢆ

ꢊ ꢋ ꢆ ꢌ

ꢂ ꣆ꢆ ꢏ ꢆ ꢒ ꢓꢔꢕ꣆

ꢇ ꢈ

∅

ꢍ

ꢨ

ꢕ

ꢨ

ꢜ

ꢉ

ꢝ

ꢦ

ꢞ

ꢲ

ꢫ

ꢞ

ꢿ

ꣀ

ꢣ

ꢤ

ꢥ

ꢨ

ꢣ

ꢫ

ꢦ

ꢣ

ꢦ

ꢨ

ꢪ

ꢫ

ꢠ

ꢥ

ꢱ

ꢤ

ꢫ

ꢦ

ꢨꢠ

ꢫ

ꢩ

ꢞ

ꢲ

ꢞ

ꢲ

ꢬ

ꢞ

ꢮ

ꢣ

ꢨꢝ

ꢠ

ꢞ

ꢤ

ꢭ

ꢞ

ꢱ

ꢨ

ꢫ

ꢥ

ꢨ

ꢿ ꢞ

ꢒ

ꢥ

ꢦ

ꢣ

ꢦ

ꢥ

ꢒ

ꢠ

ꢥ

ꢿ

ꢭ

ꢩ

ꢞ

ꢫ

ꢪ

ꢱ

ꢯ

ꢱ

ꢩ

ꢞ

Figure 17. I/O Jitter

Figure 18. Transition Time Test Reference

138

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

MPC93R51FA [MOTOROLA]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E