MPC962305DT-1HR2 [MOTOROLA]
Low-Cost 3.3 V Zero Delay Buffer; 低成本3.3 V零延迟缓冲器型号: | MPC962305DT-1HR2 |
厂家: | MOTOROLA |
描述: | Low-Cost 3.3 V Zero Delay Buffer |
文件: | 总12页 (文件大小:447K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MOTOROLA
Order number: MPC962305
Rev 5, 08/2004
SEMICONDUCTOR TECHNICAL DATA
MPC962305
MPC962309
Low-Cost 3.3 V Zero Delay Buffer
The MPC962309 is a zero delay buffer designed to distribute high-speed
clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one
reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin
version of the MPC962309 which drives five outputs with one reference input.
The -1H versions of these devices have higher drive than the -1 devices and
can operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs
which lock to an input clock presented on the REF pin. The PLL feedback is
on-chip and is obtained from the CLOCKOUT pad.
D SUFFIX
8-LEAD SOIC PACKAGE
CASE 751-06
Features
•
•
•
•
•
•
•
1:5 LVCMOS zero-delay buffer (MPC962305)
1:9 LVCMOS zero-delay buffer (MPC962309)
Zero input-output propagation delay
Multiple low-skew outputs
DT SUFFIX
8-LEAD TSSOP PACKAGE
CASE 948J-01
250 ps max output-output skew
700 ps max device-device skew
Supports a clock I/O frequency range of 10 MHz to 133 MHz,
compatible with CPU and PCI bus frequencies
D SUFFIX
16-LEAD SOIC PACKAGE
CASE 751B-05
•
Low jitter, 200 ps max cycle-cycle, and compatible with Pentium® based
systems
•
•
Test Mode to bypass PLL (MPC962309 only. See “Select Input Decoding”)
8-pin SOIC or 8-pin TSSOP package (MPC962305);16-pin SOIC or 16-pin
TSSOP package (MPC962309)
•
•
•
•
Single 3.3 V supply
Ambient temperature range: –40°C to +85°C
Compatible with the CY2305, CY23S05, CY2309, CY23S09
Spread spectrum compatible
DT SUFFIX
16-LEAD TSSOP PACKAGE
CASE 948F-01
Functional Description
The MPC962309 has two banks of four outputs each, which can be con-
trolled by the Select Inputs as shown in Table 3.Select Input Decoding for
MPC962309. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied
to the outputs for chip and system testing purposes.
The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this
state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0 µA of current draw for the device. The PLL
shuts down in one additional case as shown in Table 3.Select Input Decoding for MPC962309.
Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this
situation, the difference between the output skews of two devices will be less than 700 ps.
All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to be
less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps.
The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information page.
The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and MPC962309-1H,
are available to provide faster rise and fall times of the base device.
For More Information On This Product,
© Motorola, Inc. 2004
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC962305 MPC962309
Block Diagram
Pin Configuration
SOIC/TSSOP
Top View
CLKOUT
PLL
REF
CLKOUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MUX
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
CLKA4
CLKA3
VDD
CLKA1
CLKA2
CLKA3
CLKA4
REF
GND
CLKB4
CLKB3
S1
CLKB1
CLKB2
CLKB3
CLKB4
SOIC/TSSOP
Top View
S2
S1
Select Input
Decoding
REF
CLKOUT
1
2
3
4
8
7
6
5
CLK2
CLK1
GND
CLK4
VDD
CLK3
Table 1. Pin Description for MPC962309
Pin
Signal
Description
REF1
1
Input reference frequency, 5 V-tolerant input
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3 V supply
CLKA12
2
3
4
CLKA22
VDD
5
6
GND
Ground
CLKB12
CLKB22
S23
Buffered clock output, Bank B
7
8
Buffered clock output, Bank B
Select input, bit 2
S13
9
Select input, bit 1
CLKB32
10
11
Buffered clock output, Bank B
Buffered clock output, Bank B
CLKB42
GND
12
13
Ground
VDD
3.3 V supply
CLKA32
CLKA42
CLKOUT2
14
15
16
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered output, internal feedback on this pin
Table 2. Pin Description for MPC962305
Pin
Signal
Description
REF1
1
Input reference frequency, 5 V-tolerant input
Buffered clock output
CLK22
2
3
CLK12
GND
Buffered clock output
4
5
Ground
CLK32
VDD
Buffered clock output
6
7
8
3.3 V supply
CLK42
Buffered clock output
CLKOUT2
Buffered clock output, internal feedback on this pin3
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
TIMING SOLUTIONS
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MPC962305 MPC962309
Table 3. Select Input Decoding for MPC962309
CLKOUT1
Driven
S2
0
S1
0
CLOCK A1–A4
Three-State
Driven
CLOCK B1–B4
Three-State
Three-State
Driven
Output Source
PLL
PLL Shutdown
N
N
Y
N
0
1
Driven
PLL
1
0
Driven
Driven
Reference
PLL
1
1
Driven
Driven
Driven
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference
and output.
Table 4. Maximum Ratings
Characteristics
Value
Unit
V
Supply Voltage to Ground Potential
DC Input Voltage (Except Ref)
−0.5 to +3.9
−0.5 to VDD+0.5
V
DC Input Voltage REF
Storage Temperature
Junction Temperature
−0.5 to 5.5
−65 to +150
150
V
°C
°C
V
Static Discharge Voltage (per MIL-STD-883, Method 3015)
>2000
Table 5. Operating Conditions for MPC962305-X and MPC962309-X Industrial Temperature Devices
Parameter
Description
Min
Max
Unit
VDD
Supply Voltage
3.0
3.6
V
TA
CL
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
−40
85
30
10
7
°C
pF
pF
pF
CL
CIN
Table 6. Electrical Characteristics for MPC962305-X and MPC962309-X Industrial Temperature Devices1
Parameter
Description
Input LOW Voltage2
Test Conditions
Min
Max
Unit
VIL
0.8
V
Input HIGH Voltage2
Input LOW Current
VIH
IIL
2.0
V
µA
µA
V
VIN = 0 V
VIN = VDD
50.0
100.0
0.4
IIH
Input HIGH Current
Output LOW Voltage3
VOL
IOL = 8 mA (−1)
IOH = 12 mA (−1H)
Output HIGH Voltage3
VOH
IOH = −8 mA (−1)
2.4
V
IOL = −12 mA (−1H)
I
DD (PD mode)
IDD
Power Down Supply Current
Supply Current
REF = 0 MHz
25.0
35.0
µA
Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
mA
1. All parameters are specified with loaded outputs.
2. REF input has a threshold voltage of VPP/2.
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
MOTOROLA
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MPC962305 MPC962309
Table 7. Switching Characteristics for MPC962305-1 and MPC962309-1 Industrial Temperature Devices1
Parameter
Name
Test Conditions
Min
Typ
Max
Unit
t1
Output Frequency
30-pF load
10-pF load
10
10
100
133.33
MHz
MHz
Duty Cycle2 = t2 ÷ t1
Measured at 1.4 V, FOUT = 66.67 MHz
40.0
50.0
60.0
%
Rise Time2
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
All outputs equally loaded
t3
t4
2.50
2.50
250
ns
ns
ps
ps
Fall Time2
Output to Output Skew2
t5
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge2
0
5
±350
Measured at VDD/2
t6B
Delay, REF Rising Edge to
CLKOUT Rising Edge2
Measured at VDD/2. Measured in PLL Bypass Mode,
MPC962309 device only
1
8.7
ns
ps
Device to Device Skew2
Measured at VDD/2 on the CLKOUT pins of devices
t7
0
700
Cycle to Cycle Jitter2
PLL Lock Time2
Measured at 66.67 MHz, loaded outputs
tJ
200
1.0
ps
tLOCK
ms
Stable power supply, valid clock presented on REF pin
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Table 8. Switching Characteristics for MPC962305-1H and MPC962309-1H Industrial Temperature Devices1
Parameter
Name
Test Conditions
Min
Typ
Max
Unit
t1
Output Frequency
30-pF load
10-pF load
10
10
100
133.33
MHz
MHz
Duty Cycle2 = t2 ÷ t1
Duty Cycle2 = t2 ÷ t1
Measured at 1.4 V, FOUT = 66.67 MHz
Measured at 1.4 V, FOUT < 50 MHz
40.0
45.0
50.0
55.0
60.0
55.0
%
%
Rise Time2
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
All outputs equally loaded
t3
t4
1.50
1.50
250
ns
ns
ps
ps
Fall Time2
Output to Output Skew2
t5
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge2
0
5
±350
Measured at VDD/2
t6B
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL Bypass Mode,
CLKOUT Rising Edge2
1
1
8.7
ns
ps
MPC962309 device only
Device to Device Skew2
Measured at VDD/2 on the CLKOUT pins of devices
t7
0
700
Output Slew Rate2
Cycle to Cycle Jitter2
PLL Lock Time2
Measured between 0.8 V and 2.0 V using Test Circuit #2
Measured at 66.67 MHz, loaded outputs
t8
tJ
V/ns
ps
200
1.0
tLOCK
ms
Stable power supply, valid clock presented on REF pin
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
TIMING SOLUTIONS
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MPC962305 MPC962309
APPLICATIONS INFORMATION
VCC
VCC
1.4 V
CCLK
GND
VCC ÷ 2
GND
VCC
VCC
1.4 V
VCC ÷ 2
FB_IN
GND
GND
t5
t6
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device
Figure 1. Output-to-Output Skew tSK(O)
Figure 2. Static Phase Offset Test Reference
VCC
VCC
1.4 V
DEVICE 1
DEVICE 2
VCC ÷ 2
GND
GND
t2
VCC
VCC ÷ 2
t1
DC = t2/t1 x 100%
GND
t7
The time from the PLL controlled edge to the non-controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
Figure 4. Device-to-Device Skew
Figure 3. Output Duty Cycle (DC)
VCC = 3.3 V
2.0
0.8
tJ = |tN–tN+1
|
tN
tN+1
t4
t3
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
Figure 5. Cycle-to-Cycle Jitter
Figure 6. Output Transition Time Test Reference
MOTOROLA
TIMING SOLUTIONS
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MPC962305 MPC962309
Test Circuit #1
Test Circuit #2
VDD
VDD
1 K Ω
0.1 µF
0.1 µF
0.1 µF
CLKOUT
OUTPUTS
GND
OUTPUTS
CLKOUT
CLOAD
1 K Ω
10 pF
VDD
GND
VDD
GND
GND
0.1 µF
Test Circuit for all parameters except t8
Test Circuit for t8, Output slew rate on –1H, –5 device
Table 9. Ordering Information
Ordering Code
Package Type
MPC962305D-1
8-pin 150-mil SOIC
MPC962305D-1R2
MPC962305D-1H
MPC962305D-1HR2
MPC962305DT-1H
MPC962305DT-1HR2
MPC962309D-1
8-pin 150-mil SOIC-Tape and Reel
8-pin 150-mil SOIC
8-pin 150-mil SOIC-Tape and Reel
8-pin 150-mil TSSOP
8-pin 150-mil TSSOP-Tape and Reel
16-pin 150-mil SOIC
MPC962309D-1R2
MPC962309D-1H
MPC962309D-1HR2
MPC962309DT-1H
MPC962309DT-1HR2
16-pin 150-mil SOIC-Tape and Reel
16-pin 150-mil SOIC
16-pin 150-mil SOIC-Tape and Reel
16-pin 4.4-mm TSSOP
16-pin 4.4-mm TSSOP-Tape and Reel
TIMING SOLUTIONS
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MPC962305 MPC962309
PACKAGE DIMENSIONS
D SUFFIX
8-LEAD SOIC PACKAGE
CASE 751-06
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
D
A
C
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
1
5
4
M
M
B
0.25
H
E
h
X 45˚
MILLIMETERS
θ
B
e
DIM
A
A1
B
C
D
E
e
H
h
MIN
1.35
0.10
0.35
0.19
4.80
3.80
MAX
1.75
0.25
0.49
0.25
5.00
4.00
A
C
SEATING
PLANE
L
1.27 BSC
0.10
5.80
0.25
0.40
0˚
6.20
0.50
1.25
7˚
A1
B
L
q
M
S
S
A
0.25
C
B
D SUFFIX
16-LEADSOIC PACKAGE
CASE 751B-05
ISSUE K
M
0.25
B
1.75
1.35
A
6.2
0.25
8X 5.8
PIN'S
NUMBER
0.10
0.49
0.35
16X
6
T A B
1
16
M
0.25
14X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
PIN 1 INDEX
1.27
10.0
9.8
2. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
3. DATUMS A AND B TO BE DETERMINED AT THE
4
A
A
PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
4. THIS DIMENSION DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURRS. MOLD
FLASH, PROTRUSION OR GATE BURRS SHALL
NOT EXCEED 0.15MM PER SIDE.THIS
8
9
DIMENSION IS DETERMINED AT THE PLANE
SEATING
PLANE
WHERE THE BOTTOM OF THE LEADS EXIT
T
4.0
THE PLASTIC BODY.
5. THIS DIMENSION DOES NOT INCLUDE
INTER-LEAD FLASH OR PROTRUSIONS.
INTER-LEAD FLASH AND PROTRUSIONS
16X
B
3.8
0.1 T
SHALL NOT EXCEED 0.25MM PER SIDE.THIS
DIMENSION IS DETERMINED AT THE PLANE
5
WHERE THE BOTTOM OF THE LEADS EXIT
THE PLASTIC BODY.
6. THIS DIMENSION DOES NOT INCLUDE
0.25
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL NOT CAUSE
0.50
0.25X45˚
THE LEAD WIDTH TO EXCEED 0.62MM.
0.19
1.25
0.40
7˚
0˚
SECTION A-A
MOTOROLA
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MPC962305 MPC962309
PACKAGE DIMENSIONS
DT SUFFIX
8-LEAD TSSOP PACKAGE
CASE 948J-01
ISSUE O
K 8x REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
0.10 (0.004)
T U
V
S
0.15 (0.006) T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25
(0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
8
5
2X L/2
J J1
B
-U-
L
PIN 1
IDENT.
SECTION N-N
4
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
N
0.25 (0.010)
S
0.15 (0.006) T
U
A
M
-V-
MILLIMETERS
INCHES
N
DIM MIN
MAX
3.10
4.50
1.20
0.15
0.75
MIN
MAX
0.122
0.177
0.047
0.006
0.030
A
B
C
D
F
2.90
4.30
---
0.114
0.169
---
F
0.05
0.50
0.002
0.020
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.50
0.09
0.09
0.19
0.19
0.60
0.20
0.16
0.30
0.25
0.020
0.004
0.004
0.007
0.007
0.024
0.008
0.006
0.012
0.010
-W-
C
0.10 (0.004)
G
SEE DETAIL E
SEATING
PLANE
6.40 BSC
0˚ 8˚
0.252 BSC
0˚ 8˚
_
-T-
D
M
_
_
_
H
TIMING SOLUTIONS
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MPC962305 MPC962309
PACKAGE DIMENSIONS
DT SUFFIX
16-LEAD TSSOP PACKAGE
CASE 948F-01
ISSUE O
K
16X REF
M
S
S
V
0.10 (0.004)
T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
0.15 (0.006) T U
K
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K1
16
9
2X L/2
J1
B
-U-
SECTION N-N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T U
A
M
-V-
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
4.90
4.30
---
MAX
5.10
4.50
1.20
0.15
0.75
MIN
MAX
0.200
0.177
0.047
0.006
0.030
N
0.193
0.169
---
F
0.05
0.50
0.002
0.020
DETAIL E
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
-W-
C
0.10 (0.004)
6.40 BSC
0.252 BSC
8˚
H
DETAIL E
M
0˚
8˚
0˚
SEATING
PLANE
-T-
D
G
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MPC962305 MPC962309
NOTES
TIMING SOLUTIONS
10
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MPC962305 MPC962309
NOTES
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provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license
under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product
could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their
respective owners.
© Motorola, Inc. 2004
HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution
P.O. Box 5405, Denver, Colorado 80217
1-800-521-6274 or 480-768-2130
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center
3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan
81-3-3440-3569
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre
2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong
852-26668334
HOME PAGE: http://motorola.com/semiconductors
MPC962305
For More Information On This Product,
Go to: www.freescale.com
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