MRFIC1502R2 [MOTOROLA]

RF/MICROWAVE DOWN CONVERTER, PLASTIC, LQFP-48;


型号：	MRFIC1502R2
厂家：	MOTOROLA
描述：	RF/MICROWAVE DOWN CONVERTER, PLASTIC, LQFP-48 射频微波
文件：	总8页 (文件大小：137K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Order this document

by MRFIC1502/D

SEMICONDUCTOR TECHNICAL DATA

The MRFIC Line

This integrated circuit is intended for GPS receiver applications. The dual

conversion design is implemented in Motorola’s low–cost high performance

MOSAIC 3 silicon bipolar process and is packaged in a low–cost surface mount

TQFP–48 package. In addition to the mixers, a VCO, a PLL and a loop filter are

integrated on–chip. Output IF is nominally 9.5 MHz.

1.575 GHz GPS

DOWNCONVERTER

•

65 dB Minimum Conversion Gain

5 Volts Operation

50 mA Typical Current Consumption

Low–Cost, Low Profile Plastic LQFP Package

Order MRFIC1502R2 for Tape and Reel.

R2 Suffix = 1,500 Units per 16 mm, 13 inch Reel.

•

Device Marking = M1502

CASE 932–02

(LQFP–48)

TO FROM

BPF BPF

GND GND GND GND RF IN GND

GND

GND GND

38 37

CC1

TQFP–48

36 GND

GND

38 MHz TRAP

VCO VT

GND

CC5

BYPASS CAP

IF OUT

VCO

ACTIVE

FILTER

GND

CC2

VCO CE

GND

30 GND

GAIN CONTROL

SF CAP1

GND

LOOP

FILTER

CC3

PHASE

DETECTOR

GND

SF CAP2

GND

C2A C2B

CB DCX0

CC4

GND CLK GND GND

OUT

Pin Connections and Functional Block Diagram

MOTOROLA WIRELESS SEMICONDUCTOR

SOLUTIONS DEVICE DATA

MRFIC1502

Motorola, Inc. 2001

Rev 1

MAXIMUM RATINGS

Rating

Symbol

Limit

+6.0

Unit

Vdc

°C

DC Supply Voltage

DC Supply Current

Operating Ambient Temperature

Storage Temperature Range

– 40 to +100

– 65 to +150

+260

stg

°C

Lead Soldering Temperature Range (10 seconds)

—

°C

ELECTRICAL CHARACTERISTICS (T = 25°C, and V

= 5 V, Tested in Circuit shown in Figure 1 unless otherwise noted)

Min

4.75

—

Typ

—

Max

5.25

Unit

Vdc

Characteristic

Supply Voltage

Supply Current

—

L–Band Gain (Measured from L–Band Input to 47 MHz Output)

—

IF Gain (Measured from 47 MHz Input to 9.5 MHz Output with Gain

Control at Maximum)

—

Conversion Gain (Measured from L–Band Input to 9.5 MHz Output with

Gain Control at Maximum)

—

Gain Control (Externally Adjustable 0 to 5.0 V, Maximum at 0 V)

Noise Figure (Double Sideband)

—

400

9.5

2:1

2000

–7

—

L–Band Input VSWR (Measured into 50 Ω; 1575.42 ± 5.0 MHz)

First IF Output VSWR (Measured into 50 Ω; 47.74 ± 5.0 MHz)

Second IF Output VSWR (Measured into 50 Ω; 9.5 ± 5.0 MHz)

Input Impedance @ 1st IF 47.7 ± 5 MHz (For Reference Only)

Output 1.0 dB Compression Point

—

Ω

—

dBm

mVpp

First LO (Measured at the First IF Output)

–20

–45

–50

–25

–45

—

All Other Harmonics (Measured at the First IF Output)

38.1915 MHz Leakage at First IF Output

—

Second LO (Measured at the Second IF Output)

All Other Harmonics (Measured at Second IF Output)

Reference Oscillator Input

—

4500

Clock Output

Frequency

2Xf

ref

—

2Xf

ref

Amplitude

Low

HIgh

—

2.0

0.8

—

(Clock Amplitude Measured with the Output Loaded in 15 pF and 40 kΩ)

Duty Cycle

1.2

—

3.0

—

VCO Lock Voltage

—

0.16

Phase Detector Gain

VCO Modulation Sensitivity

V/Radian

MHz/V

—

MRFIC1502

MOTOROLA WIRELESS SEMICONDUCTOR

SOLUTIONS DEVICE DATA

C22

C21

C23

C34

C24

INPUT

L10

C19

C20

C18

TQFP–48

CR1

C31

C17

C14

C16

C36

C13

C12

C15

ACTIVE

FILTER

VCO

IF OUTPUT

C10

C35

C11

GAIN CONTROL

LOOP

FILTER

PHASE

DETECTOR

C36

C37

DXCO

CLOCK

OUTPUT

C1, C8, C10, C12, C13, C15,

C19, C20, C37

C4, C5

C6, C7, C31

C2, C3

C14

C16, C18, C36

C17

C24

C35

CR1

68 pF, ATC

1.0 pF, ATC*

2.7 pF, MA45233–123, MACOM

2.2 µH, 1008CS–222XKBC, COILCRAFT

10,000 pF

5600 pF

1000 pF

1.0 µF

3.9 pF, ATC

27 pF, ATC

15 pF, ATC

5.6 pF, ATC

47 pF, ATC

120 pF, ATC

L1, L4, L5, L10

2.2 nH, LL2012–F2N2S, TOKO

2.2 µH

220 nH

0.56 µH

0.27 µH

10 kΩ

C21

C9, C11, C34, C36

C22, C23

220 Ω

* See Application Information on following pages for importance of emitter capacitance

Figure 1. Test Circuit Configuration

MOTOROLA WIRELESS SEMICONDUCTOR

SOLUTIONS DEVICE DATA

MRFIC1502

Table 1. Port Impedance Derived from Circuit Characterization

Ohms

(MHz)

Pin Number

Pin Name

RF IN

–16.09

11.3

1575.42

47.74

9.5

38.3

54.45

TO BPF

FROM BPF

IF OUT

1.5

560

–850

represents the input impedance of the pin.

APPLICATION INFORMATION

Design Philosophy

The MRFIC1502 design is a standard dual downconver-

sion configuration with an integrated fixed frequency phase–

locked loop to generate the two local oscillators and the

buffer to generate the sampling clock for a digital correlator

and decimator. The active device for the L–band VCO is also

integrated on the chip. This chip is designed in the third gen-

eration of Motorola’s Oxide Self Aligned Integrated Circuits

(MOSAIC 3) silicon bipolar process.

This filtering is primarily to reduce the amount of LO leakage

into the final IF amplifier and is achieved using a single 3.9

pF capacitor across the differential ports. The value of the

capacitor determines the high frequency of the low pass

structure.

The supply pin for the IF circuits is pin 33. This supply pin

should be isolated from the other chip supplies in order to re-

duce the amount of coupling. The recommended capacitors

are a 47 pF and a 0.01 µF, in parallel to bypass the supply to

ground and should be placed physically as close to the pin as

possible.

Circuit Considerations

The RF input to the MRFIC1502 is internally matched to 50

ohms. Therefore, only AC coupling is required on the input.

The output of the amplifier is fed directly into the first mixer.

This mixer is an active Gilbert Cell configuration. The output

of the mixer is brought off–chip for filtering of the unwanted

The output of the second IF amplifier is 50 ohms with a

bandwidth of ±5.0 MHz. This signal must be filtered before

being digitized in order to limit the noise entering the A/D

converter.

mixer products. The amplifier and mixer have their own V

supply (pin 42) in order to reduce the amount of coupling to

the other circuits. There are two bypass capacitors on this

pin, one for the high frequency components and one for the

lower frequency components. These two capacitors should

be placed physically as close to the bias pin as possible to

reduce the inductance in the path. The capacitors should

also be grounded as close to the ground of the IC as pos-

sible, preferably through a ground plane.

The output impedance of the first mixer is 50 ohms, while

the input impedance to the first IF amplifier is 1 kΩ. There is

a trap (zero) designed in at the second LO frequency to limit

the amount of LO leakage into the high gain first IF amplifier.

The first IF amplifier is a variable gain amplifier with 25 dB

of gain and 40 dB of gain control. The gain control pin can be

grounded to provide the maximum gain out of the amplifier. If

the baseband design utilizes a multi–bit A/D converter in the

digital signal processing chip, this amplifier could be used to

control the input to the A/D converter. The amplifier has an

external bypassing capacitor. This capacitor should be on

the order of 0.01 µF, and again should be located near the

package pin.

VCO Resonator Design

The design and layout of the circuits around the voltage

controlled oscillator (VCO) are the most sensitive of the en-

tire layout. The active device and biasing resistors are inte-

grated on the MRFIC1502. The external circuits consist of

the power supply decoupling, the capacitors for the inte-

grated supply superfilter, the resonator and frequency adjust-

ing elements, and the bypassing capacitor on the emitter of

the active device.

The VCO supply is isolated from the rest of the PLL circuits

in order to reduce the amount of noise that could cause fre-

quency/phase noise in the VCO. The supply should be fil-

tered using a 22 µH inductor in series and a 27 pF and 0.01

µF in parallel. The 27 pF capacitor should be series resonant

at least as high as the VCO frequency to get the most L–

band bypassing as possible. The on–chip supply filter re-

quires two capacitors off–chip to filter the supply. The

capacitors on the input (pin 8) and output (pin 10) of the filter

are 1.0 µF, and the output also has a high frequency bypass

capacitor in parallel. The input capacitor should not be smaller

than a 1.0 µF to insure stability of the supply filter.

The second mixer design is also a Gilbert Cell

configuration. The interface between the mixer and the

second IF amplifier is differential in order to increase noise

immunity. This differential interface is also brought off–chip

so that some additional filtering could be added in parallel

between the output of the mixer and input to the amplifier.

The VCO design is a standard negative resistance cell

with a buffer amplifier. The resonating structure is connected

to the base of the active device and consists of a coupling

capacitor, a hyper–abrupt varactor diode, and a wire wound

chip inductor. With the values shown on the application

MRFIC1502

MOTOROLA WIRELESS SEMICONDUCTOR

SOLUTIONS DEVICE DATA

circuit, the VCO is centered at 1527.7 MHz, and the gain of

the VCO is approximately 20 MHz/Volt.

discrete components around the loop filter and VCO is very

critical to the performance of the phase–locked loop. Care

should be taken in routing the VCO control voltage line from

the output of the loop filter to the varactor diode.

The output of the divide by 40 is buffered by a clock trans-

lator that converts the low level sine wave into a TTL level

square wave. The loading on the buffer is high so the peak

currents can reach as high as 50 mA with the maximum load

of 1.0 kΩ in parallel with 40 pF on the output. Therefore, the

The above performance is heavily dependent on the ca-

pacitive structure that is used as the emitter bypass on pin 6.

The total capacitance should be 1.0 pF; that can be achieved

using either a discrete element or a microstrip open circuited

stub. The evaluation circuit shown uses a 1.0 pF capacitor.

Phase–locked Loop Design

The VCO signal at 1527.68 MHz is divided by 40 to get the

second LO frequency of 38.19 MHz. In addition to providing

the LO to the second mixer, the 38 MHz signal is output

through a translator and is used as the sampling clock for the

digital correlator and decimator circuits. There is an addition-

al divide by two so the signal used by the phase detector is at

19.096 MHz. The reference input to the phase detector (pin 18)

has an input sensitivity of 400 mVpp minimum and 2.5 Vpp

maximum.

translator has a dedicated V

supply, pin 28, which requires

external bypassing and isolation. The recommended bypas-

sing uses two capacitors in parallel, a 47 pF and a 0.01 µF

capacitor.

Conclusion

The MRFIC1502 offers a highly integrated downconverter

solution for GPS receivers. For more detailed applications in-

formation on GPS system design refer to application note

AN1610, “Using Motorola’s MRFIC1502 in Global Position-

ing System Receivers.”

The loop filter design is the standard op–amp loop filter,

resulting in a type 2 second order loop. The layout of the

MOTOROLA WIRELESS SEMICONDUCTOR

SOLUTIONS DEVICE DATA

MRFIC1502

PACKAGE DIMENSIONS

PLASTIC PACKAGE

CASE 932–03

(LQFP–48)

ISSUE F

NOTES:

0.200 AB T–U Z

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE AB IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS T, U, AND Z TO BE DETERMINED AT

DATUM PLANE AB.

DETAIL Y

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE AC.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 PER SIDE. DIMENSIONS A AND B DO

INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE AB.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED

0.350.

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.0076.

9. EXACT SHAPE OF EACH CORNER IS OPTIONAL.

MILLIMETERS

DIM MIN

MAX

7.000 BSC

3.500 BSC

7.000 BSC

3.500 BSC

T, U, Z

1.400 1.600

0.170 0.270

1.350 1.450

0.170 0.230

0.500 BSC

0.050 0.150

0.090 0.200

0.500 0.700

DETAIL Y

0.200 AC T–U Z

0.080 AC

12 REF

0.090 0.160

0.250 BSC

0.150 0.250

9.000 BSC

4.500 BSC

9.000 BSC

4.500 BSC

0.200 REF

1.000 REF

BASE METAL

TOP & BOTTOM

0.080

AC T–U Z

SECTION AE–AE

DETAIL AD

MRFIC1502

MOTOROLA WIRELESS SEMICONDUCTOR

SOLUTIONS DEVICE DATA

NOTES

MOTOROLA WIRELESS SEMICONDUCTOR

SOLUTIONS DEVICE DATA

MRFIC1502

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HOME PAGE: http://www.motorola.com/semiconductors/

MRFIC1502

MOTOROLA WIRELESS SEMICONDUCTOR

SOLUTIONS DEVICE DATA

◊

MRFIC1502/D

MRFIC1502R2 [MOTOROLA]

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