MTB50P03HDL [MOTOROLA]
TMOS POWER FET LOGIC LEVEL 50 AMPERES 30 VOLTS; TMOS功率场效应晶体管逻辑电平50安培30伏
| 型号： | MTB50P03HDL |
| 厂家： | 
MOTOROLA |
| 描述： | TMOS POWER FET LOGIC LEVEL 50 AMPERES 30 VOLTS |
| 文件： | 总12页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MTB50P03HDL/D
SEMICONDUCTOR TECHNICAL DATA
Motorola Preferred Device
TMOS POWER FET
LOGIC LEVEL
50 AMPERES
30 VOLTS
P–Channel Enhancement–Mode Silicon Gate
2
The D PAK package has the capability of housing a larger die
R
= 0.025 OHM
DS(on)
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower R
capabilities. This advanced
DS(on)
high–cell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
D
G
•
•
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
CASE 418B–03, Style 2
2
D PAK
S
•
•
•
•
•
Diode is Characterized for Use in Bridge Circuits
I
and V
Specified at Elevated Temperature
DSS
DS(on)
Short Heatsink Tab Manufactured — Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Symbol
Value
30
Unit
Vdc
Vdc
Drain–Source Voltage
V
DSS
Drain–Gate Voltage (R
= 1.0 MΩ)
Gate–Source Voltage — Continuous
V
DGR
30
GS
V
±15
± 20
Vdc
Vpk
GS
Gate–Source Voltage — Non–Repetitive (t ≤ 10 ms)
V
GSM
p
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (t ≤ 10 µs)
I
I
50
31
150
Adc
Apk
D
D
I
p
DM
Total Power Dissipation
Derate above 25°C
P
D
125
1.0
2.5
Watts
W/°C
Watts
Total Power Dissipation @ T = 25°C, when mounted with the minimum recommended pad size
C
Operating and Storage Temperature Range
T , T
stg
– 55 to 150
1250
°C
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C
E
AS
mJ
J
(V
DD
= 25 Vdc, V
= 5.0 Vdc, Peak I = 50 Apk, L = 1.0 mH, R = 25 Ω)
GS L G
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
R
θJC
R
θJA
R
θJA
1.0
62.5
50
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
T
L
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET, and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
Motorola, Inc. 1997
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(V = 0 Vdc, I = 250 µAdc)
Temperature Coefficient (Positive)
(C ≥ 2.0) (3)
pk
V
Vdc
(BR)DSS
30
—
—
26
—
—
GS
D
mV/°C
µAdc
Zero Gate Voltage Drain Current
I
DSS
(V
DS
(V
DS
= 30 Vdc, V
= 30 Vdc, V
= 0 Vdc)
= 0 Vdc, T = 125°C)
—
—
—
—
1.0
10
GS
GS
J
Gate–Body Leakage Current
(V = ±15 Vdc, V = 0 Vdc)
I
nAdc
Vdc
GSS
—
—
100
GS
DS
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(C ≥ 3.0) (3)
pk
V
GS(th)
(V
DS
= V , I = 250 µAdc)
GS
1.0
—
1.5
4.0
2.0
—
D
Threshold Temperature Coefficient (Negative)
mV/°C
Static Drain–Source On–Resistance
(C ≥ 3.0) (3)
pk
R
V
mOhm
DS(on)
(V
GS
= 5.0 Vdc, I = 25 Adc)
—
20.9
25
D
Drain–Source On–Voltage (V
= 5.0 Vdc)
Vdc
GS
DS(on)
(I = 50 Adc)
—
—
0.83
—
1.5
1.3
D
(I = 25 Adc, T =125°C)
D
J
Forward Transconductance
(V = 5.0 Vdc, I = 25 Adc)
g
FS
mhos
15
20
—
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
—
—
—
3500
1550
550
4900
2170
770
pF
ns
iss
(V
DS
= 25 Vdc, V
= 0 Vdc,
GS
f = 1.0 MHz)
Output Capacitance
C
oss
Transfer Capacitance
C
rss
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
—
—
—
—
—
—
—
—
22
340
90
30
466
117
300
100
—
d(on)
(V = 15 Vdc, I = 50 Adc,
Rise Time
DD
DS
D
t
r
V
= 5.0 Vdc,
GS
G
Turn–Off Delay Time
Fall Time
t
d(off)
R
= 2.3 Ω)
t
218
74
f
Gate Charge
(See Figure 8)
Q
Q
Q
Q
nC
T
1
2
3
13.6
44.8
35
(V
= 24 Vdc, I = 50 Adc,
D
V
GS
= 5.0 Vdc)
—
—
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
V
Vdc
ns
SD
(I = 50 Adc, V
= 0 Vdc)
S
GS
= 0 Vdc, T = 125°C)
—
—
2.39
1.84
3.0
—
(I = 50 Adc, V
S
GS
J
Reverse Recovery Time
(See Figure 15)
t
—
—
—
—
106
58
—
—
—
—
rr
t
a
(I = 50 Adc, V
= 0 Vdc,
S
GS
dI /dt = 100 A/µs)
S
t
48
b
Reverse Recovery Stored Charge
Q
0.246
µC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
—
—
3.5
7.5
—
—
nH
nH
D
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit – Typ
C
=
pk
3 x SIGMA
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
100
80
100
T
J
= – 55°C
V
≥ 5 V
T
= 25°C
V
= 10 V
5 V
DS
J
GS
8 V
6 V
25°C
100°C
80
60
40
4 V
4.5 V
60
3.5 V
40
3 V
20
0
20
0
2.5 V
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
1.5
1.9
2.3
2.7
3.1
3.5
3.9
4.3
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
V , GATE–TO–SOURCE VOLTAGE (VOLTS)
GS
DS
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.029
0.027
0.025
0.023
0.021
0.019
0.017
0.015
0.022
0.021
0.020
0.019
0.018
V
= 5 V
T
= 25°C
GS
V
= 5 V
J
GS
T
= 100°C
J
25°C
0.017
0.016
0.015
10 V
– 55°C
0
20
40
60
80
100
0
20
40
I , DRAIN CURRENT (AMPS)
D
60
80
100
I
, DRAIN CURRENT (AMPS)
D
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
1.35
1.25
1.15
1.05
1000
100
10
V
= 0 V
GS
V
= 5 V
GS
= 25 A
I
D
T
= 125°C
J
0.95
0.85
100°C
– 50
– 25
0
25
50
75
100
C)
125
150
0
5
10
15
20
25
30
T , JUNCTION TEMPERATURE (
°
V
DS
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
J
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–to–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off–state condition when cal-
culating t
and is read at a voltage corresponding to the
d(on)
on–state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
) can be made from a rudimentary analysis of
G(AV)
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resis-
tive load, V remains virtually constant at a level known as
GS
the plateau voltage, V
. Therefore, rise and fall times may
SGP
be approximated by the following:
t = Q x R /(V
– V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
V
= the gate drive voltage, which varies from zero to V
GG
GG
R
= the gate drive resistance
G
and Q and V
are read from the gate charge curve.
GSP
2
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R
= R
C
C
In [V
/(V
GG GG
– V
)]
GSP
d(on)
G
iss
In (V
/V
GG GSP
)
d(off)
G
iss
14000
12000
V
= 0 V
V
= 0 V
DS
GS
T
= 25°C
J
C
iss
10000
8000
6000
4000
2000
0
C
rss
C
C
iss
oss
C
rss
10
10
5
0
5
15
20
25
V
V
DS
GS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
6
5
4
3
2
1
0
30
25
20
15
1000
V
V
= 30 V
= 10 V
I = 50 A
D
J
DD
GS
QT
T
= 25°C
t
r
V
GS
t
f
Q1
Q2
t
d(off)
100
I
T
= 50 A
= 25°C
D
J
10
5
t
d(on)
Q3
V
DS
0
10
0
10
20
30
40
50
60
70
80
1
10
Q , TOTAL GATE CHARGE (nC)
R
, GATE RESISTANCE (Ohms)
T
G
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse re-
covery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
di/dts. The diode’s negative di/dt during t is directly con-
a
trolled by the device clearing the stored charge. However,
the positive di/dt during t is an uncontrollable diode charac-
b
teristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of t /t serves
b a
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier de-
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
vice, therefore it has a finite reverse recovery time, t , due to
rr
the storage of minority carrier charge, Q , as shown in the
RR
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
(shorter t ), have less stored charge and a softer reverse re-
rr
covery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise gen-
erated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.
diode with short t and low Q
these losses.
specifications to minimize
rr
RR
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ring-
ing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
50
V
= 0 V
GS
= 25°C
T
J
40
30
20
10
0
0.4 0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
V
, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
Motorola TMOS Power MOSFET Transistor Device Data
5
di/dt = 300 A/µs
Standard Cell Density
t
rr
High Cell Density
t
rr
t
b
t
a
t, TIME
Figure 11. Reverse Recovery Time (t )
rr
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (T ) of 25°C. Peak
C
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance – Gen-
eral Data and Its Use.”
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (I
)
DM
) is exceeded, and that the transition
(I
), the energy rating is specified at rated continuous cur-
DM
nor rated voltage (V
DSS
rent (I ), in accordance with industry custom. The energy rat-
D
time (t , t ) does not exceed 10 µs. In addition the total power
r f
ing must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at cur-
averaged over a complete switching cycle must not exceed
(T
– T )/(R ).
J(MAX)
C
θJC
rents below rated continuous I can safely be assumed to
A power MOSFET designated E–FET can be safely used
D
in switching circuits with unclamped inductive loads. For reli-
equal the values indicated.
1000
1400
V
= 20 V
GS
SINGLE PULSE
= 25
I
= 50 A
D
1200
1000
800
T
°C
C
100
100 µs
600
1 ms
10
1
10 ms
400
dc
R
LIMIT
DS(on)
200
0
THERMAL LIMIT
PACKAGE LIMIT
0.1
1.0
10
100
25
50
75
100
125
C)
150
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
DS
J
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
6
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
1.0
D = 0.5
0.2
0.1
P
(pk)
0.1
R
(t) = r(t) R
JC θJC
0.05
0.02
θ
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
t
READ TIME AT t
1
1
0.01
t
T
– T = P
R (t)
(pk) θJC
2
J(pk)
C
DUTY CYCLE, D = t /t
SINGLE PULSE
1 2
0.01
1.0E–05
1.0E–04
1.0E–03
1.0E–02
t, TIME (s)
1.0E–01
1.0E+00
1.0E+01
Figure 14. Thermal Response
3
R
= 50°C/W
θJA
Board material = 0.065 mil FR–4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size ≈ 450 mils x 350 mils
2.5
2.0
di/dt
1.5
1
I
S
t
rr
t
t
a
b
TIME
0.5
0
0.25 I
t
S
p
25
50
75
100
125
150
I
S
T , AMBIENT TEMPERATURE (
°C)
A
2
Figure 16. D PAK Power Derating Curve
Figure 15. Diode Reverse Recovery Waveform
Motorola TMOS Power MOSFET Transistor Device Data
7
2
INFORMATION FOR USING THE D PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.
0.74
18.79
0.065
1.651
0.420
10.66
0.07
1.78
0.14
3.56
0.330
8.38
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by T
junction temperature of the die, R
, the maximum rated
, the thermal resistance
R
versus drain pad area is shown in Figure 17.
J(max)
θJA
θJA
70
from the device junction to ambient, and the operating
temperature, T . Using the values provided on the data sheet,
Board Material = 0.0625
″
A
G–10/FR–4, 2 oz Copper
T
= 25°C
A
P
can be calculated as follows:
D
60
50
2.5 Watts
3.5 Watts
T
– T
A
J(max)
P
=
D
R
θJA
40
30
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T of 25°C, one can
5 Watts
A
2
calculate the power dissipation of the device. For a D PAK
device, P is calculated as follows.
D
20
0
2
4
6
8
10
12
14
16
A, AREA (SQUARE INCHES)
150°C – 25°C
= 2.5 Watts
P
=
D
Figure 17. Thermal Resistance versus Drain Pad
50°C/W
2
Area for the D PAK Package (Typical)
2
The50°C/WfortheD PAKpackageassumestheuseofthe
recommended footprint on a glass epoxy printed circuit board
to achieve a power dissipation of 2.5 Watts. There are other
alternatives to achieving higher power dissipation from the
surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad . Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
8
Motorola TMOS Power MOSFET Transistor Device Data
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. Solder
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of
brass or stainless steel. For packages such as the SC–59,
SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223,
SO–8, SO–14, SO–16, and SMB/SMC diode packages, the
stencil opening should be the same as the pad size or a 1:1
SOLDER PASTE
OPENINGS
STENCIL
2
registration. This is not the case with the DPAK and D PAK
packages. If one uses a 1:1 opening to screen solder onto the
drain pad, misalignment and/or “tombstoning” may occur due
to an excess of solder. For these two packages, the opening
in the stencil for the paste should be approximately 50% of the
tab area. The opening for the leads is still a 1:1 registration.
Figure 18. Typical Stencil for DPAK and
2
D PAK Packages
2
Figure 18 shows a typical stencil for the DPAK and D PAK
packages. The pattern of the opening in the stencil for the
drain pad is not critical as long as it allows approximately 50%
of the pad to be covered with paste.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Always preheat the device.
• The delta temperature between the preheat and soldering
should be 100°C or less.*
• Mechanical stress or shock should not be applied during
cooling.
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
* Due to shadowing and the inability to set the wave height to
2
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
incorporate other surface mount components, the D PAK is
not recommended for wave soldering.
Motorola TMOS Power MOSFET Transistor Device Data
9
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/in-
frared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177–189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a figure
for belt speed. Taken together, these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
19 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
typeofsolderused, andthetypeofboardorsubstratematerial
being used. This profile shows temperature versus time. The
STEP 5
HEATING
ZONES 4 & 7
“SPIKE”
STEP 6
VENT
STEP 7
COOLING
STEP 1
PREHEAT
ZONE 1
“RAMP”
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
STEP 2
VENT
“SOAK” ZONES 2 & 5
“RAMP”
STEP 3
HEATING
205
PEAK AT
SOLDER JOINT
° TO 219°C
200
°
C
C
170°C
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
160°C
150°C
150
°
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
100°C
140°C
MASS OF ASSEMBLY)
100
°
C
C
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
50°
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 19. Typical Solder Heating Profile
10
Motorola TMOS Power MOSFET Transistor Device Data
PACKAGE DIMENSIONS
C
E
V
–B–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
4
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
INCHES
MILLIMETERS
A
DIM
A
B
C
D
E
G
H
J
MIN
MAX
0.380
0.405
0.190
0.035
0.055
MIN
8.64
9.65
4.06
0.51
1.14
MAX
9.65
10.29
4.83
0.89
1.40
0.340
0.380
0.160
0.020
0.045
S
1
2
3
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
–T–
SEATING
PLANE
K
0.100 BSC
2.54 BSC
0.080
0.018
0.090
0.575
0.045
0.110
0.025
0.110
0.625
0.055
2.03
0.46
2.79
0.64
J
G
K
S
V
2.29
2.79
H
14.60
1.14
15.88
1.40
D 3 PL
M
M
0.13 (0.005)
T B
CASE 418B–03
ISSUE C
Motorola TMOS Power MOSFET Transistor Device Data
11
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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