MTP12N10ELWC [MOTOROLA]
12A, 100V, 0.16ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB;
| 型号： | MTP12N10ELWC |
| 厂家： | 
MOTOROLA |
| 描述： | 12A, 100V, 0.16ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB 晶体 晶体管 功率场效应晶体管 开关 脉冲 局域网 |
| 文件： | 总6页 (文件大小：242K) |
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by MTP12N10E/D
SEMICONDUCTOR TECHNICAL DATA
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
12 AMPERES
100 VOLTS
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
R
= 0.16 OHM
DS(on)
D
•
•
•
Designed to Eliminate the Need for External Zener Transient
Suppressor — Absorbs High Energy in the Avalanche Mode
Commutating Safe Operating Area (CSOA) Specified for Use
in Half and Full Bridge Circuits
Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
G
S
•
•
Diode is Characterized for Use in Bridge Circuits
I
and V Specified at Elevated Temperature
DSS
DS(on)
CASE 221A–06, Style 5
TO–220AB
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Symbol
Value
100
Unit
Vdc
Vdc
Vdc
Drain–Source Voltage
V
DSS
Drain–Gate Voltage (R
= 1.0 MΩ)
Gate–Source Voltage — Continuous
V
DGR
100
GS
V
GS
±20
±40
Gate–Source Voltage — Single Pulse (t ≤ 50 µs)
p
Drain Current — Continuous
Drain Current — Single Pulse (t ≤ 10 µs)
I
12
30
Adc
D
I
p
DM
Total Power Dissipation @ T = 25°C
Derate above 25°C
P
D
79
0.53
Watts
W/°C
C
Operating and Storage Temperature Range
T , T
stg
–55 to 175
290
°C
J
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (T ≤ 175°C)
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C
E
AS
mJ
J
(V
DD
= 25 V, V = 10 V, L = 4.03 mH, R = 25 Ω, Peak I = 12 A)
GS G L
(See Figures 15, 16 and 17)
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient°
R
R
1.9
62.5
°C/W
°C
θJC
θJA
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
T
260
L
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
Motorola, Inc. 1996
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
V
(BR)DSS
(V
GS
= 0, I = 250 µAdc)
100
—
—
110
—
—
Vdc
mV/°C
D
Temperature Coefficient (positive)
Zero Gate Voltage Drain Current
I
µA
DSS
—
—
—
—
10
100
(V
DS
(V
DS
= 100 V, V
= 100 V, V
= 0)°
GS
GS
= 0, T = 150°C)
J
Gate–Body Leakage Current, Forward (V
GSF
= 20 Vdc, V
DS
= 0)
= 0)
I
—
—
—
—
100
100
nAdc
nAdc
GSSF
Gate–Body Leakage Current, Reverse (V
= 20 Vdc, V
DS
I
GSR
GSSR
ON CHARACTERISTICS*
Gate Threshold Voltage
V
Vdc
GS(th)
(V
DS
= V , I = 250 µAdc)
Temperature Coefficient (negative)µ
2.0
—
3.0
6.0
4.0
—
GS
D
mV/°C
Ohm
Vdc
Static Drain–Source On–Resistance (V
= 10 Vdc, I = 6.0 Adc)
R
V
—
0.125
0.16
GS
D
DS(on)
Drain–Source On–Voltage (V
GS
= 10 Vdc)
DS(on)
—
—
1.5
1.4
2.4
1.92
(I = 12 Adc)°
D
(I = 6.0 Adc, T = 150°C)
D
J
g
Forward Transconductance (V
DS
≥ 15 V, I = 6.0 A)
4.0
5.0
—
mhos
pF
D
FS
DYNAMIC CHARACTERISTICS
Input Capacitance
C
C
—
—
—
600
70
—
—
—
iss
(V
DS
= 25 V, V = 0,
GS
Reverse Transfer Capacitance
f = 1.0 MHz)
See Figure 14
rss
Output Capacitance
C
230
oss
SWITCHING CHARACTERISTICS (T = 100°C)
J
Turn–On Delay Time
t
—
—
—
—
—
—
—
—
10
64
21
30
18
4.0
10
8.0
—
—
—
—
26
—
—
—
ns
d(on)
(V
DD
= 50 V, I = 12 A,
D
Rise Time
t
r
V
= 10 V, R = 12 Ω)
GS
G
Turn–Off Delay Time
Fall Time
t
d(off)
See Figure 7
t
f
Gate Charge
Q
T
Q
1
Q
2
Q
3
nC
(V
DS
= 80 V, I = 12 A,
D
V
= 10 Vdc)
GS
See Figures 5 and 6
SOURCE–DRAIN DIODE CHARACTERISTICS*
Forward On–Voltage
V
—
—
—
1.0
0.83
110
2.5
—
Vdc
ns
SD
(I = 12 A, V
= 0)
= 0, T = 150°C)
S
GS
(I = 12 A, V
S
GS
J
Reverse Recovery Time
(I = 12 A, V
= 0,
dI /dt = 100 A/µs, V = 50 V)
t
—
S
GS
R
rr
S
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)″
(Measured from the drain lead 0.25″ from package to center of die)
L
d
nH
—
—
3.5
4.5
—
—
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
s
—
7.5
—
* Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
24
20
24
V
= 10 V
GS
V
≥ 15 V
9 V
T
= –55°C
T
= 25°C
DS
J
J
20
16
12
8
100°C
25°C
8 V
7 V
16
12
8
6 V
5 V
4
4
0
0
5
10
0
1
2
3
4
0
2
4
6
8
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
V
, GATE–TO–SOURCE VOLTAGE (VOLTS)
DS
GS
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.6
2.2
2
V
= 10 V
V
= 10 V
= 6 A
GS
GS
0.5
0.4
0.3
0.2
I
D
1.8
1.6
1.4
1.2
1
T
= 100
°
C
J
25
°C
0.1
0
–55°C
0.8
0.6
0
3
6
9
12
15
18
21
24
–50
–25
0
25
50
75
100
125
C)
150
175
I
, DRAIN CURRENT (AMPS)
T , JUNCTION TEMPERATURE (
°
D
J
Figure 3. On–Resistance versus Drain Current
Figure 4. On–Resistance Variation
with Temperature
20
16
12
100
80
I
V
T
= 12 A
D
V
= 80 V
DS
+18 V
47 k
V
DS
= 25°C
DD
J
SAME
DEVICE
TYPE
1 mA
10 V
60
100 k
Q
T
AS DUT
V
15 V
0.1 µF
in
2N3904
8
4
0
40
20
0
Q
1
2N3904
Q
FERRITE
BEAD
2
100 k
V
GS
DUT
100
47 k
Q
3
0
5
10
15
20
25
V
= 15 V ; PULSE WIDTH ≤ 100 µs, DUTY CYCLE ≤ 10%.
pk
in
Q , TOTAL GATE CHARGE (nC)
g
Figure 5. Gate Charge Test Circuit
Figure 6. Gate–To–Source and
Drain–To–Source Voltage versus Gate Charge
Motorola TMOS Power MOSFET Transistor Device Data
3
SAFE OPERATING AREA INFORMATION
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain–to–source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25°C and a maxi-
mum junction temperature of 175°C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, “Transient Thermal Resistance–General Data
and Its Use” provides detailed instructions.
The power averaged over a complete switching cycle must
be less than:
T
– T
J(max)
C
R
θJC
1000
100
V
I
= 50 V
= 12 A
= 10 V
= 25°C
t
DD
D
r
t
f
V
T
GS
t
d(off)
J
t
d(on)
SWITCHING SAFE OPERATING AREA
10
1
The switching safe operating area (SOA) of Figure 9 is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, I
and the breakdown voltage, BV . The
DM
DSS
10
100
, GATE RESISTANCE (OHMS)
1000
switching SOA shown in Figure 9 is applicable for both turn–
on and turn–off of the devices for switching times less than
one microsecond.
R
G
Figure 7. Resistive Switching Time
versus Gate Resistance
1000
40
30
20
V
= 20 V
GS
SINGLE PULSE
= 25
T
°C
C
100
10
OPERATION LIMITED IN THIS
AREA BY R
DS(on)
100
1 ms
µs
10 ms
dc
T
≤ 175°C
J
10
0
1
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1
10
100
0
20
40
60
80
100
120
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
V , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
DS
Figure 8. Maximum Rated Forward Biased
Safe Operating Area
Figure 9. Maximum Rated Switching
Safe Operating Area
1
D = 0.5
0.5
0.3
0.2
0.2
0.1
0.1
P
(pk)
R
R
(t) = r(t) R
θ
θ
θ
JC
JC
JC
°C/W MAX
0.05
0.02
= 1.9
0.05
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
t
0.03
0.02
1
1
(pk)
t
2
0.01
T
– T = P
R
(t)
JC
J(pk)
50
C
θ
DUTY CYCLE, D = t /t
1 2
SINGLE PULSE
0.02 0.05
0.01
0.01
0.1
0.2
0.5
1
2
5
10
20
100
200
500
1000
t, TIME (ms)
Figure 10. Thermal Response
4
Motorola TMOS Power MOSFET Transistor Device Data
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of Figure
12 defines the limits of safe operation for commutated sour-
ce-drain current versus re-applied drain voltage when the
source-drain diode has undergone forward bias. The curve
15 V
0
V
GS
shows the limitations of I
and peak V for a given rate of
FM
DS
I
change of source current. It is applicable when waveforms
similar to those of Figure 11 are present. Full or half-bridge
PWM DC motor controllers are common applications requir-
ing CSOA data.
FM
dl /dt
s
90%
I
S
t
rr
10%
Device stresses increase with increasing rate of change of
source current so dI /dt is specified with a maximum value.
t
on
I
s
RM
Higher values of dI /dt require an appropriate derating of I
,
s
FM
0.25 I
RM
peak V
or both. Ultimately dI /dt is limited primarily by de-
DS
s
vice, package, and circuit impedances. Maximum device
V
DS(pk)
stress occurs during t as the diode goes from conduction to
rr
V
R
reverse blocking.
V
isthepeakdrain–to–sourcevoltagethatthedevice
DS(pk)
must sustain during commutation; I
dV /dt
DS
V
DS
is the maximum for-
FM
V
dsL
V
f
ward source-drain diode current just prior to the onset of
commutation.
MAX. CSOA
STRESS AREA
V
is specified at rated BV
to ensure that the CSOA
R
DSS
stress is maximized as I decays from I
to zero.
S
RM
R
should be minimized during commutation. T has only
GS
a second order effect on CSOA.
J
Figure 11. Commutating Waveforms
Stray inductances in Motorola’s test circuit are assumed to
be practical minimums.
15
R
GS
DUT
12
9
T
≤
175
°C
J
I
= 12 A
S
–
dIs/dt
≤
100 A/
µs
V
≤ 100 V
V
R
R
I
I
S
L
i
+
FM
V
6
DS
+
20 V
–
3
V
GS
V
= 80% OF RATED BV
DSS
R
0
0
20
40
60
80
100 120
140 160 180 200
V
= V + L dl /dt
dsL
f i s
V
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
DS
Figure 13. Commutating Safe Operating Area
Test Circuit
Figure 12. Commutating Safe Operating
Area (CSOA)
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintendedor unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola TMOS Power MOSFET Transistor Device Data
5
300
250
200
150
100
2000
1500
V
= 0 V
V
= 0 V
GS
DS
PEAK I = 12 A
L
V
= 25 V
DD
1000
500
C
C
iss
oss
50
0
C
rss
0
25
50
75
100
125
150
C)
175
15
0
15
30
45
60
V
V
DS
GS
T , STARTING JUNCTION TEMPERATURE (
°
J
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 14. Capacitance Variation
Figure 15. Maximum Avalanche Energy versus
Starting Junction Temperature
BV
DSS
L
V
DS
I
L
I
L(t)
V
DD
R
G
t
V
DD
t
P
t, (TIME)
Figure 16. Unclamped Inductive Switching
Test Circuit
Figure 17. Unclamped Inductive Switching
Waveforms
PACKAGE DIMENSIONS
SEATING
PLANE
–T–
INCHES
MIN
MILLIMETERS
C
B
F
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
MAX
0.620
0.405
0.190
0.035
0.147
0.105
0.155
0.025
0.562
0.060
0.210
0.120
0.110
0.055
0.255
0.050
–––
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.46
12.70
1.15
4.83
2.54
2.04
1.15
5.97
0.00
1.15
–––
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.64
14.27
1.52
5.33
3.04
2.79
1.39
6.47
1.27
–––
T
S
0.570
0.380
0.160
0.025
0.142
0.095
0.110
0.018
0.500
0.045
0.190
0.100
0.080
0.045
0.235
0.000
0.045
–––
4
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
A
K
Q
Z
1
2
3
U
H
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
U
V
L
R
V
J
Z
0.080
2.04
CASE 221A–06
G
TO–220AB
ISSUE Y
D
N
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MTP12N10E/D
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