MTP52N06VL [MOTOROLA]
TMOS POWER FET 52 AMPERES 60 VOLTS RDS(on) = 0.025 OHM; TMOS功率FET 52安培60伏特的RDS（on ） = 0.025 OHM
| 型号： | MTP52N06VL |
| 厂家： | 
MOTOROLA |
| 描述： | TMOS POWER FET 52 AMPERES 60 VOLTS RDS(on) = 0.025 OHM |
| 文件： | 总8页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MTP52N06VL/D
SEMICONDUCTOR TECHNICAL DATA
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
52 AMPERES
60 VOLTS
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
R
= 0.025 OHM
DS(on)
TM
D
New Features of TMOS V
•
On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low R Technology
DS(on)
Faster Switching than E–FET Predecessors
G
•
Features Common to TMOS V and TMOS E–FETS
S
•
•
•
Avalanche Energy Specified
and V Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS E–FET
CASE 221A–06, Style 5
TO–220AB
I
DSS
DS(on)
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Symbol
Value
60
Unit
Drain–to–Source Voltage
V
DSS
Vdc
Vdc
Drain–to–Gate Voltage (R
= 1.0 MΩ)
Gate–to–Source Voltage — Continuous
V
DGR
60
GS
V
± 15
± 25
Vdc
Vpk
GS
Gate–to–Source Voltage — Non–repetitive (t ≤ 10 ms)
V
GSM
p
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (t ≤ 10 µs)
I
I
52
41
182
Adc
D
D
I
Apk
p
DM
Total Power Dissipation
Derate above 25°C
P
D
188
1.25
Watts
W/°C
Operating and Storage Temperature Range
T , T
stg
–55 to 175
406
°C
J
Single Pulse Drain–to–Source Avalanche Energy — STARTING T = 25°C
E
AS
mJ
J
(V
DD
= 25 Vdc, V
= 5 Vdc, PEAK I = 52 Apk, L = 0.3 mH, R = 25 Ω)
GS L G
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
R
R
0.8
62.5
°C/W
°C
θJC
θJA
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds
T
260
L
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 3
Motorola, Inc. 1996
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(V = 0 Vdc, I = .25 mAdc)
Temperature Coefficient (Positive)
(Cpk ≥ 2.0) (3)
V
(BR)DSS
60
—
—
65
—
—
Vdc
mV/°C
GS
D
Zero Gate Voltage Drain Current
I
µAdc
DSS
(V
DS
(V
DS
= 60 Vdc, V
= 60 Vdc, V
= 0 Vdc)
= 0 Vdc, T = 150°C)
—
—
—
—
10
100
GS
GS
J
Gate–Body Leakage Current (V
= ± 15 Vdc, V
= 0 Vdc)
DS
I
—
—
100
nAdc
GS
GSS
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(Cpk ≥ 2.0) (3)
(Cpk ≥ 2.0) (3)
V
GS(th)
(V
= V , I = 250 µAdc)
1.0
—
1.5
4.5
2.0
—
Vdc
mV/°C
DS
GS
D
Threshold Temperature Coefficient (Negative)
Static Drain–to–Source On–Resistance
R
V
Ohm
Vdc
DS(on)
(V
GS
= 5 Vdc, I = 26 Adc)
—
0.022
0.025
D
Drain–to–Source On–Voltage
DS(on)
(V
GS
(V
GS
= 5 Vdc, I = 52 Adc)
—
—
—
—
1.6
1.4
D
= 5 Vdc, I = 26 Adc, T = 150°C)
D
J
Forward Transconductance (V
= 6.3 Vdc, I = 20 Adc)
g
FS
17
30
—
Mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
—
—
—
1900
550
2660
770
iss
(V
DS
= 25 Vdc, V
GS
f = 1.0 MHz)
= 0 Vdc,
Output Capacitance
C
oss
Transfer Capacitance
C
170
340
rss
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
—
—
—
—
—
—
—
—
15
500
100
200
62
30
1000
200
400
90
ns
d(on)
(V
= 30 Vdc, I = 52 Adc,
D
Rise Time
DD
DS
t
r
V
= 5 Vdc,
GS
G
Turn–Off Delay Time
Fall Time
t
d(off)
R
= 9.1 Ω)
t
f
Gate Charge
(See Figure 8)
Q
T
Q
1
Q
2
Q
3
nC
4.0
31
—
(V
= 48 Vdc, I = 52 Adc,
D
V
GS
= 5 Vdc)
—
16
—
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
V
Vdc
ns
SD
(I = 52 Adc, V
= 0 Vdc)
S
GS
= 0 Vdc, T = 150 °C)
—
—
1.03
0.9
1.5
—
(I = 52 Adc, V
S
GS
J
Reverse Recovery Time
t
—
—
—
—
104
63
—
—
—
—
rr
t
a
(I = 52 Adc, V
= 0 Vdc,
S
GS
dI /dt = 100 A/µs)
S
t
41
b
Reverse Recovery Stored Charge
Q
0.28
µC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
L
D
nH
—
—
3.5
4.5
—
—
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
nH
—
7.5
—
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit – Typ
C
=
pk
3 x SIGMA
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
110
100
110
V
= 10 V
GS
T
= 25°C
V
≥ 10 V
6 V
J
DS
100
90
80
70
60
50
T
= –55°C
8 V
7 V
J
5 V
90
80
70
60
50
40
30
20
100°C
25°C
4 V
3 V
40
30
20
10
0
10
0
0
1
2
3
4
5
6
7
8
9
10
0.5 1.0 1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
V , GATE–TO–SOURCE VOLTAGE (VOLTS)
GS
DS
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
.070
.060
.050
.040
.030
.020
.010
0
.040
.035
.030
T
= 25°C
V
= 5 V
J
GS
V
= 5 V
10 V
GS
.025
.020
.015
.010
T
= 100°C
J
25°C
–55°C
.005
0
0
10
20
30
I
40
50
60
70
80
90 100 110
0
10
20
30
I
40
50
60
70
80
90 100 110
, DRAIN CURRENT (AMPS)
, DRAIN CURRENT (AMPS)
D
D
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
1000
100
10
1.8
V
= 5 V
GS
= 26 A
V
= 0 V
GS
1.6
1.4
1.2
1
I
D
T
= 125°C
J
100°C
0.8
0.6
0.4
0.2
0
1
–50
–25
0
25
50
75
100
125
C)
150
175
0
10
20
30
40
50
60
T , JUNCTION TEMPERATURE (
°
V
DS
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
J
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined
by how fast the FET input capacitance can be charged by
current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off–state condition when cal-
culating t
and is read at a voltage corresponding to the
d(on)
on–state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also compli-
cates the mathematics. And finally, MOSFETs have finite
internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance is
difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely
operated into an inductive load; however, snubbing reduces
switching losses.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
) can be made from a rudimentary analysis of
G(AV)
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resis-
tive load, V remains virtually constant at a level known as
GS
the plateau voltage, V
. Therefore, rise and fall times may
SGP
be approximated by the following:
t = Q x R /(V
– V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
V
= the gate drive voltage, which varies from zero to V
GG
GG
R
= the gate drive resistance
G
and Q and V
are read from the gate charge curve.
GSP
2
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R
= R
C
C
In [V
/(V
GG GG
– V
)]
GSP
d(on)
G
iss
In (V
/V
GG GSP
)
d(off)
G
iss
8000
7000
6000
5000
V
= 0 V
V
= 0 V
DS
GS
T
= 25
°C
J
C
iss
C
rss
4000
3000
C
iss
2000
1000
0
C
oss
C
rss
10
5
0
5
10
15
20
25
V
V
DS
GS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
10
9
30
27
24
21
18
15
12
9
1000
100
QT
V
= 30 V
= 52 A
= 5 V
= 25°C
DD
t
r
I
V
T
D
GS
8
7
6
5
V
GS
t
f
J
t
d(off)
Q2
Q1
4
3
2
10
1
t
d(on)
I
T
= 52 A
= 25°C
D
J
6
3
0
70
1
0
Q3
10
V
DS
0
20
30
40
50
60
1
10
, GATE RESISTANCE (OHMS)
G
100
Q , TOTAL CHARGE (nC)
R
T
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
55
V
= 0 V
GS
= 25°C
50
45
40
35
30
25
20
15
10
T
J
5
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
1
1.05
V
, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
current (I
), the energy rating is specified at rated
DM
(I
) nor rated voltage (V ) is exceeded and the transition
DM DSS
continuous current (I ), in accordance with industry custom.
D
time (t ,t ) do not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
r f
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
(T
– T )/(R ).
J(MAX)
C
θJC
currents below rated continuous I can safely be assumed to
A Power MOSFET designated E–FET can be safely used
D
in switching circuits with unclamped inductive loads. For
Motorola TMOS Power MOSFET Transistor Device Data
equal the values indicated.
5
SAFE OPERATING AREA
1000
100
450
400
V
= 15 V
GS
SINGLE PULSE
= 25
I
= 52 A
D
10 µs
T
°C
C
350
300
250
200
150
100
100 µs
1 ms
10
1
10 ms
10
R
LIMIT
dc
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
50
0
0.1
1
100
25
50
75
100
125
150
C)
175
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (°
DS
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1
D = 0.5
0.2
0.1
P
(pk)
0.1
0.05
0.02
R
(t) = r(t) R
JC θJC
θ
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
t
READ TIME AT t
T
1
1
0.01
t
– T = P R (t)
(pk) θJC
2
J(pk)
C
DUTY CYCLE, D = t /t
1 2
SINGLE PULSE
0.01
1.0E–05
1.0E–04
1.0E–03
1.0E–02
1.0E–01
1.0E+00
1.0E+01
t, TIME (s)
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
t
a
b
TIME
0.25 I
t
S
p
I
S
Figure 14. Diode Reverse Recovery Waveform
6
Motorola TMOS Power MOSFET Transistor Device Data
PACKAGE DIMENSIONS
NOTES:
SEATING
PLANE
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–T–
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
C
S
B
F
T
4
INCHES
MIN
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
MAX
0.620
0.405
0.190
0.035
0.147
0.105
0.155
0.025
0.562
0.060
0.210
0.120
0.110
0.055
0.255
0.050
–––
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.46
12.70
1.15
4.83
2.54
2.04
1.15
5.97
0.00
1.15
–––
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.64
14.27
1.52
5.33
3.04
2.79
1.39
6.47
1.27
–––
A
K
Q
Z
0.570
0.380
0.160
0.025
0.142
0.095
0.110
0.018
0.500
0.045
0.190
0.100
0.080
0.045
0.235
0.000
0.045
–––
STYLE 5:
1
2
3
U
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
H
L
R
V
J
G
T
U
V
D
N
Z
0.080
2.04
CASE 221A–06
ISSUE Y
Motorola TMOS Power MOSFET Transistor Device Data
7
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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MTP52N06VL/D
◊
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