MTP6N60EAJ [MOTOROLA]

暂无描述;


型号：	MTP6N60EAJ
厂家：	MOTOROLA
描述：	暂无描述晶体晶体管功率场效应晶体管开关脉冲局域网
文件：	总8页 (文件大小：160K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Order this document

by MTP6N60E/D

SEMICONDUCTOR TECHNICAL DATA

Motorola Preferred Device

N–Channel Enhancement–Mode Silicon Gate

TMOS POWER FET

6.0 AMPERES

600 VOLTS

This high voltage MOSFET uses an advanced termination

scheme to provide enhanced voltage–blocking capability without

degrading performance over time. In addition, this advanced TMOS

E–FET is designed to withstand high energy in the avalanche and

commutation modes. The new energy efficient design also offers a

drain–to–source diode with a fast recovery time. Designed for high

voltage, high speed switching applications in power supplies,

converters and PWM motor controls, these devices are particularly

well suited for bridge circuits where diode speed and commutating

safe operating areas are critical and offer additional safety margin

against unexpected voltage transients.

= 1.2 OHMS

DS(on)

•

Robust High Voltage Termination

Avalanche Energy Specified

Source–to–Drain Diode Recovery Time Comparable to a Discrete

Fast Recovery Diode

•

Diode is Characterized for Use in Bridge Circuits

and V

Specified at Elevated Temperature

DSS

DS(on)

CASE 221A–06, Style 5

TO–220AB

MAXIMUM RATINGS (T = 25°C unless otherwise noted)

Rating

Symbol

Value

600

Unit

Vdc

Drain–to–Source Voltage

DSS

Drain–to–Gate Voltage (R

= 1.0 MΩ)

DGR

600

Gate–to–Source Voltage — Continuous

— Non–Repetitive (t ≤ 10 ms)

±20

±40

Vdc

Vpk

GSM

Drain Current — Continuous

— Continuous @ 100°C

— Single Pulse (t ≤ 10 µs)

6.0

4.6

Adc

Apk

Total Power Dissipation

Derate above 25°C

125

1.0

Watts

W/°C

Operating and Storage Temperature Range

T , T

J stg

–55 to 150

°C

Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C

= 100 Vdc, V

= 10 Vdc, I = 2.0 Apk, L = 10 mH, R = 25 Ω)

GS L G

405

Thermal Resistance — Junction to Case°

— Junction to Ambient°

1.0

62.5

°C/W

°C

θJC

θJA

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds

260

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

Motorola TMOS Power MOSFET Transistor Device Data

Motorola, Inc. 1997

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

(BR)DSS

= 0 Vdc, I = 0.25 µAdc)

600

—

689

—

Vdc

mV/°C

Temperature Coefficient (Positive)

Zero Gate Voltage Drain Current

µAdc

DSS

= 600 Vdc, V

= 0 Vdc)

= 0 Vdc, T = 125°C)

—

1.0

Gate–Body Leakage Current (V

= ±20 Vdc, V

= 0 Vdc)

—

100

nAdc

GSS

ON CHARACTERISTICS (1)

Gate Threshold Voltage

GS(th)

= V , I = 250 µAdc)

2.0

—

3.0

7.1

4.0

—

Vdc

mV/°C

Temperature Coefficient (Negative)

Static Drain–to–Source On–Resistance (V

Drain–to–Source On–Voltage

= 10 Vdc, I = 3.0 Adc)

—

0.94

1.2

Ohms

Vdc

DS(on)

= 10 Vdc, I = 6.0 Adc)

—

6.0

—

8.6

7.6

= 10 Vdc, I = 3.0 Adc, T = 125°C)

Forward Transconductance (V

= 15 Vdc, I = 3.0 Adc)

2.0

5.5

—

mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

—

1498

158

2100

220

iss

= 25 Vdc, V

f = 1.0 MHz)

= 0 Vdc,

Output Capacitance

oss

Reverse Transfer Capacitance

rss

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time

—

d(on)

= 300 Vdc, I = 6.0 Adc,

Rise Time

= 10 Vdc,

Turn–Off Delay Time

Fall Time

d(off)

= 9.1 Ω)

Gate Charge

35.5

8.1

14.1

15.8

= 300 Vdc, I = 6.0 Adc,

= 10 Vdc)

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (1)

Vdc

(I = 6.0 Adc, V

= 0 Vdc)

= 0 Vdc, T = 125°C)

—

0.83

0.72

1.2

—

(I = 6.0 Adc, V

Reverse Recovery Time

—

266

166

100

2.5

—

(I = 6.0 Adc, V

= 0 Vdc,

dI /dt = 100 A/µs)

Reverse Recovery Stored Charge

µC

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from contact screw on tab to center of die)

(Measured from the drain lead 0.25″ from package to center of die)

—

3.5

4.5

—

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

—

7.5

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.

(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

= 10 V

≥ 10 V

= 25

°C

6 V

7 V

8 V

5 V

4 V

100°C

25°C

= –55

°C

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics

Figure 2. Transfer Characteristics

1.4

1.3

1.2

1.1

2.5

2.0

1.5

1.0

0.5

= 25°C

= 10 V

= 100°C

= 10 V

15 V

25°C

1.0

0.9

0.8

–55°C

, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current

and Temperature

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

2.5

10000

1000

= 10 V

= 0 V

= 3 A

= 125°C

100°C

1.5

100

0.5

25°C

–50

–25

100

125

150

100

200

300

400

500

600

T , JUNCTION TEMPERATURE (

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 5. On–Resistance Variation with

Temperature

Figure 6. Drain–To–Source Leakage

Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled.

The lengths of various switching intervals (∆t) are deter-

mined by how fast the FET input capacitance can be charged

by current from the generator.

The capacitance (C ) is read from the capacitance curve at

a voltage corresponding to the off–state condition when cal-

iss

culating t

and is read at a voltage corresponding to the

d(on)

on–state when calculating t

d(off)

At high switching speeds, parasitic circuit elements com-

plicate the analysis. The inductance of the MOSFET source

lead, inside the package and in the circuit wiring which is

common to both the drain and gate current paths, produces a

voltage at the source which reduces the gate drive current.

The voltage is determined by Ldi/dt, but since di/dt is a func-

tion of drain current, the mathematical solution is complex.

The MOSFET output capacitance also complicates the

mathematics. And finally, MOSFETs have finite internal gate

resistance which effectively adds to the resistance of the

driving source, but the internal resistance is difficult to mea-

sure and, consequently, is not specified.

The resistive switching time variation versus gate resis-

tance (Figure 9) shows how typical switching performance is

affected by the parasitic circuit elements. If the parasitics

were not present, the slope of the curves would maintain a

value of unity regardless of the switching speed. The circuit

used to obtain the data is constructed to minimize common

inductance in the drain and gate circuit loops and is believed

readily achievable with board mounted components. Most

power electronic loads are inductive; the data in the figure is

taken with a resistive load, which approximates an optimally

snubbed inductive load. Power MOSFETs may be safely op-

erated into an inductive load; however, snubbing reduces

switching losses.

The published capacitance data is difficult to use for calculat-

ing rise and fall because drain–gate capacitance varies

greatly with applied voltage. Accordingly, gate charge data is

used. In most cases, a satisfactory estimate of average input

current (I

) can be made from a rudimentary analysis of

G(AV)

the drive circuit so that

t = Q/I

G(AV)

During the rise and fall time interval when switching a resis-

tive load, V remains virtually constant at a level known as

the plateau voltage, V

. Therefore, rise and fall times may

SGP

be approximated by the following:

t = Q x R /(V

– V )

GSP

t = Q x R /V

GSP

where

= the gate drive voltage, which varies from zero to V

= the gate drive resistance

and Q and V

are read from the gate charge curve.

GSP

During the turn–on and turn–off delay times, gate current is

not constant. The simplest calculation uses appropriate val-

ues from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

= R

In [V

/(V

GG GG

– V

)]

GSP

d(on)

iss

In (V

GG GSP

)

d(off)

iss

3200

10000

= 0 V

V = 0 V

= 25°C

= 0 V

iss

2400

1600

1000

100

oss

iss

rss

800

oss

rss

100

1000

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 7b. High Voltage Capacitance Variation

Figure 7a. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

300

200

1000

100

= 300 V

= 6 A

= 10 V

= 25°C

d(off)

100

d(on)

= 6 A

= 25°C

, GATE RESISTANCE (OHMS)

100

Q , TOTAL CHARGE (nC)

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

= 0 V

= 25

°C

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous drain–to–source voltage and

drain current that a transistor can handle safely when it is for-

ward biased. Curves are based upon maximum peak junc-

able operation, the stored energy from circuit inductance dis-

sipated in the transistor while in avalanche must be less than

the rated limit and adjusted for operating conditions differing

from those specified. Although industry practice is to rate in

terms of energy, avalanche energy capability is not a con-

stant. The energy rating decreases non–linearly with an in-

crease of peak current in avalanche and peak junction

temperature.

tion temperature and a case temperature (T ) of 25°C. Peak

repetitive pulsed power limits are determined by using the

thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal Resistance–Gener-

al Data and Its Use.”

Although many E–FETs can withstand the stress of drain–

to–source avalanche at currents up to rated pulsed current

Switching between the off–state and the on–state may tra-

verse any load line provided neither rated peak current (I

)

) is exceeded and the transition time

), the energy rating is specified at rated continuous cur-

nor rated voltage (V

DSS

rent (I ), in accordance with industry custom. The energy rat-

(t ,t ) do not exceed 10 µs. In addition the total power aver-

r f

ing must be derated for temperature as shown in the

accompanying graph (Figure 12). Maximum energy at cur-

aged over a complete switching cycle must not exceed

– T )/(R ).

J(MAX)

θJC

rents below rated continuous I can safely be assumed to

A Power MOSFET designated E–FET can be safely used

in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

equal the values indicated.

SAFE OPERATING AREA

100

450

400

350

= 20 V

SINGLE PULSE

= 25

= 6 A

°C

10 µs

300

250

200

150

100

100 µs

1 ms

1.0

0.1

10 ms

LIMIT

DS(on)

THERMAL LIMIT

PACKAGE LIMIT

100

125

150

0.1

100

1000

T , STARTING JUNCTION TEMPERATURE (

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

D = 0.5

0.2

0.1

0.05

(pk)

(t) = r(t) R

JC θJC

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

0.02

READ TIME AT t

0.01

SINGLE PULSE

– T = P

R (t)

(pk) θJC

J(pk)

DUTY CYCLE, D = t /t

1 2

0.01

0.00001

0.0001

0.001

0.01

t, TIME (SECONDS)

0.1

Figure 13. Thermal Response

di/dt

TIME

0.25 I

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE DIMENSIONS

NOTES:

SEATING

PLANE

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

–T–

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL

BODY AND LEAD IRREGULARITIES ARE

ALLOWED.

INCHES

MIN

MILLIMETERS

DIM

MAX

0.620

0.405

0.190

0.035

0.147

0.105

0.155

0.025

0.562

0.060

0.210

0.120

0.110

0.055

0.255

0.050

–––

MIN

14.48

9.66

4.07

0.64

3.61

2.42

2.80

0.46

12.70

1.15

4.83

2.54

2.04

1.15

5.97

0.00

1.15

–––

MAX

15.75

10.28

4.82

0.88

3.73

2.66

3.93

0.64

14.27

1.52

5.33

3.04

2.79

1.39

6.47

1.27

–––

0.570

0.380

0.160

0.025

0.142

0.095

0.110

0.018

0.500

0.045

0.190

0.100

0.080

0.045

0.235

0.000

0.045

–––

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

0.080

2.04

CASE 221A–06

ISSUE Y

Motorola TMOS Power MOSFET Transistor Device Data

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola

datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”

must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of

others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury

ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

Motorola was negligent regarding the design or manufacture of the part. Motorola and

Opportunity/Affirmative Action Employer.

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal

Mfax is a trademark of Motorola, Inc.

How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;

JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1,

P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488

Customer Focus Center: 1–800–521–6274

Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1–602–244–6609

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

Motorola Fax Back System

– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

– http://sps.motorola.com/mfax/

HOME PAGE: http://motorola.com/sps/

MTP6N60E/D

◊

Motorola TMOS Power MOSFET Transistor Device Data

MTP6N60EAJ [MOTOROLA]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E