MTW14N50E [MOTOROLA]
TMOS POWER FET 14 AMPERES 500 VOLTS RDS(on) = 0.40 OHM; TMOS功率FET 14安培500伏的RDS（on ） = 0.40 OHM
| 型号： | MTW14N50E |
| 厂家： | 
MOTOROLA |
| 描述： | TMOS POWER FET 14 AMPERES 500 VOLTS RDS(on) = 0.40 OHM |
| 文件： | 总8页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MTW14N50E/D
SEMICONDUCTOR TECHNICAL DATA
Motorola Preferred Device
TMOS POWER FET
14 AMPERES
500 VOLTS
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
R
= 0.40 OHM
DS(on)
•
Designed to Replace External Zener Transient Suppressor —
Absorbs High Energy in the Avalanche Mode
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
•
D
•
•
Diode is Characterized for Use in Bridge Circuits
I
and V
Specified at Elevated Temperature
DSS
DS(on)
G
CASE 340K–01, Style 1
TO–247AE
S
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Symbol
Value
500
Unit
Vdc
Vdc
Vdc
Adc
Drain–Source Voltage
V
DSS
Drain–Gate Voltage (R
GS
= 1.0 MΩ)
V
DGR
500
Gate–Source Voltage — Continuous
V
GS
±20
Drain Current — Continuous
Drain Current — Continuous @ 100°C
I
I
14
9.0
60
D
D
Drain Current — Single Pulse (t ≤ 10 µs)
I
Apk
p
DM
Total Power Dissipation
Derate above 25°C
P
D
180
1.44
Watts
W/°C
Operating and Storage Temperature Range
T , T
stg
–55 to 150
860
°C
J
Single Pulse Drain–to–Source Avalanche Energy — STARTING T = 25°C
E
AS
mJ
J
(V
DD
= 50 Vdc, V
= 10 Vpk, I = 14 Apk, L = 8.8 mH, R = 25 Ω )
GS L G
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
R
θJC
R
θJA
0.7
40
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
T
L
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4
Motorola, Inc. 1996
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
V
(BR)DSS
(V
GS
= 0 V, I = 250 µAdc)
500
—
—
520
—
—
Vdc
mV/°C
D
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
µAdc
DSS
GSS
(V
DS
(V
DS
= 500 Vdc, V
= 500 Vdc, V
= 0)
—
—
—
—
250
1000
GS
GS
= 0, T = 125°C)
J
Gate–Body Leakage Current (V
= ±20 Vdc, V
= 0)
DS
I
—
—
100
nAdc
GS
ON CHARACTERISTICS*
Gate Threshold Voltage
V
GS(th)
(V
DS
= V , I = 250 µAdc)
2.0
—
3.2
7.0
4.0
—
Vdc
mV/°C
GS
D
Temperature Coefficient (Negative)
Static Drain–Source On–Resistance (V
= 10 Vdc, I = 7.0 Adc)
R
V
—
0.32
0.40
Ohm
Vdc
GS
D
DS(on)
Drain–Source On–Voltage (V
= 10 Vdc)
GS
DS(on)
(I = 14 Adc)
—
—
—
—
6.7
5.6
D
(I = 7.0 Adc, T = 125°C)
D
J
Forward Transconductance (V
= 15 Vdc, I = 7.0 Adc)
g
FS
5.0
—
—
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
—
—
—
2510
280
67
3510
392
94
iss
(V
DS
= 25 Vdc, V
GS
f = 1.0 MHz)
= 0,
Output Capacitance
C
oss
Reverse Transfer Capacitance
C
rss
SWITCHING CHARACTERISTICS*✝
Turn–On Delay Time
t
—
—
—
—
—
—
—
—
28
80
80
60
65
17
47
34
60
160
160
120
85
ns
d(on)
(V
= 250 Vdc, I = 14 Adc,
D
Rise Time
DD
t
r
V
= 10 Vdc,
GS
G
Turn–Off Delay Time
Fall Time
t
d(off)
R
= 4.7 Ω)
t
f
Gate Charge
Q
T
Q
1
Q
2
Q
3
nC
—
(V
= 400 Vdc, I = 14 Adc,
DS
D
V
GS
= 10 Vdc)
—
—
SOURCE–DRAIN DIODE CHARACTERISTICS*
Forward On–Voltage
V
—
—
1.0
0.9
1.6
—
Vdc
ns
(I = 14 Adc, V
= 0)
SD
S
GS
= 0, T = 125°C)
(I = 14 Adc, V
S
GS
J
Reverse Recovery Time
t
—
—
—
—
390
245
145
5.35
—
—
—
—
rr
t
a
(I = 14 Adc, V
= 0,
S
GS
dI /dt = 100 A/µs, V
= 0)
S
GS
t
b
Reverse Recovery Stored Charge
Q
µC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
—
—
5.0
13
—
—
nH
nH
D
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
✝Switching characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
20
18
16
14
20
7 V
10 V
T
= 25
°C
18
16
14
6 V
V
≥ 10 V
J
DS
12
10
8
12
10
8
–55
°C
T
= 100°C
J
V
= 5 V
25°
C
GS
6
6
4
4
2
2
0
4 V
9
0
0
1
2
3
4
5
6
7
8
10
0
0
0
1
2
3
4
5
6
7
8
9
10
V
, GATE–TO–SOURCE VOLTAGE (VOLTS)
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
GS
DS
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
1.0
0.38
0.36
0.34
0.32
0.30
0.28
0.26
0.24
0.22
0.20
V
= 10V
GS
T
= 25°C
J
0.8
0.6
0.4
0.2
0.0
T
= 100°C
J
V
= 10 V
GS
T
= 25°C
J
V
= 15 V
GS
T
= –55
°C
J
0
4
8
12
16
20
24
28
4
8
12
16
20
24
28
I
, DRAIN CURRENT (AMPS)
I
, DRAIN CURRENT (AMPS)
D
D
Figure 3.On–Resistance versus Drain Current
Figure 4.On–Resistance versus Drain Current
2.5
100000
V
= 0 V
GS
T
T
= 125
= 100
°
C
C
J
J
20000
10000
2.0
1.5
1.0
2000
1000
°
200
100
T
= 25°C
J
V
= 10 V
GS
= 7 A
0.5
0
I
D
20
10
–50
0
50
100
150
200
100
V , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
200
300
400
500
T , JUNCTION TEMPERATURE (
°C)
J
Figure 5.On–Resistance Variation
With Temperature
Figure 6.Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off–state condition when cal-
culating t
and is read at a voltage corresponding to the
d(on)
on–state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 10) shows how typical switching performance
is affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
) can be made from a rudimentary analysis of
G(AV)
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resis-
tive load, V remains virtually constant at a level known as
GS
the plateau voltage, V
. Therefore, rise and fall times may
SGP
be approximated by the following:
t = Q x R /(V
– V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
V
= the gate drive voltage, which varies from zero to V
GG
GG
R
= the gate drive resistance
G
and Q and V
are read from the gate charge curve.
GSP
2
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R
= R
C
C
In [V
/(V
GG GG
– V
)]
GSP
d(on)
G
iss
In (V
/V
GG GSP
)
d(off)
G
iss
8000
10000
T
= 25°C
V
= 0 V
J
T
= 25
°C
V
= 0 V
DS
J
GS
7000
6000
5000
4000
C
iss
V
= 0 V
GS
2000
1000
C
iss
200
100
C
oss
3000
2000
C
rss
C
oss
1000
0
20
10
C
rss
10
5
0
5
10
15
20
25
1
2
10
20
100
200
1000
V
V
DS
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
GS
DS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7a. Low Voltage Capacitance Variation
Figure 7b. High Voltage Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
15
12
9
500
400
300
200
10000
T
= 25°C
= 14 A
J
t
t
T
I
V
= 25
J
°
C
d(off)
I
V
D
V
= 14 A
DS
= 400 V
D
DD
GS
DS
2000
1000
= 250 V
= 10 V
Q
T
V
d(on)
Q
1
200
100
6
3
0
Q
2
t
r
V
GS
100
0
t
f
20
10
Q
3
0
10
20
30
40
50
60
70
80
90
100
1
2
10
R , GATE RESISTANCE (OHMS)
G
20
100
200
1000
Q , TOTAL CHARGE (nC)
T
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
14
T
V
= 25°C
J
12
10
8
= 0 V
GS
dI /dt = 100 A/µs
S
6
4
2
0
0
0.2
0.4
0.6
0.8
1
V
, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain–to–source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction tem-
operation, the stored energy from circuit inductance dissi-
pated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
perature and a case temperature (T ) of 25°C. Peak repetitive
C
pulsed power limits are determined by using the thermal re-
sponse data in conjunction with the procedures discussed in
AN569, “Transient Thermal Resistance–General Data and Its
Use.”
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (I
)
DM
(I
), the energy rating is specified at rated continuous cur-
DM
nor rated voltage (V
) is exceeded and the transition time
DSS
rent (I ), in accordance with industry custom. The energy rat-
D
(t ,t ) do not exceed 10µs. In addition the total power averaged
r f
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
over a complete switching cycle must not exceed (T
–
J(MAX)
T )/(R
).
C
θJC
rents below rated continuous I can safely be assumed to
A Power MOSFET designated E–FET can be safely used in
switching circuits with unclamped inductive loads. For reliable
D
equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
5
900
800
700
600
500
100
V
= 20 V
GS
SINGLE PULSE
= 25
10 µs
PEAK I = 14 A
D
V
= 50 V
T
°C
DD
C
20
10
100 µs
1 ms
400
300
200
100
0
2
1
10 ms
dc
THERMAL LIMIT
PACKAGE LIMIT
0.2
0.1
R
LIMIT
DS(on)
25
50
75
100
125
C)
150
1
2
10
20
100
200
1000
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
DS
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1
D = 0.5
= 0.2
0.2
= 0.1
0.1
= 0.05
= 0.02
= 0.01
R
R
(t) = r(t) R
θ
θ
θ
JC
JC
JC
°C/W MAX
0.02
0.01
DUTY CYCLE, D = t /t
1 2
= 0.7
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
P
(pk)
SINGLE PULSE
t
1
1
(pk)
t
2
T
– T = P
R
(t)
JC
J(pk)
C
θ
0.002
0.001
0.01
0.02
0.1
0.2
1
2
10
20
100
200
1000
t, TIME (ms)
Figure 13. Thermal Response
6
Motorola TMOS Power MOSFET Transistor Device Data
PACKAGE DIMENSIONS
–T–
E
–Q–
M
M
0.25 (0.010)
T B
NOTES:
–B–
C
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
4
2. CONTROLLING DIMENSION: MILLIMETER.
U
L
MILLIMETERS
INCHES
DIM
A
B
C
D
E
MIN
19.7
15.3
4.7
1.0
1.27 REF
2.0
5.5 BSC
2.2
0.4
14.2
MAX
20.3
15.9
5.3
MIN
MAX
0.799
0.626
0.209
0.055
A
K
0.776
0.602
0.185
0.039
0.050 REF
0.079
R
1
2
3
1.4
F
2.4
0.094
STYLE 1:
PIN 1. GATE
–Y–
G
H
J
K
L
0.216 BSC
P
2.6
0.8
14.8
0.087
0.016
0.559
0.102
0.031
0.583
2. DRAIN
3. SOURCE
4. DRAIN
5.5 NOM
0.217 NOM
P
3.7
3.55
5.0 NOM
5.5 BSC
3.0
4.3
3.65
0.146
0.140
0.197 NOM
0.217 BSC
0.118 0.134
0.169
0.144
V
H
Q
R
U
V
F
J
G
D
3.4
M
S
0.25 (0.010)
Y
Q
CASE 340K–01
ISSUE O
Motorola TMOS Power MOSFET Transistor Device Data
7
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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