PCF5232CAB80_技术文档

Product Brief

MCF5235PB/D

Rev. 0, 5/2004

MCF523x Family

Integrated

Microprocessor

Product Brief

The MCF523x is a family of highly-integrated 32-bit microcontrollers based on the V2

ColdFire microarchitecture. Featuring a 16 or 32 channel eTPU, 64 Kbytes of internal SRAM,

a 2-bank SDRAM controller, four 32-bit timers with dedicated DMA, a 4 channel DMA

controller, up to 2 CAN modules, 3 UA a queued SPI, the MCF523x family has been designed

for general purpose industrial control applications. It is also a high-performance upgrade for

users of the MC68332. This document provides an overview of the MCF523x microcontroller

family, focusing on its highly diverse feature set, as well as providing an “at-a-glance”

comparison to the MC68332.

This 32-bit device is based on the Version 2 ColdFire reduced instruction set computer (RISC)

core operating at a core frequency up to 150 MHz and bus frequency up to 75 MHz. On-chip

modules include:

•

V2 ColdFire core with enhanced multiply-accumulate unit (EMAC) providing 144

Dhrystone 2.1 MIPS @ 150 MHz

•

eTPU with 16 or 32 channels, 6 Kbytes of code memory and 1.5 Kbytes of data

memory with Nexus Class 1 debug support

•

64 Kbytes of internal SRAM

External bus speed of one half the CPU operating frequencey (75 MHz bus @ 150

MHz core)

•

10/100 Mbps bus-mastering Ethernet controller

8 Kbytes of configurable instruction/data cache

Three universal asynchronous receiver/transmitters (UARTs)

Controller area network 2.0B (FlexCAN) module

— Optional second FlexCAN module multiplexed with the third UART

Inter-integrated circuit (I²C™) bus controller

•

Queued serial peripheral interface (QSPI) module

Hardware cryptography accelerator (optional)

— Random number generator

— DES/3DES/AES block cipher engine

— MD5/SHA-1/HMAC accelerator

•

Four channel 32-bit direct memory access (DMA) controller

Four channel 32-bit input capture/output compare timers with optional DMA support

MCF523x Family Configurations

•

Four channel 16-bit periodic interrupt timers (PITs)

Programmable software watchdog timer

Interrupt controller capable of handling up to 126 interrupt sources

Clock module with integrated phase locked loop (PLL)

External bus interface module including a 2-bank synchronous DRAM controller

32-bit non-multiplexed bus with up to 8 chip select signals that support paged mode Flash

memories

To locate any published errata or updates for this document, refer to the ColdFire products website at

http://www.motorola.com/coldfire.

1 MCF523x Family Configurations

Table 1. MCF523x Family Configurations

Module

5232

5233

5234

5235

ColdFire V2 Core with EMAC

(Enhanced Multiply-Accumulate

Unit)

x

Enhanced Time Processor Unit

with memory (eTPU)

16-ch

6K

32-ch

6K

16-ch

6K

16-ch

6K

up to 150 MHz

up to 144

System Clock

Performance (Dhrystone/2.1 MIPS)

Instruction/Data Cache

8 Kbytes

64 Kbytes

Static RAM (SRAM)

Interrupt Controllers (INTC)

Edge Port Module (EPORT)

External Interface Module (EIM)

2

x

2

x

2

x

2

x

4-channel Direct-Memory Access

(DMA)

x

SDRAM Controller

Fast Ethernet Controller (FEC)

—

Cryptography Hardware

Accelerators

—

x

Watchdog Timer (WDT)

x

4

x

3

x

4

x

3

x

4

x

3

x

4

x

3

x

Four Periodic Interrupt Timers (PIT)

32-bit DMA Timers

QSPI

UART(s)

I²C

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BlockDiagram

Table 1. MCF523x Family Configurations (continued)

Module

5232

5233

5234

5235

FlexCAN 2.0B - Controller-Area

Network communication module

1

2

1

2

General Purpose I/O Module

(GPIO)

x

JTAG - IEEE 1149.1 Test Access

Port

160 QFP

196

MAPBGA

Package

256

MAPBGA MAPBGA MAPBGA

2 Block Diagram

The superset device in the MCF523x family comes in a 256 mold array process ball grid array (MAPBGA)

package. Figure 1 shows a top-level block diagram of the MCF5235.

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Block Diagram

SDRAMC

QSPI

EIM

I2C_SDA

I2C_SCL

UnTXD

CHIP

SELECTS

(To/From SRAM backdoor)

UnRXD

EBI

UnRTS

INTC0 INTC1

Arbiter

UnCTS

DTOUTn

DTINn

FEC

FAST

CANRX

CANTX

eTPU

ETHERNET

(To/From PADI)

CONTROLLER

(FEC)

UART

0

UART UART

2

QSPI

I C

1

2

SDRAMC

D[31:0]

A[23:0]

DTIM

3

DTIM DTIM

DTIM

0

(To/From PADI)

4 CH DMA

1

2

R/W

(To/From

PADI)

CS[3:0]

TA

DREQ[2:0]

DACK[2:0]

TSIZ[1:0]

TEA

JTAG_EN

V2 ColdFire CPU

BS[3:0]

EMAC

DIV

NEXUS

eTPU

JTAG

TAP

64 Kbytes

SRAM

(8Kx16)x4

8 Kbytes

CACHE

(1Kx32)x2

PORTS

(GPIO)

(To/From PADI)

CIM

Watchdog

Timer

(To/From Arbiter)

SKHA

RNGA

MDHA

PLL

CLKGEN

PIT0

PIT1

PIT2

PIT3

FlexCAN

(x2)

(To/From INTC)

Edge

Port

Cryptography

Modules

Figure 1. MCF5235 Block Diagram

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Features

3 Features

This document contains information on a new product. Specifications and information herein are subject to

change without notice.

3.1 Feature Overview

•

Version 2 ColdFire variable-length RISC processor core

— Static operation

— 32-bit address and data path on-chip

— Processor core runs at twice the bus frequency

— Sixteen general-purpose 32-bit data and address registers

— Implements the ColdFire Instruction Set Architecture, ISA_A, with extensions to support the

user stack pointer register, and 4 new instructions for improved bit processing

— Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit

signal processing algorithms

— Illegal instruction decode that allows for 68K emulation support

Enhanced Time Processor Unit (eTPU)

— Event triggered VLIW processor timer subsystem

— 32 channels

•

— 24-bit timer resolution

— 6 Kbyte of code memory and 1.5 Kbyte of data memory

— Variable number of parameters allocatable per channel

— Double match/capture channels

— Angle mode support

— DMA and interrupt request support

— Nexus Class 1 Debug support

•

System debug support

— Integrated debug supports both ColdFire Debug and Nexus class 1 features on a single port

with cross triggering operations for ease of use

— Unified programming model including both ColdFire and Nexus debug registers

— Real time trace for determining dynamic execution path

— Background debug mode (BDM) for in-circuit debugging

— Real time debug support, with two user-visible hardware breakpoint registers (PC and address

with optional data) that can be configured into a 1- or 2-level trigger

•

On-chip memories

— 8-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache

— 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus

masters (e.g., DMA, FEC)

Fast Ethernet Controller (FEC)

— 10 BaseT capability, half duplex or full duplex

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Features

— 100 BaseT capability, half duplex or full duplex

— On-chip transmit and receive FIFOs

— Built-in dedicated DMA controller

— Memory-based flexible descriptor rings

— Media independent interface (MII) to external transceiver (PHY)

FlexCAN Modules (up to 2)

•

— Full implementation of the CAN protocol specification version 2.0B

– Standard Data and Remote Frames (up to 109 bits long)

– Extended Data and Remote Frames (up to 127 bits long)

– 0–8 bytes data length

– Programmable bit rate up to 1 Mbit/sec

— Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 bytes data length

each, configurable as Rx or Tx, all supporting standard and extended messages

— Unused MB space can be used as general purpose RAM space

— Listen only mode capability

— Content-related addressing

— Three programmable mask registers: global (for MBs 0-13), special for MB14 and special for

MB15

— Programmable transmit-first scheme: lowest ID or lowest buffer number

— “Time stamp” based on 16-bit free-running timer

— Global network time, synchronized by a specific message

Three Universal Asynchronous Receiver Transmitters (UARTs)

— 16-bit divider for clock generation

•

— Interrupt control logic

— Maskable interrupts

— DMA support

— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity

— Up to 2 stop bits in 1/16 increments

— Error-detection capabilities

— Modem support includes request-to-send (URTS) and clear-to-send (UCTS) lines for two

UARTs

— Transmit and receive FIFO buffers

•

I²C Module

— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads

— Fully compatible with industry-standard I²C bus

— Master or slave modes support multiple masters

— Automatic interrupt generation with programmable level

Queued Serial Peripheral Interface (QSPI)

— Full-duplex, three-wire synchronous transfers

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— Up to four chip selects available

— Master mode operation only

— Programmable master bit rates

— Up to 16 pre-programmed transfers

Four 32-bit DMA Timers

•

— 13-ns resolution at 75MHz

— Programmable sources for clock input, including an external clock option

— Programmable prescaler

— Input-capture capability with programmable trigger edge on input pin

— Output-compare with programmable mode for the output pin

— Free run and restart modes

— Maskable interrupts on input capture or reference-compare

— DMA trigger capability on input capture or reference-compare

Four Periodic Interrupt Timers (PITs)

•

— 16-bit counter

— Selectable as free running or count down

Software Watchdog Timer

— 16-bit counter

— Low power mode support

Phase Locked Loop (PLL)

— Crystal or external oscillator reference

— 8 to 25 MHz reference frequency for normal PLL mode

— 24 to 75 MHz oscillator reference frequency for 1:1 mode

— Separate clock output pin

•

Interrupt Controllers (x2)

— Support for up to 110 interrupt sources organized as follows:

– 103 fully-programmable interrupt sources

– 7 fixed-level external interrupt sources

— Unique vector number for each interrupt source

— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)

— Support for hardware and software interrupt acknowledge (IACK) cycles

— Combinatorial path to provide wake-up from low power modes

DMA Controller

•

— Four fully programmable channels

— Dual-address and single-address transfer support with 8-, 16- and 32-bit data capability along

with support for 16-byte (4 x 32-bit) burst transfers

— Source/destination address pointers that can increment or remain constant

— 24-bit byte transfer counter per channel

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Features

— Auto-alignment transfers supported for efficient block movement

— Bursting and cycle steal support

— Software-programmable connections between the four DMA channels and the 14 DMA

requesters in the UARTs (6), 32-bit timers (4), and external logic (4)

•

External Bus Interface

— Glueless connections to external memory devices (e.g., SRAM, Flash, ROM, etc.)

— SDRAM controller supports 8-, 16-, and 32-bit wide memory devices

— Support for n-1-1-1 burst fetches from page mode Flash

— Glueless interface to SRAM devices with or without byte strobe inputs

— Programmable wait state generator

— 32-bit bidirectional data bus

— 24-bit address bus

— Up to eight chip selects available

— Byte/write enables (byte strobes)

— Ability to boot from external memories that are 8, 16, or 32 bits wide

Chip Integration Module (CIM)

•

— System configuration during reset

— Selects one of four clock modes

— Sets boot device and its data port width

— Configures output pad drive strength

— Unique part identification number and part revision number

— Reset

– Separate reset in and reset out signals

– Six sources of reset: Power-on reset (POR), External, Software, Watchdog, PLL loss of

clock, PLL loss of lock

– Status flag indication of source of last reset

General Purpose I/O interface

•

— Up to 142 bits of general purpose I/O

— Bit manipulation supported via set/clear functions

— Unused peripheral pins may be used as extra GPIO

JTAG support for system level board testing

3.2 V2 Core Overview

The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The

two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address generation and instruction

fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting

execution in the Operand Execution Pipeline (OEP). The OEP includes two pipeline stages. The first stage

decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction

execution and calculates operand effective addresses, if needed.

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Features

The V2 core implements the ColdFire Instruction Set Architecture Revision A with added support for a

separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the

MCF523x core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processing

capabilities. The EMAC implements a 4-stage execution pipeline, optimized for 32 x 32 bit operations, with

support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsigned

integers as well as signed fractional operands as well as a complete set of instructions to process these data

types. The EMAC provides superb support for execution of DSP operations within the context of a single

processor at a minimal hardware cost.

3.3 Enhanced Time Processor Unit (eTPU)

The eTPU is an intelligent programmable I/O controller with its own core and memory system, allowing it

to perform complex timing and I/O management independently of the CPU. The eTPU is essentially a

co-processor designed for timing control, I/O handling, serial communications, motor control. and engine

control applications and accesses data without the host CPU’s intervention. Consequently, the host CPU

setup and service times for each timer event are minimized or eliminated.

The eTPU is an enhanced version of the TPU module implemented on the MC68332 and MPC500 products.

Enhancements of the eTPU include a more powerful processor which handles high-level C code efficiently

and allows for more functionality and increased performace. Although there is no compatibility at

microcode level, the eTPU maintains several features of older TPU versions and is conceptually almost

identical. The eTPU library is a superset of the standard TPU library functions modified to take advantage

of enhancements in the eTPU. These, along with a C compiler, make it relatively easy to port older

applications. By providing source code for the Motorola library, it is possible for the eTPU to support the

users own function development.

The eTPU has up to 32 timer channels in addition to having 6 Kbytes of code memory and 1.5 Kbytes of

data memory that stores software modules downloaded at boot time and that can be mixed and matched as

required for any specific application.

3.3.1 eTPU Functions

Any one of the following four sets of functions can be loaded into the device.

3.3.1.1 Set 1 (General)

•

PWM – Full featured Pulse Width modulation

ICOC – Input Capture / Output Compare

PFM – Pulse and frequency measurement

PPA – Pulse / Period Accumulate

SM – Stepper motor

QOM – Queued Output Match for complex outputs

UART – Serial interface

SPI – Synchronous serial interface

POC – Protected Output Compare

SPWM – Synchronized Pulse Width Modulation

GPIO – General purpose I/O (only needed for Puma)

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Features

3.3.1.2 Set 2 (Automotive)

•

All functions from set 1

AngleClock - Engine position decoding based on the crank tooth signal

CamDecode - Engine position synchronization based on the cam signal

FuelControl - Control the fuel pulse delivery

SparkControl - Control the spark firing angle and dwell time

AnglePulse – Output signal based on angle

3.3.1.3 Set 3 (Motor Control 1)

•

All functions from set 1

DC – DC motor with permanent magnet

DCE – DC motor with separately excited stator windings

BLDC – Brushless DC motor with Hall sensors

QD - Quadrature decode function

HS - Hall sensor signals decode function

3.3.1.4 Set 4 (Motor Control 2)

•

All functions from set 1.

ACIM – 3-phase AC induction motor with V/Hz control

ACIMVC – 3-phase AC induction motor with vector control

PMSMVC – 3-phase PM motor with vector control

PMSMTVC – 3-phase PM motor with torque vector control

QD - Quadrature decode function

HS - Hall sensor signals decode function

3.4 Debug Module

The ColdFire processor core debug interface is provided to support system debugging in conjunction with

low-cost debug and emulator development tools. Through a standard debug interface, users can access

real-time trace and debug information. This allows the processor and system to be debugged at full speed

without the need for costly in-circuit emulators. The debug interface is a superset of the BDM interface

provided on Motorola’s 683xx family of parts.

The on-chip breakpoint resources include a total of 6 programmable registers—a set of address registers

(with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask register),

and one 32-bit PC register plus a 32-bit PC mask register. These registers can be accessed through the

dedicated debug serial communication channel or from the processor’s supervisor mode programming

model. The breakpoint registers can be configured to generate triggers by combining the address, data, and

PC conditions in a variety of single or dual-level definitions. The trigger event can be programmed to

generate a processor halt or initiate a debug interrupt exception.

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Features

To support program trace, the Version 2 debug module provides processor status (PST[3:0]) and debug data

(DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand data,

and branch target addresses defining processor activity at the CPU’s clock rate.

The integration of the eTPU on the MCF523x family marks the first time that ColdFire and Nexus debug

subsystems have been present in a single device. The eTPU’s Nexus functionality has been merged into the

standard ColdFire debug model. This includes access to the eTPU Nexus debug registers via the standard

ColdFire BDM serial interface or the processor WDEBUG instruction and run/halt cross triggering

capability between eTPU Nexus and ColdFire BDM.

3.5 JTAG

The MCF523x supports circuit board test strategies based on the Test Technology Committee of IEEE and

the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state

controller, an instruction register, and three test registers (a 1-bit bypass register, a 326-bit boundary-scan

register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register.

Test logic, implemented using static logic design, is independent of the device system logic.

The MCF523x implementation can do the following:

•

Perform boundary-scan operations to test circuit board electrical continuity

Sample MCF523x system pins during operation and transparently shift out the result in the

boundary scan register

•

Bypass the MCF523x for a given circuit board test by effectively reducing the boundary-scan

register to a single bit

•

Disable the output drive to pins during circuit-board testing

Drive output pins to stable levels

3.6 On-chip Memories

3.6.1 Cache

The 8-Kbyte cache can be configured into one of three possible organizations: an 8-Kbyte instruction cache,

an 8-Kbyte data cache or a split 4-Kbyte instruction/4-Kbyte data cache. The configuration is

software-programmable by control bits within the privileged Cache Configuration Register (CACR). In all

configurations, the cache is a direct-mapped single-cycle memory, organized as 512 lines, each containing

16 bytes of data. The memories consist of a 512-entry tag array (containing addresses and control bits) and

a 8-Kbyte data array, organized as 2048 x 32 bits.

If the desired address is mapped into the cache memory, the output of the data array is driven onto the

ColdFire core's local data bus, completing the access in a single cycle. If the data is not mapped into the tag

memory, a cache miss occurs and the processor core initiates a 16-byte line-sized fetch. The cache module

includes a 16-byte line fill buffer used as temporary storage during miss processing. For all data cache

configurations, the memory operates in write-through mode and all operand writes generate an external bus

cycle.

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Features

3.6.2 SRAM

The SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core can access

in a single cycle. The location of the memory block can be set to any 64-Kbyte boundary within the 4-Gbyte

address space. The memory is ideal for storing critical code or data structures, for use as the system stack,

or for storing FEC data buffers. Because the SRAM module is physically connected to the processor’s

high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from

the debug module.

The SRAM module is also accessible by the DMA and FEC non-core bus masters. The dual-ported nature

of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor

and a DMA device operate in alternate regions of the SRAM to maximize system performance. As an

example, system performance can be increased significantly if Ethernet packets are moved from the FEC

into the SRAM (rather than external memory) prior to any processing.

3.7 Fast Ethernet Controller (FEC)

The MCF523x’s integrated Fast Ethernet Controller (FEC) performs the full set of IEEE 802.3/Ethernet

CSMA/CD media access control and channel interface functions. The FEC supports connection and

functionality for the 10/100 Mbps 802.3 media independent interface (MII). It requires an external

transceiver (PHY) to complete the interface to the media.

3.8 FlexCAN

There are up to 2 FlexCAN modules on the MCF523x (refer to Table 1). The FlexCAN module is a

communication controller implementing the 2.0B CAN protocol. The CAN protocol is commonly used as

an industrial control serial data bus, meeting the specific requirements of real-time processing, reliable

operation in a harsh EMI environment, cost-effectiveness, and required bandwidth. FlexCAN contains 16

message buffers.

3.9 UARTs

The MCF523x contains three full-duplex UARTs that function independently. The three UARTs can be

clocked by the system bus clock, eliminating the need for an externally supplied clock. They can use DMA

requests on transmit-ready and receive-ready as well as interrupt requests for servicing. Flow control is only

available on two of the UARTs.

3.10 I²C Bus

The I²C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange,

minimizing the interconnection between devices. This bus is suitable for applications requiring occasional

communications over a short distance between many devices.

3.11 QSPI

The queued serial peripheral interface module provides a high-speed synchronous serial peripheral interface

with queued transfer capability. It allows up to 16 transfers to be queued at once, eliminating CPU

intervention between transfers.

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Features

3.12 Cryptography

The superset device, MCF5235, incorporates small, fast, dedicated hardware accelerators for random

number generation, message digest and hashing, and the DES, 3DES, and AES block cipher functions

allowing for the implementation of common Internet security protocol cryptography operations with

performance well in excess of software-only algorithms.

3.13 DMA Timers (DTIM0-DTIM3)

There are four independent, DMA-transfer-generating 32-bit timers (DTIM[3:0]) on the MCF523x. Each

timer module incorporates a 32-bit timer with a separate register set for configuration and control. The

timers can be configured to operate from the system clock or from an external clock source using one of the

DTINx signals. If the system clock is selected, it can be divided by 16 or 1. The input clock is further divided

by a user-programmable 8-bit prescaler which clocks the actual timer counter register (TCRn). Each of these

timers can be configured for input capture or reference compare mode. By configuring the internal registers,

each timer may be configured to assert an external signal, generate an interrupt on a particular event or cause

a DMA transfer.

3.14 Periodic Interrupt Timers (PIT0-PIT3)

The four periodic interrupt timers (PIT[3:0]) are 16-bit timers that provide precise interrupts at regular

intervals with minimal processor intervention. Each timer can either count down from the value written in

its PIT modulus register, or it can be a free-running down-counter.

3.15 Software Watchdog Timer

The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The watchdog counter is

a free-running down-counter that generates a reset on underflow. To prevent a reset, software must

periodically restart the countdown.

3.16 Clock Module and Phase Locked Loop (PLL)

The clock module contains a crystal oscillator (OSC), phase-locked loop (PLL), reduced frequency divider

(RFD), status/control registers, and control logic. To improve noise immunity, the PLL and OSC have their

own power supply inputs, VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins,

VDD and VSS.

3.17 Interrupt Controllers (INTC0/INTC1)

There are two interrupt controllers on the MCF523x, each of which can support up to 63 interrupt sources

each for a total of 126. Each interrupt controller is organized as 7 levels with 9 interrupt sources per level.

Each interrupt source has a unique interrupt vector, and 56 of the 63 sources of a given controller provide a

programmable level [1-7] and priority within the level.

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Features

3.18 DMA Controller

The Direct Memory Access (DMA) Controller Module provides an efficient way to move blocks of data

with minimal processor interaction. The DMA module provides four channels (DMA0-DMA3) that allow

byte, word, longword or 16-byte burst line transfers. These transfers are triggered by software explicitly

setting a DCRn[START] bit. Other sources include the DMA timer, external sources via the DREQ signal,

UARTs, and the eTPU. The DMA controller supports single or dual address to off-chip devices or dual

address to on-chip devices.

3.19 External Bus Interface (EBI)

The external bus interface handles the transfer of information between the core and memory, peripherals, or

other processing elements in the external address space. Features have been added to support external Flash

modules, for secondary wait states on reads and writes, and a signal to support Active-Low Address Valid

(a signal on most Flash memories).

Programmable chip-select outputs provide signals to enable external memory and peripheral circuits,

providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing.

Base memory address and block size are programmable, with some restrictions. For example, the starting

address must be on a boundary that is a multiple of the block size. Each chip select can be configured to

provide read and write enable signals suitable for use with most popular static RAMs and peripherals. Data

bus width (8-bit, 16-bit, or 32-bit) is programmable on all chip selects, and further decoding is available for

protection from user mode access or read-only access.

3.20 SDRAM Controller

The SDRAM controller provides all required signals for glueless interfacing to a variety of

JEDEC-compliant SDRAM devices. SRAS/SCAS address multiplexing is software configurable for

different page sizes. To maintain refresh capability without conflicting with concurrent accesses on the

address and data buses, SD_SRAS, SD_SCAS, SD_WE, SD_CS[1:0] and SD_CKE are dedicated SDRAM

signals.

3.21 Reset

The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the

system, and keep track of what caused the last reset. There are six sources of reset:

•

External

Power-on reset (POR)

Watchdog timer

Phase locked-loop (PLL) loss of lock

PLL loss of clock

Software

External reset on the RSTOUT pin is software-assertable independent of chip reset state. There are also

software-readable status flags indicating the cause of the last reset.

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Documentation

3.22 GPIO

Like the MC68332, unused bus interface and peripheral pins on the MCF523x can be used as discrete

general-purpose inputs and outputs. These are managed by a dedicated GPIO module that logically groups

all pins into ports located within a contiguous block of memory-mapped control registers.

All of the pins associated with the external bus interface may be used for several different functions. Their

primary function is to provide an external memory interface to access off-chip resources. When not used for

this, all of the pins may be used as general-purpose digital I/O pins. In some cases, the pin function is set by

the operating mode, and the alternate pin functions are not supported.

The digital I/O pins on the MCF523x are grouped into 8-bit ports. Some ports do not use all eight bits. Each

port has registers that configure, monitor, and control the port pins.

4 Documentation

Table 2 lists the documents that provide a complete description of the MCF523x and their development

support tools. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales

office, the Motorola Literature Distribution Center, or through the Motorola world-wide web address at

http://www.motorola.com/semiconductors.

Table 2. MCF523x Documentation

Motorola

Document

Number

Title

Revision

Status

MCF5232 RISC Microprocessor Hardware

Specifications

MCF5235EC/D

0

Available

MCF5235RM/D

MCF5235PB/D

MCF523xFS

eTPURM/D

MCF523x Reference Manual

MCF523x Product Brief

MCF523x Fact Sheet

eTPU User Manual

0

Available

This document

Available

—

In Process

The ColdFire Family of 32-Bit Microprocessors

Family Overview and Technology Roadmap

Available under

NDA

CFPRODFACT/D

MCF5xxxWP

0

MCF5xxxWP WHITE PAPER: Motorola ColdFire

VL RISC Processors

Available under

NDA

MAPBGAPP

CFPRM/D

MAPBGA 4-Layer Example

0

2

Available

ColdFire Family Programmer's Reference Manual

4.1 Document Revision History

Table 3 provides a revision history for this document.

Table 3. Document Revision History

Substantive Change(s)

Rev. No.

0

Initial release.

MOTOROLA

15

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

HOW TO REACH US:

USA / EUROPE / Locations Not Listed:

Motorola Literature Distribution

P.O. Box 5405

Denver, Colorado 80217

1-800-521-6274 or 480-768-2130

JAPAN:

Motorola Japan Ltd.

SPS, Technical Information Center

3-20-1, Minami-Azabu Minato-ku

Tokyo, 106-8573 Japan

81-3-3440-3569

ASIA/PACIFIC:

Motorola Semiconductors H.K. Ltd.

Silicon Harbour Centre

2 Dai King Street

Tai Po Industrial Estate

Tai Po, N.T., Hong Kong

852-26668334

HOME PAGE:

http://motorola.com/semiconductors

Information in this document is provided solely to enable system and software implementers to

use Motorola products. There are no express or implied copyright licenses granted hereunder to

design or fabricate any integrated circuits or integrated circuits based on the information in this

document.

Motorola reserves the right to make changes without further notice to any products herein.

Motorola makes no warranty, representation or guarantee regarding the suitability of its products

for any particular purpose, nor does Motorola assume any liability arising out of the application

or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters which may be provided in

Motorola data sheets and/or specifications can and do vary in different applications and actual

performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. Motorola does not

convey any license under its patent rights nor the rights of others. Motorola products are not

designed, intended, or authorized for use as components in systems intended for surgical

implant into the body, or other applications intended to support or sustain life, or for any other

application in which the failure of the Motorola product could create a situation where personal

injury or death may occur. Should Buyer purchase or use Motorola products for any such

unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers,

employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages,

and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that Motorola was negligent regarding the design or manufacture of the part.

MOTOROLA and the Stylized M Logo are registered in the U.S. Patent and Trademark Office.

All other product or service names are the property of their respective owners. Motorola, Inc. is

an Equal Opportunity/Affirmative Action Employer.

MCF5235PB/D, Rev. 0, 5/2004


型号：	PCF5232CAB80
厂家：	MOTOROLA
描述：	RISC Microprocessor, 32-Bit, 80MHz, CMOS, PQFP160 外围集成电路
文件：	总16页 (文件大小：570K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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