PPC7457RX1300LB_技术文档

Advance Information

MPC7457EC/D

Rev. 2, 7/2003

MPC7457

RISC Microprocessor

Hardware Speciﬁcations

This document is primarily concerned with the PowerPC™ MPC7457; however, unless

otherwise noted, all information here also applies to the MPC7447. The MPC7457 and

MPC7447 are implementations of the PowerPC microprocessor family of reduced instruction

set computer (RISC) microprocessors. This document describes pertinent electrical and

physical characteristics of the MPC7457. For functional characteristics of the processor, refer

to the MPC7450 RISC Microprocessor Family User’s Manual.

This document contains the following topics:

Topic

Page

Section 1.1, “Overview”

Section 1.2, “Features”

1

2

Section 1.3, “Comparison with the MPC7455, MPC7445, MPC7450, MPC7451,

and MPC7441”

7

10

33

35

41

47

61

Section 1.4, “General Parameters”

Section 1.5, “Electrical and Thermal Characteristics”

Section 1.6, “Pin Assignments”

Section 1.7, “Pinout Listings”

Section 1.8, “Package Description”

Section 1.9, “System Design Information”

Section 1.10, “Document Revision History”

Section 1.11, “Ordering Information”

To locate any published updates for this document, refer to the website at

http://www.motorola.com/semiconductors.

1.1 Overview

The MPC7457 is the fourth implementation of the fourth generation (G4) microprocessors

from Motorola. The MPC7457 implements the full PowerPC 32-bit architecture and is

targeted at networking and computing systems applications. The MPC7457 consists of a

processor core, a 512-Kbyte L2, and an internal L3 tag and controller which support a glueless

backside L3 cache through a dedicated high-bandwidth interface. The MPC7447 is identical

to the MPC7457 except it does not support the L3 cache interface.

Features

Figure 1 shows a block diagram of the MPC7457. The core is a high-performance superscalar design

supporting a double-precision ﬂoating-point unit and a SIMD multimedia unit. The memory storage

subsystem supports the MPX bus interface to main memory and other system resources. The L3 interface

supports 1, 2, or 4 Mbytes of external SRAM for L3 cache and/or private memory data. For systems

implementing 4 Mbytes of SRAM, a maximum of 2 Mbytes may be used as cache; the remaining 2 Mbytes

must be private memory.

Note that the MPC7457 is a footprint-compatible, drop-in replacement in a MPC7455 application if the core

power supply is 1.3 V.

1.2 Features

This section summarizes features of the MPC7457 implementation of the PowerPC architecture.

Major features of the MPC7457 are as follows:

•

High-performance, superscalar microprocessor

— As many as four instructions can be fetched from the instruction cache at a time

— As many as three instructions can be dispatched to the issue queues at a time

— As many as 12 instructions can be in the instruction queue (IQ)

— As many as 16 instructions can be at some stage of execution simultaneously

— Single-cycle execution for most instructions

— One instruction per clock cycle throughput for most instructions

— Seven-stage pipeline control

•

Eleven independent execution units and three register ﬁles

— Branch processing unit (BPU) features static and dynamic branch prediction

– 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache

of branch instructions that have been encountered in branch/loop code sequences. If a target

instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can

be made available from the instruction cache. Typically, a fetch that hits the BTIC provides

the ﬁrst four instructions in the target stream.

– 2048-entry branch history table (BHT) with two bits per entry for four levels of

prediction—not-taken, strongly not-taken, taken, and strongly taken

– Up to three outstanding speculative branches

– Branch instructions that do not update the count register (CTR) or link register (LR) are

often removed from the instruction stream.

– Eight-entry link register stack to predict the target address of Branch Conditional to Link

Register (bclr) instructions

— Four integer units (IUs) that share 32 GPRs for integer operands

– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except

multiply, divide, and move to/from special-purpose register instructions

– IU2 executes miscellaneous instructions including the CR logical operations, integer

multiplication and division instructions, and move to/from special-purpose register

instructions

2

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Features

Figure 1. MPC7457 Block Diagram

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

3

Features

— Five-stage FPU and a 32-entry FPR ﬁle

– Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations

– Supports non-IEEE mode for time-critical operations

– Hardware support for denormalized numbers

– Thirty-two 64-bit FPRs for single- or double-precision operands

— Four vector units and 32-entry vector register ﬁle (VRs)

– Vector permute unit (VPU)

– Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as

vector add instructions (vaddsbs, vaddshs, and vaddsws, for example)

– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as

vector multiply add instructions (vmhaddshs, vmhraddshs, and vmladduhm, for

example)

– Vector ﬂoating-point unit (VFPU)

— Three-stage load/store unit (LSU)

– Supports integer, ﬂoating-point, and vector instruction load/store trafﬁc

– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream

operations

– Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-cycle

throughput

– Four-cycle FPR load latency (single, double) with one-cycle throughput

– No additional delay for misaligned access within double-word boundary

– Dedicated adder calculates effective addresses (EAs)

– Supports store gathering

– Performs alignment, normalization, and precision conversion for ﬂoating-point data

– Executes cache control and TLB instructions

– Performs alignment, zero padding, and sign extension for integer data

– Supports hits under misses (multiple outstanding misses)

– Supports both big- and little-endian modes, including misaligned little-endian accesses

•

Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions,

respectively, in a cycle. Instruction dispatch requires the following:

— Instructions can be dispatched only from the three lowest IQ entries—IQ0, IQ1, and IQ2

— A maximum of three instructions can be dispatched to the issue queues per clock cycle

— Space must be available in the CQ for an instruction to dispatch (this includes instructions that

are assigned a space in the CQ but not in an issue queue)

•

Rename buffers

— 16 GPR rename buffers

— 16 FPR rename buffers

— 16 VR rename buffers

Dispatch unit

— Decode/dispatch stage fully decodes each instruction

4

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Features

•

Completion unit

— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all

instructions ahead of it have been completed, the instruction has ﬁnished execution, and no

exceptions are pending.

— Guarantees sequential programming model (precise exception model)

— Monitors all dispatched instructions and retires them in order

— Tracks unresolved branches and ﬂushes instructions after a mispredicted branch

— Retires as many as three instructions per clock cycle

•

Separate on-chip L1 instruction and data caches (Harvard architecture)

— 32-Kbyte, eight-way set-associative instruction and data caches

— Pseudo least-recently-used (PLRU) replacement algorithm

— 32-byte (eight-word) L1 cache block

— Physically indexed/physical tags

— Cache write-back or write-through operation programmable on a per-page or per-block basis

— Instruction cache can provide four instructions per clock cycle; data cache can provide four

words per clock cycle

— Caches can be disabled in software

— Caches can be locked in software

— MESI data cache coherency maintained in hardware

— Separate copy of data cache tags for efﬁcient snooping

— Parity support on cache and tags

— No snooping of instruction cache except for icbi instruction

— Data cache supports AltiVec LRU and transient instructions

— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word

forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical

double-word forwarding.

•

Level 2 (L2) cache interface

— On-chip, 512-Kbyte, eight-way set-associative uniﬁed instruction and data cache

— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches

— A total nine-cycle load latency for an L1 data cache miss that hits in L2

— PLRU replacement algorithm

— Cache write-back or write-through operation programmable on a per-page or per-block basis

— 64-byte, two-sectored line size

— Parity support on cache

•

Level 3 (L3) cache interface (not implemented on MPC7447)

— Provides critical double-word forwarding to the requesting unit

— Internal L3 cache controller and tags

— External data SRAMs

— Support for 1-, 2-, and 4-Mbyte (MB) total SRAM space

— Support for 1- or 2-MB of cache space

— Cache write-back or write-through operation programmable on a per-page or per-block basis

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

5

Features

— 64-byte (1-MB) or 128-byte (2-MB) sectored line size

— Private memory capability for half (1 MB minimum) or all of the L3 SRAM space for a total of

1- , 2- , or 4-MB of private memory

— Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2 pipelined

synchronous Burst SRAMs, and pipelined (register-register) Late Write synchronous Burst

SRAMs

— Supports parity on cache and tags

— Conﬁgurable core-to-L3 frequency divisors

— 64-bit external L3 data bus sustains 64 bits per L3 clock cycle

Separate memory management units (MMUs) for instructions and data

— 52-bit virtual address; 32- or 36-bit physical address

— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments

•

— Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and

memory coherency enforced/memory coherency not enforced on a page or block basis

— Separate IBATs and DBATs (eight each) also deﬁned as SPRs

— Separate instruction and data translation lookaside buffers (TLBs)

– Both TLBs are 128-entry, two-way set-associative, and use LRU replacement algorithm

– TLBs are hardware- or software-reloadable (that is, on a TLB miss a page table search is

performed in hardware or by system software)

•

Efﬁcient data ﬂow

— Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows up to 256 bits

— The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs

— L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache

— As many as eight outstanding, out-of-order, cache misses are allowed between the L1 data

cache and L2/L3 bus

— As many as 16 out-of-order transactions can be present on the MPX bus

— Store merging for multiple store misses to the same line. Only coherency action taken

(address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed).

— Three-entry ﬁnished store queue and ﬁve-entry completed store queue between the LSU and the

L1 data cache

— Separate additional queues for efﬁcient buffering of outbound data (such as castouts and

write-through stores) from the L1 data cache and L2 cache

•

Multiprocessing support features include the following:

— Hardware-enforced, MESI cache coherency protocols for data cache

— Load/store with reservation instruction pair for atomic memory references, semaphores, and

other multiprocessor operations

Power and thermal management

— 1.6-V processor core

— The following three power-saving modes are available to the system:

– Nap—Instruction fetching is halted. Only those clocks for the time base, decrementer, and

JTAG logic remain running. The part goes into the doze state to snoop memory operations

on the bus and then back to nap using a QREQ/QACK processor-system handshake

protocol.

6

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441

– Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the

PLL in a locked and running state. All internal functional units are disabled.

– Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system

can then disable the SYSCLK source for greater system power savings. Power-on reset

procedures for restarting and relocking the PLL must be followed on exiting the deep sleep

state.

— Thermal management facility provides software-controllable thermal management. Thermal

management is performed through the use of three supervisor-level registers and an

MPC7457-speciﬁc thermal management exception.

— Instruction cache throttling provides control of instruction fetching to limit power consumption

Performance monitor can be used to help debug system designs and improve software efﬁciency

In-system testability and debugging features through JTAG boundary-scan capability

Testability

•

— LSSD scan design

— IEEE 1149.1 JTAG interface

— Array built-in self test (ABIST)—factory test only

Reliability and serviceability

•

— Parity checking on system bus and L3 cache bus

— Parity checking on the L2 and L3 cache tag arrays

1.3 Comparison with the MPC7455, MPC7445,

MPC7450, MPC7451, and MPC7441

Table 1 compares the key features of the MPC7457 with the key features of the earlier MPC7455,

MPC7445, MPC7450, MPC7451, and MPC7441. To achieve a higher frequency, the number of logic levels

per cycle is reduced. Also, to achieve this higher frequency, the pipeline of the MPC7457 is extended

(compared to the MPC7400), while maintaining the same level of performance as measured by the number

of instructions executed per cycle (IPC).

Table 1. Microarchitecture Comparison

MPC7450/MPC7451/

Microarchitectural Specs

MPC7457/MPC7447

MPC7455/MPC7445

MPC7441

Basic Pipeline Functions

Logic inversions per cycle

18

Pipeline stages up to execute

Total pipeline stages (minimum)

5

7

5

7

5

7

Pipeline maximum instruction

throughput

3 + Branch

Pipeline Resources

Instruction buffer size

12

16

12

16

12

16

Completion buffer size

Renames (integer, ﬂoat, vector)

16, 16, 16

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

7

Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441

Table 1. Microarchitecture Comparison (continued)

MPC7450/MPC7451/

MPC7441

Microarchitectural Specs

MPC7457/MPC7447

MPC7455/MPC7445

Maximum Execution Throughput

SFX

3

Vector

2 (Any 2 of 4 Units)

1

2 (Any 2 of 4 Units)

1

2 (Any 2 of 4 Units)

1

Scalar ﬂoating-point

Out-of-Order Window Size in Execution Queues

SFX integer units

Vector units

1 Entry × 3 Queues

In Order, 4 Queues

In Order

1 Entry × 3 Queues

In Order, 4 Queues

In Order

In Order, 4 Queues

In Order

Scalar ﬂoating-point unit

Branch Processing Resources

Prediction structures

BTIC, BHT, Link Stack BTIC, BHT, Link Stack BTIC, BHT, Link Stack

BTIC size, associativity

BHT size

128-Entry, 4-Way

2K-Entry

Link stack depth

8

3

1

6

8

3

1

6

8

3

1

6

Unresolved branches supported

Branch taken penalty (BTIC hit)

Minimum misprediction penalty

Execution Unit Timings (Latency-Throughput)

Aligned load (integer, ﬂoat, vector)

Misaligned load (integer, ﬂoat, vector)

L1 miss, L2 hit latency

3-1, 4-1, 3-1

4-2, 5-2, 4-2

9 Data/13 Instruction

SFX (aDd Sub, Shift, Rot, Cmp, logicals)

Integer multiply (32 × 8, 32 × 16, 32 × 32)

Scalar ﬂoat

1-1

3-1, 3-1, 4-2

5-1

1-1

3-1, 3-1, 4-2

5-1

1-1

3-1, 3-1, 4-2

5-1

VSFX (vector simple)

1-1

VCFX (vector complex)

4-1

VFPU (vector ﬂoat)

4-1

VPER (vector permute)

2-1

MMUs

TLBs (instruction and data)

Tablewalk mechanism

128-Entry, 2-Way

Hardware + Software

8/8

128-Entry, 2-Way

Hardware + Software

8/8

128-Entry, 2-Way

Hardware + Software

4/4

Instruction BATs/data BATs

8

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441

Table 1. Microarchitecture Comparison (continued)

MPC7450/MPC7451/

Microarchitectural Specs

MPC7457/MPC7447

MPC7455/MPC7445

MPC7441

L1 I Cache/D Cache Features

Size

32K/32K

8-Way

Way

32K/32K

8-Way

Way

32K/32K

8-Way

Way

Associativity

Locking granularity

Parity on I cache

Word

Parity on D cache

Byte

Number of D cache misses (load/store)

Data stream touch engines

5/1

4 Streams

On-Chip Cache Features

Cache level

L2

Size/associativity

Access width

512-Kbyte/8-Way

256-Kbyte/8-Way

256 Bits

2

256 Bits

2

256 Bits

2

Number of 32-byte sectors/line

Parity

Byte

1

Off-Chip Cache Support

Cache level

L3

2

Total SRAM space supported

On-chip tag logical size (cache space)

Associativity

1 MB, 2MB, 4 MB

1 MB, 2 MB

1MB, 2MB

8-Way

1 MB, 2 MB

1MB, 2MB

8-Way

1MB, 2MB

8-Way

2, 4

Number of 32-byte sectors/line

Off-Chip data SRAM support

Data path width

2, 4

MSUG2 DDR, LW, PB2 MSUG2 DDR, LW, PB2 MSUG2 DDR, LW, PB2

64

1 MB, 2 MB, 4MB

Byte

64

1 MB, 2 MB

Byte

64

1 MB, 2 MB

Byte

Direct mapped SRAM sizes

Parity

Notes:

1. Not implemented on MPC7447, MPC7445, or MPC7441.

2. The MPC7457 supports up to 4 MB of SRAM, of which a maximum of 2 MB can be conﬁgured as cache memory;

the remaining 2 MB may be unused or conﬁgured as private memory.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

9

General Parameters

1.4 General Parameters

The following list provides a summary of the general parameters of the MPC7457:

Technology

Die size

0.13 µm CMOS, nine-layer metal

9.1 mm × 10.8 mm

Transistor count

Logic design

Packages

58 million

Fully-static

MPC7447: Surface mount 360 ceramic ball grid array (CBGA)

MPC7457: Surface mount 483 ceramic ball grid array (CBGA)

1.3 V ± 50 mV DC nominal

Core power supply

I/O power supply

1.8 V ± 5% DC, or

2.5 V ± 5% DC

1.5 Electrical and Thermal Characteristics

This section provides the AC and DC electrical speciﬁcations and thermal characteristics for the MPC7457.

1.5.1 DC Electrical Characteristics

The tables in this section describe the MPC7457 DC electrical characteristics.Table 2 provides the absolute

maximum ratings.

1

Table 2. Absolute Maximum Ratings

Characteristic

Symbol

Maximum Value

Unit

Notes

Core supply voltage

PLL supply voltage

V

TBD

V

2

DD

AV

2

DD

Processor bus supply voltage BVSEL = 0

BVSEL = HRESET or OV

OV

GV

TBD

3, 4

3, 5

3, 6

3, 7

3, 8

9, 10

DD

in

TBD

DD

L3 bus supply voltage

L3VSEL = ¬HRESET

L3VSEL = 0

Not Supported

TBD

L3VSEL = HRESET or GV

Processor bus

L3 bus

TBD

DD

Input voltage

V

TBD

in

JTAG signals

TBD

in

10

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

1

Table 2. Absolute Maximum Ratings (continued)

Characteristic

Symbol

Maximum Value

Unit

Notes

Storage temperature range

Notes:

T

TBD

°C

stg

1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only,

and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device

reliability or cause permanent damage to the device.

2. Caution: V /AV must not exceed OV /GV by more than 1.0 V during normal operation; this limit may be

DD

exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

3. Caution: OV /GV must not exceed V /AV by more than 2.0 V during normal operation; this limit may be

DD

exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

4. BVSEL must be set to 0, such that the bus is in 1.8 V mode.

5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode.

6. This mode is not supported on current MPC7457 devices.

7. L3VSEL must be set to 0, such that the bus is in 1.8 V mode.

8. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode.

9. Caution: V must not exceed OV or GV by more than 0.3 V at any time including during power-on reset.

in

DD

10. V may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

in

Figure 2 shows the undershoot and overshoot voltage on the MPC7457.

OV /GV + 20%

DD

OV /GV + 5%

DD

OV /GV

DD

V

IH

V

IL

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

of t

SYSCLK

Figure 2. Overshoot/Undershoot Voltage

The MPC7457 provides several I/O voltages to support both compatibility with existing systems and

migration to future systems. The MPC7457 core voltage must always be provided at nominal 1.3 V (see

Table 4 for actual recommended core voltage). Voltage to the L3 I/Os and processor interface I/Os are

provided through separate sets of supply pins and may be provided at the voltages shown in Table 3. The

input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation

of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied to the

OV or GV power pins.

DD

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

11

Electrical and Thermal Characteristics

Table 3. Input Threshold Voltage Setting

Processor Bus Input

Threshold is Relative to:

L3 Bus Input Threshold is

Relative to:

1

BVSEL Signal

L3VSEL Signal

Notes

0

1.8 V

Not Available

2.5 V

0

1.8 V

Not Available

2.5 V

2, 3

2, 4

2

¬HRESET

HRESET

1

¬HRESET

HRESET

1

2.5 V

2

Notes:

1. Not implemented on MPC7447.

2. Caution: The input threshold selection must agree with the OV /GV voltages supplied. See notes in Table 2.

DD

3. If used, pull-down resistors should be less than 250 Ω.

4. ¬HRESET is the inverse of HRESET. Operation of the processor bus or L3 interface in this mode is not supported

for current MPC7457 devices.

Table 4 provides the recommended operating conditions for the MPC7457.

1

Table 4. Recommended Operating Conditions

Recommended Value

Characteristic

Symbol

Unit

Notes

Min

Max

Core supply voltage

PLL supply voltage

V

1.3 V ± 50 mV

V

°C

DD

AV

1.3 V ± 50 mV

1.8 V ± 5%

2

DD

Processor bus supply voltage BVSEL = 0

BVSEL = HRESET or OV

OV

GV

DD

in

2.5 V ± 5%

DD

L3 bus supply voltage

L3VSEL = 0

1.8 V ± 5%

L3VSEL = HRESET or GV

L3VSEL = ¬HRESET

Processor bus

2.5 V ± 5%

DD

Not Supported

3

Input voltage

V

GND

0

OV

GV

OV

DD

L3 bus

in

JTAG signals

in

Die-junction temperature

T

105

j

Notes:

1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions

is not guaranteed.

2. This voltage is the input to the ﬁlter discussed in Section 1.9.2, “PLL Power Supply Filtering,” and not necessarily

the voltage at the AV pin which may be reduced from V by the ﬁlter.

DD

3. Operation of the L3 interface in this mode is not supported for current MPC7457 devices.

12

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

Table 5 provides the package thermal characteristics for the MPC7457.

1

Table 5. Package Thermal Characteristics

Value

Characteristic

Symbol

Unit

Notes

MPC7447

MPC7457

Junction-to-ambient thermal resistance, natural

convection

R

22

14

16

11

20

°C/W

2, 3

2, 4

JA

θ

Junction-to-ambient thermal resistance, natural

convection, four-layer (2s2p) board

R

14

15

11

JMA

θ

Junction-to-ambient thermal resistance, 200 ft/min

airﬂow, single-layer (1s) board

R

Junction-to-ambient thermal resistance, 200 ft/min

airﬂow, four-layer (2s2p) board

Junction-to-board thermal resistance

Junction-to-case thermal resistance

Notes:

R

6

°C/W

5

6

JB

JC

θ

R

<0.1

θ

1. Refer to Section 1.9.8, “Thermal Management Information,” for more details about thermal management.

2. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, airﬂow, power dissipation of other components on the board, and board thermal

resistance.

3. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

4. Per JEDEC JESD51-6 with the board horizontal.

5. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

6. Thermal resistance between the die and the case top surface as measured by the cold plate method

(MIL SPEC-883 Method 1012.1) with the calculated case temperature.The actual value of R

for the part is less

θJC

than 0.1˚C/W.

Table 6 provides the DC electrical characteristics for the MPC7457.

Table 6. DC Electrical Speciﬁcations

At recommended operating conditions. See Table 4.

Nominal

Characteristic

Bus

Voltage

Symbol

Min

Max

Unit Notes

1

Input high voltage

1.5

1.8

2.5

1.5

1.8

2.5

—

V

Not Supported

OV /GV × 0.65 OV /GV + 0.3

V

2

IH

(all inputs except SYSCLK)

DD

1.7

OV /GV + 0.3

V

DD

Input low voltage

(all inputs except SYSCLK)

V

Not Supported

V

2, 6

IL

–0.3

1.4

OV /GV × 0.35

V

DD

0.7

V

SYSCLK input high voltage

SYSCLK input low voltage

Input leakage current,

CV

OV + 0.3

V

IH

DD

—

CV

–0.3

—

0.4

30

V

IL

—

I

µA

2, 3

in

V

= GV /OV

DD DD

in

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

13

Electrical and Thermal Characteristics

Table 6. DC Electrical Speciﬁcations (continued)

At recommended operating conditions. See Table 4.

Nominal

Characteristic

Bus

Voltage

Symbol

Min

Max

Unit Notes

1

High-impedance (off-state)

—

I

—

30

µA

2, 3, 4

TSI

leakage current, V = GV /OV

DD

in

DD

Output high voltage, I = –5 mA

1.8

2.5

1.8

2.5

—

V

OV /GV – 0.45

—

V

OH

DD

1.7

OH

Output low voltage, I = 5 mA

V

—

0.45

0.7

9.5

8.0

V

OL

V

OL

Capacitance,

L3 interface

C

pF

5

in

V

= 0 V,

in

All other inputs

f = 1 MHz

Notes:

1. Nominal voltages; see Table 4 for recommended operating conditions.

2. For processor bus signals, the reference is OV while GV is the reference for the L3 bus signals.

DD

3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals.

4. The leakage is measured for nominal OV /GV and V , or both OV /GV and V must vary in the same

DD

direction (for example, both OV and V vary by either +5% or –5%).

DD

5. Capacitance is periodically sampled rather than 100% tested.

6. This mode is not supported on current MPC7457 devices.

Table 7 provides the power consumption for the MPC7457.

Table 7. Power Consumption for MPC7457

Processor (CPU) Frequency

Unit

Notes

867 MHz

1.0 GHz

1.3 GHz

Full-Power Mode

Typical

14.8

21.0

15.8

22.0

18.7

26.0

W

1, 2

1, 3

Maximum

Doze Mode

Typical

—

W

4

Nap Mode

Typical

5.2

5.1

5.2

5.1

5.2

5.1

W

1, 2

Sleep Mode

Deep Sleep Mode (PLL Disabled)

14

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

Table 7. Power Consumption for MPC7457 (continued)

Processor (CPU) Frequency

Unit

Notes

867 MHz

5.0

1.0 GHz

1.3 GHz

5.0

Typical

5.0

W

1, 2

Notes:

1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power

(OV and GV ) or PLL supply power (AV ). OV and GV power is system dependent, but is typically

DD

<5% of V power. Worst case power consumption for AV < 3 mW.

DD

2. Typical power is an average value measured at the nominal recommended V (see Table 4) and 65°C while

DD

running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.

3. Maximum power is the average measured at nominal V and maximum operating junction temperature (see

DD

Table 4) while running an entirely cache-resident, contrived sequence of instructions which keep all the execution

units maximally busy.

4. Doze mode is not a user-deﬁnable state; it is an intermediate state between full-power and either nap or sleep

mode. As a result, power consumption for this mode is not tested.

1.5.2 AC Electrical Characteristics

This section provides the AC electrical characteristics for the MPC7457. After fabrication, functional parts

are sorted by maximum processor core frequency as shown in Section 1.5.2.1, “Clock AC Speciﬁcations,”

and tested for conformance to the AC speciﬁcations for that frequency. The processor core frequency is

determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold

by maximum processor core frequency; see Section 1.11, “Ordering Information.”

1.5.2.1 Clock AC Speciﬁcations

Table 8 provides the clock AC timing speciﬁcations as deﬁned in Figure 3 and represents the tested

operating frequencies of the devices. The maximum system bus frequency, f

, given in Table 8 is

SYSCLK

considered a practical maximum in a typical single-processor system. The actual maximum SYSCLK

frequency for any application of the MPC7457 will be a function of the AC timings of the MPC7457, the

AC timings for the system controller, bus loading, printed-circuit board topology, trace lengths, and so forth,

and may be less than the value given in Table 8.

Table 8. Clock AC Timing Speciﬁcations

At recommended operating conditions. See Table 4.

Maximum Processor Core Frequency

Characteristic

Symbol

867 MHz

1 GHz

1.3 GHz

Unit

Notes

Min

Max

Min

Max

Min

Max

Processor frequency

VCO frequency

f

600

1200

33

867

1733

167

30

600

1200

33

1000

2000

167

30

600

1200

33

1300

2600

167

30

MHz

ns

1

core

f

VCO

SYSCLK frequency

SYSCLK cycle time

SYSCLK rise and fall time

f

t

1, 2

2

SYSCLK

6.0

t

, t

—

1.0

—

1.0

—

1.0

ns

3

KR KF

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

15

Electrical and Thermal Characteristics

Table 8. Clock AC Timing Speciﬁcations (continued)

At recommended operating conditions. See Table 4.

Maximum Processor Core Frequency

867 MHz 1 GHz 1.3 GHz

Characteristic

Symbol

Unit

Notes

Min

Max

Min

Max

Min

Max

SYSCLK duty cycle

t

/

40

60

40

60

40

60

%

4

KHKL

measured at OV /2

t

SYSCLK

DD

SYSCLK jitter

Internal PLL relock time

Notes:

—

± 150

100

—

± 150

100

—

± 150

100

ps

5, 6

7

µs

1. Caution:The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)

frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.9.1, “PLL Conﬁguration,” for valid

PLL_CFG[0:4] settings.

2. Assumes lightly-loaded, single-processor system.

3. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V.

4. Timing is guaranteed by design and characterization.

5. This represents total input jitter—short term and long term combined—and is guaranteed by design.

6. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to

allow cascade connected PLL-based devices to track SYSCLK drivers with the speciﬁed jitter.

7. Relock timing is guaranteed by design and characterization.PLL-relock time is the maximum amount of time required

for PLL lock after a stable V and SYSCLK are reached during the power-on reset sequence.This speciﬁcation also

DD

applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET

must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset

sequence.

Figure 3 provides the SYSCLK input timing diagram.

CV

t

IH

VM

SYSCLK

CV

IL

t

KHKL

t

KF

KR

t

SYSCLK

VM = Midpoint Voltage (OV /2)

DD

Figure 3. SYSCLK Input Timing Diagram

16

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

1.5.2.2 Processor Bus AC Speciﬁcations

Table 9 provides the processor bus AC timing speciﬁcations for the MPC7457 as deﬁned in Figure 4 and

Figure 5. Timing speciﬁcations for the L3 bus are provided in Section 1.5.2.3, “L3 Clock AC

Speciﬁcations.”

1

Table 9. Processor Bus AC Timing Speciﬁcations

At recommended operating conditions. See Table 4.

All Speed Grades

2

Parameter

Symbol

Unit

Notes

Min

Max

Mode select input setup to HRESET

HRESET to mode select input hold

t

8

0

—

t

3, 4, 5, 6

3, 6

MVRH

SYSCLK

ns

MXRH

Input setup times:

ns

A[0:35], AP[0:4]

t

1.8

—

AVKH

DVKH

IVKH

D[0:63], DP[0:7]

t

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TBST, TSIZ[0:2], TT[0:3], QACK, TA, TBEN, TEA, TS,

EXT_QUAL, PMON_IN, SHD[0:1]

t

Input hold times:

A[0:35], AP[0:4]

t

0

—

AXKH

DXKH

D[0:63], DP[0:7]

t

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TBST, TSIZ[0:2], TT[0:3], QACK, TA, TBEN, TEA, TS,

EXT_QUAL, PMON_IN, SHD[0:1]

t

IXKH

Output valid times:

A[0:35], AP[0:4]

t

—

2.0

KHAV

KHDV

KHOV

D[0:63], DP[0:7]

t

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TBST, TSIZ[0:2], TT[0:3], QACK, TA, TBEN, TEA, TS,

EXT_QUAL, PMON_IN, SHD[0:1]

t

Output hold times:

A[0:35], AP[0:4]

t

0.5

—

KHAX

KHDX

KHOX

D[0:63], DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TBST, TSIZ[0:2], TT[0:3], QACK, TA, TBEN, TEA, TS,

EXT_QUAL, PMON_IN, SHD[0:1]

SYSCLK to output enable

t

0.5

—

ns

KHOE

SYSCLK to output high impedance (all except TS, ARTRY,

SHD0, SHD1)

t

3.5

KHOZ

SYSCLK to TS high impedance after precharge

Maximum delay to ARTRY/SHD0/SHD1 precharge

t

—

1

t

5, 7, 8

KHTSPZ

SYSCLK

t

5, 8,

9, 10

KHARP

SYSCLK

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

17

Electrical and Thermal Characteristics

Table 9. Processor Bus AC Timing Speciﬁcations (continued)

1

At recommended operating conditions. See Table 4.

All Speed Grades

2

Parameter

Symbol

Unit

Notes

Min

Max

SYSCLK to ARTRY/SHD0/SHD1 high impedance after

precharge

t

—

2

t

5, 8,

9, 10

KHARPZ

SYSCLK

Notes:

1. All input speciﬁcations are measured from the midpoint of the signal in question to the midpoint of the rising edge

of the input SYSCLK. All output speciﬁcations are measured from the midpoint of the rising edge of SYSCLK to the

midpoint of the signal in question. All output timings assume a purely resistive 50-Ω load (see Figure 4). Input and

output timings are measured at the pin; time-of-ﬂight delays must be added for trace lengths, vias, and connectors

in the system.

2. The symbology used for timing speciﬁcations herein follows the pattern of t

for inputs and

(signal)(state)(reference)(state)

t

for outputs. For example, t

symbolizes the time input signals (I) reach the valid state

(reference)(state)(signal)(state)

IVKH

(V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t

symbolizes the

KHOV

time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read

as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of

the reference and its state for inputs) and output hold time can be read as the time from the rising edge (KH) until

the output went invalid (OX).

3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 5).

4. This speciﬁcation is for conﬁguration mode select only.

5. t

is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the

sysclk

period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.

6. Mode select signals are: BVSEL, L3VSEL, PLL_CFG[0:4], BMODE[0:1].

7. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then

precharged high before returning to high impedance as shown in Figure 6. The nominal precharge width for TS is

0.5 × t

, that is, less than the minimum t

period, to ensure that another master asserting TS on the

SYSCLK

following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal

asserted. Output valid time is tested for precharge.The high-impedance behavior is guaranteed by design.

8. Guaranteed by design and not tested.

9. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately

following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any

master asserting it low in the ﬁrst clock following AACK will then go to high impedance for one clock before

precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY

is 1.0 t

; that is, it should be high impedance as shown in Figure 6 before the ﬁrst opportunity for another

SYSCLK

master to assert ARTRY. Output valid and output hold timing is tested for the signal asserted.The high-impedance

behavior is guaranteed by design.

10.According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of

TS. Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for

up to an entire cycle (crossing a bus cycle boundary) before being three-stated again.The nominal precharge width

for SHD0 and SHD1 is 1.0 t

to bus (PLL conﬁgurations).

. The edges of the precharge vary depending on the programmed ratio of core

SYSCLK

Figure 4 provides the AC test load for the MPC7457.

Output

OV /2

DD

Z = 50 Ω

0

R = 50 Ω

L

Figure 4. AC Test Load

18

MPC7457 RISC Microprocessor Hardware Speciﬁcations

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Electrical and Thermal Characteristics

Figure 5 provides the mode select input timing diagram for the MPC7457.

VM

HRESET

t

MVRH

t

MXRH

Mode Signals

VM = Midpoint Voltage (OV /2)

DD

Figure 5. Mode Input Timing Diagram

Figure 6 provides the input/output timing diagram for the MPC7457.

SYSCLK

VM

t

AXKH

IXKH

t

AVKH

t

IVKH

All Inputs

t

KHAV

KHAX

KHDX

KHOX

t

KHDV

t

KHOV

All Outputs

(Except TS,

ARTRY, SHD0, SHD1)

t

KHOE

t_KHOZ

All Outputs

(Except TS,

ARTRY, SHD0, SHD1)

t_KHTSPZ

t

KHTSV

t

KHTSX

t_KHTSV

TS

t_KHARPZ

t_KHARV

t_KHARP

ARTRY,

SHD0,

SHD1

t_KHARX

VM = Midpoint Voltage (OV /2)

DD

Figure 6. Input/Output Timing Diagram

1.5.2.3 L3 Clock AC Speciﬁcations

The L3_CLK frequency is programmed by the L3 conﬁguration register (L3CR[6:8]) core-to-L3 divisor

ratio. See Table 18 for example core and L3 frequencies at various divisors. Table 10 provides the potential

range of L3_CLK output AC timing speciﬁcations as deﬁned in Figure 7.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

19

Electrical and Thermal Characteristics

The maximum L3_CLK frequency is the core frequency divided by two. Given the high core frequencies

available in the MPC7457, however, most SRAM designs will be not be able to operate in this mode using

current technology and, as a result, will select a greater core-to-L3 divisor to provide a longer L3_CLK

period for read and write access to the L3 SRAMs. Therefore, the maximum L3_CLK frequency shown in

Table 10 is considered to be the practical maximum in a typical system. The maximum L3_CLK frequency

for any application of the MPC7457 will be a function of the AC timings of the MPC7457, the AC timings

for the SRAM, bus loading, and printed-circuit board trace length, and may be greater or less than the value

given in Table 10.

Motorola is similarly limited by system constraints and cannot perform tests of the L3 interface on a

socketed part on a functional tester at the maximum frequencies of Table 10. Therefore, functional operation

and AC timing information are tested at core-to-L3 divisors which result in L3 frequencies at 200 MHz or

less.

Table 10. L3_CLK Output AC Timing Speciﬁcations

At recommended operating conditions. See Table 4.

All Speed Grades

Parameter

Symbol

Unit

Notes

Min

Max

L3 clock frequency

L3 clock cycle time

L3 clock duty cycle

f

t

—

200

—

MHz

ns

1

2

3

4

L3_CLK

5.0

L3_CLK

t

/t

50

%

CHCL L3_CLK

L3 clock output-to-output skew (L1_CLK0 to L1_CLK1)

t

—

100

ps

L3CSKW1

L3CSKW2

L3 clock output-to-output skew (L1_CLK[0:1] to

L1_ECHO_CLK[2:3])

TBD

ps

L3 clock jitter

—

TBD

ps

5

Notes:

1. The maximum L3 clock frequency (and minimum L3 clock period) will be system dependent. See Section 1.5.2.3,

“L3 Clock AC Speciﬁcations,” for an explanation that this maximum frequency is not functionally tested at speed by

Motorola. The minimum L3 clock frequency and period are f

and t

, respectively.

SYSCLK

2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.

3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control

signals which are common to both SRAM chips in the L3.

4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for

PB2 or Late Write SRAM.This parameter is critical to the write data signals which are separately latched onto each

SRAM part by these pairs of signals.

5. Guaranteed by design and not tested.The input jitter on SYSCLK affects L3 output clocks and the L3 address/data/

control signals equally and, therefore, is already comprehended in the AC timing and does not have to be

considered in the L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock period

caused by supply voltage noise or thermal effects. This must be accounted for, along with clock skew, in any L3

timing analysis.

20

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

The L3_CLK timing diagram is shown in Figure 7.

t

L3CF

L3_CLK

L3CR

t

CHCL

L3_CLK0

L3_CLK1

VM

t

L3CSKW1

For PB2 or Late Write:

L3_ECHO_CLK1

VM

t

L3CSKW2

L3_ECHO_CLK3

VM

t

Figure 7. L3_CLK_OUT Output Timing Diagram

1.5.2.4

L3 Bus AC Speciﬁcations

The MPC7457 L3 interface supports three different types of SRAM: source-synchronous, double data rate

(DDR) MSUG2 SRAM, Late Write SRAMs, and pipeline burst (PB2) SRAMs. Each requires a different

protocol on the L3 interface and a different routing of the L3 clock signals. The type of SRAM is

programmed in L3CR[22:23] and the MPC7457 then follows the appropriate protocol for that type. The

designer must connect and route the L3 signals appropriately for each type of SRAM. Following are some

observations about the L3 interface.

•

The routing for the point-to-point signals (L3_CLK[0:1], L3DATA[0:63], L3DP[0:7], and

L3_ECHO_CLK[0:3]) to a particular SRAM must be delay matched.

•

For 1-Mbyte of SRAM, use L3_ADDR[16:0] (L3_ADDR[0] is LSB)

For 2-Mbyte of SRAM, use L3_ADDR[17:0] (L3_ADDR[0] is LSB)

No pull-up resistors are required for the L3 interface

For high speed operations, L3 interface address and control signals should be a ‘T’ with minimal

stubs to the two loads; data and clock signals should be point-to-point to their single load. Figure 8

shows the AC test load for the L3 interface.

Output

GV /2

DD

Z = 50 Ω

0

R = 50 Ω

L

Figure 8. AC Test Load for the L3 Interface

In general, if routing is short, delay-matched, and designed for incident wave reception and minimal

reﬂection, there is a high probability that the AC timing of the MPC7457 L3 interface will meet the

maximum frequency operation of appropriately chosen SRAMs. This is despite the pessimistic,

guard-banded AC speciﬁcations (see Table 12, Table 13, and Table 14), the limitations of functional testers

described in Section 1.5.2.3, “L3 Clock AC Speciﬁcations,” and the uncertainty of clocks and signals which

inevitably make worst-case critical path timing analysis pessimistic.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

21

Electrical and Thermal Characteristics

More speciﬁcally, certain signals within groups should be delay-matched with others in the same group

while intergroup routing is less critical. Only the address and control signals are common to both SRAMs

and additional timing margin is available for these signals. The double-clocked data signals are grouped

with individual clocks as shown in Figure 9 or Figure 11, depending on the type of SRAM. For example,

for the MSUG2 DDR SRAM (see Figure 9); L3DATA[0:31], L3DP[0:3], and L3_CLK[0] form a closely

coupled group of outputs from the MPC7457; while L3DATA[0:15], L3DP[0:1], and L3_ECHO_CLK[0]

form a closely coupled group of inputs.

The MPC7450 RISC Microprocessor Family User’s Manual refers to logical settings called ‘sample points’

used in the synchronization of reads from the receive FIFO. The computation of the correct value for this

setting is system-dependent and is described in the MPC7450 RISC Microprocessor Family User’s Manual.

Three speciﬁcations are used in this calculation and are given in Table 11. It is essential that all three

speciﬁcations are included in the calculations to determine the sample points, as incorrect settings can result

in errors and unpredictable behavior. For more information, see the MPC7450 RISC Microprocessor Family

User’s Manual.

Table 11. Sample Points Calculation Parameters

Parameter

Symbol

Max

Unit

Notes

Delay from processor clock to internal_L3_CLK

Delay from internal_L3_CLK to L3_CLK[n] output pins

Delay from L3_ECHO_CLK[n] to receive latch

Notes:

t

3/4

3

t

1

2

3

AC

CO

ECI

L3_CLK

t

ns

t

3

ns

1. This speciﬁcation describes a logical offset between the internal clock edge used to launch the L3 address and

control signals (this clock edge is phase-aligned with the processor clock edge) and the internal clock edge used

to launch the L3_CLK[n] signals. With proper board routing, this offset ensures that the L3_CLK[n] edge will arrive

at the SRAM within a valid address window and provide adequate setup and hold time. This offset is reﬂected in

the L3 bus interface AC timing speciﬁcations, but must also be separately accounted for in the calculation of sample

points and, thus, is speciﬁed here.

2. This speciﬁcation is the delay from a rising or falling edge on the internal_L3_CLK signal to the corresponding rising

or falling edge at the L3CLK[n] pins.

3. This speciﬁcation is the delay from a rising or falling edge of L3_ECHO_CLK[n] to data valid and ready to be

sampled from the FIFO.

1.5.2.4.1 Effects of L3OHCR Settings on L3 Bus AC Speciﬁcations

The AC timing of the L3 interface can be adjusted using the L3 Output Hold Control Register (L3OCHR).

Each ﬁeld controls the timing for a group of signals. TheAC timing speciﬁcations presented herein represent

the AC timing when the register contains the default value of 0x0000_0000. Incrementing a ﬁeld delays the

associated signals, increasing the output valid time and hold time of the affected signals. In the special case

of delaying an L3_CLK signal, the net effect is to decrease the output valid and output hold times of all

signals being latched relative to that clock signal. The amount of delay added is summarized in Table 12.

Note that these settings affect output timing parameters only and do not impact input timing parameters of

the L3 bus in any way.

22

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing

At recommended operating conditions. See Table 4.

Output Valid Time

Output Hold Time

Unit Notes

1

Field name

Affected Signals

Value

Parameter

Symbol

Parameter

Symbol

2

3

2

3

Change

L3AOH

L3_ADDR[18:0],

L3_CNTL[0:1]

0b00

0b01

t

0

t

0

ps

4

L3CHOV

L3CHOX

+50

0b10

+100

+150

0

+100

+150

0

0b11

L3CLKn_OH Allsignalslatched

by SRAM

0b000

0b001

0b010

0b011

0b100

0b101

0b110

0b111

0b000

0b001

0b010

0b011

0b100

0b101

0b111

t

,

t

,

4

5

4

L3CHOV

L3CHOX

,

L3CHDX

t

,

L3CHDV

L3CLDV

– 50

– 100

– 150

– 200

– 250

– 300

– 350

0

– 50

– 100

– 150

– 200

– 250

– 300

– 350

0

connected to

t

L3CLDX,

L3_CLKn

L3DOHn

L3_DATA[n:n+7],

L3_DP[n/8]

t

,

t

,

L3CHDV

L3CHDX

t

L3CLDV

L3CLDX,

+50

+100

+150

+200

+250

+350

+100

+150

+200

+250

+350

Notes:

1. See the MPC7450 RISC Microprocessor Family User’s Manual for speciﬁc information regarding L3OHCR.

2. See Table 13 and Table 14 for more information.

3. Guaranteed by design; not tested or characterized.

4. Default value.

5. Increasing values of L3CLKn_OH delay the L3_CLKn signal, effectively decreasing the output valid and output hold

times of all signals latched relative to that clock signal by the SRAM; see Figure 9 and Figure 11.

1.5.2.4.2 L3 Bus AC Speciﬁcations for DDR MSUG2 SRAMs

When using DDR MSUG2 SRAMs at the L3 interface, the parts should be connected as shown in Figure 9.

Outputs from the MPC7457 are actually launched on the edges of an internal clock phase-aligned to

SYSCLK (adjusted for core and L3 frequency divisors). L3_CLK0 and L3_CLK1 are this internal clock

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

23

Electrical and Thermal Characteristics

output with 90° phase delay, so outputs are shown synchronous to L3_CLK0 and L3_CLK1. Output valid

times are typically negative when referenced to L3_CLKn because the data is launched one-quarter period

before L3_CLKn to provide adequate setup time at the SRAM after the delay-matched address, control,

data, and L3_CLKn signals have propagated across the printed-wiring board.

Inputs to the MPC7457 are source-synchronous with the CQ clock generated by the DDR MSUG2 SRAMs.

These CQ clocks are received on the L3_ECHO_CLKn inputs of the MPC7457. An internal circuit delays

the incoming L3_ECHO_CLKn signal such that it is positioned within the valid data window at the internal

receiving latches. This delayed clock is used to capture the data into these latches which comprise the

receive FIFO. This clock is asynchronous to all other processor clocks. This latched data is subsequently

read out of the FIFO synchronously to the processor clock. The time between writing and reading the data

is set by the using the sample point settings deﬁned in the L3CR register.

Table 13 provides the L3 bus interface AC timing speciﬁcations for the conﬁguration as shown in Figure 9,

assuming the timing relationships shown in Figure 10 and the loading shown in Figure 8.

Table 13. L3 Bus Interface AC Timing Speciﬁcations for MSUG2

At recommended operating conditions. See Table 4.

All Speed Grades

Parameter

Symbol

Unit

Notes

Min

Max

L3_CLK rise and fall time

t

, t

—

– 0.35

2.1

0.75

—

ns

1

L3CR L3CF

Setup times: Data and parity

Input hold times: Data and parity

Valid times: Data and parity

t

, t

2, 3, 4

2, 4

L3DVEH L3DVEL

t

, t

—

L3DXEH L3DXEL

t

, t

—

(– t

/4) +

5, 6, 7, 8

L3CHDV L3CLDV

L3CLK

0.60

Valid times: All other outputs

t

—

(t

/4) +

ns

5, 7, 8

5, 6, 7, 8

5, 7, 8

L3CHOV

L3CLK

0.65

Output hold times: Data and parity

Output hold times: All other outputs

t

, t

(t

/4) –

L3CLK

—

L3CHDX L3CLDX,

0.60

t

(t

/4) –

—

L3CHOX

L3CLK

0.50

L3_CLK to high impedance: Data and

parity

t

—

TBD

L3CLDZ

24

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

Table 13. L3 Bus Interface AC Timing Speciﬁcations for MSUG2 (continued)

At recommended operating conditions. See Table 4.

All Speed Grades

Parameter

Symbol

Unit

Notes

Min

Max

L3_CLK to high impedance: All other

outputs

t

—

TBD

ns

L3CHOZ

Notes:

1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV

.

DD

2. For DDR, all input speciﬁcations are measured from the midpoint of the signal in question to the midpoint voltage

of the rising or falling edge of the input L3_ECHO_CLKn (see Figure 10). Input timings are measured at the pins.

3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10. For consistency

with other input setup time speciﬁcations, this will be treated as negative input setup time.

4. t

/4 is one-fourth the period of L3_CLKn.This parameter indicates that the MPC7457 can latch an input signal

L3_CLK

that is valid for only a short time before and a short time after the midpoint between the rising and falling (or falling

and rising) edges of L3_ECHO_CLKn at any frequency.

5. All output speciﬁcations are measured from the midpoint voltage of the rising (or for DDR write data, also the falling)

edge of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output

timings assume a purely resistive 50-Ω load (see Figure 8).

6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10. For consistency with other

output valid time speciﬁcations, this will be treated as negative output valid time.

7. t

/4 is one-fourth the period of L3_CLKn. This parameter indicates that the speciﬁed output signal is actually

L3_CLK

launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output

valid and output hold times such that the speciﬁed output signal will be valid for approximately one L3_CLK period

starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock

period after the edge it will be sampled.

8. Assumes default value of L3OHCR. See Section 1.5.2.4.1, “Effects of L3OHCR Settings on L3 Bus AC

Speciﬁcations” for more information.

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25

Electrical and Thermal Characteristics

Figure 9 shows the typical connection diagram for the MPC7457 interfaced to MSUG2 DDR SRAMs.

SRAM 0

SA[18:0]

L3ADDR[18:0]

MPC7457

B3 GND

L3_CNTL[0]

L3_CNTL[1]

B1

B2

CQ

G

GND

LBO GND

Denotes

L3_ECHO_CLK[0]

Receive (SRAM

to MPC7457)

Aligned Signals

{L3DATA[0:15], L3DP[0:1]}

L3_CLK[0]

CQ

CK

NC

D[0:17]

CK

{L3DATA[16:31], L3DP[2:3]}

L3_ECHO_CLK[1]

1

GV /2

D[18:35]

CQ

DD

Denotes

Transmit

SRAM 1

SA[18:0]

(MPC7457 to

SRAM)

B3 GND

B1

Aligned Signals

G

GND

LBO GND

B2

L3ECHO_CLK[2]

CQ

{L3_DATA[32:47], L3DP[4:5]}

D[0:17]

CQ

CK

NC

L3_CLK[1]

CK

{L3DATA[48:63], L3DP[6:7]}

L3_ECHO_CLK[3]

1

D[18:35]

CQ

GV /2

DD

Note:

1. Or as recommended by SRAM manufacturer for single-ended clocking.

Figure 9. Typical Source Synchronous 4-Mbyte L3 Cache DDR Interface

26

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

Figure 10 shows the L3 bus timing diagrams for the MPC7457 interfaced to MSUG2 SRAMs.

Outputs

L3_CLK[0,1]

VM

t

L3CHOZ

L3CHOV

t

L3CHOX

ADDR, L3CNTL

L3DATA WRITE

t

L3CLDV

t

L3CLDZ

t

L3CHDV

t

L3CHDX

t

L3CLDX

Note: t

and t

as drawn here will be negative numbers, that is, output valid time will be

L3CHDV

time before the clock edge.

L3CLDV

Inputs

L3_ECHO_CLK[0,1,2,3]

VM

t

L3DXEL

t

L3DVEL

t

L3DVEH

L3 Data and Data

Parity Inputs

L3DXEH

Note: t

and t

as drawn here will be negative numbers, that is, input setup time will be

L3DVEH

L3DVEL

time after the clock edge.

VM = Midpoint Voltage (GV /2)

DD

Figure 10. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs

1.5.2.4.3 L3 Bus AC Speciﬁcations for PB2 and Late Write SRAMs

When using PB2 or Late Write SRAMs at the L3 interface, the parts should be connected as shown in

Figure 11. These SRAMs are synchronous to the MPC7457; one L3_CLKn signal is output to each SRAM

to latch address, control, and write data. Read data is launched by the SRAM synchronous to the delayed

L3_CLKn signal it received. The MPC7457 needs a copy of that delayed clock which launched the SRAM

read data to know when the returning data will be valid. Therefore, L3_ECHO_CLK1 and

L3_ECHO_CLK3 must be routed halfway to the SRAMs and then returned to the MPC7457 inputs

L3_ECHO_CLK0 and L3_ECHO_CLK2, respectively. Thus, L3_ECHO_CLK0 and L3_ECHO_CLK2 are

phase-aligned with the input clock received at the SRAMs. The MPC7457 will latch the incoming data on

the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2.

Table 14 provides the L3 bus interface AC timing speciﬁcations for the conﬁguration shown in Figure 11,

assuming the timing relationships of Figure 12 and the loading of Figure 8.

MOTOROLA

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27

Electrical and Thermal Characteristics

Table 14. L3 Bus Interface AC Timing Speciﬁcations for PB2 and Late Write SRAMs

At recommended operating conditions. See Table 4.

All Speed Grades

Parameter

Symbol

Unit

Notes

Min

Max

L3_CLK rise and fall time

t

, t

—

TBD

—

0.75

—

ns

1, 2

2, 3

L3CR L3CF

Setup times: Data and parity

Input hold times: Data and parity

Valid times: Data and parity

t

L3DVEH

L3DXEH

L3CHDV

L3CHOV

L3CHDX

L3CHOX

t

TBD

—

2, 3

—

2, 4, 5, 6

5, 6

Valid times: All other outputs

t

—

Output hold times: Data and parity

Output hold times: All other outputs

L3_CLK to high impedance: Data and parity

L3_CLK to high impedance: All other outputs

Notes:

TBD

—

2, 4, 5, 6

2, 5, 6

2

—

t

TBD

L3CHDZ

L3CHOZ

t

—

2

1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV

2. Timing behavior and characterization are currently being evaluated.

.

DD

3. All input speciﬁcations are measured from the midpoint of the signal in question to the midpoint voltage of the rising

edge of the input L3_ECHO_CLKn (see Figure 10). Input timings are measured at the pins.

4. All output speciﬁcations are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of

the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive

50-Ω load (see Figure 10).

5. t

/4 is one-fourth the period of L3_CLKn. This parameter indicates that the speciﬁed output signal is actually

L3_CLK

launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output

valid and output hold times such that the speciﬁed output signal will be valid for approximately one L3_CLK period

starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock

period after the edge it will be sampled.

6. Assumes default value of L3OHCR. See Section 1.5.2.4.1, “Effects of L3OHCR Settings on L3 Bus AC

Speciﬁcations” for more information.

28

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

Figure 11 shows the typical connection diagram for the MPC7457 interfaced to PB2 SRAMs or Late Write

SRAMs.

SRAM 0

L3_ADDR[16:0]

L3_CNTL[0]

L3_CNTL[1]

MPC7457

SA[16:0]

SS

SW

L3_ECHO_CLK[0]

Denotes

Receive (SRAM

to MPC7457)

Aligned Signals

{L3_DATA[0:15], L3_DP[0:1]}

DQ[0:17]

GND

ZZ

G

L3_CLK[0]

K

{L3_DATA[16:31], L3_DP[2:3]}

1

GV /2

DQ[18:36]

K

DD

L3_ECHO_CLK[1]

L3_ECHO_CLK[2]

Denotes

Transmit

SRAM 1

SA[16:0]

(MPC7457 to

SRAM)

SS

Aligned Signals

SW

{L3_DATA[32:47], L3_DP[4:5]}

L3_CLK[1]

GND

ZZ

G

DQ[0:17]

K

{L3_DATA[48:63], L3_DP[6:7]}

1

DQ[18:36]

K

GV /2

DD

L3_ECHO_CLK[3]

Note:

1. Or as recommended by SRAM manufacturer for single-ended clocking.

Figure 11. Typical Synchronous 1-MByte L3 Cache Late Write or PB2 Interface

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MPC7457 RISC Microprocessor Hardware Speciﬁcations

29

Electrical and Thermal Characteristics

Figure 12 shows the L3 bus timing diagrams for the MPC7457 interfaced to PB2 or Late Write SRAMs.

Outputs

L3_CLK[0,1]

L3_ECHO_CLK[1,3]

VM

t

L3CHOX

L3CHOV

ADDR, L3_CNTL

t

L3CHOZ

t

L3CHDV

L3CHDX

L3DATA WRITE

t

L3CHDZ

Inputs

L3_ECHO_CLK[0,2]

VM

t

L3DVEH

t

L3DXEH

Parity Inputs

L3 Data and Data

VM = Midpoint Voltage (GV /2)

DD

Figure 12. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs

1.5.2.5

IEEE 1149.1 AC Timing Speciﬁcations

Table 15 provides the IEEE 1149.1 (JTAG) AC timing speciﬁcations as deﬁned in Figure 14 through

Figure 17.

1

Table 15. JTAG AC Timing Speciﬁcations (Independent of SYSCLK)

At recommended operating conditions. See Table 4.

Parameter

TCK frequency of operation

Symbol

Min

Max

Unit

Notes

f

t

0

33.3

—

MHz

ns

TCLK

TCK cycle time

30

15

0

TCLK

TCK clock pulse width measured at 1.4 V

TCK rise and fall times

TRST assert time

t

—

ns

JHJL

t

and t

2

ns

JR

JF

t

25

—

ns

2

3

TRST

Input setup times:

Boundary-scan data

TMS, TDI

ns

t

4

0

—

DVJH

IVJH

t

Input hold times:

Boundary-scan data

TMS, TDI

ns

3

4

t

20

25

—

DXJH

IXJH

t

Valid times:

Boundary-scan data

TDO

t

4

20

25

JLDV

JLOV

30

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

1

Table 15. JTAG AC Timing Speciﬁcations (Independent of SYSCLK) (continued)

At recommended operating conditions. See Table 4.

Parameter

Symbol

Min

Max

Unit

Notes

Output hold times:

Boundary-scan data

TDO

ns

4

t

TBD

JLDX

JLOX

TCK to output high impedance:

Boundary-scan data

TDO

ns

4, 5

t

3

19

9

JLDZ

JLOZ

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal

in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load

(see Figure 13). Time-of-ﬂight delays must be added for trace lengths, vias, and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization.

Figure 13 provides the AC test load for TDO and the boundary-scan outputs of the MPC7457.

Output

OV /2

DD

Z = 50 Ω

0

R = 50 Ω

L

Figure 13. Alternate AC Test Load for the JTAG Interface

Figure 14 provides the JTAG clock input timing diagram.

TCLK

VM

t

VM

t

JF

JHJL

JR

t

TCLK

VM = Midpoint Voltage (OV /2)

DD

Figure 14. JTAG Clock Input Timing Diagram

Figure 15 provides the TRST timing diagram.

VM

TRST

t

TRST

VM = Midpoint Voltage (OV /2)

DD

Figure 15. TRST Timing Diagram

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MPC7457 RISC Microprocessor Hardware Speciﬁcations

31

Electrical and Thermal Characteristics

Figure 16 provides the boundary-scan timing diagram.

TCK

VM

t

DVJH

t

DXJH

Boundary

Input

Data Valid

Data Inputs

t

JLDV

t

JLDX

Boundary

Output Data Valid

Data Outputs

t

JLDZ

Boundary

Data Outputs

Output Data Valid

VM = Midpoint Voltage (OV /2)

DD

Figure 16. Boundary-Scan Timing Diagram

Figure 17 provides the test access port timing diagram.

TCK

TDI, TMS

TDO

VM

t

IVJH

t

IXJH

Input

Data Valid

t

JLOV

JLOX

t

Output Data Valid

t

JLOZ

TDO

Output Data Valid

VM = Midpoint Voltage (OV /2)

DD

Figure 17. Test Access Port Timing Diagram

32

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Pin Assignments

1.6 Pin Assignments

Figure 18 (in PartA) shows the pinout of the MPC7447, 360 CBGA package as viewed from the top surface.

Part B shows the side proﬁle of the CBGA package to indicate the direction of the top surface view.

Part A

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Not to Scale

Part B

Substrate Assembly

Encapsulant

View

Die

Figure 18. Pinout of the MPC7447, 360 CBGA Package as Viewed from the Top Surface

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

33

Pin Assignments

Figure 19 (in PartA) shows the pinout of the MPC7457, 483 CBGA package as viewed from the top surface.

Part B shows the side proﬁle of the CBGA package to indicate the direction of the top surface view.

Part A

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

Not to Scale

Part B

Substrate Assembly

Encapsulant

View

Die

Figure 19. Pinout of the MPC7457, 483 CBGA Package as Viewed from the Top Surface

34

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Pinout Listings

1.7 Pinout Listings

Table 16 provides the pinout listing for the MPC7447, 360 CBGA package. Table 17 provides the pinout

listing for the MPC7457, 483 CBGA package.

NOTE

This pinout is not compatible with the MPC750, MPC7400, or MPC7410

360 BGA package.

Table 16. Pinout Listing for the MPC7447, 360 CBGA Package

1

Signal Name

A[0:35]

Pin Number

Active

I/O

I/F Select

Notes

E11, H1, C11, G3, F10, L2, D11, D1, C10,

G2, D12, L3, G4, T2, F4, V1, J4, R2, K5,

W2, J2, K4, N4, J3, M5, P5, N3, T1, V2,

U1, N5, W1, B12, C4, G10, B11

High

I/O

BVSEL

2

AACK

R1

Low

High

Low

—

Input

I/O

BVSEL

N/A

AP[0:4]

ARTRY

C1, E3, H6, F5, G7

N2

A8

M1

G9

F8

D2

B7

J1

I/O

3

AV

Input

Output

Input

Output

Input

Output

I/O

DD

BG

Low

High

Low

High

BVSEL

BMODE0

BMODE1

BR

4

5

BVSEL

CI

1, 6

3

CKSTP_IN

CKSTP_OUT

CLK_OUT

D[0:63]

A3

B1

H2

R15, W15,T14,V16, W16,T15, U15, P14,

V13,W13,T13, P13, U14,W14, R12,T12,

W12, V12, N11, N10, R11, U11, W11,

T11, R10, N9, P10, U10, R9, W10, U9,

V9, W5, U6, T5, U5, W7, R6, P7, V6, P17,

R19, V18, R18, V19, T19, U19, W19, U18,

W17, W18, T16, T18, T17, W3, V17, U4,

U8, U7, R7, P6, R8, W8, T8

DBG

M2

Low

High

Low

High

Low

Input

I/O

BVSEL

DP[0:7]

DRDY

T3, W4, T4, W9, M6, V3, N8, W6

R3

Output

Input

I/O

7

8

9

DTI[0:3]

EXT_QUAL

GBL

G1, K1, P1, N1

A11

E2

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

35

Pinout Listings

Table 16. Pinout Listing for the MPC7447, 360 CBGA Package (continued)

1

Signal Name

GND

Pin Number

Active

I/O

I/F Select

Notes

B5, C3, D6, D13, E17, F3, G17, H4, H7,

H9, H11, H13, J6, J8, J10, J12, K7, K3,

K9, K11, K13, L6, L8, L10, L12, M4, M7,

M9, M11, M13, N7, P3, P9, P12, R5, R14,

R17, T7, T10, U3, U13, U17, V5, V8, V11,

V15

—

N/A

HIT

B2

D8

D4

G8

B3

Low

High

—

Output

Input

—

BVSEL

—

7

HRESET

INT

L1_TSTCLK

L2_TSTCLK

No Connect

9

10

11

A6, A13, A14, A15, A16, A17, A18, A19,

B13, B14, B15, B16, B17, B18, B19, C13,

C14, C15, C16, C17, C18, C19, D14, D15,

D16, D17, D18, D19, E12, E13, E14, E15,

E16, E19, F12, F13, F14, F15, F16, F17,

F18, F19, G11, G12, G13, G14, G15,

G16, G19, H14, H15, H16, H17, H18,

H19, J14, J15, J16, J17, J18, J19, K15,

K16, K17, K18, K19, L14, L15, L16, L17,

L18, L19, M14, M15, M16, M17, M18,

M19, N12, N13, N14, N15, N16, N17,

N18, N19, P15, P16, P18, P19

LSSD_MODE

MCP

E8

C9

Low

—

Input

—

BVSEL

N/A

6, 12

OV

B4, C2, C12, D5, E18, F2, G18, H3, J5,

K2, L5, M3, N6, P2, P8, P11, R4, R13,

R16, T6, T9, U2, U12, U16, V4, V7, V10,

V14

DD

PLL_CFG[0:4]

PMON_IN

PMON_OUT

QACK

B8, C8, C7, D7, A7

High

Low

—

Input

Output

Input

Output

I/O

BVSEL

D9

13

3

A9

G5

QREQ

P4

SHD[0:1]

SMI

E4, H5

F9

Input

Output

SRESET

SYSCLK

TA

A2

A10

K6

Low

High

Low

TBEN

E1

TBST

F11

36

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Pinout Listings

Table 16. Pinout Listing for the MPC7447, 360 CBGA Package (continued)

1

Signal Name

TCK

Pin Number

Active

I/O

I/F Select

Notes

C6

B9

A4

L1

High

Low

—

Input

Output

Input

I/O

BVSEL

N/A

TDI

6

TDO

TEA

TEST[0:3]

TEST[4]

TMS

A12, B6, B10, E10

12

9

D10

—

F1

High

Low

High

Low

—

6

TRST

TS

A5

6, 14

3

L4

TSIZ[0:2]

TT[0:4]

WT

G6, F7, E7

E5, E6, F6, E9, C5

D3

Output

I/O

Output

—

3

V

H8, H10, H12, J7, J9, J11, J13, K8, K10,

K12, K14, L7, L9, L11, L13, M8, M10, M12

DD

Notes:

1. OV supplies power to the processor bus, JTAG, and all control signals;andV supplies power to the processor

DD

core and the PLL (after ﬁltering to become AV ). To program the I/O voltage, connect BVSEL to either GND

DD

(selects 1.8 V) or to HRESET (selects 2.5 V). If used, the pull-down resistor should be less than 250 Ω. For actual

recommended value of V or supply voltages see Table 4.

in

2. Unused address pins must be pulled down to GND.

3. These pins require weak pull-up resistors (for example, 4.7 kΩ) to maintain the control signals in the negated state

after they have been actively negated and released by the MPC7447 and other bus masters.

4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at

HRESET going high.

5. This signal must be negated during reset, by pull up to OV or negation by ¬HRESET (inverse of HRESET), to

DD

ensure proper operation.

6. Internal pull up on die.

7. Ignored in 60x bus mode.

8. These signals must be pulled down to GND if unused, or if the MPC7447 is in 60x bus mode.

9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.

10. This test signal is recommended to be tied to HRESET; however, other conﬁgurations will not adversely affect

performance.

11. These signals are for factory use only and must be left unconnected for normal machine operation.

12. These input signals are for factory use only and must be pulled up to OV for normal machine operation.

DD

13. This pin can externally cause a performance monitor event. Counting of the event is enabled via software.

14. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper

operation.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

37

Pinout Listings

Table 17. Pinout Listing for the MPC7457, 483 CBGA Package

1

Signal Name

Pin Number

Active

I/O

I/F Select

Notes

A[0:35]

E10, N4, E8, N5, C8, R2, A7, M2, A6, M1,

A10, U2, N2, P8, M8, W4, N6, U6, R5,Y4, P1,

P4, R6, M7, N7, AA3, U4, W2, W1, W3, V4,

AA1, D10, J4, G10, D9

High

I/O

BVSEL

2

AACK

U1

Low

High

Low

—

Input

I/O

BVSEL

N/A

AP[0:4]

ARTRY

L5, L6, J1, H2, G5

T2

B2

R3

C6

C4

K1

G6

R1

F3

K6

N1

I/O

3

AV

Input

Output

Input

Output

Input

Output

I/O

DD

BG

Low

High

Low

High

BVSEL

N/A

BMODE0

BMODE1

BR

4

5

BVSEL

CI

6, 7

3

BVSEL

CKSTP_IN

CKSTP_OUT

CLK_OUT

D[0:63]

AB15,T14, R14, AB13,V14, U14, AB14,W16,

AA11, Y11, U12, W13, Y14, U13, T12, W12,

AB12, R12, AA13, AB11,Y12, V11, T11, R11,

W10, T10, W11, V10, R10, U10, AA10, U9,

V7, T8, AB4, Y6, AB7, AA6, Y8, AA7, W8,

AB10, AA16, AB16, AB17, Y18, AB18, Y16,

AA18,W14, R13,W15, AA14,V16,W6, AA12,

V6, AB9, AB6, R7, R9, AA9, AB8, W9

DBG

V1

Low

High

Low

High

Low

Input

I/O

BVSEL

DP[0:7]

DRDY

AA2, AB3, AB2, AA8, R8, W5, U8, AB5

T6

Output

Input

I/O

8

9

DTI[0:3])

EXT_QUAL

GBL

P2, T5, U3, P6

B9

10

M4

38

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Pinout Listings

Table 17. Pinout Listing for the MPC7457, 483 CBGA Package (continued)

1

Signal Name

GND

Pin Number

Active

I/O

I/F Select

Notes

A22, B1, B5, B12, B14, B16, B18, B20, C3,

C9, C21, D7, D13, D15, D17, D19, E2, E5,

E21, F10, F12, F14, F16, F19, G4, G7, G17,

G21, H13, H15, H19, H5, J3, J10, J12, J14,

J17, J21, K5, K9, K11, K13, K15, K19, L10,

L12, L14, L17, L21, M3, M6, M9, M11, M13,

M19, N10, N12, N14, N17, N21, P3, P9, P11,

P13, P15, P19, R17, R21, T13, T15, T19, T4,

T7, T9, U17, U21, V2, V5, V8, V12, V15, V19,

W7, W17, W21, Y3, Y9, Y13, Y15, Y20, AA5,

AA17, AB1, AB22

—

N/A

GV

B13, B15, B17, B19, B21, D12, D14, D16,

D18, D21, E19, F13, F15, F17, F21, G19,

H12, H14, H17, H21, J19, K17, K21, L19,

M17, M21, N19, P17, P21, R15, R19, T17,

T21, U19, V17, V21, W19, Y21

—

N/A

11

8

DD

HIT

K2

A3

J6

Low

High

Output

Input

Output

BVSEL

N/A

HRESET

INT

L1_TSTCLK

L2_TSTCLK

L3VSEL

H4

J2

10

12

A4

6, 7

L3ADDR[18:0]

H11, F20, J16, E22, H18, G20, F22, G22,

H20, K16, J18, H22, J20, J22, K18, K20, L16,

K22, L18

L3VSEL

L3_CLK[0:1]

L3_CNTL[0:1]

L3DATA[0:63]

V22, C17

L20, L22

High

Low

High

Output

I/O

L3VSEL

AA19, AB20, U16, W18, AA20, AB21, AA21,

T16, W20, U18, Y22, R16, V20, W22, T18,

U20, N18, N20, N16, N22, M16, M18, M20,

M22, R18, T20, U22, T22, R20, P18, R22,

M15, G18, D22, E20, H16, C22, F18, D20,

B22, G16, A21, G15, E17, A20, C19, C18,

A19, A18, G14, E15, C16, A17, A16, C15,

G13, C14, A14, E13, C13, G12, A13, E12,

C12

L3DP[0:7]

AB19, AA22, P22, P16, C20, E16, A15, A12

High

HIgh

Low

—

I/O

Input

I/O

L3VSEL

BVSEL

N/A

L3_ECHO_CLK[0,2] V18, E18

L3_ECHO_CLK[1,3] P20, E14

LSSD_MODE

MCP

F6

B8

Input

—

7, 13

14

No Connect

A8, A11, B6, B11, C11, D11, D3, D5, E11, E7,

F2, F11, G2, H9

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

39

Pinout Listings

Table 17. Pinout Listing for the MPC7457, 483 CBGA Package (continued)

1

Signal Name

Pin Number

Active

I/O

I/F Select

Notes

OV

B3, C5, C7, C10, D2, E3, E9, F5, G3, G9, H7,

J5, K3, L7, M5, N3, P7, R4, T3, U5, U7, U11,

U15, V3, V9, V13, Y2, Y5, Y7, Y10, Y17, Y19,

AA4, AA15

—

N/A

DD

PLL_CFG[0:4]

PMON_IN

PMON_OUT

QACK

QREQ

SHD[0:1]

SMI

A2, F7, C2, D4, H8

High

Low

—

Input

Output

Input

Output

I/O

BVSEL

N/A

E6

15

3

B4

K7

Y1

L4, L8

G8

Input

Output

Input

Output

Input

I/O

SRESET

SYSCLK

TA

G1

D6

N8

Low

High

Low

High

Low

—

TBEN

L3

TBST

B7

TCK

J7

TDI

E4

7

TDO

H1

TEA

T1

TEST[0:5]

TEST[6]

TMS

B10, H6, H10, D8, F9, F8

13

10

A9

—

K4

High

Low

High

Low

—

7

TRST

C1

7, 16

3

TS

P5

TSIZ[0:2]

TT[0:4]

WT

L1,H3,D1

F1, F4, K8, A5, E1

L2

Output

I/O

Output

—

3

V

J9, J11, J13, J15, K10, K12, K14, L9, L11,

L13, L15, M10, M12, M14, N9, N11, N13, N15,

P10, P12, P14

DD

40

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Package Description

Table 17. Pinout Listing for the MPC7457, 483 CBGA Package (continued)

1

Signal Name

Pin Number

Active

I/O

I/F Select

Notes

VDD_SENSE[0:1]

G11, J8

—

N/A

17

Notes:

1. OV supplies power to the processor bus, JTAG, and all control signals except the L3 cache controls

DD

(L3CTL[0:1]); GV supplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7],

DD

L3_ECHO_CLK[0:3], and L3_CLK[0:1]) and the L3 control signals L3_CNTL[0:1]; and V supplies power to the

DD

processor core and the PLL (after ﬁltering to become AV ). For actual recommended value of V or supply

DD

in

voltages, see Table 4.

2. Unused address pins must be pulled down to GND.

3. These pins require weak pull-up resistors (for example, 4.7 kΩ) to maintain the control signals in the negated state

after they have been actively negated and released by the MPC7457 and other bus masters.

4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at

HRESET going high.

5. This signal must be negated during reset, by pull up to OV or negation by ¬HRESET (inverse of HRESET), to

DD

ensure proper operation.

6. To program the processor interface I/O voltage, connect BVSEL to either GND (selects 1.8 V) or to HRESET

(selects 2.5 V).To program the L3 interface, connect L3VSEL to either GND (selects 1.8 V) or to HRESET (selects

2.5 V). If used, pull-down resistors should be less than 250 Ω.

7. Internal pull up on die.

8. Ignored in 60x bus mode.

9. These signals must be pulled down to GND if unused or if the MPC7457 is in 60x bus mode.

10. These input signals for factory use only and must be pulled down to GND for normal machine operation.

11. Power must be supplied to GV , even when the L3 interface is disabled or unused.

DD

12. This test signal is recommended to be tied to HRESET; however, other conﬁgurations will not adversely affect

performance.

13. These input signals are for factory use only and must be pulled up to OV for normal machine operation.

DD

14. These signals are for factory use only and must be left unconnected for normal machine operation.

15. This pin can externally cause a performance monitor event. Counting of the event is enabled via software.

16. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper

operation.

17. These pins are internally connected to V . They are intended to allow an external device to detect the core

DD

voltage level present at the processor core. If unused, they must be connected directly to V or left unconnected.

DD

1.8 Package Description

The following sections provide the package parameters and mechanical dimensions for the CBGA package.

1.8.1 Package Parameters for the MPC7447, 360 CBGA

The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360-lead

ceramic ball grid array (CBGA).

Package outline

Interconnects

Pitch

25 × 25 mm

360 (19 × 19 ball array – 1)

1.27 mm (50 mil)

Minimum module height 2.72 mm

Maximum module height 3.24 mm

Ball diameter

0.89 mm (35 mil)

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

41

Package Description

1.8.2 Mechanical Dimensions for the MPC7447, 360 CBGA

Figure 20 provides the mechanical dimensions and bottom surface nomenclature for the MPC7447, 360

CBGA package.

2X

Capacitor Region

0.2

NOTES:

D

B

1. DIMENSIONING AND

TOLERANCING PER ASME

Y14.5M, 1994.

D1

D2

D3

A1 CORNER

2. DIMENSIONS IN

MILLIMETERS.

A

3. TOP SIDE A1 CORNER

INDEX IS A METALIZED

FEATURE WITH VARIOUS

SHAPES.BOTTOM SIDE A1

CORNER IS DESIGNATED

WITH A BALL MISSING

FROM THE ARRAY.

0.15 A

E3

E4

E

Millimeters

E2

E1

DIM

MIN

MAX

A

2.72

0.80

1.10

—

3.20

1.00

1.30

0.6

2X

A1

A2

A3

b

0.2

D4

C

171819

2 3 4 5 6 7 8 9 10 111213141516

1

W

V

U

0.82

0.93

T

R

P

N

M

L

D

25.00 BSC

D1

D2

D3

D4

e

—

8.0

—

11.3

—

A3

K

J

6.5

A2

A1

H

G

F

10.9

11.1

E

D

C

B

A

1.27 BSC

25.00 BSC

0.35 A

E

E1

E2

E3

E4

—

8.0

—

11.3

e

360X

b

—

6.5

0.3 A B C

A

0.15

9.55

9.75

Figure 20. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7447,

360 CBGA Package

42

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Package Description

1.8.3 Substrate Capacitors for the MPC7447, 360 CBGA

Figure 21 shows the connectivity of the substrate capacitor pads for the MPC7447, 360 CBGA. All

capacitors are 100 nF.

Pad Number

Capacitor

A1 CORNER

-1

-2

C1

C2

GND

V

DD

V

C1-1 C2-1 C3-1 C4-1 C5-1 C6-1

C1-2 C2-2 C3-2 C4-2 C5-2 C6-2

C3

OV

DD

C4

V

DD

C5

DD

C6

C7

C8

C9

OV

DD

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

V

DD

C18-2 C17-2 C16-2 C15-2 C14-2 C13-2

C18-1 C17-1 C16-1 C15-1 C14-1 C13-1

OV

DD

V

DD

OV

DD

V

DD

OV

DD

V

DD

Figure 21. Substrate Bypass Capacitors for the MPC7447, 360 CBGA

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

43

Package Description

1.8.4 Package Parameters for the MPC7457, 483 CBGA

The package parameters are as provided in the following list. The package type is 29 × 29 mm, 483-lead

ceramic ball grid array (CBGA).

Package outline

Interconnects

29 × 29 mm

483 (22 × 22 ball array – 1)

1.27 mm (50 mil)

—

Pitch

Minimum module height

Maximum module height 3.22 mm

Ball diameter

0.89 mm (35 mil)

1.8.5 Mechanical Dimensions for the MPC7457, 483 CBGA

Figure 21 provides the mechanical dimensions and bottom surface nomenclature for the MPC7457, 483

CBGA package.

44

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Package Description

2X

Capacitor Region

0.2

D

B

D1

D2

NOTES:

D3

A1 CORNER

1. DIMENSIONINGAND

TOLERANCING

A

PER ASME Y14.5M, 1994.

2. DIMENSIONSIN

MILLIMETERS.

0.15 A

3. TOP SIDE A1 CORNER

INDEX IS A METALIZED

FEATURE WITH VARIOUS

SHAPES. BOTTOM SIDE.

A1 CORNER IS

E3

E2

E

E4

DESIGNATEDWITH A BALL

MISSING FROM THE

ARRAY.

E1

Millimeters

DIM

MIN

MAX

2X

0.2

A

2.72

0.80

1.10

--

3.20

1.00

1.30

0.60

0.93

D4

C

A1

A2

A3

b

20

3 4 5 6 7 8 9 10 111213141516 171819 21 22

1 2

AB

AA

Y

0.82

W

V

D

29.00 BSC

U

T

D1

D2

D3

D4

e

—

8.5

—

12.5

—

R

P

N

M

L

A3

8.4

K

J

A2

A1

10.9

11.1

H

G

F

1.27 BSC

29.00 BSC

A

E

D

C

B

A

E

0.35 A

E1

E2

E3

E4

—

8.5

—

12.5

—

8.4

e

483X

b

0.3 A B C

0.15

9.55

9.75

A

Figure 22. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7457,

483 CBGA Package

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

45

Package Description

1.8.6 Substrate Capacitors for the MPC7457, 483 CBGA

Figure 23 shows the connectivity of the substrate capacitor pads for the MPC7457, 483 CBGA. All

capacitors are 100 nF.

Pad Number

A1 CORNER

Capacitor

-1

-2

C1

C2

GND

OV

DD

C1-1 C2-1 C3-1

C1-2 C2-2 C3-2

C4-1 C5-1 C6-1

C4-2 C5-2 C6-2

V

DD

C3

GV

DD

C4

V

DD

C5

C6

GV

DD

C7

V

DD

C8

C9

GV

DD

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

V

DD

GV

DD

V

DD

C18-2 C17-2 C16-2 C15-2 C14-2 C13-2

C18-1 C17-1 C16-1 C15-1 C14-1 C13-1

OV

DD

V

DD

OV

DD

V

DD

OV

DD

V

DD

Figure 23. Substrate Bypass Capacitors for the MPC7457, 483 CBGA

46

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

System Design Information

1.9 System Design Information

This section provides system and thermal design recommendations for successful application of the

MPC7457.

1.9.1 PLL Conﬁguration

The MPC7457 PLL is conﬁgured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency, the

PLL conﬁguration signals set the internal CPU and VCO frequency of operation. The PLL conﬁguration for

the MPC7457 is shown in Table 18 for a set of example frequencies. In this example, shaded cells represent

settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with

the 1-GHz column in Table 8. Note that these conﬁgurations were different in devices prior to Rev F; see

Section 1.11.2, “Part Numbers Not Fully Addressed by This Document,” for more information regarding

documentation of prior revisions.

Table 18. MPC7457 Microprocessor PLL Conﬁguration Example for 1.3 GHz Parts

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-

Core

Core-to-

VCO

Bus (SYSCLK) Frequency

PLL_

CFG[0:4]

33.3

MHz

50

MHz

66.6

MHz

75

MHz

83

MHz

100

MHz

133

MHz

167

MHz

Multiplier Multiplier

01000

10000

10100

10110

10010

11010

01010

00100

00010

11000

01100

01111

01110

2x

3x

2x

500

(1000)

4x

532

667

(1064) (1333)

5x

500

667

835

(1000) (1333) (1670)

5.5x

6x

550

733

919

(1100) (1466) (1837)

600 800 1002

(1200) (1600) (2004)

650 866 1086

6.5x

7x

540

(1080) (1300) (1730) (2171)

525

580

700

931

1169

(1050) (1160) (1400) (1862) (2338)

7.5x

8x

500

563

623

750

1000

1253

(1000) (1125) (1245) (1500) (2000) (2505)

533

600

664

800

1064

(1066) (1200) (1328) (1600) (2128)

8.5x

9x

566 638 706 850 1131

(1132) (1276) (1412) (1700) (2261)

600 675 747 900 1197

(1200) (1350) (1494) (1800) (2394)

633 712 789 950 1264

9.5x

(1266) (1524) (1578) (1900) (2528)

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

47

System Design Information

Table 18. MPC7457 Microprocessor PLL Conﬁguration Example for 1.3 GHz Parts (continued)

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-

Core

Core-to-

VCO

Bus (SYSCLK) Frequency

PLL_

CFG[0:4]

33.3

MHz

50

MHz

66.6

MHz

75

MHz

83

MHz

100

MHz

133

MHz

167

MHz

Multiplier Multiplier

10101

10001

10011

00000

10111

11111

01011

11100

11001

00011

11011

00001

00101

00111

01001

01101

11101

00110

10x

10.5x

11x

2x

500

667

750

830

1000

(1000) (1333) (1500) (1660) (2000)

525

700

938

872

1050

(1050) (1400) (1876) (1744) (2100)

550 733 825 913 1100

(1100) (1466) (1650) (1826) (2200)

11.5x

12x

575

(1150)

766

(532)

863

955

1150

(1726) (1910) (2300)

600

800

900 996 1200

(1200) (1600) (1800) (1992) (2400)

12.5x

13x

600

833

938

1038

1250

(1200) (1666) (1876) (2076) (2500)

650 865 975 1079 1300

(1300) (1730) (1950) (2158) (2600)

675 900 1013 1121

13.5x

14x

(1350) (1800) (2026) (2242)

700 933 1050 1162

(1400) (1866) (2100) (2324)

750 1000 1125 1245

15x

500

(1000) (1500) (2000) (2250) (2490)

16x

533

800

1066

1200

(1066) (1600) (2132) (2400)

17x

566 850 1132 1275

(1132) (1900) (2264) (2550)

600 900 1200

18x

(1200) (1800) (2400)

667 1000

20x

(1334) (2000)

700 1050

(1400) (2100)

21x

24x

800

1200

(1600) (2400)

28x

933

(1866)

PLL bypass

PLL off, SYSCLK clocks core circuitry directly

48

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

System Design Information

Table 18. MPC7457 Microprocessor PLL Conﬁguration Example for 1.3 GHz Parts (continued)

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-

Core

Core-to-

VCO

Bus (SYSCLK) Frequency

PLL_

CFG[0:4]

33.3

MHz

50

MHz

66.6

MHz

75

MHz

83

MHz

100

MHz

133

MHz

167

MHz

Multiplier Multiplier

11110

PLL off

PLL off, no core clocking occurs

Notes:

1. PLL_CFG[0:4] settings not listed are reserved.

2. The sample bus-to-core frequencies shown are for reference only. Some PLL conﬁgurations may select bus,

core, or VCO frequencies which are not useful, not supported, or not tested for by the MPC7455; see

Section 1.5.2.1, “Clock AC Speciﬁcations,” for valid SYSCLK, core, and VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled.

However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL,

must be driven at one-half the frequency of SYSCLK and offset in phase to meet the required input setup t

IVKH

and hold time t

(see Table 9). The result will be that the processor bus frequency will be one-half SYSCLK

IXKH

while the internal processor is clocked at SYSCLK frequency. This mode is intended for factory use and

emulator tool use only.

Note: The AC timing speciﬁcations given in this document do not apply in PLL-bypass mode.

4. In PLL-off mode, no clocking occurs inside the MPC7455 regardless of the SYSCLK input.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

49

System Design Information

1.9.2 PLL Power Supply Filtering

The AV power signal is provided on the MPC7457 to provide power to the clock generation PLL. To

DD

ensure stability of the internal clock, the power supplied to the AV input signal should be ﬁltered of any

DD

noise in the 500 kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in

Figure 22 using surface mount capacitors with minimum effective series inductance (ESL) is recommended.

The circuit should be placed as close as possible to the AV pin to minimize noise coupled from nearby

DD

circuits. It is often possible to route directly from the capacitors to the AV pin, which is on the periphery

DD

of the 360 CBGA footprint and very close to the periphery of the 483 CBGA footprint, without the

inductance of vias.

The PLL power supply ﬁlter provided in the MPC7457 RISC Microprocessor Hardware Speciﬁcations has

been found to be less effective for Rev 1.1 devices with the low core voltages described in this speciﬁcation.

As a result, the recommended value for the resistor in the circuit is being evaluated and a new

recommendation is indicated in Figure 24. Motorola continues to evaluate the ﬁltering requirements of the

MPC7457 and will make updated recommendations as needed. Note that this recommendation applies to

Rev. 1.1 devices only.

400 Ω

V

AV

DD

2.2 µF

Low ESL Surface Mount Capacitors

GND

Figure 24. PLL Power Supply Filter Circuit

1.9.3 Decoupling Recommendations

Due to the MPC7457 dynamic power management feature, large address and data buses, and high operating

frequencies, the MPC7457 can generate transient power surges and high frequency noise in its power

supply, especially while driving large capacitive loads. This noise must be prevented from reaching other

components in the MPC7457 system, and the MPC7457 itself requires a clean, tightly regulated source of

power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each

V

, OV , and GV

pin of the MPC7457. It is also recommended that these decoupling capacitors

DD

receive their power from separate V , OV /GV , and GND power planes in the PCB, utilizing short

DD

traces to minimize inductance.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic surface mount technology (SMT)

capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where

connections are made along the length of the part. Consistent with the recommendations of Dr. Howard

Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to

previous recommendations for decoupling Motorola microprocessors, multiple small capacitors of equal

value are recommended over using multiple values of capacitance.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the V , GV , and OV planes, to enable quick recharging of the smaller chip capacitors. These

DD

bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response time

necessary. They should also be connected to the power and ground planes through two vias to minimize

inductance. Suggested bulk capacitors: 100–330 µF (AVX TPS tantalum or Sanyo OSCON).

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

51

System Design Information

1.9.4 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level. Unused active low inputs should be tied to OV . Unused active high inputs should be connected to

DD

GND. All NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external V , OV , GV , and GND pins in the

DD

MPC7457. If the L3 interface is not used, GV

should be connected to the OV power plane, and

DD

L3VSEL should be connected to BVSEL; the remainder of the L3 interface may be left unterminated.

1.9.5 Output Buffer DC Impedance

The MPC7457 processor bus and L3 I/O drivers are characterized over process, voltage, and temperature.

To measure Z , an external resistor is connected from the chip pad to OV or GND. Then, the value of

0

DD

each resistor is varied until the pad voltage is OV /2 (see Figure 23).

DD

The output impedance is the average of two components, the resistances of the pull-up and pull-down

devices. When data is held low, SW2 is closed (SW1 is open), and R is trimmed until the voltage at the

N

pad equals OV /2. R then becomes the resistance of the pull-down devices. When data is held high, SW1

DD

N

is closed (SW2 is open), and R is trimmed until the voltage at the pad equals OV /2. R then becomes

P

DD

P

the resistance of the pull-up devices. R and R are designed to be close to each other in value. Then, Z =

P

N

0

(R + R )/2.

P

N

OV

DD

R

N

SW2

SW1

Pad

Data

R

P

OGND

Figure 25. Driver Impedance Measurement

Table 20 summarizes the signal impedance results. The impedance increases with junction temperature and

is relatively unaffected by bus voltage.

Table 20. Impedance Characteristics

V

= 1.5 V, OV = 1.8 V ± 5%, T = 5°–85°C

DD

DD j

Impedance

Processor Bus

L3 Bus

Unit

Z

Typical

33–42

31–51

34–42

32–44

Ω

0

Maximum

52

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

System Design Information

1.9.6 Pull-Up/Pull-Down Resistor Requirements

The MPC7457 requires high-resistive (weak: 4.7-kΩ) pull-up resistors on several control pins of the bus

interface to maintain the control signals in the negated state after they have been actively negated and

released by the MPC7457 or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.

Some pins designated as being for factory test must be pulled up to OV or down to GND to ensure proper

DD

device operation. For the MPC7447, 360 BGA, the pins that must be pulled up to OV are: LSSD_MODE

DD

and TEST[0:3]; the pins that must be pulled down to GND are: L1_TSTCLK and TEST[4]. For the

MPC7457, 483 BGA, the pins that must be pulled up to OV are: LSSD_MODE and TEST[0:5]; the pins

DD

that must be pulled down are: L1_TSTCLK and TEST[6]. The CKSTP_IN signal should likewise be pulled

up through a pull-up resistor (weak or stronger: 4.7–1 kΩ) to prevent erroneous assertions of this signal.

In addition, the MPC7457 has one open-drain style output that requires a pull-up resistor (weak or stronger:

4.7–1 kΩ) if it is used by the system. This pin is CKSTP_OUT.

If pull-down resistors are used to conﬁgure BVSEL or L3VSEL, the resistors should be less than 250 Ω (see

Table 16). Because PLL_CFG[0:4] must remain stable during normal operation, strong pull-up and

pull-down resistors (1 kΩ or less) are recommended to conﬁgure these signals in order to protect against

erroneous switching due to ground bounce, power supply noise or noise coupling.

During inactive periods on the bus, the address and transfer attributes may not be driven by any master and

may, therefore, ﬂoat in the high-impedance state for relatively long periods of time. Because the MPC7457

must continually monitor these signals for snooping, this ﬂoat condition may cause excessive power draw

by the input receivers on the MPC7457 or by other receivers in the system. It is recommended that these

signals be pulled up through weak (4.7-kΩ) pull-up resistors by the system, or that they may be otherwise

driven by the system during inactive periods of the bus. The snooped address and transfer attribute inputs

are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.

If extended addressing is not used, A[0:3] are unused and must be pulled low to GND through weak

pull-down resistors. If the MPC7457 is in 60x bus mode, DTI[0:3] must be pulled low to GND through weak

pull-down resistors.

The data bus input receivers are normally turned off when no read operation is in progress and, therefore,

do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require

pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The

data bus signals are: D[0:63] and DP[0:7].

If address or data parity is not used by the system, and the respective parity checking is disabled through

HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and

should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity

checking should also be disabled through HID0, and all parity pins may be left unconnected by the system.

The L3 interface does not normally require pull-up resistors.

1.9.7 JTAG Conﬁguration Signals

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the

IEEE 1149.1 speciﬁcation, but is provided on all processors that implement the PowerPC architecture.

While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more

reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.

Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,

simply tying TRST to HRESET is not practical.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

53

System Design Information

The COP function of these processors allows a remote computer system (typically, a PC with dedicated

hardware and debugging software) to access and control the internal operations of the processor. The COP

interface connects primarily through the JTAG port of the processor, with some additional status monitoring

signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control

the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers,

power supply failures, or push-button switches, then the COP reset signals must be merged into these signals

with logic.

The arrangement shown in Figure 24 allows the COP port to independently assert HRESET or TRST, while

ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used,

TRST should be tied to HRESET through a 0-Ω isolation resistor so that it is asserted when the system reset

signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during power-on. While

Motorola recommends that the COP header be designed into the system as shown in Figure 24, if this is not

possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need

to be wired onto the system in debug situations.

The COP header shown in Figure 24 adds many beneﬁts—breakpoints, watchpoints, register and memory

examination/modiﬁcation, and other standard debugger features are possible through this interface—and

can be as inexpensive as an unpopulated footprint for a header to be added when needed.

The COP interface has a standard header for connection to the target system, based on the 0.025"

square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has

pin 14 removed as a connector key.

There is no standardized way to number the COP header shown in Figure 24; consequently, many different

pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then

left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter

clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in

Figure 24 is common to all known emulators.

The QACK signal shown in Figure 24 is usually connected to the PCI bridge chip in a system and is an input

to the MPC7457 informing it that it can go into the quiescent state. Under normal operation this occurs

during a low-power mode selection. In order for COP to work, the MPC7457 must see this signal asserted

(pulled down). While shown on the COP header, not all emulator products drive this signal. If the product

does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator products

implement open-drain type outputs and can only drive QACK asserted; for these tools, a pull-up resistor can

be implemented to ensure this signal is deasserted when it is not being driven by the tool. Note that the

pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never necessary to

populate both in a system. To preserve correct power-down operation, QACK should be merged via logic

so that it also can be driven by the PCI bridge.

54

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

System Design Information

SRESET

From Target

Board Sources

(if any)

SRESET

HRESET

QACK

10 kΩ

HRESET

13

11

OV

DD

SRESET

OV

DD

OV

5

0 Ω

TRST

1

3

5

7

9

2

4

6

8

TRST

4

VDD_SENSE

6

OV

DD

10 kΩ

2 kΩ

1

5

DD

CHKSTP_OUT

15

10 kΩ

10

OV

DD

Key

14

11 12

KEY

10 kΩ

2

DD

13

CHKSTP_IN

TMS

No Pin

CHKSTP_IN

TMS

8

9

1

3

7

2

15

16

COP Connector

Physical Pin Out

TDO

TDI

TDO

TDI

TCK

QACK

NC

QACK

10

6

3

OV

2 kΩ

DD

12

4

10 kΩ

16

Notes:

1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7457. Connect

pin 5 of the COP header to OV with a 10-kΩ pull-up resistor.

DD

2. Key location; pin 14 is not physically present on the COP header.

3. Component not populated. Populate only if debug tool does not drive QACK.

4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.

5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP

header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect

HRESET from the target source to TRST of the part through a 0-Ω isolation resistor.

6. Though deﬁned as a No-Connect, it is a common and recommended practice to use pin 12 as an

additional GND pin for improved signal integrity.

Figure 26. JTAG Interface Connection

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

55

System Design Information

1.9.8 Thermal Management Information

This section provides thermal management information for the ceramic ball grid array (CBGA) package for

air-cooled applications. Proper thermal control design is primarily dependent on the system-level

design—the heat sink, airﬂow, and thermal interface material. To reduce the die-junction temperature, heat

sinks may be attached to the package by several methods—spring clip to holes in the printed-circuit board

or package, and mounting clip and screw assembly (see Figure 25); however, due to the potential large mass

of the heat sink, attachment through the printed-circuit board is suggested. If a spring clip is used, the spring

force should not exceed 10 pounds.

CBGA Package

Heat Sink

Clip

Thermal

Interface Material

Printed-Circuit Board

Figure 27. Package Exploded Cross-Sectional View with Several Heat Sink Options

The board designer can choose between several types of heat sinks to place on the MPC7457. There are

several commercially available heat sinks for the MPC7457 provided by the following vendors:

Aavid Thermalloy

80 Commercial St.

Concord, NH 03301

Internet: www.aavidthermalloy.com

603-224-9988

408-749-7601

Alpha Novatech

473 Sapena Ct. #15

Santa Clara, CA 95054

Internet: www.alphanovatech.com

International Electronic Research Corporation (IERC) 818-842-7277

413 North Moss St.

Burbank, CA 91502

Internet: www.ctscorp.com

Tyco Electronics

800-522-6752

Chip Coolers™

P.O. Box 3668

Harrisburg, PA 17105-3668

Internet: www.chipcoolers.com

56

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

System Design Information

Wakeﬁeld Engineering

33 Bridge St.

603-635-5102

Pelham, NH 03076

Internet: www.wakeﬁeld.com

Ultimately, the ﬁnal selection of an appropriate heat sink depends on many factors, such as thermal

performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.

1.9.8.1 Internal Package Conduction Resistance

For the exposed-die packaging technology, shown in Table 3, the intrinsic conduction thermal resistance

paths are as follows:

•

The die junction-to-case (actually top-of-die since silicon die is exposed) thermal resistance

The die junction-to-ball thermal resistance

Figure 26 depicts the primary heat transfer path for a package with an attached heat sink mounted to a

printed-circuit board.

External Resistance

Radiation

Convection

Heat Sink

Thermal Interface Material

Die/Package

Die Junction

Package/Leads

Internal Resistance

Printed-Circuit Board

Radiation

Convection

External Resistance

(Note the internal versus external package resistance.)

Figure 28. C4 Package with Heat Sink Mounted to a Printed-Circuit Board

Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink

attach material (or thermal interface material), and ﬁnally to the heat sink where it is removed by forced-air

convection.

Because the silicon thermal resistance is quite small, for a ﬁrst-order analysis, the temperature drop in the

silicon may be neglected. Thus, the thermal interface material and the heat sink conduction/convective

thermal resistances are the dominant terms.

1.9.8.2 Thermal Interface Materials

A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the

thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism,

Figure 27 shows the thermal performance of three thin-sheet thermal-interface materials (silicone,

graphite/oil, ﬂoroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure.

As shown, the performance of these thermal interface materials improves with increasing contact pressure.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

57

System Design Information

The use of thermal grease signiﬁcantly reduces the interface thermal resistance. That is, the bare joint results

in a thermal resistance approximately seven times greater than the thermal grease joint.

Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board

(see Figure 25). Therefore, the synthetic grease offers the best thermal performance, considering the low

interface pressure and is recommended due to the high power dissipation of the MPC7457. Of course, the

selection of any thermal interface material depends on many factors—thermal performance requirements,

manufacturability, service temperature, dielectric properties, cost, etc.

Silicone Sheet (0.006 in.)

2

Bare Joint

Floroether Oil Sheet (0.007 in.)

Graphite/Oil Sheet (0.005 in.)

Synthetic Grease

1.5

1

0.5

0

10

20

30

40

50

60

70

80

Contact Pressure (psi)

Figure 29. Thermal Performance of Select Thermal Interface Material

The board designer can choose between several types of thermal interface. Heat sink adhesive materials

should be selected based on high conductivity, yet adequate mechanical strength to meet equipment

shock/vibration requirements. There are several commercially available thermal interfaces and adhesive

materials provided by the following vendors:

The Bergquist Company

18930 West 78 St.

800-347-4572

th

Chanhassen, MN 55317

Internet: www.bergquistcompany.com

Chomerics, Inc.

781-935-4850

77 Dragon Ct.

Woburn, MA 01888-4014

Internet: www.chomerics.com

58

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

System Design Information

Dow-Corning Corporation

Dow-Corning Electronic Materials

2200 W. Salzburg Rd.

800-248-2481

Midland, MI 48686-0997

Internet: www.dow.com

Shin-Etsu MicroSi, Inc.

10028 S. 51st St.

Phoenix, AZ 85044

888-642-7674

888-246-9050

Internet: www.microsi.com

Thermagon Inc.

4707 Detroit Ave.

Cleveland, OH 44102

Internet: www.thermagon.com

The following section provides a heat sink selection example using one of the commercially available heat

sinks.

1.9.8.3 Heat Sink Selection Example

For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:

T = T + T + (R + R

+ R ) × P

θsa d

j

I

r

θJC

θint

where:

T is the die-junction temperature

j

T is the inlet cabinet ambient temperature

I

T is the air temperature rise within the computer cabinet

r

R

is the junction-to-case thermal resistance

θJC

θint

θsa

is the adhesive or interface material thermal resistance

is the heat sink base-to-ambient thermal resistance

P is the power dissipated by the device

d

During operation, the die-junction temperatures (T ) should be maintained less than the value speciﬁed in

j

Table 4. The temperature of air cooling the component greatly depends on the ambient inlet air temperature

and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T )

a

may range from 30° to 40°C. The air temperature rise within a cabinet (T ) may be in the range of 5° to 10°C.

r

The thermal resistance of the thermal interface material (R ) is typically about 1.5°C/W. For example,

θint

assuming a T of 30°C, a T of 5°C, a CBGA package R

= 0.1, and a typical power consumption (P ) of

a

r

θJC

d

18.7 W, the following expression for T is obtained:

j

Die-junction temperature: T = 30°C + 5°C + (0.1°C/W + 1.5°C/W + θ ) × 18.7 W

j

sa

For this example, a R value of 2.1°C/W or less is required to maintain the die junction temperature below

θsa

the maximum value of Table 4.

Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common

ﬁgure-of-merit used for comparing the thermal performance of various microelectronic packaging

technologies, one should exercise caution when only using this metric in determining thermal management

because no single parameter can adequately describe three-dimensional heat ﬂow. The ﬁnal die-junction

operating temperature is not only a function of the component-level thermal resistance, but the system-level

design and its operating conditions. In addition to the component's power consumption, a number of factors

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

59

System Design Information

affect the ﬁnal operating die-junction temperature—airﬂow, board population (local heat ﬂux of adjacent

components), heat sink efﬁciency, heat sink attach, heat sink placement, next-level interconnect technology,

system air temperature rise, altitude, etc.

Due to the complexity and the many variations of system-level boundary conditions for today's

microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection,

and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models

for the board, as well as system-level designs.

For system thermal modeling, the MPC7447 and MPC7457 thermal model is shown in Figure 28. Four

volumes will be used to represent this device. Two of the volumes, solder ball, and air and substrate, are

modeled using the package outline size of the package. The other two, die, and bump and underﬁll, have the

same size as the die. The silicon die should be modeled 9.64 × 11.0 × 0.74 mm with the heat source applied

as a uniform source at the bottom of the volume. The bump and underﬁll layer is modeled as 9.64 × 11.0 ×

0.69 mm (or as a collapsed volume) with orthotropic material properties: 0.6 W/(m • K) in the xy-plane and

2 W/(m • K) in the direction of the z-axis. The substrate volume is 25 × 25 × 1.2 mm (MPC7447) or 29 ×

29 × 1.2 mm (MPC7457), and this volume has 18 W/(m • K) isotropic conductivity. The solder ball and air

layer is modeled with the same horizontal dimensions as the substrate and is 0.9 mm thick. It can also be

modeled as a collapsed volume using orthotropic material properties: 0.034 W/(m • K) in the xy-plane

direction and 3.8 W/(m • K) in the direction of the z-axis.

Die

Bump and Underfill

z

Substrate

Solder and Air

Conductivity

Value

Unit

Bump and Underﬁll

Side View of Model (Not to Scale)

k

0.6

2

W/(m • K)

x

y

z

x

Substrate

18

Substrate

Die

k

Solder Ball and Air

k

0.034

3.8

x

y

z

y

Top View of Model (Not to Scale)

Figure 30. Recommended Thermal Model of MPC7447 and MPC7457

60

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Document Revision History

1.10 Document Revision History

Table 21 provides a revision history for this hardware speciﬁcation.

Table 21. Document Revision History

Rev. No.

Substantive Change(s)

0

1

Initial release.

• Removed support for 1.5 V L3 interface voltage from Tables 3 and 4. 1.5 V I/O voltage is not

supported in current MPC7457 devices.

• Added package thermal characteristics values to Table 5, made minor revisions to Section 1.9.8.

• Added preliminary AC timing values to Tables 10 and 12.

• Added footnotes to Table 17.

1.1

2

Nontechnical reformatting

• Added substrate capacitor information in Sections 1.8.3 and 1.8.6.

• Increased minimum processor and VCO frequencies in Table 8 from 500 MHz and 1000 MHz to 600

MHz and 1200 MHz (respectively).

• Corrected maximum processor frequency for 1300 MHz devices inTable 8 (changed from 1333 MHz

to 1300 MHz).

• Added value for to t

Table 10.

L3CSKW1

• Added L3OHCR information in Section 1.5.2.4.1.

• Added values for t and t

to Table 11.

CO

ECI

• Added Note 8 to Table 13 and Note 6 to Table 14.

• Changed resistor value in PLL ﬁlter in Figure 24 from 10 Ω to 400 Ω.

• Added 867 MHz speed grade.

• Corrected Product Code in Tables 22 and 23.

• Added pull-up/pull-down recommendations for CKSTP_IN and PLL_CFG[0:4] to Section 1.9.6.

1.11 Ordering Information

Ordering information for the parts fully covered by this speciﬁcation document is provided in

Section 1.11.1, “Part Numbers Fully Addressed by This Document.” Note that the individual part numbers

correspond to a maximum processor core frequency. For available frequencies, contact your local Motorola

sales ofﬁce. In addition to the processor frequency, the part numbering scheme also includes an application

modiﬁer which may specify special application conditions. Each part number also contains a revision level

code which refers to the die mask revision number. Section 1.11.2, “Part Numbers Not Fully Addressed by

This Document,” lists the part numbers which do not fully conform to the speciﬁcations of this document.

These special part numbers require an additional document called a part number speciﬁcation.

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

61

Ordering Information

1.11.1 Part Numbers Fully Addressed by This Document

Table 22 provides the Motorola part numbering nomenclature for the MPC7457.

Table 22. Part Numbering Nomenclature

PPC

74x7

RX

nnnn

L

x

Product

Code

Part

Identiﬁer

Processor

Frequency

Application

Modiﬁer

Package

Revision Level

1

2

PPC

7457

7447

RX = CBGA

867

1000

1300

L: 1.3 V ± 50 mV

B: 1.1; PVR = 8002 0101

0 to 105°C

Notes:

1. Processor core frequencies supported by parts addressed by this speciﬁcation only. Parts addressed by part

number speciﬁcations may support other maximum core frequencies.

2. The P preﬁx in a Motorola part number designates a “Pilot Production Prototype” as deﬁned by Motorola SOP 3-13.

These parts have only preliminary reliability and characterization data. Before pilot production prototypes may be

shipped, written authorization from the customer must be on ﬁle in the applicable sales ofﬁce acknowledging the

qualiﬁcation status and the fact that product changes may still occur while shipping pilot production prototypes.

62

MPC7457 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Ordering Information

1.11.2 Part Numbers Not Fully Addressed by This Document

Parts with application modiﬁers or revision levels not fully addressed in this speciﬁcation document are

described in separate part number speciﬁcations which supplement and supersede this document. As such

parts are released, these speciﬁcations will be listed in this section.

Table 23. Part Numbering Nomenclature

PPC

74x7

RX

nnnn

N

x

Product

Code

Part

Identiﬁer

Processor

Frequency

Application

Modiﬁer

Package

Revision Level

1

PPC

7457

7447

RX = CBGA

1000

N: 1.1 V ± 50 mV

B: 1.1; PVR = 8002 0101

0 to 105°C

1.11.3 Part Marking

Parts are marked as the example shown in Figure 29.

PPC7457

RX1300LB

PPC7447

RX1300LB

MMMMMM

ATWLYYWWA

MMMMMM

ATWLYYWWA

7447

BGA

7457

BGA

Notes:

MMMMMM is the 6-digit mask number.

ATWLYYWWA is the traceability code.

CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.

Figure 31. Part Marking for BGA Device

MOTOROLA

MPC7457 RISC Microprocessor Hardware Speciﬁcations

63

HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:

Motorola Literature Distribution

P.O. Box 5405, Denver, Colorado 80217

1-480-768-2130

(800) 521-6274

JAPAN:

Motorola Japan Ltd.

SPS, Technical Information Center

3-20-1, Minami-Azabu Minato-ku

Tokyo 106-8573 Japan

Information in this document is provided solely to enable system and software implementers to use

Motorola products.There are no express or implied copyright licenses granted hereunder to design

or fabricate any integrated circuits or integrated circuits based on the information in this document.

81-3-3440-3569

ASIA/PACIFIC:

Motorola Semiconductors H.K. Ltd.

Silicon Harbour Centre, 2 Dai King Street

Tai Po Industrial Estate, Tai Po, N.T., Hong Kong

852-26668334

Motorola reserves the right to make changes without further notice to any products herein.

Motorola makes no warranty, representation or guarantee regarding the suitability of its products

for any particular purpose, nor does Motorola assume any liability arising out of the application or

use of any product or circuit, and speciﬁcally disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters which may be provided in

Motorola data sheets and/or speciﬁcations can and do vary in different applications and actual

performance may vary over time. All operating parameters, including “Typicals” must be validated

for each customer application by customer’s technical experts. Motorola does not convey any

license under its patent rights nor the rights of others. Motorola products are not designed,

intended, or authorized for use as components in systems intended for surgical implant into the

body, or other applications intended to support or sustain life, or for any other application in which

the failure of the Motorola product could create a situation where personal injury or death may

occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized

application, Buyer shall indemnify and hold Motorola and its ofﬁcers, employees, subsidiaries,

afﬁliates, and distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that Motorola was

negligent regarding the design or manufacture of the part.

TECHNICAL INFORMATION CENTER:

(800) 521-6274

HOME PAGE:

www.motorola.com/semiconductors

Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Ofﬁce.

digital dna is a trademark of Motorola, Inc. The described product is a PowerPC microprocessor.

The PowerPC name is a trademark of IBM Corp. and used under license. All other product or

service names are the property of their respective owners. Motorola, Inc. is an Equal

Opportunity/Afﬁrmative Action Employer.

MPC7457EC/D


型号：	PPC7457RX1300LB
厂家：	MOTOROLA
描述：	RISC Microprocessor, 32-Bit, 1300MHz, CMOS, CBGA483, 29 X 29 MM, 1.27 MM HEIGHT, CERAMIC, BGA-483 时钟外围集成电路
文件：	总64页 (文件大小：1101K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PPC7457RX1300LB [MOTOROLA]

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