SCM6323AYJ12A [MOTOROLA]
64K x 16 Bit 3.3 V Asynchronous Fast Static RAM; 64K ×16位3.3 V的异步快速静态RAM
| 型号： | SCM6323AYJ12A |
| 厂家： | 
MOTOROLA |
| 描述： | 64K x 16 Bit 3.3 V Asynchronous Fast Static RAM |
| 文件： | 总12页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MCM6323A/D
SEMICONDUCTOR TECHNICAL DATA
MCM6323A
Product Preview
64K x 16 Bit 3.3 V Asynchronous
Fast Static RAM
The MCM6323A is a 1,048,576 bit static random access memory organized
as 65,536 words of 16 bits. Static design eliminates the need for external clocks
or timing strobes; CMOS circuitry reduces power consumption and provides for
greater reliability.
YJ PACKAGE
400 MIL SOJ
CASE 919–01
TS PACKAGE
44–LEAD
The MCM6323A is equipped with chip enable (E), write enable (W), and output
enable (G) pins, allowing for greater system flexibility and eliminating bus contention
problems. Separate byte enable controls (LB and UB) allow individual bytes to be
written and read. LB controls the 8 DQa bits, while UB controls the 8 DQb bits.
The MCM6323A is available in a 400 mil small–outline J–leaded (SOJ) pack-
age and a 44–lead TSOP Type II package in copper leadframe for optimum
printed circuit board (PCB) reliability.
TSOP TYPE II
CASE 924A–01
PIN ASSIGNMENT
A
A
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
A
•
•
•
•
•
•
•
•
Single 3.3 V ± 0.3 V Power Supply
Fast Access Time: 10, 12, 15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Data Byte Control
A
A
A
A
G
A
UB
LB
E
Fully Static Operation
DQa
DQa
DQa
DQa
DQb
DQb
DQb
DQb
Power Operation: 140/135/130 mA Maximum, Active AC
Industrial Temperature Option: – 40 to + 85°C
Part Number: SCM6323AYJ10A
V
11
12
13
14
15
16
17
34
33
32
31
30
29
28
V
BLOCK DIAGRAM
DD
SS
V
V
SS
DD
OUTPUT
ENABLE
BUFFER
G
HIGH BYTE OUTPUT ENABLE
LOW BYTE OUTPUT ENABLE
DQa
DQa
DQa
DQa
W
DQb
DQb
DQb
DQb
NC
A
HIGH
BYTE
OUTPUT
BUFFER
7
8
DQb
8
8
A
ADDRESS
BUFFERS
9
ROW
COLUMN
16
DECODER DECODER
A
18
19
20
21
22
27
26
25
24
23
HIGH
BYTE
WRITE
DRIVER
A
A
8
8
A
A
CHIP
E
ENABLE
BUFFER
A
A
NC
NC
SENSE
AMPS
64K x 16
BIT
16
LOW
BYTE
OUTPUT
BUFFER
WRITE
ENABLE
BUFFER
MEMORY
ARRAY
W
8
8
DQa
8
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
UB . . . . . . . . . . . . . . . . . . . . . . . . Upper Byte
LB . . . . . . . . . . . . . . . . . . . . . . . . . Lower Byte
DQa . . . . . . . . . . . . Lower Data Input/Output
DQb . . . . . . . . . . . . Upper Data Input/Output
LOW
BYTE
WRITE
DRIVER
8
8
LB
UB
BYTE
ENABLE
BUFFER
HIGH BYTE WRITE ENABLE
LOW BYTE WRITE ENABLE
V
DD
V
SS
. . . . . . . . . . . . . . + 3.3 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
This document contains information on a new product under development. Motorola reserves the right
to change or discontinue this product without notice.
REV 1
10/17/97
Motorola, Inc. 1997
TRUTH TABLE (X = Don’t Care)
E
H
L
L
L
L
L
L
L
L
G
X
H
X
L
W
X
H
X
H
H
H
L
LB
X
X
H
L
UB
X
X
H
H
L
Mode
V
Current
DQa’s
High–Z
High–Z
High–Z
DQb’s
High–Z
High–Z
High–Z
High–Z
DD
Not Selected
Output Disabled
Output Disabled
Low Byte Read
High Byte Read
Word Read
I
, I
SB1 SB2
I
I
I
I
I
I
I
I
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
D
out
L
H
L
High–Z
D
D
out
out
L
L
D
out
X
X
X
L
H
L
Low Byte Write
High Byte Write
Word Write
D
High–Z
in
L
H
L
High–Z
D
D
in
in
L
L
D
in
ABSOLUTE MAXIMUM RATINGS (See Notes)
Rating Symbol
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
thatnormal precautions be taken to avoid appli-
cation of any voltage higher than maximum
rated voltages to these high–impedance cir-
cuits.
This CMOS memory circuit has been de-
signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
andtransverse air flow of at least500linearfeet
per minute is maintained.
Value
– 0.5 to + 4.6
– 0.5 to V + 0.5
Unit
Supply Voltage
V
DD
V
V
Voltage on Any Pin
V
in
DD
± 20
Output Current per Pin
Package Power Dissipation
Temperature Under Bias
I
mA
W
out
P
.75
D
Commerial
Industrial
T
bias
– 10 to + 85
– 45 to + 90
°C
Operating Temperature
Commerial
Industrial
T
A
0 to + 70
– 40 to + 85
°C
°C
Storage Temperature
NOTES:
T
stg
– 55 to + 150
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposuretohigherthanrecommendedvoltagesforextended
periods of time could affect device reliability.
2. All voltages are referenced to V
.
SS
3. Powerdissipationcapabilitywillbedependentuponpackagecharacteristicsanduse
environment.
MCM6323A
2
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V ± 0.3 V, T = 0 to 70°C, Unless Otherwise Noted)
DD
(T = – 40 to + 85°C for Industrial Temperature Offering)
A
A
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
3.0
2.2
Typ
3.3
—
Max
Unit
V
Power Supply Voltage
V
DD
3.6
Input High Voltage
V
IH
V
V
+ 0.3**
DD
Input Low Voltage
V
IL
—
0.8
V
– 0.5*
*V (min) = – 0.5 V dc; V (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
IL
**V (max) = V
IL
+ 0.3 V dc; V (max) = V
+ 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
IH
DD
IH
DD
DC CHARACTERISTICS
Parameter
Symbol
Min
—
Max
± 1.0
± 1.0
0.4
Unit
µA
µA
V
Input Leakage Current (All Inputs, V = 0 to V
)
I
lkg(I)
in
DD
Output Leakage Current (E = V , V
IH out
= 0 to V
)
I
—
DD
lkg(O)
Output Low Voltage
(I
OL
(I
OL
= + 4.0 mA)
= + 100 µA)
V
OL
—
V
+ 0.2
SS
Output High Voltage
(I
OH
(I
OH
= – 4.0 mA)
= – 100 µA)
V
OH
2.4
—
V
V
– 0.2
DD
POWER SUPPLY CURRENTS (See Note 1)
Parameter
Symbol
6323A–10 6323A–12 6323A–15
Unit
Notes
AC Active Supply Current (I
out
= 0 mA)
Commerical
Industrial
I
140
150
135
140
130
135
mA
mA
mA
2
DDA
(V
= max, f = f
)
DD
max
AC Standby Current (E = V , V
IH DD
= max,
Commerical
Industrial
I
40
45
35
40
30
35
2
SB1
SB2
f = f
)
max
CMOS Standby Current (V
= max, f = 0 MHz,
Commerical
Industrial
I
5
5
5
5
5
5
DD
+ 0.2 V,
E ≥ V
DD
or ≥ V
– 0.2 V, V ≤ V
– 0.2 V)
in
SS
DD
NOTES:
1. Typical current = 25°C @ 3.3 V.
2. Reference AC Operating Conditions and Characteristics for input and timing (V /V , t /t , pulse level 0 to 3.0 V, V = 3.0 V, V = 0 V).
IH IL r f IH IL
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Typ
—
Max
Unit
pF
Address Input Capacitance
Control Input Capacitance
Input/Output Capacitance
C
C
6
6
8
in
in
—
pF
C
—
pF
I/O
MCM6323A
3
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V ± 0.3 V, T = 0 to +70°C, Unless Otherwise Noted)
DD
(T = – 40 to + 85°C for Industrial Temperature Offering)
A
A
Logic Input Timing Measurement Reference Level . . . . . . . . 1.50 V
Logic Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.50 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
READ CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM6323A–10
MCM6323A–12
MCM6323A–15
Parameter
Symbol
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Min
10
—
—
—
3
Max
—
10
10
4
Min
12
—
—
—
3
Max
—
12
12
5
Min
15
—
—
—
3
Max
—
15
15
6
Read Cycle Time
t
5
AVAV
Address Access Time
t
AVQV
Enable Access Time
t
ELQV
GLQV
AXQX
Output Enable Access Time
Output Hold from Address Change
Enable Low to Output Active
Output Enable Low to Output Active
Enable High to Output High–Z
Output Enable High to Output High–Z
Byte Enable Access Time
t
t
6
—
—
—
4
—
—
—
5
—
—
—
6
t
3
3
3
6, 7, 8
6, 7, 8
6, 7, 8
6, 7, 8
ELQX
GLQX
EHQZ
GHQZ
t
t
0
0
0
—
—
—
0
—
—
—
0
—
—
—
0
t
4
5
6
t
4
5
6
BLQV
BLQX
BHQZ
Byte Enable Low to Output Active
Byte High to Output High–Z
t
—
5
—
5
—
5
6, 7, 8
6, 7, 8
t
0
0
0
NOTES:
1. W is high for read cycle.
2. For common I/O applications, minimization, or elimination of bus contention conditions is necessary during read and write cycles.
3. Device is continuously selected (E = V , G = V , and LB and/or UB = V ).
IL IL IL
4. Addresses valid prior to or coincident with E going low.
5. All read cycle timings are referenced from the last valid address to the first transitioning address.
6. Transition is measured 200 mV from steady–state voltage.
7. At any given voltage and temperature, t
device to device.
(max) < t
ELQX
(min), and t
(max) < t (min), both for a given device and from
GLQX
EHQZ
GHQZ
8. This parameter is sampled and not 100% tested.
MCM6323A
4
MOTOROLA FAST SRAM
OUTPUT
30 pF
Z
= 50 Ω
R
= 50 Ω
0
L
1.5 V
Figure 1. Equivalent AC Test Load
2.0
1.5
1.0
0.5
OUTPUT
C
L
0
– 0.5
0
20
40
60
80
100
LUMPED CAPACITANCE, C (pF)
L
@ T = 25
°C, V
= 3.3 V
DD
Figure 2. Lumped Capacitive Load and Typical Derating Curve
+0.3
+0.2
+0.3
+0.2
+0.1
0
+0.1
0
–0.1
–0.1
–0.2
– 0.2
– 0.3
3.0
3.1
3.2
3.3
3.4
3.5
3.6
–50
–25
0
25
50
C)
= 3.3 V
75
100
OUTPUT
V
T (°
DD (V)
30 pF
@ V
DD
@ T = 25
°
C
Figure 3. Derating Across Temperature and Voltage
MCM6323A
5
MOTOROLA FAST SRAM
READ CYCLE 1 (See Note 7)
t
AVAV
A (ADDRESS)
Q (DATA OUT)
t
AXQX
PREVIOUS DATA VALID
DATA VALID
t
AVQV
READ CYCLE 2 (See Note 8)
t
AVAV
A (ADDRESS)
t
AVQV
t
ELQV
E (CHIP ENABLE)
t
EHQZ
t
ELQX
G (OUTPUT ENABLE)
t
t
GLQV
GHQZ
t
GLQX
BLQX
LB, UB (BYTE ENABLE)
Q (DATA OUT)
t
t
BHQZ
BLQV
t
DATA VALID
MCM6323A
6
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6323A–10
MCM6323A–12
MCM6323A–15
Parameter
Symbol
Unit
ns
Notes
Min
10
0
Max
—
Min
12
0
Max
—
Min
15
0
Max
—
Write Cycle Time
t
3
AVAV
Address Setup Time
t
—
—
—
ns
AVWL
Address Valid to End of Write
Write Pulse Width
t
8
—
9
—
10
10
—
ns
AVWH
t
,
8
—
9
—
—
ns
WLWH
t
WLEH
Byte Pulse Width
t
t
,
8
—
9
—
10
—
ns
BLWH
BLEH
Data Valid to End of Write
Data Hold Time
t
4
0
0
3
0
—
—
4
5
0
0
3
0
—
—
5
6
0
0
3
0
—
—
6
ns
ns
ns
ns
ns
DVWH
t
WHDX
Write Low to Data High–Z
Write High to Output Active
Write Recovery Time
NOTES:
t
4, 5, 6
4, 5, 6
WLQZ
t
—
—
—
—
—
—
WHQX
t
WHAX
1. A write occurs during the overlap of E low, W low, and LB and/or UB low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage.
5. At any given voltage and temperature, t
6. This parameter is sampled and not 100% tested.
max < t
min both for a given device and from device to device.
WHQX
WLQZ
WRITE CYCLE 1
(W Controlled)
t
AVAV
A (ADDRESS)
t
t
WHAX
AVWH
E (CHIP ENABLE)
t
WLEH
WLWH
t
W (WRITE ENABLE)
t
t
t
WHDX
AVWL
BLEH
BLWH
t
LB, UB (BYTE ENABLE)
t
DVWH
D (DATA IN)
DATA VALID
t
WLQZ
HIGH–Z
HIGH–Z
Q (DATA OUT)
t
WHQX
MCM6323A
7
MOTOROLA FAST SRAM
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM6323A–10
MCM6323A–12
MCM6323A–15
Parameter
Symbol
Unit
ns
Notes
Min
10
0
Max
—
Min
12
0
Max
—
Min
15
0
Max
—
Write Cycle Time
t
3
AVAV
Address Setup Time
t
—
—
—
ns
AVEL
Address Valid to End of Write
Enable to End of Write
t
8
—
9
—
10
10
—
ns
AVEH
t
t
,
8
—
9
—
—
ns
4, 5
ELEH
ELWH
Data Valid to End of Write
Data Hold Time
t
t
4
0
0
—
—
—
5
0
0
—
—
—
6
0
0
—
—
—
ns
ns
ns
DVEH
EHDX
Write Recovery Time
NOTES:
t
EHAX
1. A write occurs during the overlap of E low, W low, and LB and/or UB low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
(E Controlled)
t
AVAV
A (ADDRESS)
t
t
EHAX
AVEH
t
ELEH
E (CHIP ENABLE)
t
t
AVEL
ELWH
W (WRITE ENABLE)
LB, UB (BYTE ENABLE)
t
t
EHDX
DVEH
D (DATA IN)
DATA VALID
HIGH–Z
Q (DATA OUT)
MCM6323A
8
MOTOROLA FAST SRAM
WRITE CYCLE 3 (B Controlled, See Notes 1 and 2)
MCM6323A–10
MCM6323A–12
MCM6323A–15
Parameter
Symbol
Unit
ns
Notes
Min
10
0
Max
—
Min
12
0
Max
—
Min
15
0
Max
—
Write Cycle Time
t
3
AVAV
Address Setup Time
t
—
—
—
ns
AVBL
Address Valid to End of Write
Write Pulse Width
t
8
—
9
—
10
10
—
ns
AVBH
t
,
8
—
9
—
—
ns
WLWH
t
WLEH
Byte Pulse Width
t
t
t
,
,
8
—
9
—
10
—
ns
BLWH
BLEH
BLBH
DVBH
BHDX
WLQZ
Data Valid to End of Write
Data Hold Time
t
5
0
0
3
0
—
—
4
6
0
0
3
0
—
—
5
7
0
0
3
0
—
—
6
ns
ns
ns
ns
ns
t
Write Low to Data High–Z
Write High to Output Active
Write Recovery Time
NOTES:
t
4, 5, 6
4, 5, 6
t
—
—
—
—
—
—
WHQX
t
BHAX
1. A write occurs during the overlap of E low, W low, and LB and/or UB low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage.
5. At any given voltage and temperature, t
6. This parameter is sampled and not 100% tested.
max < t
min both for a given device and from device to device.
WHQX
WLQZ
WRITE CYCLE 3
(B Controlled)
t
AVAV
A (ADDRESS)
t
t
BHAX
AVBH
E (CHIP ENABLE)
t
t
BLEH
AVBL
t
t
BLWH
BLBH
LB, UB (BYTE ENABLE)
t
t
BHDX
WLEH
WLWH
t
W (WRITE ENABLE)
D (DATA IN)
t
DVBH
DATA VALID
t
WLQZ
HIGH–Z
HIGH–Z
Q (DATA OUT)
t
WHQX
MCM6323A
9
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM 6323A YJ
XX
X
X
Motorola Memory Prefix
Part Number
Shipping Method (R = Tape and Reel,
Blank = Rails for SOJ, Blank = Trays for TSOP)
Temperature (Blank = Commercial, A = Industrial)
Speed (10 = 10 ns, 12 = 12 ns, 15 = 15 ns)
Package (YJ = 400 mil SOJ, TS = 44–Lead
TSOP Type II)
Full Commercial Part Numbers — MCM6323AYJ10
MCM6323AYJ10R
MCM6323AYJ12
MCM6323AYJ12R
MCM6323ATS12
MCM6323AYJ15
MCM6323AYJ15R
MCM6323ATS15
MCM6323ATS15R
MCM6323ATS10
MCM6323ATS10R MCM6323ATS12R
Full Industrial Part Numbers —
SCM6323AYJ10A
SCM6323AYJ10AR SCM6323AYJ12AR
SCM6323ATS10A SCM6323ATS12A
SCM6323ATS10AR SCM6323ATS12AR
SCM6323AYJ12A
SCM6323AYJ15A
SCM6323AYJ15AR
SCM6323ATS15A
SCM6323ATS15AR
MCM6323A
10
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
YJ PACKAGE
400 MIL SOJ
CASE 919–01
44
23
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
E1
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
TIE BAR BURRS AND GATE BURRS. MOLD
FLASH, TIE BAR BURRS AND GATE BURRS
SHALL NOT EXCEED 0.006 PER END. DIMENSION
E1 DOES NOT INCLUDE INTERLEAD FLASH.
INTERLEAD FLASH SHALL NOT EXCEED 0.010
PER SIDE.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. DIMENSIONS D AND E1 AND,
HENCE, DATUMS A AND B, ARE DETERMINED AT
THE OUTERMOST EXTREMES OF THE PLASTIC
BODY EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
5. DIMENSION b1 DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE
SHOULDER WIDTH TO EXCEED b1 MAX BY
MORE THAN 0.005. THE DAMBAR INTRUSION(S)
SHALL NOT REDUCE THE SHOULDER WIDTH TO
LESS THAN 0.001 BELOW b1 MIN.
1
22
B
A
D
44X b1
L
0.007
C A B
42X
e
A
A3
SEATING
PLANE
A
e /2
0.004
C
C
44X b
0.007
M
C
A
B
C
INCHES
DIM
A
A1
A2
A3
b
b1
D
E
MIN
MAX
0.148
–––
0.128
0.025
0.082
0.035
0.015
0.026
1.120
0.435
0.395
E
–––
0.045
0.020
0.032
1.130
0.445
0.405
M
0.007
A B
A
A2
E1
E2
e
0.370 BSC
0.050 BSC
0.030 0.040
44X R R1
R1
E2 /2
A1
E2
VIEW A–A
0.015
B
22 ZONES 2X
MCM6323A
11
MOTOROLA FAST SRAM
TS PACKAGE
44–LEAD
TSOP TYPE II
CASE 924A–01
VIEW A
R (R1)
B
4
4
2
3
R (R2)
A1
E1
L
A
A
DETAIL A
ROTATED 90 CLOCKWISE
b1
1
22
BASE METAL
A
A
D1
A2
22X E
c1
c
M
0
0
.
C0 A
8
(
0
.
2
)
b
M
0.008 (0.2)
T Z
44X
SECTION A–A
40 PLACES
0.004 (0.1)
C
NOTES:
SEATING
PLANE
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION
IS 0.006 (0.015) PER SIDE.
4X e /2
C
42X
e
4. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSIONS. DAMBAR PROTRUSIONS SHALL
NOT ALLOW THE b DIMENSION TO EXCEED 0.023
(0.58).
INCHES
MILLIMETERS
DIM
A
A1
A2
b
b1
c
c1
D1
e
E
E1
L
R1
R2
MIN
MAX
0.050
0.006
0.042
0.018
0.016
0.008
0.006
MIN
–––
MAX
1.270
0.152
1.067
0.457
0.406
0.203
0.152
–––
0.002
0.038
0.012
0.012
0.005
0.004
0.721
0.051
0.965
0.305
0.305
0.127
0.101
0.729 18.313 18.517
0.0315 BSC
0.800 BSC
0.470 11.582 11.938
0.404 10.058 10.262
0.456
0.396
0.016
0.004 REF
0.004 REF
0.023
0.406
0.100 REF
0.100 REF
0.584
0
5
0
5
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